coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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1019 discussions

New patch to review for coreboot: libpayload: Enable SSE and FPU on demand
by Patrick Rudolph 12 Feb '17

12 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18345 -gerrit commit 953b58791878c2139d5c4b0a9848d426974ea261 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 15 10:49:48 2017 +0100 libpayload: Enable SSE and FPU on demand Use cpuid feature bits to detect and enable FPU and SSE instructions. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: … [View More]

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New patch to review for coreboot: libpayload: Add cpuid function
by Patrick Rudolph 12 Feb '17

12 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18344 -gerrit commit 6dcf825e75fd181139bde49ea99581e2242e7e4e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 15 10:47:59 2017 +0100 libpayload: Add cpuid function Copy memtest86Plus cpuid and enabled it for CONFIG_LP_GPL. Change-Id: I62198e5b4823b53c26a5921de4a8e9c59e05fcd1 Signed-off-by: Patrick Rudolph <siro(a)… [View More]das-labor.org> --- payloads/libpayload/arch/x86/Makefile.inc | 1 + payloads/libpayload/arch/x86/cpuid.c | 99 +++++++++++ payloads/libpayload/include/x86/arch/cpuid.h | 241 +++++++++++++++++++++++++++ 3 files changed, 341 insertions(+) diff --git a/payloads/libpayload/arch/x86/Makefile.inc b/payloads/libpayload/arch/x86/Makefile.inc index 6517bf1..9c4292a 100644 --- a/payloads/libpayload/arch/x86/Makefile.inc +++ b/payloads/libpayload/arch/x86/Makefile.inc @@ -38,6 +38,7 @@ libc-y += exception_asm.S exception.c # Will fall back to default_memXXX() in libc/memory.c if GPL not allowed. libc-$(CONFIG_LP_GPL) += string.c +libc-$(CONFIG_LP_GPL) += cpuid.c libgdb-y += gdb.c diff --git a/payloads/libpayload/arch/x86/cpuid.c b/payloads/libpayload/arch/x86/cpuid.c new file mode 100644 index 0000000..6e35bc3 --- /dev/null +++ b/payloads/libpayload/arch/x86/cpuid.c @@ -0,0 +1,99 @@ +/* + * This file is part of the libpayload project and has been + * taken from Memtest86Plus, which is licensed under GPLv2. + * + * Copyright 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <arch/cpuid.h> + +struct cpu_ident cpu_id; + +void get_cpuid(void) +{ + unsigned int *v, dummy[3]; + char *p, *q; + + /* Get max std cpuid & vendor ID */ + cpuid(0x0, &cpu_id.max_cpuid, &cpu_id.vend_id.uint32_array[0], + &cpu_id.vend_id.uint32_array[2], &cpu_id.vend_id.uint32_array[1]); + cpu_id.vend_id.char_array[11] = 0; + + /* Get processor family information & feature flags */ + if (cpu_id.max_cpuid >= 1) { + cpuid(0x00000001, &cpu_id.vers.flat, &cpu_id.info.flat, + &cpu_id.fid.uint32_array[1], &cpu_id.fid.uint32_array[0]); + } + + /* Get the digital thermal sensor & power management status bits */ + if (cpu_id.max_cpuid >= 6) + cpuid(0x00000006, &cpu_id.dts_pmp, &dummy[0], &dummy[1], &dummy[2]); + + /* Get the max extended cpuid */ + cpuid(0x80000000, &cpu_id.max_xcpuid, &dummy[0], &dummy[1], &dummy[2]); + + /* Get extended feature flags, only save EDX */ + if (cpu_id.max_xcpuid >= 0x80000001) { + cpuid(0x80000001, &dummy[0], &dummy[1], + &dummy[2], &cpu_id.fid.uint32_array[2]); + } + + /* Get the brand ID */ + if (cpu_id.max_xcpuid >= 0x80000004) { + v = (unsigned int *)&cpu_id.brand_id; + cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]); + cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]); + cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]); + cpu_id.brand_id.char_array[47] = 0; + } + /* + * Intel chips right-justify this string for some dumb reason; + * undo that brain damage: + */ + p = q = &cpu_id.brand_id.char_array[0]; + while (*p == ' ') + p++; + if (p != q) { + while (*p) + *q++ = *p++; + while (q <= &cpu_id.brand_id.char_array[48]) + *q++ = '\0'; /* Zero-pad the rest */ + } + + /* Get cache information */ + switch (cpu_id.vend_id.char_array[0]) { + case 'A': + /* AMD Processors */ + /* The cache information is only in ecx and edx so only save + * those registers */ + if (cpu_id.max_xcpuid >= 0x80000005) { + cpuid(0x80000005, &dummy[0], &dummy[1], + &cpu_id.cache_info.uint[0], &cpu_id.cache_info.uint[1]); + } + if (cpu_id.max_xcpuid >= 0x80000006) { + cpuid(0x80000006, &dummy[0], &dummy[1], + &cpu_id.cache_info.uint[2], &cpu_id.cache_info.uint[3]); + } + break; + case 'G': + /* Intel Processors, Need to do this in init.c */ + break; + } + + /* Turn off mon bit since monitor based spin wait may not be reliable */ + cpu_id.fid.bits.mon = 0; +} diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h new file mode 100644 index 0000000..7628b88 --- /dev/null +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -0,0 +1,241 @@ +/* + * This file is part of the libpayload project and has been + * taken from Memtest86Plus, which is licensed under GPLv2. + * + * Copyright 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * + */ + +#ifndef __ARCH_CPUID_H__ +#define __ARCH_CPUID_H__ +#if IS_ENABLED(CONFIG_LP_GPL) + +#include <stdint.h> + +#define CPUID_VENDOR_LENGTH 3 /* 3 GPRs hold vendor ID */ +#define CPUID_VENDOR_STR_LENGTH (CPUID_VENDOR_LENGTH * sizeof(uint32_t) + 1) +#define CPUID_BRAND_LENGTH 12 /* 12 GPRs hold vendor ID */ +#define CPUID_BRAND_STR_LENGTH (CPUID_BRAND_LENGTH * sizeof(uint32_t) + 1) + +extern struct cpu_ident cpu_id; + +static inline void __cpuid(unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + /* ecx is often an input as well as an output. */ + asm volatile("\t" + "push %%ebx; cpuid; mov %%ebx, %%edi; pop %%ebx" + : "=a" (*eax), + "=D" (*ebx), + "=c" (*ecx), + "=d" (*edx) + : "0" (*eax), "2" (*ecx)); +} + +static inline void cpuid(unsigned int op, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + *eax = op; + *ecx = 0; + __cpuid(eax, ebx, ecx, edx); +} + +/* Some CPUID calls want 'count' to be placed in ecx */ +static inline void cpuid_count(unsigned int op, int count, + unsigned int *eax, unsigned int *ebx, + unsigned int *ecx, unsigned int *edx) +{ + *eax = op; + *ecx = count; + __cpuid(eax, ebx, ecx, edx); +} + +void get_cpuid(void); + +/* Typedef for storing the Cache Information */ +typedef union { + unsigned char ch[48]; + uint32_t uint[12]; + struct { + uint32_t fill1:24; /* Bit 0 */ + uint32_t l1_i_sz:8; + uint32_t fill2:24; + uint32_t l1_d_sz:8; + uint32_t fill3:16; + uint32_t l2_sz:16; + uint32_t fill4:18; + uint32_t l3_sz:14; + uint32_t fill5[8]; + } amd; +} cpuid_cache_info_t; + +/* Typedef for storing the CPUID Vendor String */ +typedef union { + /* Note: the extra byte in the char array is for '\0'. */ + char char_array[CPUID_VENDOR_STR_LENGTH]; + uint32_t uint32_array[CPUID_VENDOR_LENGTH]; +} cpuid_vendor_string_t; + +/* Typedef for storing the CPUID Brand String */ +typedef union { + /* Note: the extra byte in the char array is for '\0'. */ + char char_array[CPUID_BRAND_STR_LENGTH]; + uint32_t uint32_array[CPUID_BRAND_LENGTH]; +} cpuid_brand_string_t; + +/* Typedef for storing CPUID Version */ +typedef union { + uint32_t flat; + struct { + uint32_t stepping:4; /* Bit 0 */ + uint32_t model:4; + uint32_t family:4; + uint32_t processorType:2; + uint32_t reserved1514:2; + uint32_t extendedModel:4; + uint32_t extendedFamily:8; + uint32_t reserved3128:4; /* Bit 31 */ + } bits; +} cpuid_version_t; + +/* Typedef for storing CPUID Processor Information */ +typedef union { + uint32_t flat; + struct { + uint32_t brandIndex:8; /* Bit 0 */ + uint32_t cflushLineSize:8; + uint32_t logicalProcessorCount:8; + uint32_t apicID:8; /* Bit 31 */ + } bits; +} cpuid_proc_info_t; + +/* Typedef for storing CPUID Feature flags */ +typedef union { + uint32_t flat; + struct { + uint32_t dummy:1; + } bits; +} cpuid_custom_features; + +/* Typedef for storing CPUID Feature flags */ +typedef union { + uint32_t uint32_array[3]; + struct { + uint32_t fpu:1; /* EDX feature flags, bit 0 */ + uint32_t vme:1; + uint32_t de:1; + uint32_t pse:1; + uint32_t rdtsc:1; + uint32_t msr:1; + uint32_t pae:1; + uint32_t mce:1; + uint32_t cx8:1; + uint32_t apic:1; + uint32_t bit10:1; + uint32_t sep:1; + uint32_t mtrr:1; + uint32_t pge:1; + uint32_t mca:1; + uint32_t cmov:1; + uint32_t pat:1; + uint32_t pse36:1; + uint32_t psn:1; + uint32_t cflush:1; + uint32_t bit20:1; + uint32_t ds:1; + uint32_t acpi:1; + uint32_t mmx:1; + uint32_t fxsr:1; + uint32_t sse:1; + uint32_t sse2:1; + uint32_t ss:1; + uint32_t htt:1; + uint32_t tm:1; + uint32_t bit30:1; + uint32_t pbe:1; /* EDX feature flags, bit 31 */ + uint32_t sse3:1; /* ECX feature flags, bit 0 */ + uint32_t mulq:1; + uint32_t dtes64:1; + uint32_t mon:1; + uint32_t dscpl:1; + uint32_t vmx:1; + uint32_t smx:1; + uint32_t eist:1; + uint32_t tm2:1; + uint32_t ssse3:1; + uint32_t cnxtid:1; + uint32_t bit11:1; + uint32_t fma:1; + uint32_t cx16:1; + uint32_t xtpr:1; + uint32_t pdcm:1; + uint32_t bits_16_17:2; + uint32_t dca:1; + uint32_t sse41:1; + uint32_t sse42:1; + uint32_t x2apic:1; + uint32_t movbe:1; + uint32_t popcnt:1; + uint32_t bit24:1; + uint32_t aesni:1; + uint32_t xsave:1; + uint32_t osxsave:1; + uint32_t avx:1; + uint32_t f16c:1; + uint32_t rdrand:1; + uint32_t bit31:1; + uint32_t bits0_28:29; /* EDX extended feature flags, bit 0 */ + uint32_t lm:1; /* Long Mode */ + uint32_t bits_30_31:2; /* EDX extended feature flags, bit 32 */ + } bits; +} cpuid_feature_flags_t; + +/* An overall structure to cache all of the CPUID information */ +struct cpu_ident { + uint32_t max_cpuid; + uint32_t max_xcpuid; + uint32_t dts_pmp; + cpuid_version_t vers; + cpuid_proc_info_t info; + cpuid_feature_flags_t fid; + cpuid_vendor_string_t vend_id; + cpuid_brand_string_t brand_id; + cpuid_cache_info_t cache_info; + cpuid_custom_features custom; +}; + +struct cpuid4_eax { + uint32_t ctype:5; + uint32_t level:3; + uint32_t is_self_initializing:1; + uint32_t is_fully_associative:1; + uint32_t reserved:4; + uint32_t num_threads_sharing:12; + uint32_t num_cores_on_die:6; +}; + +struct cpuid4_ebx { + uint32_t coherency_line_size:12; + uint32_t physical_line_partition:10; + uint32_t ways_of_associativity:10; +}; + +struct cpuid4_ecx { + uint32_t number_of_sets:32; +}; + +#endif +#endif + [View Less]

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Patch set updated for coreboot: mainboard/google/eve: Generate fingerprint device using SPI SSDT generator
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18343 -gerrit commit bd95df5292459d88e38cfd1e0684b04459bd4ddb Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Feb 11 12:02:40 2017 -0800 mainboard/google/eve: Generate fingerprint device using SPI SSDT generator Use the newly added SPI SSDT generator for adding fingerprint device. BUG=chrome-os-partner:59832 BRANCH=None … [View More] TEST=Compiles successfully. Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/eve/Kconfig | 1 + src/mainboard/google/eve/acpi/mainboard.asl | 49 ----------------------------- src/mainboard/google/eve/devicetree.cb | 11 ++++++- src/mainboard/google/eve/dsdt.asl | 3 -- 4 files changed, 11 insertions(+), 53 deletions(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index e83e7d9..1a4a4c5 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl deleted file mode 100644 index a55308f..0000000 --- a/src/mainboard/google/eve/acpi/mainboard.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_SB.PCI0.SPI1) -{ - Device (FPC) - { - Name (_HID, "PRP0001") - Name (_UID, 1) - Name (_CRS, ResourceTemplate () - { - SpiSerialBus ( - 0, // DeviceSelection (CS0) - PolarityLow, // DeviceSelectionPolarity - FourWireMode, // WireMode - 8, // DataBitLength - ControllerInitiated, // SlaveMode - 1000000, // ConnectionSpeed (1MHz) - ClockPolarityLow, // ClockPolarity - ClockPhaseFirst, // ClockPhase - "\\_SB.PCI0.SPI1", // ResourceSource - 0, // ResourceSourceIndex - ResourceConsumer, // ResourceUsage - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { - "compatible", - Package () { "fpc,fpc1020" } - }, - } - }) - } -} diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index d619d60..c8d8175 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -256,7 +256,16 @@ chip soc/intel/skylake device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = ""PRP0001"" + register "uid" = "1" + register "speed" = "1000000" + register "compat_string" = ""fpc,fpc1020"" + register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)" + device spi 0 on end + end + end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 22b92f3..2882d50 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -67,7 +67,4 @@ DefinitionBlock( { #include "acpi/dptf.asl" } - - /* ACPI code for EC functions */ - #include "acpi/mainboard.asl" } [View Less]

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Patch set updated for coreboot: drivers/spi: Add support for generating SPI device in SSDT
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18342 -gerrit commit 1cf6d79f17bf77502ff84578998c33ad034c0858 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Feb 11 11:16:18 2017 -0800 drivers/spi: Add support for generating SPI device in SSDT Similar to I2C driver, add support for generating SPI device and required properties in SSDT for ACPI. BUG=chrome-os-partner:… [View More]59832 BRANCH=None TEST=Compiles succesfully. Verified SPI device generated in SSDT on poppy. Change-Id: Ic4da79c823131d54d9eb3652b86f6e40fe643ab5 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/acpi/Kconfig | 18 +++++ src/drivers/spi/acpi/Makefile.inc | 16 +++++ src/drivers/spi/acpi/acpi.c | 147 ++++++++++++++++++++++++++++++++++++++ src/drivers/spi/acpi/chip.h | 32 +++++++++ 4 files changed, 213 insertions(+) diff --git a/src/drivers/spi/acpi/Kconfig b/src/drivers/spi/acpi/Kconfig new file mode 100644 index 0000000..c1653d5 --- /dev/null +++ b/src/drivers/spi/acpi/Kconfig @@ -0,0 +1,18 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2017 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config DRIVERS_SPI_ACPI + bool + depends on HAVE_ACPI_TABLES diff --git a/src/drivers/spi/acpi/Makefile.inc b/src/drivers/spi/acpi/Makefile.inc new file mode 100644 index 0000000..7ae6e45 --- /dev/null +++ b/src/drivers/spi/acpi/Makefile.inc @@ -0,0 +1,16 @@ +# +# This file is part of the coreboot project. +# +# Copyright 2017 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-$(CONFIG_DRIVERS_SPI_ACPI) += acpi.c diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c new file mode 100644 index 0000000..1c18ed4 --- /dev/null +++ b/src/drivers/spi/acpi/acpi.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <device/spi.h> +#include <spi-generic.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +static int spi_acpi_get_bus(struct device *dev) +{ + struct device *spi_dev; + struct device_operations *ops; + + if (!dev->bus || !dev->bus->dev) + return -1; + + spi_dev = dev->bus->dev; + ops = spi_dev->ops; + + if (ops && ops->ops_spi_bus && + ops->ops_spi_bus->dev_to_bus) + return ops->ops_spi_bus->dev_to_bus(spi_dev); + + return -1; +} + +static void spi_acpi_fill_ssdt_generator(struct device *dev) +{ + struct drivers_spi_acpi_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd = NULL; + struct spi_cfg spi_cfg; + struct spi_slave slave; + int bus = -1, cs = dev->path.spi.cs; + struct acpi_spi spi = { + .device_select = cs, + .speed = config->speed, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + bus = spi_acpi_get_bus(dev); + if (bus == -1) { + printk(BIOS_ERR, "%s: ERROR: Cannot get bus for device.\n", + dev_path(dev)); + return; + } + + if (!config->hid) { + printk(BIOS_ERR, "%s: ERROR: HID required.\n", dev_path(dev)); + return; + } + + if (spi_setup_slave(bus, cs, &slave)) { + printk(BIOS_ERR, "%s: ERROR: SPI setup failed.\n", + dev_path(dev)); + return; + } + + if (spi_get_config(&slave, &spi_cfg)) { + printk(BIOS_ERR, "%s: ERROR: SPI get config failed.\n", + dev_path(dev)); + return; + } + + spi.device_select_polarity = spi_cfg.cs_polarity; + spi.wire_mode = spi_cfg.wire_mode; + spi.data_bit_length = spi_cfg.data_bit_length; + spi.clock_phase = spi_cfg.clk_phase; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->hid); + if (config->cid) + acpigen_write_name_string("_CID", config->cid); + acpigen_write_name_integer("_UID", config->uid); + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_spi(&spi); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + if (config->compat_string) { + dsd = acpi_dp_new_table("_DSD"); + acpi_dp_add_string(dsd, "compatible", config->compat_string); + acpi_dp_write(dsd); + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *spi_acpi_name(struct device *dev) +{ + struct drivers_spi_acpi_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + + snprintf(name, sizeof(name), "S%03.3X", spi_acpi_get_bus(dev)); + name[4] = '\0'; + return name; +} + +static struct device_operations spi_acpi_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .acpi_name = &spi_acpi_name, + .acpi_fill_ssdt_generator = &spi_acpi_fill_ssdt_generator, +}; + +static void spi_acpi_enable(struct device *dev) +{ + dev->ops = &spi_acpi_ops; +} + +struct chip_operations drivers_spi_acpi_ops = { + CHIP_NAME("SPI Device") + .enable_dev = &spi_acpi_enable +}; diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h new file mode 100644 index 0000000..4e7f8e7 --- /dev/null +++ b/src/drivers/spi/acpi/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPI_ACPI_CHIP_H__ +#define __SPI_ACPI_CHIP_H__ + +#include <arch/acpi_device.h> + +struct drivers_spi_acpi_config { + const char *hid; /* ACPI _HID (required) */ + const char *cid; /* ACPI _CID */ + const char *name; /* ACPI Device Name */ + const char *desc; /* Device Description */ + unsigned uid; /* ACPI _UID */ + unsigned speed; /* Bus speed in Hz(required) */ + const char *compat_string; /* Compatible string for _HID=PRP0001 */ + struct acpi_irq irq; /* Interrupt */ +}; + +#endif /* __SPI_ACPI_CHIP_H__ */ [View Less]

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Patch set updated for coreboot: soc/intel/skylake: Add support for SPI device
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18341 -gerrit commit f6f1ab302a9075607b957311787739d61b43b4be Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Feb 11 11:06:19 2017 -0800 soc/intel/skylake: Add support for SPI device Add a new PCI driver for SPI devices with supported PCI ids. Also, provide a translation table to convert struct device structure into SPI bus … [View More]number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: If860eb819f2ce5ae5443f808b356af57f86c52be Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/include/soc/pci_devs.h | 10 ++++++++ src/soc/intel/skylake/spi.c | 37 ++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 974f1d8..a19a7c6 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -176,4 +176,14 @@ static inline int i2c_devfn_to_bus(unsigned devfn) return -1; } +static inline int spi_devfn_to_bus(unsigned devfn) +{ + switch (devfn) { + case PCH_DEVFN_SPI: return 0; + case PCH_DEVFN_GSPI0: return 1; + case PCH_DEVFN_GSPI1: return 2; + } + return -1; +} + #endif diff --git a/src/soc/intel/skylake/spi.c b/src/soc/intel/skylake/spi.c index ddff4dc..6571fd5 100644 --- a/src/soc/intel/skylake/spi.c +++ b/src/soc/intel/skylake/spi.c @@ -15,6 +15,12 @@ */ #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/spi.h> +#include <soc/ramstage.h> #include <spi-generic.h> /* SPI controller managing the flash-device SPI. */ @@ -61,3 +67,34 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) + +static int spi_dev_to_bus(struct device *dev) +{ + return spi_devfn_to_bus(dev->path.pci.devfn); +} + +static struct spi_bus_operations spi_bus_ops = { + .dev_to_bus = &spi_dev_to_bus, +}; + +static struct device_operations spi_dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_smbus, + .ops_pci = &soc_pci_ops, + .ops_spi_bus = &spi_bus_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9d24, 0x9d29, 0x9d2a, 0 +}; + +static const struct pci_driver pch_spi __pci_driver = { + .ops = &spi_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif [View Less]

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Patch set updated for coreboot: device: Add a new "SPI" device type
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18340 -gerrit commit adea8487311fbd1cb9a4d7f312a63eef2bf596e6 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Feb 11 10:57:23 2017 -0800 device: Add a new "SPI" device type Add support for a new "SPI" device type in the devicetree to bind a device on the SPI bus. Allow device to provide chip select number for the device as a … [View More]parameter. Add spi_bus_operations with operation dev_to_bus which allows SoCs to define a translation method for converting "struct device" into a unique SPI bus number. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/device/device_util.c | 10 ++++++++++ src/include/device/device.h | 2 ++ src/include/device/path.h | 10 +++++++++- src/include/device/spi.h | 30 ++++++++++++++++++++++++++++++ 4 files changed, 51 insertions(+), 1 deletion(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 1a0a60f..e31ade5 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -250,6 +250,9 @@ u32 dev_path_encode(device_t dev) case DEVICE_PATH_GENERIC: ret |= dev->path.generic.subid << 8 | dev->path.generic.id; break; + case DEVICE_PATH_SPI: + ret |= dev->path.spi.cs; + break; case DEVICE_PATH_NONE: default: break; @@ -319,6 +322,10 @@ const char *dev_path(device_t dev) "GENERIC: %d.%d", dev->path.generic.id, dev->path.generic.subid); break; + case DEVICE_PATH_SPI: + snprintf(buffer, sizeof (buffer), "SPI: %02x", + dev->path.spi.cs); + break; default: printk(BIOS_ERR, "Unknown device path type: %d\n", dev->path.type); @@ -390,6 +397,9 @@ int path_eq(struct device_path *path1, struct device_path *path2) equal = (path1->generic.id == path2->generic.id) && (path1->generic.subid == path2->generic.subid); break; + case DEVICE_PATH_SPI: + equal = (path1->spi.cs == path2->spi.cs); + break; default: printk(BIOS_ERR, "Unknown device type: %d\n", path1->type); break; diff --git a/src/include/device/device.h b/src/include/device/device.h index 47509f7..e21384b 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -23,6 +23,7 @@ struct pci_bus_operations; struct i2c_bus_operations; struct smbus_bus_operations; struct pnp_mode_ops; +struct spi_bus_operations; /* Chip operations */ struct chip_operations { @@ -64,6 +65,7 @@ struct device_operations { #endif const struct pci_operations *ops_pci; const struct i2c_bus_operations *ops_i2c_bus; + const struct spi_bus_operations *ops_spi_bus; const struct smbus_bus_operations *ops_smbus_bus; const struct pci_bus_operations * (*ops_pci_bus)(device_t dev); const struct pnp_mode_ops *ops_pnp_mode; diff --git a/src/include/device/path.h b/src/include/device/path.h index 9d7fb38..b600272 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -14,6 +14,7 @@ enum device_path_type { DEVICE_PATH_CPU_BUS, DEVICE_PATH_IOAPIC, DEVICE_PATH_GENERIC, + DEVICE_PATH_SPI, /* * When adding path types to this table, please also update the @@ -33,7 +34,8 @@ enum device_path_type { "DEVICE_PATH_CPU", \ "DEVICE_PATH_CPU_BUS", \ "DEVICE_PATH_IOAPIC", \ - "DEVICE_PATH_GENERIC" \ + "DEVICE_PATH_GENERIC", \ + "DEVICE_PATH_SPI", \ } struct domain_path @@ -58,6 +60,11 @@ struct i2c_path unsigned mode_10bit; }; +struct spi_path +{ + unsigned cs; +}; + struct apic_path { unsigned apic_id; @@ -107,6 +114,7 @@ struct device_path { struct cpu_path cpu; struct cpu_bus_path cpu_bus; struct generic_path generic; + struct spi_path spi; }; }; diff --git a/src/include/device/spi.h b/src/include/device/spi.h new file mode 100644 index 0000000..4315ebc --- /dev/null +++ b/src/include/device/spi.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DEVICE_SPI_H__ +#define __DEVICE_SPI_H__ + +struct device; +struct spi_bus_operations { + /* + * This is a SoC-specific method that can be provided to translate the + * 'struct device' for a SPI controller into a unique SPI bus + * number. Returns -1 if the bus number for this bus cannot be + * determined. + */ + int (*dev_to_bus)(struct device *dev); +}; + +#endif /* __DEVICE_SPI_H__ */ [View Less]

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Patch set updated for coreboot: sconfig: Add a new "SPI" device type
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18339 -gerrit commit d4918790e4c6277869884a0514ba3c24c0cc954a Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Feb 11 00:50:38 2017 -0800 sconfig: Add a new "SPI" device type Update sconfig lex and yacc files to add support for a new "SPI" device type in the devicetree. SPI device takes only parameter i.e. chip select number … [View More]for the device on the SPI bus. Re-generate the shipped files for sconfig using flex 2.6.0 and bison 3.0.4 (make CONFIG_SCONFIG_GENPARSER=1). Clean up local paths that leak into generated files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Change-Id: If0831e25b3e4ed87827ad92356d7bf47b6387884 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- util/sconfig/lex.yy.c_shipped | 245 +++++++++++++++++++------------------ util/sconfig/main.c | 5 + util/sconfig/sconfig.l | 1 + util/sconfig/sconfig.tab.c_shipped | 30 ++--- util/sconfig/sconfig.tab.h_shipped | 3 +- util/sconfig/sconfig.y | 2 +- 6 files changed, 151 insertions(+), 135 deletions(-) diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 2600296..500636b 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -208,7 +208,7 @@ struct yy_buffer_state /* Number of characters read into yy_ch_buf, not including EOB * characters. */ - int yy_n_chars; + yy_size_t yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to @@ -278,7 +278,7 @@ static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */ /* yy_hold_char holds the character lost when yytext is formed. */ static char yy_hold_char; -static int yy_n_chars; /* number of characters read into yy_ch_buf */ +static yy_size_t yy_n_chars; /* number of characters read into yy_ch_buf */ yy_size_t yyleng; /* Points to current character in buffer. */ @@ -373,8 +373,8 @@ static void yy_fatal_error (yyconst char msg[] ); *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 33 -#define YY_END_OF_BUFFER 34 +#define YY_NUM_RULES 34 +#define YY_END_OF_BUFFER 35 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -382,22 +382,23 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[130] = +static yyconst flex_int16_t yy_accept[132] = { 0, - 0, 0, 34, 32, 1, 3, 32, 32, 32, 27, - 27, 25, 28, 32, 28, 28, 28, 32, 32, 32, - 32, 32, 32, 32, 32, 1, 3, 32, 0, 32, - 32, 0, 2, 27, 28, 32, 32, 32, 32, 28, - 32, 32, 32, 32, 32, 32, 20, 32, 32, 32, - 7, 32, 32, 32, 32, 31, 31, 32, 0, 26, - 32, 32, 15, 32, 32, 19, 24, 32, 12, 32, - 32, 18, 32, 8, 9, 11, 32, 32, 32, 0, - 29, 4, 32, 32, 32, 32, 32, 32, 32, 32, - 32, 30, 30, 32, 32, 32, 32, 32, 32, 13, - - 32, 32, 32, 5, 16, 32, 32, 10, 32, 32, - 32, 17, 22, 32, 32, 32, 32, 32, 6, 32, - 32, 32, 32, 32, 21, 32, 14, 23, 0 + 0, 0, 35, 33, 1, 3, 33, 33, 33, 28, + 28, 26, 29, 33, 29, 29, 29, 33, 33, 33, + 33, 33, 33, 33, 33, 1, 3, 33, 0, 33, + 33, 0, 2, 28, 29, 33, 33, 33, 33, 29, + 33, 33, 33, 33, 33, 33, 21, 33, 33, 33, + 7, 33, 33, 33, 33, 33, 32, 32, 33, 0, + 27, 33, 33, 15, 33, 33, 20, 25, 33, 12, + 33, 33, 19, 33, 8, 9, 11, 33, 18, 33, + 33, 0, 30, 4, 33, 33, 33, 33, 33, 33, + 33, 33, 33, 31, 31, 33, 33, 33, 33, 33, + + 33, 13, 33, 33, 33, 5, 16, 33, 33, 10, + 33, 33, 33, 17, 23, 33, 33, 33, 33, 33, + 6, 33, 33, 33, 33, 33, 22, 33, 14, 24, + 0 } ; static yyconst YY_CHAR yy_ec[256] = @@ -440,102 +441,104 @@ static yyconst YY_CHAR yy_meta[39] = 1, 1, 1, 1, 1, 1, 1, 1 } ; -static yyconst flex_uint16_t yy_base[137] = +static yyconst flex_uint16_t yy_base[139] = { 0, - 0, 0, 200, 0, 197, 201, 195, 37, 41, 38, - 160, 0, 44, 182, 54, 78, 60, 174, 45, 177, - 42, 47, 172, 157, 0, 189, 201, 77, 185, 87, - 69, 186, 201, 0, 86, 104, 173, 162, 151, 93, - 158, 153, 163, 154, 162, 156, 162, 147, 147, 154, - 0, 150, 144, 150, 154, 0, 201, 101, 166, 0, - 159, 139, 152, 142, 149, 0, 0, 144, 0, 143, - 133, 0, 137, 0, 0, 0, 136, 127, 154, 153, - 0, 0, 138, 137, 130, 122, 121, 127, 132, 117, - 111, 0, 201, 122, 126, 118, 120, 119, 124, 0, - - 108, 95, 92, 0, 0, 101, 85, 102, 96, 80, - 76, 0, 0, 83, 73, 77, 63, 64, 0, 64, - 62, 50, 51, 33, 0, 28, 0, 0, 201, 40, - 129, 131, 133, 135, 137, 139 + 0, 0, 202, 0, 199, 203, 197, 37, 41, 38, + 162, 0, 44, 184, 54, 78, 60, 176, 45, 179, + 42, 47, 174, 41, 0, 192, 203, 77, 188, 87, + 91, 189, 203, 0, 88, 104, 176, 165, 154, 93, + 161, 156, 166, 157, 165, 159, 165, 150, 150, 157, + 0, 153, 147, 153, 150, 156, 0, 203, 101, 168, + 0, 161, 141, 154, 144, 151, 0, 0, 146, 0, + 145, 135, 0, 139, 0, 0, 0, 138, 0, 129, + 156, 155, 0, 0, 140, 139, 132, 124, 123, 129, + 134, 119, 113, 0, 203, 124, 128, 120, 122, 121, + + 126, 0, 110, 110, 107, 0, 0, 109, 93, 104, + 98, 84, 84, 0, 0, 89, 77, 87, 71, 66, + 0, 64, 62, 50, 47, 33, 0, 28, 0, 0, + 203, 40, 129, 131, 133, 135, 137, 139 } ; -static yyconst flex_int16_t yy_def[137] = +static yyconst flex_int16_t yy_def[139] = { 0, - 129, 1, 129, 130, 129, 129, 130, 131, 132, 130, - 10, 130, 10, 130, 10, 10, 10, 130, 130, 130, - 130, 130, 130, 130, 130, 129, 129, 131, 133, 134, - 132, 135, 129, 10, 10, 10, 130, 130, 130, 10, - 130, 130, 130, 130, 130, 130, 130, 130, 130, 130, - 130, 130, 130, 130, 130, 130, 129, 134, 136, 36, - 130, 130, 130, 130, 130, 130, 130, 130, 130, 130, - 130, 130, 130, 130, 130, 130, 130, 130, 130, 129, - 130, 130, 130, 130, 130, 130, 130, 130, 130, 130, - 130, 130, 129, 130, 130, 130, 130, 130, 130, 130, - - 130, 130, 130, 130, 130, 130, 130, 130, 130, 130, - 130, 130, 130, 130, 130, 130, 130, 130, 130, 130, - 130, 130, 130, 130, 130, 130, 130, 130, 0, 129, - 129, 129, 129, 129, 129, 129 + 131, 1, 131, 132, 131, 131, 132, 133, 134, 132, + 10, 132, 10, 132, 10, 10, 10, 132, 132, 132, + 132, 132, 132, 132, 132, 131, 131, 133, 135, 136, + 134, 137, 131, 10, 10, 10, 132, 132, 132, 10, + 132, 132, 132, 132, 132, 132, 132, 132, 132, 132, + 132, 132, 132, 132, 132, 132, 132, 131, 136, 138, + 36, 132, 132, 132, 132, 132, 132, 132, 132, 132, + 132, 132, 132, 132, 132, 132, 132, 132, 132, 132, + 132, 131, 132, 132, 132, 132, 132, 132, 132, 132, + 132, 132, 132, 132, 131, 132, 132, 132, 132, 132, + + 132, 132, 132, 132, 132, 132, 132, 132, 132, 132, + 132, 132, 132, 132, 132, 132, 132, 132, 132, 132, + 132, 132, 132, 132, 132, 132, 132, 132, 132, 132, + 0, 131, 131, 131, 131, 131, 131, 131 } ; -static yyconst flex_uint16_t yy_nxt[240] = +static yyconst flex_uint16_t yy_nxt[242] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 4, 19, 20, 4, 4, 21, 22, 4, 23, 24, 4, 4, 4, 4, 4, 29, 29, - 25, 30, 32, 33, 34, 34, 34, 128, 35, 35, + 25, 30, 32, 33, 34, 34, 34, 130, 35, 35, 35, 35, 35, 45, 35, 35, 35, 35, 35, 35, - 35, 35, 35, 50, 127, 52, 35, 35, 35, 51, - 32, 33, 46, 47, 53, 126, 48, 38, 29, 29, - 125, 56, 124, 39, 35, 35, 35, 43, 59, 59, - 123, 25, 35, 35, 35, 122, 121, 120, 40, 35, - - 35, 35, 59, 59, 119, 79, 41, 118, 117, 42, - 60, 60, 60, 116, 60, 60, 115, 114, 113, 112, - 60, 60, 60, 60, 60, 60, 111, 110, 64, 28, - 28, 31, 31, 29, 29, 58, 58, 32, 32, 59, - 59, 109, 108, 107, 106, 105, 104, 103, 102, 101, - 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, - 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, - 80, 78, 77, 76, 75, 74, 73, 72, 71, 70, - 69, 68, 67, 66, 65, 63, 62, 61, 33, 57, - 26, 55, 54, 49, 44, 37, 36, 27, 26, 129, - - 3, 129, 129, 129, 129, 129, 129, 129, 129, 129, - 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, - 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, - 129, 129, 129, 129, 129, 129, 129, 129, 129 + 35, 35, 35, 50, 129, 52, 35, 35, 35, 51, + 55, 128, 46, 47, 53, 56, 48, 38, 29, 29, + 127, 57, 126, 39, 35, 35, 35, 43, 60, 60, + 125, 25, 32, 33, 35, 35, 35, 124, 40, 35, + + 35, 35, 60, 60, 123, 81, 41, 122, 121, 42, + 61, 61, 61, 120, 61, 61, 119, 118, 117, 116, + 61, 61, 61, 61, 61, 61, 115, 114, 65, 28, + 28, 31, 31, 29, 29, 59, 59, 32, 32, 60, + 60, 113, 112, 111, 110, 109, 108, 107, 106, 105, + 104, 103, 102, 101, 100, 99, 98, 97, 96, 95, + 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, + 84, 83, 82, 80, 79, 78, 77, 76, 75, 74, + 73, 72, 71, 70, 69, 68, 67, 66, 64, 63, + 62, 33, 58, 26, 54, 49, 44, 37, 36, 27, + + 26, 131, 3, 131, 131, 131, 131, 131, 131, 131, + 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, + 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, + 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, + 131 } ; -static yyconst flex_int16_t yy_chk[240] = +static yyconst flex_int16_t yy_chk[242] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 130, 8, 9, 9, 10, 10, 10, 126, 10, 10, + 132, 8, 9, 9, 10, 10, 10, 128, 10, 10, 13, 13, 13, 19, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 21, 124, 22, 17, 17, 17, 21, - 31, 31, 19, 19, 22, 123, 19, 15, 28, 28, - 122, 28, 121, 15, 16, 16, 16, 17, 30, 30, - 120, 30, 35, 35, 35, 118, 117, 116, 16, 40, - - 40, 40, 58, 58, 115, 58, 16, 114, 111, 16, - 36, 36, 36, 110, 36, 36, 109, 108, 107, 106, - 36, 36, 36, 36, 36, 36, 103, 102, 40, 131, - 131, 132, 132, 133, 133, 134, 134, 135, 135, 136, - 136, 101, 99, 98, 97, 96, 95, 94, 91, 90, - 89, 88, 87, 86, 85, 84, 83, 80, 79, 78, - 77, 73, 71, 70, 68, 65, 64, 63, 62, 61, - 59, 55, 54, 53, 52, 50, 49, 48, 47, 46, - 45, 44, 43, 42, 41, 39, 38, 37, 32, 29, - 26, 24, 23, 20, 18, 14, 11, 7, 5, 3, - - 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, - 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, - 129, 129, 129, 129, 129, 129, 129, 129, 129, 129, - 129, 129, 129, 129, 129, 129, 129, 129, 129 + 15, 15, 15, 21, 126, 22, 17, 17, 17, 21, + 24, 125, 19, 19, 22, 24, 19, 15, 28, 28, + 124, 28, 123, 15, 16, 16, 16, 17, 30, 30, + 122, 30, 31, 31, 35, 35, 35, 120, 16, 40, + + 40, 40, 59, 59, 119, 59, 16, 118, 117, 16, + 36, 36, 36, 116, 36, 36, 113, 112, 111, 110, + 36, 36, 36, 36, 36, 36, 109, 108, 40, 133, + 133, 134, 134, 135, 135, 136, 136, 137, 137, 138, + 138, 105, 104, 103, 101, 100, 99, 98, 97, 96, + 93, 92, 91, 90, 89, 88, 87, 86, 85, 82, + 81, 80, 78, 74, 72, 71, 69, 66, 65, 64, + 63, 62, 60, 56, 55, 54, 53, 52, 50, 49, + 48, 47, 46, 45, 44, 43, 42, 41, 39, 38, + 37, 32, 29, 26, 23, 20, 18, 14, 11, 7, + + 5, 3, 131, 131, 131, 131, 131, 131, 131, 131, + 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, + 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, + 131, 131, 131, 131, 131, 131, 131, 131, 131, 131, + 131 } ; static yy_state_type yy_last_accepting_state; @@ -630,7 +633,7 @@ extern int yywrap (void ); #endif #ifndef YY_NO_UNPUT - + static void yyunput (int c,char *buf_ptr ); #endif @@ -814,13 +817,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 130 ) + if ( yy_current_state >= 132 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 201 ); + while ( yy_base[yy_current_state] != 203 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -916,39 +919,39 @@ YY_RULE_SETUP YY_BREAK case 18: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=SPI; return(BUS);} YY_BREAK case 19: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 20: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 21: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 22: YY_RULE_SETUP -{return(INHERIT);} +{return(IOAPIC_IRQ);} YY_BREAK case 23: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(INHERIT);} YY_BREAK case 24: YY_RULE_SETUP -{return(END);} +{return(SUBSYSTEMID);} YY_BREAK case 25: YY_RULE_SETUP -{return(EQUALS);} +{return(END);} YY_BREAK case 26: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 27: YY_RULE_SETUP @@ -960,12 +963,11 @@ YY_RULE_SETUP YY_BREAK case 29: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 30: -/* rule 30 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 31: /* rule 31 can match eol */ @@ -973,11 +975,16 @@ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 32: +/* rule 32 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 33: YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} + YY_BREAK +case 34: +YY_RULE_SETUP ECHO; YY_BREAK case YY_STATE_EOF(INITIAL): @@ -1235,9 +1242,9 @@ static int yy_get_next_buffer (void) else ret_val = EOB_ACT_CONTINUE_SCAN; - if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ - int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); + yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); @@ -1272,7 +1279,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 130 ) + if ( yy_current_state >= 132 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; @@ -1300,11 +1307,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 130 ) + if ( yy_current_state >= 132 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; - yy_is_jam = (yy_current_state == 129); + yy_is_jam = (yy_current_state == 131); return yy_is_jam ? 0 : yy_current_state; } @@ -1654,7 +1661,7 @@ static void yyensure_buffer_stack (void) * scanner will even need a stack. We use 2 instead of 1 to avoid an * immediate realloc on the next call. */ - num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */ + num_to_alloc = 1; // After all that talk, this was set to 1 anyways... (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc (num_to_alloc * sizeof(struct yy_buffer_state*) ); @@ -1937,7 +1944,7 @@ int yylex_destroy (void) #ifndef yytext_ptr static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) { - + int i; for ( i = 0; i < n; ++i ) s1[i] = s2[i]; @@ -1962,7 +1969,7 @@ void *yyalloc (yy_size_t size ) void *yyrealloc (void * ptr, yy_size_t size ) { - + /* The cast to (char *) in the following accommodates both * implementations that use char* generic pointers, and those * that use void* generic pointers. It works with the latter diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 81ce72b..2bc6145 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -285,6 +285,11 @@ struct device *new_device(struct device *parent, struct device *busdev, case GENERIC: new_d->path = ".type=DEVICE_PATH_GENERIC,{.generic={ .id = 0x%x, .subid = 0x%x }}"; break; + + case SPI: + new_d->path = ".type=DEVICE_PATH_SPI,{.spi={ .cs = 0x%x }}"; + break; + } return new_d; } diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index e361508..4f4084f 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -38,6 +38,7 @@ cpu_cluster {yylval.number=CPU_CLUSTER; return(BUS);} cpu {yylval.number=CPU; return(BUS);} domain {yylval.number=DOMAIN; return(BUS);} generic {yylval.number=GENERIC; return(BUS);} +spi {yylval.number=SPI; return(BUS);} irq {yylval.number=IRQ; return(RESOURCE);} drq {yylval.number=DRQ; return(RESOURCE);} io {yylval.number=IO; return(RESOURCE);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index bca06a0..116f41f 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -149,7 +149,8 @@ extern int yydebug; IOAPIC_IRQ = 281, IOAPIC = 282, PCIINT = 283, - GENERIC = 284 + GENERIC = 284, + SPI = 285 }; #endif @@ -426,7 +427,7 @@ union yyalloc #define YYLAST 39 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 30 +#define YYNTOKENS 31 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 13 /* YYNRULES -- Number of rules. */ @@ -437,7 +438,7 @@ union yyalloc /* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 284 +#define YYMAXUTOK 285 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -474,7 +475,7 @@ static const yytype_uint8 yytranslate[] = 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29 + 25, 26, 27, 28, 29, 30 }; #if YYDEBUG @@ -496,8 +497,8 @@ static const char *const yytname[] = "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", - "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip", - "@2", "device", "@3", "resource", "registers", "subsystemid", + "SPI", "$accept", "devtree", "$@1", "chipchildren", "devicechildren", + "chip", "@2", "device", "@3", "resource", "registers", "subsystemid", "ioapic_irq", YY_NULLPTR }; #endif @@ -509,7 +510,8 @@ static const yytype_uint16 yytoknum[] = { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, - 275, 276, 277, 278, 279, 280, 281, 282, 283, 284 + 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, + 285 }; # endif @@ -583,19 +585,19 @@ static const yytype_int8 yycheck[] = symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 31, 32, 0, 3, 35, 12, 36, 33, 4, - 5, 9, 35, 37, 40, 7, 12, 23, 10, 6, - 12, 38, 34, 8, 9, 24, 26, 35, 37, 39, - 41, 42, 23, 23, 23, 10, 23, 28, 23, 25, + 0, 32, 33, 0, 3, 36, 12, 37, 34, 4, + 5, 9, 36, 38, 41, 7, 12, 23, 10, 6, + 12, 39, 35, 8, 9, 24, 26, 36, 38, 40, + 42, 43, 23, 23, 23, 10, 23, 28, 23, 25, 23 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 30, 32, 31, 33, 33, 33, 33, 34, 34, - 34, 34, 34, 34, 36, 35, 38, 37, 39, 40, - 41, 41, 42 + 0, 31, 33, 32, 34, 34, 34, 34, 35, 35, + 35, 35, 35, 35, 37, 36, 39, 38, 40, 41, + 42, 42, 43 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 9666b37..3c586f5 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -71,7 +71,8 @@ extern int yydebug; IOAPIC_IRQ = 281, IOAPIC = 282, PCIINT = 283, - GENERIC = 284 + GENERIC = 284, + SPI = 285 }; #endif diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index b1e37a8..7108e67 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -29,7 +29,7 @@ static struct device *cur_parent, *cur_bus; int number; } -%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC +%token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI %% devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; [View Less]

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Patch set updated for coreboot: soc/intel/skylake: Add GSPI controller get_config support
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18338 -gerrit commit 3863a0492e7117b89a6d438bb1e1216a61edf90e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Jan 8 13:39:08 2017 -0800 soc/intel/skylake: Add GSPI controller get_config support Provide implementation of get_config routine for GSPI controller on skylake platforms. BUG=chrome-os-partner:59832 BRANCH=… [View More]

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Patch set updated for coreboot: spi: Add function callback to get configuration of SPI bus
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18337 -gerrit commit d482a28c9c0e4430e2b8eb8a9749c5c9e44f2073 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sun Jan 8 13:32:30 2017 -0800 spi: Add function callback to get configuration of SPI bus Add a new callback to spi_ctrlr structure - get_config - to obtain configuration of SPI bus from the controller driver. Also, move common … [View More] config definitions from acpi_device.h to spi-generic.h BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/include/arch/acpi_device.h | 18 +------------- src/drivers/spi/spi-generic.c | 10 ++++++++ src/include/spi-generic.h | 42 +++++++++++++++++++++++++++++++++ 3 files changed, 53 insertions(+), 17 deletions(-) diff --git a/src/arch/x86/include/arch/acpi_device.h b/src/arch/x86/include/arch/acpi_device.h index 6e8f812..aba5c2d 100644 --- a/src/arch/x86/include/arch/acpi_device.h +++ b/src/arch/x86/include/arch/acpi_device.h @@ -18,6 +18,7 @@ #include <device/i2c.h> #include <stdint.h> +#include <spi-generic.h> #define ACPI_DESCRIPTOR_LARGE (1 << 7) #define ACPI_DESCRIPTOR_INTERRUPT (ACPI_DESCRIPTOR_LARGE | 9) @@ -216,23 +217,6 @@ void acpi_device_write_i2c(const struct acpi_i2c *i2c); * ACPI SPI Bus */ -enum spi_clock_phase { - SPI_CLOCK_PHASE_FIRST, - SPI_CLOCK_PHASE_SECOND -}; - -/* SPI Flags bit 0 */ -enum spi_wire_mode { - SPI_4_WIRE_MODE, - SPI_3_WIRE_MODE -}; - -/* SPI Flags bit 1 */ -enum spi_polarity { - SPI_POLARITY_LOW, - SPI_POLARITY_HIGH -}; - struct acpi_spi { /* Device selection */ uint16_t device_select; diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 805e17a..3ef437c 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -88,6 +88,16 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, return -1; } +int spi_get_config(const struct spi_slave *slave, struct spi_cfg *cfg) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + + if (ctrlr && ctrlr->get_config) + return ctrlr->get_config(slave, cfg); + + return -1; +} + void __attribute__((weak)) spi_init(void) { /* Default weak implementation - do nothing. */ diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 7eb18a6..cc3d3cf 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -59,9 +59,38 @@ struct spi_op { enum spi_op_status status; }; +enum spi_clock_phase { + SPI_CLOCK_PHASE_FIRST, + SPI_CLOCK_PHASE_SECOND +}; + +enum spi_wire_mode { + SPI_4_WIRE_MODE, + SPI_3_WIRE_MODE +}; + +enum spi_polarity { + SPI_POLARITY_LOW, + SPI_POLARITY_HIGH +}; + +struct spi_cfg { + /* CLK phase - 0: Phase first, 1: Phase second */ + enum spi_clock_phase clk_phase; + /* CLK polarity - 0: Low, 1: High */ + enum spi_polarity clk_polarity; + /* CS polarity - 0: Low, 1: High */ + enum spi_polarity cs_polarity; + /* Wire mode - 0: 4-wire, 1: 3-wire */ + enum spi_wire_mode wire_mode; + /* Data bit length. */ + unsigned int data_bit_length; +}; + /*----------------------------------------------------------------------- * Representation of a SPI contoller. * + * get_config: Get configuration of SPI bus * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. * setup: Setup given SPI device bus. @@ -69,6 +98,8 @@ struct spi_op { * xfer_vector: Vector of SPI transfer operations. */ struct spi_ctrlr { + int (*get_config)(const struct spi_slave *slave, + struct spi_cfg *cfg); int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); int (*setup)(const struct spi_slave *slave); @@ -101,6 +132,17 @@ extern const size_t spi_ctrlr_bus_map_count; */ void spi_init(void); +/* + * Get configuration of SPI bus. + * + * slave: Pointer to slave structure. + * cfg: Pointer to SPI configuration that needs to be filled. + * + * Returns: + * 0 on success, -1 on error + */ +int spi_get_config(const struct spi_slave *slave, struct spi_cfg *cfg); + /*----------------------------------------------------------------------- * Set up communications parameters for a SPI slave. * [View Less]

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New patch to review for coreboot: mainboard/google/eve: Generate fingerprint device using SPI SSDT generator
by Furquan Shaikh 12 Feb '17

12 Feb '17

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18343 -gerrit commit b77623ace2806416a3d0ebe4214028ddf5d72500 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Sat Feb 11 12:02:40 2017 -0800 mainboard/google/eve: Generate fingerprint device using SPI SSDT generator Use the newly added SPI SSDT generator for adding fingerprint device. BUG=chrome-os-partner:59832 BRANCH=None … [View More] TEST=Compiles successfully. Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/eve/Kconfig | 1 + src/mainboard/google/eve/acpi/mainboard.asl | 49 ----------------------------- src/mainboard/google/eve/devicetree.cb | 11 ++++++- src/mainboard/google/eve/dsdt.asl | 3 -- 4 files changed, 11 insertions(+), 53 deletions(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index e83e7d9..1a4a4c5 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/eve/acpi/mainboard.asl b/src/mainboard/google/eve/acpi/mainboard.asl deleted file mode 100644 index a55308f..0000000 --- a/src/mainboard/google/eve/acpi/mainboard.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Scope (\_SB.PCI0.SPI1) -{ - Device (FPC) - { - Name (_HID, "PRP0001") - Name (_UID, 1) - Name (_CRS, ResourceTemplate () - { - SpiSerialBus ( - 0, // DeviceSelection (CS0) - PolarityLow, // DeviceSelectionPolarity - FourWireMode, // WireMode - 8, // DataBitLength - ControllerInitiated, // SlaveMode - 1000000, // ConnectionSpeed (1MHz) - ClockPolarityLow, // ClockPolarity - ClockPhaseFirst, // ClockPhase - "\\_SB.PCI0.SPI1", // ResourceSource - 0, // ResourceSourceIndex - ResourceConsumer, // ResourceUsage - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) { 0x50 } - }) - Name (_DSD, Package () { - ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), - Package () { - Package () { - "compatible", - Package () { "fpc,fpc1020" } - }, - } - }) - } -} diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index d619d60..c8d8175 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -256,7 +256,16 @@ chip soc/intel/skylake device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 + device pci 1e.3 on + chip drivers/spi/acpi + register "hid" = ""PRP0001"" + register "uid" = "1" + register "speed" = "1000000" + register "compat_string" = ""fpc,fpc1020"" + register "irq" = "IRQ_EDGE_LOW(GPP_C8_IRQ)" + device spi 0 on end + end + end # GSPI #1 device pci 1e.4 on end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl index 22b92f3..2882d50 100644 --- a/src/mainboard/google/eve/dsdt.asl +++ b/src/mainboard/google/eve/dsdt.asl @@ -67,7 +67,4 @@ DefinitionBlock( { #include "acpi/dptf.asl" } - - /* ACPI code for EC functions */ - #include "acpi/mainboard.asl" } [View Less]

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coreboot-gerrit February 2017