coreboot-gerrit December 2017

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Change in coreboot[master]: nb/intel/x4x: Clarify the raminit memory mapping
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22328 ) Change subject: nb/intel/x4x: Clarify the raminit memory mapping ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19454/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64670/ : SUCCESS -- To view, visit https://review.coreboot.org/22328 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7 Gerrit-Change-Number: 22328 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 20:18:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Store the checksum in the decoded SPD struct
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21676 ) Change subject: device/dram/ddr2.c: Store the checksum in the decoded SPD struct ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19451/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64668/ : SUCCESS -- To view, visit https://review.coreboot.org/21676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53f4a3e4030ea19e10c0fe11a99a3480644f5fae Gerrit-Change-Number: 21676 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 20:17:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Fix programming CxDRB
by Arthur Heymans (Code Review) 16 Dec '17

16 Dec '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/22911 ) Change subject: nb/intel/x4x: Fix programming CxDRB ...................................................................... Patch Set 1: Doesn't seem to change anything, so just cleaning things up... -- To view, visit https://review.coreboot.org/22911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3 Gerrit-Change-Number: 22911 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Sat, 16 Dec 2017 20:08:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/rcven.c: Change the verbosity of some messages
by Arthur Heymans (Code Review) 16 Dec '17

16 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22912 Change subject: nb/intel/x4x/rcven.c: Change the verbosity of some messages ...................................................................... nb/intel/x4x/rcven.c: Change the verbosity of some messages Displaying the whole receive enable procedure should only be done if CONFIG_DEBUG_RAM_SETUP is selected. Change-Id: Ib568621e6d044624c1c0aeb6fb08945f561395c7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/rcven.c 1 file changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/22912/1 diff --git a/src/northbridge/intel/x4x/rcven.c b/src/northbridge/intel/x4x/rcven.c index 4cd48df..c2b5ad6 100644 --- a/src/northbridge/intel/x4x/rcven.c +++ b/src/northbridge/intel/x4x/rcven.c @@ -138,7 +138,7 @@ static int decr_coarse_low(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) { - printk(BIOS_DEBUG, + printk(RAM_DEBUG, " Decreasing coarse until high to low transition is found\n"); while (sampledqs(addr, lane, channel) != DQS_LOW) { if (timing->coarse == 0) { @@ -149,7 +149,7 @@ timing->coarse--; program_timing(timing, channel, lane); } - printk(BIOS_DEBUG, " DQS low at coarse=%d medium=%d\n", + printk(RAM_DEBUG, " DQS low at coarse=%d medium=%d\n", timing->coarse, timing->medium); return 0; } @@ -157,7 +157,7 @@ static int fine_search_dqs_high(u8 channel, u8 lane, u32 addr, struct rec_timing *timing) { - printk(BIOS_DEBUG, + printk(RAM_DEBUG, " Increasing TAP until low to high transition is found\n"); /* * We use a do while loop since it happens that the strobe read @@ -184,7 +184,7 @@ program_timing(timing, channel, lane); } while (sampledqs(addr, lane, channel) != DQS_HIGH); - printk(BIOS_DEBUG, " DQS high at coarse=%d medium=%d tap:%d\n", + printk(RAM_DEBUG, " DQS high at coarse=%d medium=%d tap:%d\n", timing->coarse, timing->medium, timing->tap); return 0; } @@ -193,7 +193,7 @@ struct rec_timing *timing) { /* Look for DQS low, using quarter steps. */ - printk(BIOS_DEBUG, " Increasing medium until DQS LOW is found\n"); + printk(RAM_DEBUG, " Increasing medium until DQS LOW is found\n"); while (sampledqs(addr, lane, channel) != DQS_LOW) { if (increase_medium(timing)) { printk(BIOS_CRIT, @@ -202,7 +202,7 @@ } program_timing(timing, channel, lane); } - printk(BIOS_DEBUG, " DQS low at coarse=%d medium=%d\n", + printk(RAM_DEBUG, " DQS low at coarse=%d medium=%d\n", timing->coarse, timing->medium); return 0; } @@ -210,7 +210,7 @@ struct rec_timing *timing) { /* Look for DQS high, using quarter steps. */ - printk(BIOS_DEBUG, " Increasing medium until DQS HIGH is found\n"); + printk(RAM_DEBUG, " Increasing medium until DQS HIGH is found\n"); while (sampledqs(addr, lane, channel) != DQS_HIGH) { if (increase_medium(timing)) { printk(BIOS_CRIT, @@ -219,7 +219,7 @@ } program_timing(timing, channel, lane); } - printk(BIOS_DEBUG, " DQS high at coarse=%d medium=%d\n", + printk(RAM_DEBUG, " DQS high at coarse=%d medium=%d\n", timing->coarse, timing->medium); return 0; } @@ -316,6 +316,8 @@ struct rec_timing timing[8]; u8 mincoarse; + printk(BIOS_DEBUG, "Starting DQS receiver enable calibration\n"); + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc; MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; -- To view, visit https://review.coreboot.org/22912 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib568621e6d044624c1c0aeb6fb08945f561395c7 Gerrit-Change-Number: 22912 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Fix programming CxDRB
by Arthur Heymans (Code Review) 16 Dec '17

16 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22911 Change subject: nb/intel/x4x: Fix programming CxDRB ...................................................................... nb/intel/x4x: Fix programming CxDRB Programming CxDRB should be cumulative as explain in "Intel ® 4 Series Chipset Family datasheet". This also removes some dead code. Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr2.c 1 file changed, 9 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/22911/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 807c5a7..f0c4743 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -48,24 +48,6 @@ return mhz[speed]; } -/* Find MSB bitfield location using bit scan reverse instruction */ -static u8 msbpos(u32 val) -{ - u32 pos; - - if (val == 0) { - printk(BIOS_WARNING, "WARNING: Input to BSR is zero\n"); - return 0; - } - - asm ("bsrl %1, %0" - : "=r"(pos) - : "r"(val) - ); - - return (u8)(pos & 0xff); -} - static void clkcross_ddr2(struct sysinfo *s) { u8 i, j; @@ -1251,19 +1233,18 @@ MCHBAR8(0x660) = MCHBAR8(0x660) | 1; // DRB - FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED - && (r) < s->dimms[ch<<1].ranks) - i = ch << 1; - else - i = (ch << 1) + 1; + FOR_EACH_RANK(ch, r) { if (ch == 0) { - dra0 = (c0dra >> (8*r)) & 0x7f; - c0drb = (u16)(c0drb + drbtab[dra0]); + if (RANK_IS_POPULATED(s->dimms, ch, r)) { + dra0 = (c0dra >> (8*r)) & 0x7f; + c0drb = (u16)(c0drb + drbtab[dra0]); + } MCHBAR16(0x200 + 2*r) = c0drb; } else { - dra1 = (c1dra >> (8*r)) & 0x7f; - c1drb = (u16)(c1drb + drbtab[dra1]); + if (RANK_IS_POPULATED(s->dimms, ch, r)) { + dra1 = (c1dra >> (8*r)) & 0x7f; + c1drb = (u16)(c1drb + drbtab[dra1]); + } MCHBAR16(0x600 + 2*r) = c1drb; } } @@ -1273,14 +1254,6 @@ totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); - - rankpop1 >>= 4; - if (rankpop1) { - MCHBAR16(0x600 + 2*msbpos(rankpop1)) = c0drb + c1drb; - MCHBAR16(0x602 + 2*msbpos(rankpop1)) = c0drb + c1drb; - MCHBAR16(0x604 + 2*msbpos(rankpop1)) = c0drb + c1drb; - MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; - } /* Populated channel sizes in MiB */ size0 = s->channel_capacity[0]; -- To view, visit https://review.coreboot.org/22911 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3 Gerrit-Change-Number: 22911 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/common: Automatically generate ACPI PIRQ
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22810 ) Change subject: sb/intel/common: Automatically generate ACPI PIRQ ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64666/ : SUCCESS -- To view, visit https://review.coreboot.org/22810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Gerrit-Change-Number: 22810 Gerrit-PatchSet: 6 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 15:25:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Use generated ACPI PIRQ
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22859 ) Change subject: intel/bd82x6x: Use generated ACPI PIRQ ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19450/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64667/ : SUCCESS -- To view, visit https://review.coreboot.org/22859 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Gerrit-Change-Number: 22859 Gerrit-PatchSet: 5 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 15:23:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Add RAM voltage hooks
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22806 ) Change subject: intel/sandybridge: Add RAM voltage hooks ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19448/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64664/ : SUCCESS -- To view, visit https://review.coreboot.org/22806 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817 Gerrit-Change-Number: 22806 Gerrit-PatchSet: 3 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 15:14:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/dcp847ske: Enable RAM voltage setting
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22836 ) Change subject: intel/dcp847ske: Enable RAM voltage setting ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19449/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64665/ : SUCCESS -- To view, visit https://review.coreboot.org/22836 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib0e2b4e90b5eda2da14834f4721649fd77ec1025 Gerrit-Change-Number: 22836 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 15:13:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/dcp847ske: Add superio ACPI declarations
by build bot (Jenkins) (Code Review) 16 Dec '17

16 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22835 ) Change subject: intel/dcp847ske: Add superio ACPI declarations ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19447/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64663/ : SUCCESS -- To view, visit https://review.coreboot.org/22835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123 Gerrit-Change-Number: 22835 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 16 Dec 2017 15:13:08 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017