coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

1 participants
1623 discussions

Change in coreboot[master]: src/soc/amd/stoneyridge: Replace AMD types with coreboot types.
by Richard Spiegel (Code Review) 01 Nov '17

01 Nov '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22288 Change subject: src/soc/amd/stoneyridge: Replace AMD types with coreboot types. ...................................................................... src/soc/amd/stoneyridge: Replace AMD types with coreboot types. AMD uses u8, u16 and u32 types, while coreboot comunity uses uint8_t, uint16_t and uint32_t. Replace the types in southbridge.h function prototypes and the actual functions declared by these prototypes. BUG=b:68007655 Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/early_setup.c M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 3 files changed, 39 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22288/1 diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index ecae7ab..fc61c6b 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -33,7 +33,7 @@ void configure_stoneyridge_uart(void) { - u8 byte, byte2; + uint8_t byte, byte2; if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) return; @@ -71,7 +71,7 @@ void sb_pci_port80(void) { - u8 byte; + uint8_t byte; pci_devfn_t dev; dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); @@ -83,7 +83,7 @@ void sb_lpc_port80(void) { - u8 byte; + uint8_t byte; pci_devfn_t dev; /* Enable LPC controller */ @@ -103,7 +103,7 @@ void sb_lpc_decode(void) { pci_devfn_t dev; - u32 tmp = 0; + uint32_t tmp = 0; /* Enable I/O decode to LPC bus */ dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); @@ -170,7 +170,7 @@ static void lpc_wideio_window(uint16_t base, uint16_t size) { pci_devfn_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - u32 tmp; + uint32_t tmp; /* Support 512 or 16 bytes per range */ assert(size == 512 || size == 16); @@ -210,7 +210,7 @@ lpc_wideio_window(base, 16); } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +int s3_save_nvram_early(uint32_t dword, int size, int nvram_pos) { int i; printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", @@ -225,9 +225,9 @@ return nvram_pos; } -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +int s3_load_nvram_early(int size, uint32_t *old_dword, int nvram_pos) { - u32 data = *old_dword; + uint32_t data = *old_dword; int i; for (i = 0; i < size; i++) { outb(nvram_pos, BIOSRAM_INDEX); @@ -243,7 +243,7 @@ void sb_clk_output_48Mhz(void) { - u32 ctrl; + uint32_t ctrl; /* * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so @@ -260,7 +260,7 @@ { /* Make sure the base address is predictable */ device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); - u32 base, enables; + uint32_t base, enables; base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); enables = base & 0xf; @@ -275,7 +275,7 @@ return (uintptr_t)base; } -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +void sb_set_spi100(uint16_t norm, uint16_t fast, uint16_t alt, uint16_t tpm) { uintptr_t base = sb_spibase(); write16((void *)base + SPI100_SPEED_CONFIG, @@ -294,7 +294,7 @@ & ~SPI_RD4DW_EN_HOST); } -void sb_set_readspeed(u16 norm, u16 fast) +void sb_set_readspeed(uint16_t norm, uint16_t fast) { uintptr_t base = sb_spibase(); write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) @@ -303,7 +303,7 @@ | (fast << SPI_FAST_SPEED_SH)); } -void sb_read_mode(u32 mode) +void sb_read_mode(uint32_t mode) { uintptr_t base = sb_spibase(); write32((void *)base + SPI_CNTRL0, @@ -315,7 +315,7 @@ { device_t dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); /* LPC device */ - u32 spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + uint32_t spibase = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); } @@ -331,7 +331,7 @@ */ void sb_enable_rom(void) { - u8 reg8; + uint8_t reg8; pci_devfn_t dev; dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 55ded9f..5302bc0 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify @@ -264,28 +264,28 @@ void sb_lpc_port80(void); void sb_lpc_decode(void); void sb_pci_port80(void); -void sb_read_mode(u32 mode); -void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); -void sb_set_readspeed(u16 norm, u16 fast); +void sb_read_mode(uint32_t mode); +void sb_set_spi100(uint16_t norm, uint16_t fast, uint16_t alt, uint16_t tpm); +void sb_set_readspeed(uint16_t norm, uint16_t fast); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); -u8 pm_read8(u8 reg); -u16 pm_read16(u8 reg); -u32 pm_read32(u8 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -void pm_write32(u8 reg, u32 value); -u8 smi_read8(u8 reg); -u16 smi_read16(u8 reg); -u32 smi_read32(u8 reg); -void smi_write8(u8 reg, u8 value); -void smi_write16(u8 reg, u16 value); -void smi_write32(u8 reg, u32 value); +uint8_t pm_read8(uint8_t reg); +uint16_t pm_read16(uint8_t reg); +uint32_t pm_read32(uint8_t reg); +void pm_write8(uint8_t reg, uint8_t value); +void pm_write16(uint8_t reg, uint16_t value); +void pm_write32(uint8_t reg, uint32_t value); +uint8_t smi_read8(uint8_t reg); +uint16_t smi_read16(uint8_t reg); +uint32_t smi_read32(uint8_t reg); +void smi_write8(uint8_t reg, uint8_t value); +void smi_write16(uint8_t reg, uint16_t value); +void smi_write32(uint8_t reg, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); +int s3_load_nvram_early(int size, uint32_t *old_dword, int nvram_pos); void s3_resume_init_data(void *FchParams); -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_save_nvram_early(uint32_t dword, int size, int nvram_pos); void bootblock_fch_early_init(void); #endif /* __STONEYRIDGE_H__ */ diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index ebf791d..707e9bd 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -15,32 +15,32 @@ #include <soc/southbridge.h> -void pm_write8(u8 reg, u8 value) +void pm_write8(uint8_t reg, uint8_t value) { write8((void *)(PM_MMIO_BASE + reg), value); } -u8 pm_read8(u8 reg) +uint8_t pm_read8(uint8_t reg) { return read8((void *)(PM_MMIO_BASE + reg)); } -void pm_write16(u8 reg, u16 value) +void pm_write16(uint8_t reg, uint16_t value) { write16((void *)(PM_MMIO_BASE + reg), value); } -u16 pm_read16(u8 reg) +uint16_t pm_read16(uint8_t reg) { return read16((void *)(PM_MMIO_BASE + reg)); } -void pm_write32(u8 reg, u32 value) +void pm_write32(uint8_t reg, uint32_t value) { write32((void *)(PM_MMIO_BASE + reg), value); } -u32 pm_read32(u8 reg) +uint32_t pm_read32(uint8_t reg) { return read32((void *)(PM_MMIO_BASE + reg)); } -- To view, visit https://review.coreboot.org/22288 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e Gerrit-Change-Number: 22288 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

1 0

Change in coreboot[master]: mb/google/poppy: enable 8254 Static Clock Gating for XTAL shutdown
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22240 ) Change subject: mb/google/poppy: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/62807/ : SUCCESS -- To view, visit https://review.coreboot.org/22240 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaa37f97b5395c637fde293f48cf4589e1fe8f3fa Gerrit-Change-Number: 22240 Gerrit-PatchSet: 3 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 19:57:34 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: intel/cannonlake_rvp: enable CNVi wifi
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22094 ) Change subject: intel/cannonlake_rvp: enable CNVi wifi ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62808/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/17802/ : SUCCESS -- To view, visit https://review.coreboot.org/22094 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff Gerrit-Change-Number: 22094 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 19:49:40 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: mainboard/google/zoombini: Provide memory configuration variant API
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22205 ) Change subject: mainboard/google/zoombini: Provide memory configuration variant API ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17792/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62797/ : SUCCESS -- To view, visit https://review.coreboot.org/22205 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad Gerrit-Change-Number: 22205 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 19:40:27 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: provide common LPDDR4 memory init
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22204 ) Change subject: soc/intel/cannonlake: provide common LPDDR4 memory init ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17791/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62796/ : SUCCESS -- To view, visit https://review.coreboot.org/22204 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Gerrit-Change-Number: 22204 Gerrit-PatchSet: 8 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maximilian Schander <maxschander(a)googlemail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 19:16:52 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/stoneyridge: Consolidate duplicate comment
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22243 ) Change subject: amd/stoneyridge: Consolidate duplicate comment ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17790/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62795/ : SUCCESS -- To view, visit https://review.coreboot.org/22243 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847 Gerrit-Change-Number: 22243 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 18:28:31 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Update coding style for i2c
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22278 ) Change subject: soc/intel/skylake: Update coding style for i2c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17789/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62794/ : SUCCESS -- To view, visit https://review.coreboot.org/22278 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c Gerrit-Change-Number: 22278 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 18:11:24 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Install common i2c
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22238 ) Change subject: soc/intel/cannonlake: Install common i2c ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17787/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62792/ : SUCCESS -- To view, visit https://review.coreboot.org/22238 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Gerrit-Change-Number: 22238 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 18:08:55 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Update coding style for i2c
by build bot (Jenkins) (Code Review) 01 Nov '17

01 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22278 ) Change subject: soc/intel/skylake: Update coding style for i2c ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62793/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/17788/ : SUCCESS -- To view, visit https://review.coreboot.org/22278 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c Gerrit-Change-Number: 22278 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Nov 2017 18:00:37 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Update coding style for i2c
by Lijian Zhao (Code Review) 01 Nov '17

01 Nov '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22278 Change subject: soc/intel/skylake: Update coding style for i2c ...................................................................... soc/intel/skylake: Update coding style for i2c >From comment from https://review.coreboot.org/#/c/22238/, the coding style need to be update. TEST=N/A Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/skylake/i2c.c 1 file changed, 24 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/22278/1 diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index dce83e7..55e23e0 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -43,12 +43,18 @@ int i2c_soc_devfn_to_bus(unsigned int devfn) { switch (devfn) { - case PCH_DEVFN_I2C0: return 0; - case PCH_DEVFN_I2C1: return 1; - case PCH_DEVFN_I2C2: return 2; - case PCH_DEVFN_I2C3: return 3; - case PCH_DEVFN_I2C4: return 4; - case PCH_DEVFN_I2C5: return 5; + case PCH_DEVFN_I2C0: + return 0; + case PCH_DEVFN_I2C1: + return 1; + case PCH_DEVFN_I2C2: + return 2; + case PCH_DEVFN_I2C3: + return 3; + case PCH_DEVFN_I2C4: + return 4; + case PCH_DEVFN_I2C5: + return 5; } return -1; } @@ -56,12 +62,18 @@ int i2c_soc_bus_to_devfn(unsigned int bus) { switch (bus) { - case 0: return PCH_DEVFN_I2C0; - case 1: return PCH_DEVFN_I2C1; - case 2: return PCH_DEVFN_I2C2; - case 3: return PCH_DEVFN_I2C3; - case 4: return PCH_DEVFN_I2C4; - case 5: return PCH_DEVFN_I2C5; + case 0: + return PCH_DEVFN_I2C0; + case 1: + return PCH_DEVFN_I2C1; + case 2: + return PCH_DEVFN_I2C2; + case 3: + return PCH_DEVFN_I2C3; + case 4: + return PCH_DEVFN_I2C4; + case 5: + return PCH_DEVFN_I2C5; } return -1; } -- To view, visit https://review.coreboot.org/22278 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c Gerrit-Change-Number: 22278 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2017