coreboot-gerrit November 2017

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Change in coreboot[master]: WIP soc/amd/stoneyridge: Add ELOG to SMM
by build bot (Jenkins) (Code Review) 09 Nov '17

09 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21728 ) Change subject: WIP soc/amd/stoneyridge: Add ELOG to SMM ...................................................................... Patch Set 16: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/63188/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/18129/ : SUCCESS -- To view, visit https://review.coreboot.org/21728 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I458babe1694f042215dd0e1c3277856e340de86f Gerrit-Change-Number: 21728 Gerrit-PatchSet: 16 Gerrit-Owner: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: John E. Kabat Jr. <john.kabat(a)scarletltd.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Nov 2017 16:16:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by build bot (Jenkins) (Code Review) 09 Nov '17

09 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 34: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18128/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63187/ : SUCCESS -- To view, visit https://review.coreboot.org/21774 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 34 Gerrit-Owner: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Nov 2017 15:08:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of common CSE code for skylake
by build bot (Jenkins) (Code Review) 09 Nov '17

09 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22395 ) Change subject: soc/intel/skylake: Make use of common CSE code for skylake ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18127/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63186/ : SUCCESS -- To view, visit https://review.coreboot.org/22395 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Gerrit-Change-Number: 22395 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 09 Nov 2017 09:57:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake
by build bot (Jenkins) (Code Review) 09 Nov '17

09 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22394 ) Change subject: soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18125/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63184/ : SUCCESS -- To view, visit https://review.coreboot.org/22394 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71 Gerrit-Change-Number: 22394 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Thu, 09 Nov 2017 09:54:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of common CSE code for skylake
by Subrata Banik (Code Review) 09 Nov '17

09 Nov '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22395 to look at the new patch set (#2). Change subject: soc/intel/skylake: Make use of common CSE code for skylake ...................................................................... soc/intel/skylake: Make use of common CSE code for skylake TEST=Ensures global reset could able to reset system. Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 4 files changed, 20 insertions(+), 395 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/22395/2 -- To view, visit https://review.coreboot.org/22395 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Gerrit-Change-Number: 22395 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Include HECI BAR0 address inside iomap.h
by build bot (Jenkins) (Code Review) 09 Nov '17

09 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22393 ) Change subject: soc/intel/apollolake: Include HECI BAR0 address inside iomap.h ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18124/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63183/ : SUCCESS -- To view, visit https://review.coreboot.org/22393 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6 Gerrit-Change-Number: 22393 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Nov 2017 09:47:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of common CSE code for skylake
by build bot (Jenkins) (Code Review) 09 Nov '17

09 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22395 ) Change subject: soc/intel/skylake: Make use of common CSE code for skylake ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/18126/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/63185/ : SUCCESS -- To view, visit https://review.coreboot.org/22395 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Gerrit-Change-Number: 22395 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 09 Nov 2017 09:45:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of common CSE code for skylake
by Subrata Banik (Code Review) 09 Nov '17

09 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22395 Change subject: soc/intel/skylake: Make use of common CSE code for skylake ...................................................................... soc/intel/skylake: Make use of common CSE code for skylake TEST=Ensures global reset could able to reset system. Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/me.c 3 files changed, 20 insertions(+), 319 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/22395/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f830f54..c4957ae 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -54,6 +54,7 @@ select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT + select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_EBDA select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index fdc88f5..34cfaa3 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include <chip.h> #include <device/device.h> #include <device/pci_def.h> +#include <intelblocks/cse.h> #include <intelblocks/fast_spi.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> @@ -157,27 +158,6 @@ outw(tcocnt, tcobase + TCO1_CNT); } -static void enable_heci(void) -{ - device_t dev = PCH_DEV_CSE; - u8 pcireg; - - /* Assign Resources to HECI1 */ - /* Clear BIT 1-2 of Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for HECI1 */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS); - pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - void pch_early_iorange_init(void) { /* IO Decode Range */ @@ -216,5 +196,6 @@ enable_rtc_upper_bank(); - enable_heci(); + /* initialize Heci interface */ + heci_init(HECI1_BASE_ADDRESS); } diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f4df831..9a6d9b0 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,18 +15,19 @@ #include <arch/io.h> #include <commonlib/helpers.h> +#include <compiler.h> #include <console/console.h> +#include <delay.h> #include <device/pci.h> #include <device/pci_def.h> #include <device/pci_ids.h> +#include <intelblocks/cse.h> +#include <soc/iomap.h> +#include <soc/me.h> +#include <soc/pci_devs.h> #include <stdint.h> -#include <compiler.h> #include <stdlib.h> #include <string.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/me.h> -#include <delay.h> #include <timer.h> static inline u32 me_read_config32(int offset) @@ -368,291 +369,6 @@ } } -/* -* Aligning a byte length to length in dwords. -*/ -static u32 get_dword_length(u32 byte_length) -{ - return ALIGN_UP(byte_length, sizeof(uint32_t)) / sizeof(uint32_t); -} - -/* -* Get remaining message count in dword from circular buffer based on -* write and read offset. -*/ -static u32 get_cb_msg_count(u32 data) -{ - u8 read_offset = data >> 8; - u8 write_offset = data >> 16; - - return get_dword_length(write_offset - read_offset); -} - -static int wait_heci_ready(void) -{ - struct stopwatch sw; - int timeout = 0; - union me_csr csr; - - stopwatch_init_msecs_expire(&sw, HECI_TIMEOUT); - while (1) { - do { - csr.data = me_read_mmio32(MMIO_ME_CSR); - if (csr.fields.host_ready) - return 0; - } while (!(timeout = stopwatch_expired(&sw))); - - printk(BIOS_ERR, "ME_RDY bit is not set after 15 sec"); - return -1; - } -} - -static int wait_heci_cb_avail(u32 len) -{ - struct stopwatch sw; - union host_csr csr; - - csr.data = me_read_mmio32(MMIO_HOST_CSR); - /* - * if timeout has happened, return failure as - * the circular buffer is not empty - */ - stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT); - /* Must have room for message and message header */ - while (len > (get_dword_length(csr.fields.me_cir_depth) - - get_cb_msg_count(csr.data))) { - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, - "Circular Buffer never emptied within 5 sec"); - return -1; - } - /* wait before trying again */ - udelay(HECI_DELAY); - /* read HOST_CSR for next iteration */ - csr.data = me_read_mmio32(MMIO_HOST_CSR); - } - return 0; -} - -static int send_heci_packet(union mei_header *head, u32 len, u32 *payload) -{ - int sts; - int index; - union me_csr csr; - union host_csr hcsr; - - /* - * wait until there is sufficient room in CB - */ - sts = wait_heci_cb_avail(len + 1); - if (sts != 0) - return -1; - - /* Write message header */ - me_write_mmio32(MMIO_ME_CB_WW, head->data); - - /* Write message body */ - for (index = 0; index < len; index++) - me_write_mmio32(MMIO_ME_CB_WW, payload[index]); - - /* Set Interrupt Generate bit */ - hcsr.data = me_read_mmio32(MMIO_HOST_CSR); - hcsr.fields.int_gen = 1; - me_write_mmio32(MMIO_HOST_CSR, hcsr.data); - - /* Check if ME Ready bit is set, if set to 0 then return fatal error */ - csr.data = me_read_mmio32(MMIO_ME_CSR); - if (csr.fields.host_ready) - return 0; - else - return -1; -} - -static int recv_heci_packet(union mei_header *head, u32 *packet, - u32 *packet_size) -{ - union me_csr csr; - union host_csr hcsr; - int rec_msg = 0; - struct stopwatch sw; - u32 length, index; - - /* Clear Interrupt Status bit */ - hcsr.data = me_read_mmio32(MMIO_HOST_CSR); - hcsr.fields.int_sts = 1; - me_write_mmio32(MMIO_HOST_CSR, hcsr.data); - - /* Check if circular buffer overflow - * if yes then return fatal error - */ - csr.data = me_read_mmio32(MMIO_ME_CSR); - if (get_cb_msg_count(csr.data) > - get_dword_length(csr.fields.me_cir_buff)) - return -1; - /* - * if timeout has happened, return failure as - * the circular buffer is not empty - */ - stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); - /* go until we got message pkt */ - do { - if (stopwatch_expired(&sw)) { - printk(BIOS_ERR, - "Circular Buffer not filled within 5 sec"); - *packet_size = 0; - return -1; - } - csr.data = me_read_mmio32(MMIO_ME_CSR); - /* Read one message from HECI buffer */ - if (get_cb_msg_count(csr.data) > 0) { - head->data = me_read_mmio32(MMIO_ME_CB_RW); - /* calculate the message length in dword */ - length = get_dword_length(head->fields.length); - if (head->fields.length == 0) { - *packet_size = 0; - goto SET_IG; - } - /* Make sure, we have enough space to catch all */ - if (head->fields.length <= *packet_size) { - csr.data = me_read_mmio32(MMIO_ME_CSR); - /* get complete message into circular buffer */ - while (length > get_cb_msg_count(csr.data)) { - udelay(HECI_DELAY); - csr.data = me_read_mmio32(MMIO_ME_CSR); - } - /* here is the message */ - for (index = 0; index < length; index++) - packet[index] = - me_read_mmio32(MMIO_ME_CB_RW); - - rec_msg = 1; - *packet_size = head->fields.length; - } else { - /* Too small buffer */ - *packet_size = 0; - return -1; - } - } - } while (!rec_msg); - - /* - * Check if ME Ready bit is set, if set to 0 then return fatal error - * because ME might have reset during transaction and we might have - * read a junk data from CB - */ - csr.data = me_read_mmio32(MMIO_ME_CSR); - if (!(csr.fields.host_ready)) - return -1; -SET_IG: - /* Set Interrupt Generate bit */ - hcsr.data = me_read_mmio32(MMIO_HOST_CSR); - hcsr.fields.int_gen = 1; - me_write_mmio32(MMIO_HOST_CSR, hcsr.data); - return 0; -} - -static int -send_heci_message(void *msg, int len, u8 hostaddress, u8 clientaddress) -{ - u8 retry; - int status = -1; - u32 cir_buff_depth; - union host_csr csr; - union mei_header head; - int cur = 0; - u32 slength, rlength; - - for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { - if (wait_heci_ready() != 0) - continue; - /* HECI is ready */ - csr.data = me_read_mmio32(MMIO_HOST_CSR); - cir_buff_depth = csr.fields.me_cir_depth; - head.fields.client_address = clientaddress; - head.fields.host_address = hostaddress; - while (len > cur) { - rlength = get_dword_length(len - cur); - /* - * Set the message complete bit if this is last packet - * in message needs to be "less than" to account for - * the header OR needs to be exact equal to CB depth - */ - if (rlength <= cir_buff_depth) - head.fields.is_complete = 1; - else - head.fields.is_complete = 0; - /* - * calculate length for message header - * header length = smaller of CB buffer or - * remaining message - */ - slength = ((cir_buff_depth <= rlength) - ? ((cir_buff_depth - 1) * 4) - : (len - cur)); - head.fields.length = slength; - head.fields.reserved = 0; - /* - * send the current packet - * (cur should be treated as index for message) - */ - status = send_heci_packet(&head, - get_dword_length(head.fields.length), msg); - if (status != 0) - break; - /* update the length information */ - cur += slength; - msg += cur; - } - if (!status) - break; - } - return status; -} - -static int -recv_heci_message(void *message, u32 *message_size) -{ - union mei_header head; - int cur = 0; - u8 retry; - int status = -1; - int msg_complete = 0; - u32 pkt_buff; - - for (retry = 0; retry < MAX_HECI_MESSAGE; retry++) { - if (wait_heci_ready() != 0) - continue; - /* HECI is ready */ - while ((cur < *message_size) && (msg_complete == 0)) { - pkt_buff = *message_size - cur; - status = recv_heci_packet(&head, message + (cur >> 2), - &pkt_buff); - if (status == -1) { - *message_size = 0; - break; - } - msg_complete = head.fields.is_complete; - if (pkt_buff == 0) { - /* if not in middle of msg and msg complete bit - * is set then this is a valid zero length msg - */ - if ((cur == 0) && (msg_complete == 1)) - status = 0; - else - status = -1; - *message_size = 0; - break; - } - cur += pkt_buff; - } - if (!status) { - *message_size = cur; - break; - } - } - return status; -} - static int send_heci_reset_message(void) { int status; @@ -672,20 +388,23 @@ } __packed; struct reset_message msg = { .cmd = MKHI_GLOBAL_RESET, + .group_id = 0, + .reserved = 0, + .result = 0, .req_origin = GR_ORIGIN_BIOS_POST, .reset_type = GLOBAL_RST_TYPE }; - u32 reply_size; + size_t reply_size; - status = send_heci_message(&msg, sizeof(msg), - BIOS_HOST_ADD, HECI_MKHI_ADD); - if (status != 0) + heci_reset(); + + status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADD, HECI_MKHI_ADD); + if (status != 1) return -1; reply_size = sizeof(reply); memset(&reply, 0, reply_size); - if (recv_heci_message(&reply, &reply_size) == -1) - return -1; + heci_receive(&reply, &reply_size); /* get reply result from HECI MSG */ if (reply.result != 0) { printk(BIOS_DEBUG, "%s: Exit with Failure\n", __func__); -- To view, visit https://review.coreboot.org/22395 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e Gerrit-Change-Number: 22395 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake
by Subrata Banik (Code Review) 09 Nov '17

09 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22394 Change subject: soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake ...................................................................... soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake This patch ensures Skylake/Kabylake soc can make use of common CSE code in order to perform global reset using HECI interface. TEST=Build and boot on soraka/eve/reef/cnl-rvp Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/22394/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 617684c..6e2468c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -14,6 +14,7 @@ */ #include <arch/early_variables.h> +#include <assert.h> #include <commonlib/helpers.h> #include <console/console.h> #include <delay.h> @@ -21,12 +22,10 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/cse.h> +#include <soc/iomap.h> #include <soc/pci_devs.h> #include <string.h> #include <timer.h> - -/* default window for early boot, must be at least 12 bytes in size */ -#define HECI1_BASE_ADDRESS 0xfed1a000 /* Wait up to 15 sec for HECI to get ready */ #define HECI_DELAY_READY (15 * 1000) @@ -108,15 +107,35 @@ cse->sec_bar = tempbar; } +/* Get HECI BAR 0 from PCI configuration space */ +static uint32_t get_cse_bar(void) +{ + uintptr_t bar; + + bar = pci_read_config32(PCH_DEV_CSE, PCI_BASE_ADDRESS_0); + assert(bar != 0); + /* + * Bits 31-12 are the base address as per EDS for SPI, + * Don't care about 0-11 bit + */ + return (bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + static uint32_t read_bar(uint32_t offset) { struct cse_device *cse = car_get_var_ptr(&g_cse); + /* Reach PCI config space to get BAR incase CAR global not available */ + if (!cse->sec_bar) + cse->sec_bar = get_cse_bar(); return read32((void *)(cse->sec_bar + offset)); } static void write_bar(uint32_t offset, uint32_t val) { struct cse_device *cse = car_get_var_ptr(&g_cse); + /* Reach PCI config space to get BAR incase CAR global not available */ + if (!cse->sec_bar) + cse->sec_bar = get_cse_bar(); return write32((void *)(cse->sec_bar + offset), val); } -- To view, visit https://review.coreboot.org/22394 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71 Gerrit-Change-Number: 22394 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Include HECI BAR0 address inside iomap.h
by Subrata Banik (Code Review) 09 Nov '17

09 Nov '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22393 Change subject: soc/intel/apollolake: Include HECI BAR0 address inside iomap.h ...................................................................... soc/intel/apollolake: Include HECI BAR0 address inside iomap.h This ensures HECI1_BASE_ADDRESS macro is coming from respective SoC dirctory and not hardcoded inside common cse code. As per firmware specification HECI1_BASE_ADDRESS might be different between different socs. Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/iomap.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/22393/1 diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index c3eb66b..d4cd095 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -44,6 +44,8 @@ #define SRAM_BASE_2 0xfe902000 #define SRAM_SIZE_2 (4 * KiB) +#define HECI1_BASE_ADDRESS 0xfed1a000 + /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 -- To view, visit https://review.coreboot.org/22393 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6 Gerrit-Change-Number: 22393 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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coreboot-gerrit November 2017