coreboot-gerrit October 2017

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Change in coreboot[master]: Stoney Ridge Platforms: Make AGESA callout tables common
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21849 ) Change subject: Stoney Ridge Platforms: Make AGESA callout tables common ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61466/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16596/ : SUCCESS -- To view, visit https://review.coreboot.org/21849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Gerrit-Change-Number: 21849 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:16:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Stoney Ridge Platforms: Make AGESA callout tables common
by Martin Roth (Code Review) 03 Oct '17

03 Oct '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/21849 Change subject: Stoney Ridge Platforms: Make AGESA callout tables common ...................................................................... Stoney Ridge Platforms: Make AGESA callout tables common There was no reason to have the AGESA callout tables in each mainboard, so move them to soc/amd/common. The fch_initenv and fch_initreset functions remain in the mainboard code. BUG=b:67209686 TEST=Build and boot on Kahlee Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/amd/gardenia/BiosCallOuts.c M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c M src/soc/amd/common/BiosCallOuts.h M src/soc/amd/common/def_callouts.c 6 files changed, 48 insertions(+), 86 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/21849/1 diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index c947b0c..d077ff7 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -43,7 +43,7 @@ memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC)); } -static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; @@ -82,37 +82,3 @@ return AGESA_SUCCESS; } - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - /* Required callouts */ - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_RUNFUNC_ON_ALL_APS, agesa_RunFcnOnAllAps }, - {AMD_LATE_RUN_AP_TASK, agesa_LateRunApTask }, - {AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl }, - {AGESA_WAIT_FOR_ALL_APS, agesa_WaitForAllApsFinished }, - {AGESA_IDLE_AN_AP, agesa_IdleAnAp }, - - /* Optional callouts */ - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - //AgesaHeapRebase - Hook ID? - {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopUnsupported }, - {AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopUnsupported }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }, - {AGESA_FCH_OEM_CALLOUT, fch_initenv }, - {AGESA_EXTERNAL_VOLTAGE_ADJUST, agesa_NoopUnsupported }, - {AGESA_GNB_PCIE_CLK_REQ, agesa_NoopUnsupported }, - - /* Deprecated */ - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopUnsupported}, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - -}; - -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c index 1b7a341..d0dfbf4 100644 --- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c @@ -45,7 +45,7 @@ {-1} }; -static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; @@ -61,10 +61,3 @@ return AGESA_SUCCESS; } - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_FCH_OEM_CALLOUT, fch_initreset }, - {AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl } -}; - -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index 2e57166..681946f 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -21,7 +21,7 @@ extern const GPIO_CONTROL oem_kahlee_gpio[]; -static AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; @@ -63,37 +63,3 @@ return AGESA_SUCCESS; } - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - /* Required callouts */ - {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, - {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, - {AGESA_DO_RESET, agesa_Reset }, - {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, - {AGESA_READ_SPD, agesa_ReadSpd }, - {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_RUNFUNC_ON_ALL_APS, agesa_RunFcnOnAllAps }, - {AMD_LATE_RUN_AP_TASK, agesa_LateRunApTask }, - {AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl }, - {AGESA_WAIT_FOR_ALL_APS, agesa_WaitForAllApsFinished }, - {AGESA_IDLE_AN_AP, agesa_IdleAnAp }, - - /* Optional callouts */ - {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - //AgesaHeapRebase - Hook ID? - {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopUnsupported }, - {AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopUnsupported }, - {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }, - {AGESA_FCH_OEM_CALLOUT, fch_initenv }, - {AGESA_EXTERNAL_VOLTAGE_ADJUST, agesa_NoopUnsupported }, - {AGESA_GNB_PCIE_CLK_REQ, agesa_NoopUnsupported }, - - /* Deprecated */ - {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopUnsupported}, - {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - -}; - -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c index 4dce042..a86a0e8 100644 --- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c @@ -21,7 +21,7 @@ extern const GPIO_CONTROL oem_kahlee_gpio[]; -static AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr) { AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; @@ -37,10 +37,3 @@ return AGESA_SUCCESS; } - -const BIOS_CALLOUT_STRUCT BiosCallouts[] = { - {AGESA_FCH_OEM_CALLOUT, fch_initreset }, - {AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl } -}; - -const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h index c2c5556..846977c 100644 --- a/src/soc/amd/common/BiosCallOuts.h +++ b/src/soc/amd/common/BiosCallOuts.h @@ -60,6 +60,9 @@ AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr); +AGESA_STATUS fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr); +AGESA_STATUS fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr); + typedef struct { UINT32 CalloutName; CALLOUT_ENTRY CalloutPtr; diff --git a/src/soc/amd/common/def_callouts.c b/src/soc/amd/common/def_callouts.c index 4b71d5b..ec16f3d 100644 --- a/src/soc/amd/common/def_callouts.c +++ b/src/soc/amd/common/def_callouts.c @@ -25,6 +25,47 @@ #include <dimmSpd.h> #include <soc/southbridge.h> +#ifdef __BOOTBLOCK__ +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { + {AGESA_FCH_OEM_CALLOUT, fch_initreset }, + {AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl } +}; +#else +const BIOS_CALLOUT_STRUCT BiosCallouts[] = { + /* Required callouts */ + {AGESA_ALLOCATE_BUFFER, agesa_AllocateBuffer }, + {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, + {AGESA_DO_RESET, agesa_Reset }, + {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, + {AGESA_READ_SPD, agesa_ReadSpd }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, + {AGESA_RUNFUNC_ON_ALL_APS, agesa_RunFcnOnAllAps }, + {AMD_LATE_RUN_AP_TASK, agesa_LateRunApTask }, + {AGESA_GNB_PCIE_SLOT_RESET, agesa_PcieSlotResetControl }, + {AGESA_WAIT_FOR_ALL_APS, agesa_WaitForAllApsFinished }, + {AGESA_IDLE_AN_AP, agesa_IdleAnAp }, + + /* Optional callouts */ + {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, + //AgesaHeapRebase - Hook ID? + {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopUnsupported }, + {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopUnsupported }, + {AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE, agesa_NoopUnsupported }, + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopUnsupported }, + {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage }, + {AGESA_FCH_OEM_CALLOUT, fch_initenv }, + {AGESA_EXTERNAL_VOLTAGE_ADJUST, agesa_NoopUnsupported }, + {AGESA_GNB_PCIE_CLK_REQ, agesa_NoopUnsupported }, + + /* Deprecated */ + {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopUnsupported}, + {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, + +}; +#endif + +const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); + AGESA_STATUS GetBiosCallout(UINT32 Func, UINTN Data, VOID *ConfigPtr) { UINTN i; -- To view, visit https://review.coreboot.org/21849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b Gerrit-Change-Number: 21849 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61465/ : SUCCESS -- To view, visit https://review.coreboot.org/21774 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 7 Gerrit-Owner: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 21:33:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61464/ : ABORTED -- To view, visit https://review.coreboot.org/21774 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 6 Gerrit-Owner: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <cp_public(a)posteo.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 21:26:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21685 ) Change subject: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61463/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16595/ : SUCCESS -- To view, visit https://review.coreboot.org/21685 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Gerrit-Change-Number: 21685 Gerrit-PatchSet: 10 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 21:21:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add northbridge dsdt table
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21756 ) Change subject: soc/intel/cannonlake: Add northbridge dsdt table ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61462/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16594/ : SUCCESS -- To view, visit https://review.coreboot.org/21756 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I382d87da087ae7828eaa7ff28bc9597a332ca5bc Gerrit-Change-Number: 21756 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 20:56:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21685 ) Change subject: soc/intel/cannonlake: add initial ASL methods for SCS, GPIO ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61461/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16593/ : SUCCESS -- To view, visit https://review.coreboot.org/21685 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0dc31662dd3f5dbb3bda43aa8cf507128facde51 Gerrit-Change-Number: 21685 Gerrit-PatchSet: 9 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 20:50:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Refactor SMI handler
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21746 ) Change subject: amd/stoneyridge: Refactor SMI handler ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61460/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16592/ : SUCCESS -- To view, visit https://review.coreboot.org/21746 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Gerrit-Change-Number: 21746 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 20:46:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: WIP amd/stoneridge: Enable SMI trap on SlpTyp
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21752 ) Change subject: WIP amd/stoneridge: Enable SMI trap on SlpTyp ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61459/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16591/ : SUCCESS -- To view, visit https://review.coreboot.org/21752 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229 Gerrit-Change-Number: 21752 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 20:40:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Change SMM setup functions
by build bot (Jenkins) (Code Review) 02 Oct '17

02 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21750 ) Change subject: amd/stoneyridge: Change SMM setup functions ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61457/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16589/ : SUCCESS -- To view, visit https://review.coreboot.org/21750 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Gerrit-Change-Number: 21750 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 20:37:21 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017