coreboot-gerrit October 2017

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Change in coreboot[master]: soc/amd/common: Expand UMA settings in agesawrapper
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21855 Change subject: soc/amd/common: Expand UMA settings in agesawrapper ...................................................................... soc/amd/common: Expand UMA settings in agesawrapper Use devicetree "register" values to set the UMA configuration that will be passed to AGESA. This reduces the number of overrides required in the mainboard directory. Note that any overrides currently in place are not affected. This patch also removes the implicit check of CONFIG_GFXUMA being defined. The symbol is a bool and is always defined. Change-Id: Ibea5bcdbb57744905e77353438c876e059168e05 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.c 1 file changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/21855/1 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index a269130..659797a 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -13,10 +13,13 @@ * GNU General Public License for more details. */ +#include <device/device.h> #include <AGESA.h> #include <cbfs.h> #include <cbmem.h> #include <delay.h> +#include <chip.h> +#include <soc/pci_devs.h> #include <cpu/x86/mtrr.h> #include <FchPlatform.h> #include <heapManager.h> @@ -114,6 +117,14 @@ AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_POST_PARAMS *PostParams; + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = dev_find_slot(0, GNB_DEVFN); + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SoC devicetree config\n"); + cfg = (struct soc_amd_stoneyridge_config *)NULL; + } else { + cfg = dev->chip_info; + } LibAmdMemFill (&AmdParamStruct, 0, @@ -130,10 +141,18 @@ AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow - // the compiler to flag the error if CONFIG_GFXUMA is not set. - PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE; - PostParams->MemConfig.UmaSize = 0; + if (cfg) { + PostParams->MemConfig.UmaMode = cfg->uma_mode; + PostParams->MemConfig.UmaVersion = cfg->uma_type; + if (cfg->uma_mode == UMAMODE_SPECIFIED) + PostParams->MemConfig.UmaSize = cfg->uma_size; + else + PostParams->MemConfig.UmaSize = 0; + } else { + /* In case of a BIOS error, only attempt to set UMA. */ + PostParams->MemConfig.UmaMode = IS_ENABLED(CONFIG_GFXUMA) ? + UMA_AUTO : UMA_NONE; + } PostParams->MemConfig.BottomIo = (UINT16) (CONFIG_BOTTOMIO_POSITION >> 24); -- To view, visit https://review.coreboot.org/21855 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibea5bcdbb57744905e77353438c876e059168e05 Gerrit-Change-Number: 21855 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/gardenia: Add defines in OemCustomize.c
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21854 Change subject: amd/gardenia: Add defines in OemCustomize.c ...................................................................... amd/gardenia: Add defines in OemCustomize.c Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/OemCustomize.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/21854/1 diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 8bd8e7c..b8b3fea 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,16 +13,20 @@ * GNU General Public License for more details. */ +#include <chip.h> #include <AGESA.h> #include <agesawrapper.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE +#define MB_DIMM_SLOTS 2 +#if MB_DIMM_SLOTS > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), -- To view, visit https://review.coreboot.org/21854 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b Gerrit-Change-Number: 21854 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: google/kahlee: Add defines in OemCustomize.c
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21853 Change subject: google/kahlee: Add defines in OemCustomize.c ...................................................................... google/kahlee: Add defines in OemCustomize.c Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max supported for the device. AGESA's DRAM procedures follow the BKDG and may vary depending on the number of slots on the motherboard. DIMM numbering and ordering is also affected by this value. Replace hardcoded integers with defined values for DIMM slots and number of channels. Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/OemCustomize.c 1 file changed, 8 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/21853/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 528c7b3..878e2b9 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,16 +13,20 @@ * GNU General Public License for more details. */ +#include <chip.h> #include <AGESA.h> #include <agesawrapper.h> #include <PlatformMemoryConfiguration.h> -#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE +#define MB_DIMM_SLOTS 1 +#if MB_DIMM_SLOTS > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), - NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), MOTHER_BOARD_LAYERS(LAYERS_6), MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), -- To view, visit https://review.coreboot.org/21853 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395 Gerrit-Change-Number: 21853 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Clarify SPD structure in chip.h
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21852 Change subject: amd/stoneyridge: Clarify SPD structure in chip.h ...................................................................... amd/stoneyridge: Clarify SPD structure in chip.h Add #define values and clarify the spdAddrLookup array. Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/chip.h 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/21852/1 diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 216a819..01127b0 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -18,6 +18,10 @@ #include <stdint.h> +#define MAX_NODES 1 +#define MAX_DRAM_CH 1 +#define MAX_DIMMS_PER_CH 2 + struct soc_amd_stoneyridge_config { u32 uma_mode; /* Do not enable UMA in the system. */ @@ -43,7 +47,8 @@ #define UMATYPE_NONLEGACY 1 /* Size in units of 64KB, N/A for none and auto */ u32 uma_size; - u8 spdAddrLookup[1][1][2]; + + u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; u32 ide0_enable : 1; u32 sata0_enable : 1; u32 boot_switch_sata_ide : 1; -- To view, visit https://review.coreboot.org/21852 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6 Gerrit-Change-Number: 21852 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/intel/skylake: Use common/block/gpio
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19201 ) Change subject: soc/intel/skylake: Use common/block/gpio ...................................................................... Patch Set 49: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61469/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16599/ : SUCCESS -- To view, visit https://review.coreboot.org/19201 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099 Gerrit-Change-Number: 19201 Gerrit-PatchSet: 49 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sowmya v <sowmyav235(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:31:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Remove 16MB cbmem assert
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21850 ) Change subject: amd/stoneyridge: Remove 16MB cbmem assert ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61468/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16598/ : SUCCESS -- To view, visit https://review.coreboot.org/21850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Gerrit-Change-Number: 21850 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:26:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Manage power state variable from common PMC b...
by Shaunak Saha (Code Review) 03 Oct '17

03 Oct '17

Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/21851 Change subject: soc/intel/common/block: Manage power state variable from common PMC block ...................................................................... soc/intel/common/block: Manage power state variable from common PMC block This patch helps managing power state variables from within the library. Adds migrate_power_state which migrates the chipset power state variable,reads global power variable and adds it in cbmem for future use. This also adds get_soc_power_state_values function which returns the power state variable from cbmem or global power state variable if cbmem is not populated yet. Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/21851/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index fe0a765..69b0a09 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -22,6 +22,13 @@ struct chipset_power_state; /* + * This function checks if cbmem is possibly online at the stage when + * its called. If variable is present in cbmem then fetch it from cbmem + * and return or else returns the global power state variable. + */ +struct chipset_power_state *get_soc_power_state_values(void); + +/* * This is implemented as weak function in common pmc lib. * Clears all power management related registers as the boot * flow is past the point of needing to maintain the values. diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 78b43e4..ae26696 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <arch/io.h> #include <cbmem.h> #include <console/console.h> @@ -20,9 +21,41 @@ #include <intelblocks/pmclib.h> #include <intelblocks/gpio.h> #include <soc/pm.h> +#include <string.h> #include <timer.h> #include <vboot/vboot_common.h> +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *get_soc_power_state_values(void) +{ + struct chipset_power_state *ptr; + + if (cbmem_possibly_online()) { + ptr = cbmem_find(CBMEM_ID_POWER_STATE); + if (ptr) + return ptr; + } + + return car_get_var_ptr(&power_state); +} + +static void migrate_power_state(int is_recovery) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) + static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) { -- To view, visit https://review.coreboot.org/21851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Gerrit-Change-Number: 21851 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com>

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Change in coreboot[master]: amd/stoneyridge: Remove 16MB cbmem assert
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21850 ) Change subject: amd/stoneyridge: Remove 16MB cbmem assert ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/61467/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/16597/ : SUCCESS -- To view, visit https://review.coreboot.org/21850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Gerrit-Change-Number: 21850 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:19:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Remove 16MB cbmem assert
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded a new patch set (#2). ( https://review.coreboot.org/21850 ) Change subject: amd/stoneyridge: Remove 16MB cbmem assert ...................................................................... amd/stoneyridge: Remove 16MB cbmem assert Do not check for the top of memory being 16MB-aligned near the end of romstage. This is not the expected alignment using the default 8MB SMM region size. BUG=b:67320715 Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/romstage.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21850/2 -- To view, visit https://review.coreboot.org/21850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Gerrit-Change-Number: 21850 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Remove 16MB cbmem assert
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21850 Change subject: amd/stoneyridge: Remove 16MB cbmem assert ...................................................................... amd/stoneyridge: Remove 16MB cbmem assert Do not check for the top of memory being 16MB-aligned near the end of romstage. This is not the expected alignment using the default 8MB SMM region size. BUG=b:67320715 Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21850/1 diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 8cd4d43..7b86a3d 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -88,8 +88,7 @@ * 16 megs under cbmem top which is a safe bet to cover ramstage. */ top_of_ram = (uintptr_t) cbmem_top(); - /* cbmem_top() needs to be at least 16 MiB aligned */ - assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); -- To view, visit https://review.coreboot.org/21850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6bf0b9141232dea1a3b02794fda7af08887df119 Gerrit-Change-Number: 21850 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit October 2017