coreboot-gerrit October 2017

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Change in coreboot[master]: google/kahlee: Use devicetree register values for UMA
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21335 ) Change subject: google/kahlee: Use devicetree register values for UMA ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61476/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16605/ : SUCCESS -- To view, visit https://review.coreboot.org/21335 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52 Gerrit-Change-Number: 21335 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:50:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add UMA settings to chip.h
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21334 ) Change subject: amd/stoneyridge: Add UMA settings to chip.h ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61475/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16604/ : SUCCESS -- To view, visit https://review.coreboot.org/21334 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Gerrit-Change-Number: 21334 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:48:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Check SMI command address before reading
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21744 ) Change subject: amd/stoneyridge: Check SMI command address before reading ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61474/ : SUCCESS -- To view, visit https://review.coreboot.org/21744 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Gerrit-Change-Number: 21744 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:46:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Move pm/smi_read/write functions to util file
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21759 ) Change subject: amd/stoneyridge: Move pm/smi_read/write functions to util file ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61473/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16603/ : SUCCESS -- To view, visit https://review.coreboot.org/21759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Gerrit-Change-Number: 21759 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:39:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21749 ) Change subject: amd/stoneyridge: Add pm_read32 and pm_write32 to southbridge ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61472/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16602/ : SUCCESS -- To view, visit https://review.coreboot.org/21749 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 Gerrit-Change-Number: 21749 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:37:26 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Manage power state variable from common PMC b...
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21851 ) Change subject: soc/intel/common/block: Manage power state variable from common PMC block ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61471/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16600/ : SUCCESS -- To view, visit https://review.coreboot.org/21851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68 Gerrit-Change-Number: 21851 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:35:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Move power button SMI functions to common PMC...
by build bot (Jenkins) (Code Review) 03 Oct '17

03 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21755 ) Change subject: soc/intel/common/block: Move power button SMI functions to common PMC block ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61470/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16601/ : SUCCESS -- To view, visit https://review.coreboot.org/21755 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a73a6348fc22367ee2e68bf2c31823ebfefc525 Gerrit-Change-Number: 21755 Gerrit-PatchSet: 3 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Oct 2017 22:33:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Move DRAM clear override to devicetree
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21858 Change subject: google/kahlee: Move DRAM clear override to devicetree ...................................................................... google/kahlee: Move DRAM clear override to devicetree Kahlee needs to keep its DRAM contents after a reset. Move this override out of the OemCustomize.c file to a devicetree register setting. Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/devicetree.cb 2 files changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/21858/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 50d504d..fcfde4a 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -36,9 +36,3 @@ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), PSO_END }; - -void OemPostParams(AMD_POST_PARAMS *PostParams) -{ - /* disable memory clear for pstore memory storage and boot time */ - PostParams->MemConfig.EnableMemClr = FALSE; -} diff --git a/src/mainboard/google/kahlee/devicetree.cb b/src/mainboard/google/kahlee/devicetree.cb index 0ed3336..9bb0b43 100644 --- a/src/mainboard/google/kahlee/devicetree.cb +++ b/src/mainboard/google/kahlee/devicetree.cb @@ -18,6 +18,7 @@ { { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 }" + register "dram_clear" = "DRAM_CONTENTS_KEEP" device cpu_cluster 0 on device lapic 10 on end -- To view, visit https://review.coreboot.org/21858 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d Gerrit-Change-Number: 21858 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd: Move DRAM structure loading to agesawrapper
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21857 Change subject: soc/amd: Move DRAM structure loading to agesawrapper ...................................................................... soc/amd: Move DRAM structure loading to agesawrapper Let the generic AGESA wrapper load the PlatformMemoryConfiguration pointer with a mainboard default. For more complex configurations the mainboard may still override any structure(s) in the list. Change-Id: I2bb6e188f17644c57099c0696bae613e5dd8d34f Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/OemCustomize.c M src/mainboard/google/kahlee/OemCustomize.c M src/soc/amd/common/agesawrapper.c 3 files changed, 8 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/21857/1 diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index b8b3fea..560ece8 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -23,7 +23,7 @@ #error "Too many DIMM sockets defined for the mainboard" #endif -static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { +const PSO_ENTRY mainboard_dram_defaults[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), @@ -36,9 +36,3 @@ 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), PSO_END }; - -void OemPostParams(AMD_POST_PARAMS *PostParams) -{ - PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; -} diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 878e2b9..50d504d 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -23,7 +23,7 @@ #error "Too many DIMM sockets defined for the mainboard" #endif -static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { +const PSO_ENTRY mainboard_dram_defaults[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, MB_DIMM_SLOTS), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), @@ -39,8 +39,6 @@ void OemPostParams(AMD_POST_PARAMS *PostParams) { - PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; /* disable memory clear for pstore memory storage and boot time */ PostParams->MemConfig.EnableMemClr = FALSE; } diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index 93f7eb4..95c20d7 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -24,11 +24,14 @@ #include <FchPlatform.h> #include <heapManager.h> #include <agesawrapper.h> +#include <PlatformMemoryConfiguration.h> #include <BiosCallOuts.h> void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} #define FILECODE UNASSIGNED_FILE_FILECODE + +extern const PSO_ENTRY mainboard_dram_defaults[]; #ifndef __PRE_RAM__ /* ACPI table pointers returned by AmdInitLate */ @@ -156,7 +159,9 @@ UMA_AUTO : UMA_NONE; } PostParams->MemConfig.BottomIo = (UINT16) - (CONFIG_BOTTOMIO_POSITION >> 24); + (CONFIG_BOTTOMIO_POSITION >> 24); + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)mainboard_dram_defaults; OemPostParams(PostParams); -- To view, visit https://review.coreboot.org/21857 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2bb6e188f17644c57099c0696bae613e5dd8d34f Gerrit-Change-Number: 21857 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/common: Add DRAM clear option to agesawrapper
by Marshall Dawson (Code Review) 03 Oct '17

03 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21856 Change subject: soc/amd/common: Add DRAM clear option to agesawrapper ...................................................................... soc/amd/common: Add DRAM clear option to agesawrapper AmdInitPost() can be instructed to clear DRAM after a reset or to preserve it. Expand agesawrapper.c to tell AGESA which action to take. Note that any overrides in place are not affected by this change. Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/agesawrapper.c M src/soc/amd/stoneyridge/chip.h 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/21856/1 diff --git a/src/soc/amd/common/agesawrapper.c b/src/soc/amd/common/agesawrapper.c index 659797a..93f7eb4 100644 --- a/src/soc/amd/common/agesawrapper.c +++ b/src/soc/amd/common/agesawrapper.c @@ -142,6 +142,8 @@ PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; if (cfg) { + PostParams->MemConfig.EnableMemClr = cfg->dram_clear; + PostParams->MemConfig.UmaMode = cfg->uma_mode; PostParams->MemConfig.UmaVersion = cfg->uma_type; if (cfg->uma_mode == UMAMODE_SPECIFIED) diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 01127b0..f73b252 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -49,6 +49,12 @@ u32 uma_size; u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; + u8 dram_clear; + /* Clear DRAM - must correspond to AGESA TRUE */ + #define DRAM_CONTENTS_CLEAR 1 + /* Do not clear DRAM - must correspond to AGESA FALSE */ + #define DRAM_CONTENTS_KEEP 0 + u32 ide0_enable : 1; u32 sata0_enable : 1; u32 boot_switch_sata_ide : 1; -- To view, visit https://review.coreboot.org/21856 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d Gerrit-Change-Number: 21856 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit October 2017