Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/22240
Change subject: md/google/poppy: enable 8254 Static Clock Gating for XTAL shutdown
......................................................................
md/google/poppy: enable 8254 Static Clock Gating for XTAL shutdown
8254 Static Clock Gating should be enabled for XTAL OSC shutdown
which has a power impact. And this patch should apply with
https://review.coreboot.org/c/22236.
BUG=None
BRANCH=None
TEST=Build for kabylake board with the clock_gate_8254 policy in
devicetree set to 1.
iotools mmio_read32 0xfdc43300 should return 0x1f
Change-Id: Iaa37f97b5395c637fde293f48cf4589e1fe8f3fa
Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com>
---
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22240/1
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 1c342a4..40f0f0f 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -60,6 +60,7 @@
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
+ register "clock_gate_8254" = "1" # CGE for 8254 PIT
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
--
To view, visit https://review.coreboot.org/22240
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Iaa37f97b5395c637fde293f48cf4589e1fe8f3fa
Gerrit-Change-Number: 22240
Gerrit-PatchSet: 1
Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>
Hello Rajneesh Bhardwaj, rushikesh s kadam, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22236
to look at the new patch set (#2).
Change subject: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown
......................................................................
soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown
8254 Static Clock Gating should be enabled for XTAL OSC shutdown
which has a power impact.
BUG=None
BRANCH=None
TEST=Build for kabylake board with the clock_gate_8254 policy in
devicetree set to 1.
iotools mmio_read32 0xfdc43300 should return 0x1f
Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8
Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com>
---
M src/soc/intel/skylake/chip.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22236/2
--
To view, visit https://review.coreboot.org/22236
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8
Gerrit-Change-Number: 22236
Gerrit-PatchSet: 2
Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com>