coreboot-gerrit October 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Install common i2c
by build bot (Jenkins) (Code Review) 30 Oct '17

30 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22238 ) Change subject: soc/intel/cannonlake: Install common i2c ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17685/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62680/ : SUCCESS -- To view, visit https://review.coreboot.org/22238 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Gerrit-Change-Number: 22238 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:28:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Install common i2c
by Lijian Zhao (Code Review) 30 Oct '17

30 Oct '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22238 Change subject: soc/intel/cannonlake: Install common i2c ...................................................................... soc/intel/cannonlake: Install common i2c Add common i2c support for cannonlake. TEST=N/A Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/i2c.c 4 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22238/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 5f24ab0..7c4918b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -52,6 +52,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_ITSS + select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_P2SB diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8dfff91..9c2e422 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -15,12 +15,14 @@ bootblock-y += bootblock/report_platform.c bootblock-y += gpio.c bootblock-y += gspi.c +bootblock-y += i2c.c bootblock-y += memmap.c bootblock-y += spi.c bootblock-$(CONFIG_UART_DEBUG) += uart.c romstage-y += gpio.c romstage-y += gspi.c +romstage-y += i2c.c romstage-y += memmap.c romstage-y += pmutil.c romstage-y += reset.c @@ -35,6 +37,7 @@ ramstage-y += graphics.c ramstage-y += gspi.c ramstage-y += gpio.c +ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += pmc.c @@ -60,6 +63,7 @@ postcar-$(CONFIG_UART_DEBUG) += uart.c verstage-y += gspi.c +verstage-y += i2c.c verstage-y += pmutil.c verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index dbe211d..e2a3000 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -19,11 +19,14 @@ #define _SOC_CHIP_H_ #include <intelblocks/gspi.h> +#include <intelblocks/lpss_i2c.h> #include <stdint.h> #include <soc/pch.h> #include <soc/serialio.h> #include <soc/usb.h> #include <soc/vr_config.h> + +#define CANNONLAKE_I2C_DEV_MAX 6 struct soc_intel_cannonlake_config { /* GSPI */ @@ -245,6 +248,9 @@ * PchSerialIoHidden */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + + /* I2C bus configuration */ + struct lpss_i2c_bus_config i2c[CANNONLAKE_I2C_DEV_MAX]; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c new file mode 100644 index 0000000..dcba483 --- /dev/null +++ b/src/soc/intel/cannonlake/i2c.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <intelblocks/lpss_i2c.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include "chip.h" + +const struct lpss_i2c_bus_config *i2c_get_soc_cfg(unsigned int bus, + const struct device *dev) +{ + const struct soc_intel_cannonlake_config *config; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + config = dev->chip_info; + + return &config->i2c[bus]; +} + +uintptr_t i2c_get_soc_early_base(unsigned int bus) +{ + return EARLY_I2C_BASE(bus); +} + +int i2c_soc_devfn_to_bus(unsigned int devfn) +{ + switch (devfn) { + case PCH_DEVFN_I2C0: return 0; + case PCH_DEVFN_I2C1: return 1; + case PCH_DEVFN_I2C2: return 2; + case PCH_DEVFN_I2C3: return 3; + case PCH_DEVFN_I2C4: return 4; + case PCH_DEVFN_I2C5: return 5; + } + return -1; +} + +int i2c_soc_bus_to_devfn(unsigned int bus) +{ + switch (bus) { + case 0: return PCH_DEVFN_I2C0; + case 1: return PCH_DEVFN_I2C1; + case 2: return PCH_DEVFN_I2C2; + case 3: return PCH_DEVFN_I2C3; + case 4: return PCH_DEVFN_I2C4; + case 5: return PCH_DEVFN_I2C5; + } + return -1; +} -- To view, visit https://review.coreboot.org/22238 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Gerrit-Change-Number: 22238 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: src/mainboard/intel/glkrvp: Lid switch support
by build bot (Jenkins) (Code Review) 30 Oct '17

30 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22117 ) Change subject: src/mainboard/intel/glkrvp: Lid switch support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17682/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62677/ : SUCCESS -- To view, visit https://review.coreboot.org/22117 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9 Gerrit-Change-Number: 22117 Gerrit-PatchSet: 1 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:15:39 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown
by build bot (Jenkins) (Code Review) 30 Oct '17

30 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22237 ) Change subject: soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17684/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62679/ : SUCCESS -- To view, visit https://review.coreboot.org/22237 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef Gerrit-Change-Number: 22237 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:03:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown
by Furquan Shaikh (Code Review) 30 Oct '17

30 Oct '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22236 ) Change subject: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/22236/1/src/soc/intel/skylake/chip.c File src/soc/intel/skylake/chip.c: https://review.coreboot.org/#/c/22236/1/src/soc/intel/skylake/chip.c@208 PS1, Line 208: / Tab instead of spaces. -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:03:25 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown
by build bot (Jenkins) (Code Review) 30 Oct '17

30 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22236 ) Change subject: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17683/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62678/ : SUCCESS -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:02:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown
by Furquan Shaikh (Code Review) 30 Oct '17

30 Oct '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22236 ) Change subject: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 1: Can you please split this change into two separate changes: one for soc/intel/skylake and other for mainboard/google/poppy? -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:00:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown
by Roy Mingi Park (Code Review) 30 Oct '17

30 Oct '17

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/22237 Change subject: soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown ...................................................................... soc/intel/skylake: Turnoff XTAL Disqualification for XTAL Shutdown 24MHz Crystal Shutdown Qualification bit (0x31Ch[22]) need to be '0' if system can enter S0ix with XTAL Shutdown. BUG=None BRANCH=None TEST=Build for kabylake board with XTAL Disqualification off in pmc.h And read 24MHz Crystal Shutdown Qualification bit (0x31Ch[22]) iotools mmio_read32 0xFE00031c should return '0' on BIT[22] Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/soc/intel/skylake/include/soc/pmc.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22237/1 diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index bd86f95..76bfdd5 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -97,5 +97,5 @@ #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 #define CIR31C 0x31c -#define XTALSDQDIS (1 << 22) +#define XTALSDQDIS (0 << 22) #endif -- To view, visit https://review.coreboot.org/22237 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef Gerrit-Change-Number: 22237 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>

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Change in coreboot[master]: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown
by Roy Mingi Park (Code Review) 30 Oct '17

30 Oct '17

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/22236 Change subject: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown 8254 Static Clock Gating should be enabled for XTAL OSC shutdown which has a power impact. BUG=None BRANCH=None TEST=Build for kabylake board with the clock_gate_8254 policy in devicetree set to 1. iotools mmio_read32 0xfdc43300 should return 0x1f Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/skylake/chip.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22236/1 diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 1c342a4..40f0f0f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -60,6 +60,7 @@ register "PmConfigSlpSusMinAssert" = "1" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" + register "clock_gate_8254" = "1" # CGE for 8254 PIT register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index dfa813a..7247b4a 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -204,6 +204,10 @@ params->SendVrMbxCmd = config->SendVrMbxCmd; soc_irq_settings(params); + + /* Enable CGE for 8254 PIT due to xtal requirement */ + params->Early8254ClockGatingEnable = config->clock_gate_8254; + } void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, @@ -808,6 +812,9 @@ fsp_display_upd_value("SendVrMbxCmd", 1, original->SendVrMbxCmd, params->SendVrMbxCmd); + fsp_display_upd_value("Early8254ClockGatingEnable", 1, + original->Early8254ClockGatingEnable, + params->Early8254ClockGatingEnable); } static void pci_set_subsystem(device_t dev, unsigned int vendor, -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>

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Change in coreboot[master]: intel/common/smbus: increase spd read performance
by build bot (Jenkins) (Code Review) 30 Oct '17

30 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22072 ) Change subject: intel/common/smbus: increase spd read performance ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17681/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62676/ : SUCCESS -- To view, visit https://review.coreboot.org/22072 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 Gerrit-Change-Number: 22072 Gerrit-PatchSet: 11 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 30 Oct 2017 23:50:41 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017