coreboot-gerrit October 2017

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Change in coreboot[master]: amd/stoneyridge: Remove duplicate LPC decode setup
by Marshall Dawson (Code Review) 31 Oct '17

31 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22246 Change subject: amd/stoneyridge: Remove duplicate LPC decode setup ...................................................................... amd/stoneyridge: Remove duplicate LPC decode setup Delete the LPC I/O decode configuration from fixme.c. This code is superseded by early_setup.c. Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/fixme.c 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/22246/1 diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c index d3f5f6c..60cc2d1 100644 --- a/src/soc/amd/stoneyridge/fixme.c +++ b/src/soc/amd/stoneyridge/fixme.c @@ -66,8 +66,6 @@ void amd_initmmio(void) { UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -78,11 +76,6 @@ (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader); - - /* For serial port */ - PciData = 0xff03ffd5; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, PCU_DEV, LPC_FUNC, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; -- To view, visit https://review.coreboot.org/22246 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571 Gerrit-Change-Number: 22246 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add pci_dev macros
by Marshall Dawson (Code Review) 31 Oct '17

31 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22245 Change subject: amd/stoneyridge: Add pci_dev macros ...................................................................... amd/stoneyridge: Add pci_dev macros Add #defines that will allow easy use of PCI devices across stages. Future work can convert soc/amd/stoneyridge to use these and clean up the DEV_D18F4 macro still in place. Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/pci_devs.h 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22245/1 diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index c02727b..723899b 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -19,107 +19,132 @@ #include <device/pci_def.h> #include <rules.h> +#if !defined(__SIMPLE_DEVICE__) +#include <device/device.h> +#define _SOC_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) +#else +#include <arch/io.h> +#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) +#endif + /* GNB Root Complex */ #define GNB_DEV 0x0 #define GNB_FUNC 0 #define GNB_DEVID 0x1576 #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) +#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC) /* IOMMU */ #define IOMMU_DEV 0x0 #define IOMMU_FUNC 2 #define IOMMU_DEVID 0x1577 #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) +#define SOC_IOMMU_DEV _SOC_DEV(IOMMU_DEV, IOMMU_FUNC) /* Internal Graphics */ #define GFX_DEV 0x1 #define GFX_FUNC 0 #define GFX_DEVID 098e4 /* subject to SKU/OPN variation */ #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) +#define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) /* HD Audio 0 */ #define HDA0_DEV 0x1 #define HDA0_FUNC 1 #define HDA0_DEVID 015b3 #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) +#define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) /* Host Bridge */ #define HOST_DEV 0x2 #define HOST_FUNC 0 #define HOST_DEVID 0x157b #define HOST_DEVFN PCI_DEVFN(HOST_DEV, HOST_FUNC) +#define SOC_HOST_DEV _SOC_DEV(HOST_DEV, HOST_FUNC) /* PCIe GPP Bridge 0 */ #define PCIE0_DEV 0x2 #define PCIE0_FUNC 1 #define PCIE0_DEVID 0x157c #define PCIE0_DEVFN PCI_DEVFN(PCIE0_DEV, PCIE0_FUNC) +#define SOC_PCIE0_DEV _SOC_DEV(PCIE0_DEV, PCIE0_FUNC) /* PCIe GPP Bridge 1 */ #define PCIE1_DEV 0x2 #define PCIE1_FUNC 2 #define PCIE1_DEVID 0x157c #define PCIE1_DEVFN PCI_DEVFN(PCIE1_DEV, PCIE1_FUNC) +#define SOC_PCIE1_DEV _SOC_DEV(PCIE1_DEV, PCIE1_FUNC) /* PCIe GPP Bridge 2 */ #define PCIE2_DEV 0x2 #define PCIE2_FUNC 3 #define PCIE2_DEVID 0x157c #define PCIE2_DEVFN PCI_DEVFN(PCIE2_DEV, PCIE2_FUNC) +#define SOC_PCIE2_DEV _SOC_DEV(PCIE2_DEV, PCIE2_FUNC) /* PCIe GPP Bridge 3 */ #define PCIE3_DEV 0x2 #define PCIE3_FUNC 4 #define PCIE3_DEVID 0x157c #define PCIE3_DEVFN PCI_DEVFN(PCIE3_DEV, PCIE3_FUNC) +#define SOC_PCIE3_DEV _SOC_DEV(PCIE3_DEV, PCIE3_FUNC) /* PCIe GPP Bridge 4 */ #define PCIE4_DEV 0x2 #define PCIE4_FUNC 5 #define PCIE4_DEVID 0x157c #define PCIE4_DEVFN PCI_DEVFN(PCIE4_DEV, PCIE4_FUNC) +#define SOC_PCIE4_DEV _SOC_DEV(PCIE4_DEV, PCIE4_FUNC) /* Platform Security Processor */ #define PSP_DEV 0x8 #define PSP_FUNC 0 #define PSP_DEVID 0x1578 #define PSP_DEVFN PCI_DEVFN(PSP_DEV, PSP_FUNC) +#define SOC_PSP_DEV _SOC_DEV(PSP_DEV, PSP_FUNC) /* HD Audio 1 */ #define HDA1_DEV 0x9 #define HDA1_FUNC 2 #define HDA1_DEVID 0x157a #define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) +#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) /* HT Configuration */ #define HT_DEV 0x18 #define HT_FUNC 0 #define HT_DEVID 0x15b0 #define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) +#define SOC_HT_DEV _SOC_DEV(HT_DEV, HT_FUNC) /* Address Maps */ #define ADDR_DEV 0x18 #define ADDR_FUNC 1 #define ADDR_DEVID 0x15b1 #define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) +#define SOC_ADDR_DEV _SOC_DEV(ADDR_DEV, ADDR_FUNC) /* DRAM Configuration */ #define DCT_DEV 0x18 #define DCT_FUNC 2 #define DCT_DEVID 0x15b2 #define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) +#define SOC_DCT_DEV _SOC_DEV(DCT_DEV, DCT_FUNC) /* Misc. Configuration */ #define MISC_DEV 0x18 #define MISC_FUNC 3 #define MISC_DEVID 0x15b3 #define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) +#define SOC_MISC_DEV _SOC_DEV(MISC_DEV, MISC_FUNC) /* PM Configuration */ #define PM_DEV 0x18 #define PM_FUNC 4 #define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) +#define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #define DEV_D18F4 dev_find_slot(0, PM_DEVFN) @@ -132,12 +157,14 @@ #define NB_FUNC 5 #define NB_DEVID 0x15b5 #define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) +#define SOC_NB_DEV _SOC_DEV(NB_DEV, NB_FUNC) /* XHCI */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0 #define XHCI_DEVID 0x7914 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV, XHCI_FUNC) +#define SOC_XHCI_DEV _SOC_DEV(XHCI_DEV, XHCI_FUNC) /* SATA */ #define SATA_DEV 0x11 @@ -146,29 +173,34 @@ #define AHCI_DEVID_MS 0x7901 #define AHCI_DEVID_AMD 0x7904 #define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) /* EHCI */ #define EHCI_DEV 0x12 #define EHCI_FUNC 0 #define EHCI_DEVID 0x7908 #define EHCI1_DEVFN PCI_DEVFN(EHCI_DEV, EHCI_FUNC) +#define SOC_EHCI1_DEV _SOC_DEV(EHCI_DEV, EHCI_FUNC) /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 #define SMBUS_DEVID 0x790b #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) +#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC) /* LPC BUS */ #define PCU_DEV 0x14 #define LPC_FUNC 3 #define LPC_DEVID 0x790e #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) /* SD Controller */ #define SD_DEV 0x14 #define SD_FUNC 7 #define SD_DEVID 0x7906 #define SD_DEVFN PCI_DEVFN(SD_DEV, SD_FUNC) +#define SOC_SD_DEV _SOC_DEV(SD_DEV, SD_FUNC) #endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */ -- To view, visit https://review.coreboot.org/22245 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7 Gerrit-Change-Number: 22245 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add definitions for various NB registers
by Marshall Dawson (Code Review) 31 Oct '17

31 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22244 Change subject: amd/stoneyridge: Add definitions for various NB registers ...................................................................... amd/stoneyridge: Add definitions for various NB registers Add #define values for the first MMIO base/limit, the first I/O base/limit, and VGA enable registers. Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/northbridge.h 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/22244/1 diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index 45c67c2..9113878 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -26,9 +26,20 @@ # define CPU_CNT_MASK 0x1f /* CpuCnt + 1 = no. CPUs */ /* D18F1 - Address Map Registers */ +#define D18F1_MMIO_BASE0_LO 0x80 +# define MMIO_WE (1 << 1) +# define MMIO_RE (1 << 0) +#define D18F1_MMIO_LIMIT0_LO 0x84 +# define MMIO_NP (1 << 7) +#define D18F1_IO_BASE0 0xc0 +# define IO_WE (1 << 1) +# define IO_RE (1 << 0) +#define D18F1_IO_LIMIT0 0xc4 #define D18F1_DRAM_HOLE 0xf0 # define DRAM_HOIST_VALID (1 << 1) # define DRAM_HOLE_VALID (1 << 0) +#define D18F1_VGAEN 0xf4 +# define VGA_ADDR_ENABLE (1 << 0) enum { /* SMM handler area. */ -- To view, visit https://review.coreboot.org/22244 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760 Gerrit-Change-Number: 22244 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Consolidate duplicate comment
by Marshall Dawson (Code Review) 31 Oct '17

31 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22243 Change subject: amd/stoneyridge: Consolidate duplicate comment ...................................................................... amd/stoneyridge: Consolidate duplicate comment Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22243/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 78a4038a..828513b 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -30,14 +30,13 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* Offsets from ACPI_MMIO_BASE */ -#define APU_SMI_BASE 0xfed80200 - /* * Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid * polluting the namespace. */ +#define APU_SMI_BASE 0xfed80200 + #define PM_MMIO_BASE 0xfed80300 #define APU_UART0_BASE 0xfedc6000 -- To view, visit https://review.coreboot.org/22243 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847 Gerrit-Change-Number: 22243 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Add denition for HPET to southbridge
by Marshall Dawson (Code Review) 31 Oct '17

31 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22242 Change subject: amd/stoneyridge: Add denition for HPET to southbridge ...................................................................... amd/stoneyridge: Add denition for HPET to southbridge Add #define values for the HPET device. In Stoney Ridge, the base address is fixed and cannot be relocated. Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/22242/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 55ded9f..78a4038a 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -25,6 +25,11 @@ #define IO_APIC2_ADDR 0xfec20000 +#if IS_ENABLED(CONFIG_HPET_ADDRESS_OVERRIDE) +#error HPET address override is not allowed and must be fixed at 0xfed00000 +#endif +#define HPET_BASE_ADDRESS 0xfed00000 + /* Offsets from ACPI_MMIO_BASE */ #define APU_SMI_BASE 0xfed80200 -- To view, visit https://review.coreboot.org/22242 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd Gerrit-Change-Number: 22242 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: cpu/amdfam15.h: Add definition for MMIO config MSR
by Marshall Dawson (Code Review) 31 Oct '17

31 Oct '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22241 Change subject: cpu/amdfam15.h: Add definition for MMIO config MSR ...................................................................... cpu/amdfam15.h: Add definition for MMIO config MSR Change-Id: Ide7f37e957964d8011438057e58c3d3a43829010 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/cpu/amd/amdfam15.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22241/1 diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h index 33aa863..008d5da 100644 --- a/src/include/cpu/amd/amdfam15.h +++ b/src/include/cpu/amd/amdfam15.h @@ -26,6 +26,10 @@ # define SMM_LOCK (1 << 0) #define NB_CFG_MSR 0xC001001f +#define MMIO_CONF_BASE 0xC0010058 +# define MMIO_BUS_RANGE_SHIFT 2 +# define MMIO_RANGE_EN (1 << 0) + #define PSTATE_0_MSR 0xC0010064 #define LS_CFG_MSR 0xC0011020 -- To view, visit https://review.coreboot.org/22241 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ide7f37e957964d8011438057e58c3d3a43829010 Gerrit-Change-Number: 22241 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mainboard/google/snappy: Update touchscreen device ACPI nodes
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22146 ) Change subject: mainboard/google/snappy: Update touchscreen device ACPI nodes ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17695/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62690/ : SUCCESS -- To view, visit https://review.coreboot.org/22146 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1915ff8207502b80ecba6b63ce2ce1b866faf4c4 Gerrit-Change-Number: 22146 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 01:09:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown
by Roy Mingi Park (Code Review) 31 Oct '17

31 Oct '17

Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/22236 ) Change subject: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 2: > Patch Set 1: > > Can you please split this change into two separate changes: > one for soc/intel/skylake and other for mainboard/google/poppy? Done -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 2 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:59:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown
by Roy Mingi Park (Code Review) 31 Oct '17

31 Oct '17

Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/22236 ) Change subject: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 2: Done > Patch Set 1: > > (1 comment) -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 2 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:59:09 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22236 ) Change subject: soc/intelskylake: enable 8254 Static Clock Gating for XTAL shutdown ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17692/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62687/ : SUCCESS -- To view, visit https://review.coreboot.org/22236 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8 Gerrit-Change-Number: 22236 Gerrit-PatchSet: 2 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 31 Oct 2017 00:59:03 +0000 Gerrit-HasComments: No

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coreboot-gerrit October 2017