Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16563
-gerrit
commit f947caccce236536026f75eaa3903feb5bf2c513
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Sep 9 12:16:11 2016 +0530
driver/intel/fsp2_0: Make FSP-M binary XIP
If FSP_M_XIP is selected, then relocate FSP-M binary
while adding it in CBFS so that it can be executed in place.
Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/drivers/intel/fsp2_0/Makefile.inc | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 79b57f6..3986fe6 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -44,6 +44,9 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
$(CONFIG_FSP_M_CBFS)-type := fsp
+ifeq ($(CONFIG_FSP_M_XIP),y)
+$(CONFIG_FSP_M_CBFS)-options := --xip
+endif
cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_S_CBFS)
$(CONFIG_FSP_S_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE))
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16509
-gerrit
commit 37e3e688a215fc4988b93cca7de561ffbf1eb6d9
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Sep 7 20:18:17 2016 +0530
arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.
To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.
Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/postcar_loader.c | 59 +++++++++++++++++++++++++++----------------
1 file changed, 37 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b5d8db0..d9719ff 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -59,29 +59,44 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type)
{
- size_t align;
-
- if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
- printk(BIOS_ERR, "No more variable MTRRs: %d\n",
- pcf->max_var_mttrs);
- return;
- }
-
- /* Determine address alignment by lowest bit set in address. */
- align = addr & (addr ^ (addr - 1));
-
- if (align < size) {
- printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n",
- addr, align, size);
- size = align;
+ /*
+ * Utilize additional MTRRs if the specified size is greater than the
+ * base address alignment.
+ */
+ while (size != 0) {
+ uint32_t addr_lsb;
+ uint32_t size_msb;
+ uint32_t mtrr_size;
+
+ if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
+ printk(BIOS_ERR, "No more variable MTRRs: %d\n",
+ pcf->max_var_mttrs);
+ return;
+ }
+
+ addr_lsb = fls(addr);
+ size_msb = fms(size);
+
+ /* All MTRR entries need to have their base aligned to the mask
+ * size. The maximum size is calculated by a function of the
+ * min base bit set and maximum size bit set. */
+ if (addr_lsb > size_msb)
+ mtrr_size = 1 << size_msb;
+ else
+ mtrr_size = 1 << addr_lsb;
+
+ printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %x)\n",
+ addr, addr + mtrr_size, mtrr_size);
+
+ stack_push(pcf, pcf->upper_mask);
+ stack_push(pcf, ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID);
+ stack_push(pcf, 0);
+ stack_push(pcf, addr | type);
+ pcf->num_var_mttrs++;
+
+ size -= mtrr_size;
+ addr += mtrr_size;
}
-
- /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */
- stack_push(pcf, pcf->upper_mask);
- stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID);
- stack_push(pcf, 0);
- stack_push(pcf, addr | type);
- pcf->num_var_mttrs++;
}
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16331
-gerrit
commit e62cfdecb2ce44a81f272f33c0a09e52a4cf9147
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Aug 26 21:08:50 2016 +0530
arch/x86: Always compile postcar library in romstage
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.
The final step of moving the used and max MTRRs on to stack
is moved to a new function, that can be used outside of
postcar phase.
Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/arch/x86/include/arch/cpu.h | 6 ++++++
src/arch/x86/postcar_loader.c | 18 ++++++++++++------
3 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9b16add..38a2a8c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -213,7 +213,7 @@ romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += memset.c
romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c
+romstage-y += postcar_loader.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 5c26bcf..faa2375 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -274,6 +274,12 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type);
/*
+ * Push used MTRR and Max MTRRs on to the stack
+ * and return pointer to stack top.
+ */
+void *postcar_commit_mtrrs(struct postcar_frame *pcf);
+
+/*
* Load and run a program that takes control of execution that
* tears down CAR and loads ramstage. The postcar_frame object
* indicates how to set up the frame. If caching is enabled at
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index cc1d460..b5d8db0 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -84,6 +84,17 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
pcf->num_var_mttrs++;
}
+void *postcar_commit_mtrrs(struct postcar_frame *pcf)
+{
+ /*
+ * Place the number of used variable MTRRs on stack then max number
+ * of variable MTRRs supported in the system.
+ */
+ stack_push(pcf, pcf->num_var_mttrs);
+ stack_push(pcf, pcf->max_var_mttrs);
+ return (void *) pcf->stack;
+}
+
void run_postcar_phase(struct postcar_frame *pcf)
{
struct prog prog =
@@ -93,12 +104,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
.prog = &prog,
};
- /*
- * Place the number of used variable MTRRs on stack then max number
- * of variable MTRRs supported in the system.
- */
- stack_push(pcf, pcf->num_var_mttrs);
- stack_push(pcf, pcf->max_var_mttrs);
+ postcar_commit_mtrrs(pcf);
if (prog_locate(&prog))
die("Failed to locate after CAR program.\n");
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301
-gerrit
commit b966e6c3114f997223b00ecba6a5023f1a25b529
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 13:38:19 2016 +0530
kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.
Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/mainboard/intel/kunimitsu/Makefile.inc | 4 ++++
src/mainboard/intel/kunimitsu/ramstage.c | 2 +-
src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index cafa12c..86be420 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -34,3 +34,7 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
+endif
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..44fb9cd 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
new file mode 100644
index 0000000..10bdd21
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* TODO: Read and copy SPD and fill up Rcomp and DQ param */
+}
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 62d6fd4..0a9cb0f 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
-romstage-y += spd.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16538
-gerrit
commit eb449ea11517eab86addf0e202075edb3f9052fe
Author: Naresh G Solanki <naresh.solanki(a)intel.com>
Date: Thu Sep 8 13:25:30 2016 +0530
driver/fsp2_0: Include stdint header file in api.h
'bool' type is reported undefined due to missing stdint.h inclusion,
Fix it by including the same.
Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
---
src/drivers/intel/fsp2_0/include/fsp/api.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
index b0436e8..553fc52 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/api.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -14,6 +14,7 @@
#define _FSP2_0_API_H_
#include <stddef.h>
+#include <stdint.h>
#include <fsp/soc_binding.h>
#define FSP_SUCCESS EFI_SUCCESS