Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16565
-gerrit
commit 02909c98ed2127e964d0eca98003c58d70fa24a4
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 14:50:34 2016 -0700
intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/mainboard/intel/amenia/smihandler.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mainboard/intel/amenia/smihandler.c b/src/mainboard/intel/amenia/smihandler.c
index 05d363f..eb5377b 100644
--- a/src/mainboard/intel/amenia/smihandler.c
+++ b/src/mainboard/intel/amenia/smihandler.c
@@ -22,9 +22,6 @@
void mainboard_smi_sleep(u8 slp_typ)
{
- if (slp_typ == ACPI_S3)
- enable_gpe(GPIO_TIER_1_SCI);
-
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);
the following patch was just integrated into master:
commit e6a5f608e197b9b31eb30b84bf3359123c1e58ac
Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com>
Date: Mon Aug 29 14:03:38 2016 -0700
soc/intel/apollolake: Add functions to calculate GPIO address
Provide iosf and GPIO functions for GPIO address
calculation.
BUG=chrome-os-partner:55877
Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar(a)intel.com>
Reviewed-on: https://review.coreboot.org/16349
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16349 for details.
-gerrit
the following patch was just integrated into master:
commit 6e4204a0d196615ebb19d6f03f2eff2307bd6380
Author: Philipp Deppenwiese <zaolin(a)das-labor.org>
Date: Thu Sep 8 22:35:48 2016 +0200
util/release: Add support for signed tags and releases
* Add gpg key command-line parameter for signing.
* Add username command-line parameter for secure ssh clone.
* Tag and releases are signed.
* Generates ascii amored signature files.
Change-Id: I41347a85145dd0389e3b69939497fb8543db4996
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
Reviewed-on: https://review.coreboot.org/16553
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16553 for details.
-gerrit
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16564
-gerrit
commit 63b39cac8364d442d4e286e1397b967186fc8020
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 11:43:03 2016 -0700
soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events(through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake. This patch adds a _PRW method to powerbutton asl code.
We can use the _PRW method of powerbutton. The reason of choosing
powerbutton is its the default wake source and does not need any
_PRW method defined and we cannot define more than one _PRW for
any other wake source.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/soc/intel/apollolake/acpi/gpio.asl | 5 +++++
src/soc/intel/apollolake/include/soc/gpio_defs.h | 6 ++++++
src/soc/intel/apollolake/include/soc/pm.h | 6 ------
3 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 03b8edd..ccf915e 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -141,6 +141,11 @@ scope (\_SB) {
Return(0xf)
}
}
+ Device (SLP)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_PRW, Package() { GPIO_TIER_1_SCI, 0x3 })
+ }
}
Scope(\_GPE)
diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h
index 70f86ca..6a7f21a 100644
--- a/src/soc/intel/apollolake/include/soc/gpio_defs.h
+++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h
@@ -40,6 +40,12 @@
#define GPIO_MAX_NUM_PER_GROUP 32
+/*
+ * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
+ * and/or an SCI or SMI#.
+ */
+#define GPIO_TIER_1_SCI 15
+
#define MISCCFG_GPE0_DW0_SHIFT 8
#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT)
#define MISCCFG_GPE0_DW1_SHIFT 12
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 3ee7403..2c12c8d 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -138,12 +138,6 @@
#define PCIE_GPE_EN (1 << 9)
#define SWGPE_EN (1 << 2)
-/*
- * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
- * and/or an SCI or SMI#.
- */
-#define GPIO_TIER_1_SCI (1 << 15)
-
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x1000
#define GEN_PMCON1 0x1020
the following patch was just integrated into master:
commit 55a54f662e2e793306dc7003afbcb82b49db0a8c
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Mon Sep 5 02:38:01 2016 +1000
mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.
Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/16496 for details.
-gerrit
the following patch was just integrated into master:
commit 305224f47ae67cd8f95c53504b5ecc502878c973
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sat Sep 3 10:45:33 2016 +0200
northbridge/intel/fsp_rangeley: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/fsp_rangeley.
Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16470
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16470 for details.
-gerrit