the following patch was just integrated into master:
commit d3b55c1bb514fcf2ffd04b09be4f0baa2c93ffbc
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sat Sep 3 10:45:33 2016 +0200
southbridge/intel/fsp_rangeley: transition away from device_t
Replace the use of the old device_t definition inside
southbridge/intel/fsp_rangeley.
Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16481 for details.
-gerrit
the following patch was just integrated into master:
commit 60a6e153b02bbd968695326a50481922927a1896
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sat Sep 3 10:45:33 2016 +0200
northbridge/intel/x4x: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/x4x.
Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16472
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16472 for details.
-gerrit
the following patch was just integrated into master:
commit 100471057916cbc2d03711cca8f27bf036cdb778
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sat Sep 3 10:45:33 2016 +0200
northbridge/intel/i5000: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/i5000.
Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16471 for details.
-gerrit
the following patch was just integrated into master:
commit 7ea0fe5cbf749be1400d7094f5ecc2487fcdf163
Author: Antonello Dettori <dev(a)dettori.io>
Date: Sat Sep 3 10:45:33 2016 +0200
northbridge/intel/e7505: transition away from device_t
Replace the use of the old device_t definition inside
northbridge/intel/e7505.
Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89
Signed-off-by: Antonello Dettori <dev(a)dettori.io>
Reviewed-on: https://review.coreboot.org/16469
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16469 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16567
-gerrit
commit e2a557bce38bf6981b92a06ef96cd47e3610a555
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Sep 8 17:53:41 2016 -0600
arch/acpi_ivrs.h: Update 8-byte IVRS entry values
I put in the decimal values for these instead of the hex values.
Instead of running them through a BCD converter, update them to use
the hex values.
Change-Id: I3fa46f055c3db113758f445f947446dd5834c126
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
src/arch/x86/include/arch/acpi_ivrs.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/arch/x86/include/arch/acpi_ivrs.h b/src/arch/x86/include/arch/acpi_ivrs.h
index 96e7350..4c28a4c 100644
--- a/src/arch/x86/include/arch/acpi_ivrs.h
+++ b/src/arch/x86/include/arch/acpi_ivrs.h
@@ -91,9 +91,9 @@
#define IVHD_DEV_4_BYTE_END_RANGE 0x04
#define IVHD_DEV_8_BYTE_ALIAS_SELECT 0x42
#define IVHD_DEV_8_BYTE_ALIAS_START_RANGE 0x43
-#define IVHD_DEV_8_BYTE_EXT_SELECT 0x70
-#define IVHD_DEV_8_BYTE_EXT_START_RANGE 0x71
-#define IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV 0x72
+#define IVHD_DEV_8_BYTE_EXT_SELECT 0x46
+#define IVHD_DEV_8_BYTE_EXT_START_RANGE 0x47
+#define IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV 0x48
#define IVHD_DEV_VARIABLE 0xF0
/* IVHD Device Table Entry (DTE) Settings */
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16564
-gerrit
commit 2d4220a62a4eec4fec5da7d773a103b18fbc4145
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 11:43:03 2016 -0700
soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events(through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/soc/intel/apollolake/acpi/gpio.asl | 13 +++++++++++++
src/soc/intel/apollolake/include/soc/pm.h | 6 ------
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 03b8edd..12ef27f 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -141,6 +141,19 @@ scope (\_SB) {
Return(0xf)
}
}
+
+ /*
+ * Sleep button device ASL code. We are using this device to
+ * add the _PRW method for a dummy wake event to kernel so that
+ * before going to sleep kernel does not clear bit 15 in ACPI
+ * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
+ */
+ Device (SLP)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
+ }
}
Scope(\_GPE)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 3ee7403..2c12c8d 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -138,12 +138,6 @@
#define PCIE_GPE_EN (1 << 9)
#define SWGPE_EN (1 << 2)
-/*
- * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
- * and/or an SCI or SMI#.
- */
-#define GPIO_TIER_1_SCI (1 << 15)
-
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x1000
#define GEN_PMCON1 0x1020
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16566
-gerrit
commit baac0784f77750770e3c4a4382d9c1b11a68585b
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 15:15:27 2016 -0700
google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/mainboard/google/reef/smihandler.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index dbf9162..fe4f8c4 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -38,9 +38,6 @@ void mainboard_smi_sleep(u8 slp_typ)
pads = variant_sleep_gpio_table(&num);
gpio_configure_pads(pads, num);
- if (slp_typ == ACPI_S3)
- enable_gpe(GPIO_TIER_1_SCI);
-
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
MAINBOARD_EC_S5_WAKE_EVENTS);