Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16551
-gerrit
commit 0761a63d05d778642fa118019fd69d5a2fab9ae1
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Thu Sep 8 22:21:54 2016 +0200
gm45/gma.c: use correct id string for fake VBT
The correct id string for gm45 is "$VBT CANTIGA ".
This can be found in the gm45 option rom:
"strings vbios.bin | grep VBT".
Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/northbridge/intel/gm45/gma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index efaa210..b191f6a 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -741,7 +741,7 @@ static void gma_func0_init(struct device *dev)
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
- "$VBT IRONLAKE-MOBILE");
+ "$VBT CANTIGA ");
}
}
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16530
-gerrit
commit aa3c033fbe33c2f44d318d9e08845f15c5f42e99
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Wed Sep 7 22:10:57 2016 +0200
i945/gma.c: generate fake VBT
This generates a fake VBT for the Intel i945 graphic device.
i945 supports both the mobile chipset 945gm (calistoga)
and the desktop chipset 945gc (lakeport),
which is why a VBT with a different id string
needs to be created for each target.
The VBT id string is obtained from the vbios blob in the following way:
"strings vbios.bin | grep VBT".
Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/northbridge/intel/i945/gma.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 17e0d70..20118b8 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -623,6 +623,15 @@ static void gma_func0_init(struct device *dev)
iobase, mmiobase, graphics_base);
if (err == 0)
gfx_set_init_done(1);
+ /* Linux relies on VBT for panel info. */
+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) {
+ generate_fake_intel_oprom(&conf->gfx, dev,
+ "$VBT CALISTOGA ");
+ }
+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) {
+ generate_fake_intel_oprom(&conf->gfx, dev,
+ "$VBT LAKEPORT-G ");
+ }
#endif
}
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16496
-gerrit
commit ceabae824561e546d103e71ec680c2d7294a0d5c
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Mon Sep 5 02:38:01 2016 +1000
mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridge
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.
Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
index c433387..bd80742 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -28,7 +28,6 @@ chip northbridge/intel/x4x # Northbridge
device pci 0.0 on # Host Bridge
subsystemid 0x1458 0x5000
end
- device pci 1.0 off end # PCI Bridge to Management Engine
device pci 2.0 on # Integrated graphics controller
subsystemid 0x1458 0xd000
end
Boon Tiong Teo (boon.tiong.teo(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16519
-gerrit
commit bd78bdba71439bdbfd2dac76fa4ef4d5b04972cb
Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
Date: Mon Sep 5 16:00:07 2016 +0800
superio: Add support for Nuvoton NCT6776
Change-Id: I546879285ad8336e81798d0fbdf94f72e1fa61a2
Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
---
src/superio/nuvoton/Makefile.inc | 1 +
src/superio/nuvoton/common/early_serial.c | 3 +
src/superio/nuvoton/nct6776/Kconfig | 23 +++++++
src/superio/nuvoton/nct6776/Makefile.inc | 18 ++++++
src/superio/nuvoton/nct6776/nct6776.h | 58 ++++++++++++++++++
src/superio/nuvoton/nct6776/superio.c | 99 +++++++++++++++++++++++++++++++
6 files changed, 202 insertions(+)
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index 94cc6b7..e2e178b 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -19,5 +19,6 @@ romstage-$(CONFIG_SUPERIO_NUVOTON_COMMON_ROMSTAGE) += common/early_serial.c
subdirs-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += wpcm450
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += nct5104d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += nct5572d
+subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += nct6776
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += nct6779d
subdirs-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += nct6791d
diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c
index fca5ed6..966b8e1 100644
--- a/src/superio/nuvoton/common/early_serial.c
+++ b/src/superio/nuvoton/common/early_serial.c
@@ -63,6 +63,9 @@ static void pnp_exit_conf_state(pnp_devfn_t dev)
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
+if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A))
+ /* Route GPIO8 pin group to COM A */
+ pnp_write_config(dev, 0x2a, 0x40);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig
new file mode 100644
index 0000000..cf0fe21
--- /dev/null
+++ b/src/superio/nuvoton/nct6776/Kconfig
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_NUVOTON_NCT6776
+ bool
+ select SUPERIO_NUVOTON_COMMON_ROMSTAGE
+
+config SUPERIO_NUVOTON_NCT6776_COM_A
+ bool
+ default n
diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc
new file mode 100644
index 0000000..13fe527
--- /dev/null
+++ b/src/superio/nuvoton/nct6776/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
+## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c
diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h
new file mode 100644
index 0000000..520401e
--- /dev/null
+++ b/src/superio/nuvoton/nct6776/nct6776.h
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Both NCT6776D and NCT6776F package variants are supported. */
+
+#ifndef SUPERIO_NUVOTON_NCT6776_H
+#define SUPERIO_NUVOTON_NCT6776_H
+
+/* Logical Device Numbers (LDN). */
+#define NCT6776_FDC 0x00 /* Floppy */
+#define NCT6776_PP 0x01 /* Parallel port */
+#define NCT6776_SP1 0x02 /* Com1 */
+#define NCT6776_SP2 0x03 /* Com2 & IR */
+#define NCT6776_KBC 0x05 /* PS/2 keyboard and mouse */
+#define NCT6776_CIR 0x06
+#define NCT6776_GPIO6789_V 0x07
+#define NCT6776_WDT1_GPIO01A_V 0x08
+#define NCT6776_GPIO1234567_V 0x09
+#define NCT6776_ACPI 0x0A
+#define NCT6776_HWM_FPLED 0x0B /* Hardware monitor & front LED */
+#define NCT6776_VID 0x0D
+#define NCT6776_CIRWKUP 0x0E /* CIR wakeup */
+#define NCT6776_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */
+#define NCT6776_SVID 0x14
+#define NCT6776_DSLP 0x16 /* Deep sleep */
+#define NCT6776_GPIOA_LDN 0x17
+
+/* virtual LDN for GPIO and WDT */
+#define NCT6776_WDT1 ((0 << 8) | NCT6776_WDT1_GPIO01A_V)
+
+#define NCT6776_GPIOBASE ((0 << 8) | NCT6776_WDT1_GPIO01A_V) //?
+
+#define NCT6776_GPIO0 ((1 << 8) | NCT6776_WDT1_GPIO01A_V)
+#define NCT6776_GPIO1 ((1 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO2 ((2 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO3 ((3 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO4 ((4 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO5 ((5 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO6 ((6 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO7 ((7 << 8) | NCT6776_GPIO1234567_V)
+#define NCT6776_GPIO8 ((0 << 8) | NCT6776_GPIO6789_V)
+#define NCT6776_GPIO9 ((1 << 8) | NCT6776_GPIO6789_V)
+#define NCT6776_GPIOA ((2 << 8) | NCT6776_WDT1_GPIO01A_V)
+
+#endif /* SUPERIO_NUVOTON_NCT6776_H */
diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c
new file mode 100644
index 0000000..85f52cf
--- /dev/null
+++ b/src/superio/nuvoton/nct6776/superio.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de>
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "nct6776.h"
+
+/* Both NCT6776D and NCT6776F package variants are supported. */
+
+static void nct6776_init(struct device *dev)
+{
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ /* TODO: Might potentially need code for HWM or FDC etc. */
+ case NCT6776_KBC:
+ pc_keyboard_init(NO_AUX_DEVICE);
+ break;
+ }
+}
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = nct6776_init,
+ .ops_pnp_mode = &pnp_conf_mode_8787_aa,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, NCT6776_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_SP1, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_SP2, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1,
+ {0x0fff, 0}, {0x0fff, 4}, },
+ { &ops, NCT6776_CIR, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_ACPI},
+ { &ops, NCT6776_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+ {0x0ffe, 0}, {0x0ffe, 4}, },
+ { &ops, NCT6776_VID},
+ { &ops, NCT6776_CIRWKUP, PNP_IO0 | PNP_IRQ0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_GPIO_PP_OD},
+ { &ops, NCT6776_SVID},
+ { &ops, NCT6776_DSLP},
+ { &ops, NCT6776_GPIOA_LDN},
+ { &ops, NCT6776_WDT1},
+ { &ops, NCT6776_GPIOBASE, PNP_IO0,
+ {0x0ff8, 0}, },
+ { &ops, NCT6776_GPIO0},
+ { &ops, NCT6776_GPIO1},
+ { &ops, NCT6776_GPIO2},
+ { &ops, NCT6776_GPIO3},
+ { &ops, NCT6776_GPIO4},
+ { &ops, NCT6776_GPIO5},
+ { &ops, NCT6776_GPIO6},
+ { &ops, NCT6776_GPIO7},
+ { &ops, NCT6776_GPIO8},
+ { &ops, NCT6776_GPIO9},
+ { &ops, NCT6776_GPIOA},
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct6776_ops = {
+ CHIP_NAME("NUVOTON NCT6776 Super I/O")
+ .enable_dev = enable_dev,
+};
Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16509
-gerrit
commit 400a395f6c52a67ce12139e62564ead7120735d8
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Sep 7 20:18:17 2016 +0530
arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.
To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.
Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/postcar_loader.c | 59 +++++++++++++++++++++++++++----------------
1 file changed, 37 insertions(+), 22 deletions(-)
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index b5d8db0..d9719ff 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -59,29 +59,44 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size)
void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type)
{
- size_t align;
-
- if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
- printk(BIOS_ERR, "No more variable MTRRs: %d\n",
- pcf->max_var_mttrs);
- return;
- }
-
- /* Determine address alignment by lowest bit set in address. */
- align = addr & (addr ^ (addr - 1));
-
- if (align < size) {
- printk(BIOS_ERR, "Address (%lx) alignment (%zx) < size (%zx)\n",
- addr, align, size);
- size = align;
+ /*
+ * Utilize additional MTRRs if the specified size is greater than the
+ * base address alignment.
+ */
+ while (size != 0) {
+ uint32_t addr_lsb;
+ uint32_t size_msb;
+ uint32_t mtrr_size;
+
+ if (pcf->num_var_mttrs >= pcf->max_var_mttrs) {
+ printk(BIOS_ERR, "No more variable MTRRs: %d\n",
+ pcf->max_var_mttrs);
+ return;
+ }
+
+ addr_lsb = fls(addr);
+ size_msb = fms(size);
+
+ /* All MTRR entries need to have their base aligned to the mask
+ * size. The maximum size is calculated by a function of the
+ * min base bit set and maximum size bit set. */
+ if (addr_lsb > size_msb)
+ mtrr_size = 1 << size_msb;
+ else
+ mtrr_size = 1 << addr_lsb;
+
+ printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %x)\n",
+ addr, addr + mtrr_size, mtrr_size);
+
+ stack_push(pcf, pcf->upper_mask);
+ stack_push(pcf, ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID);
+ stack_push(pcf, 0);
+ stack_push(pcf, addr | type);
+ pcf->num_var_mttrs++;
+
+ size -= mtrr_size;
+ addr += mtrr_size;
}
-
- /* Push MTRR mask then base -- upper 32-bits then lower 32-bits. */
- stack_push(pcf, pcf->upper_mask);
- stack_push(pcf, ~(size - 1) | MTRR_PHYS_MASK_VALID);
- stack_push(pcf, 0);
- stack_push(pcf, addr | type);
- pcf->num_var_mttrs++;
}
void *postcar_commit_mtrrs(struct postcar_frame *pcf)
Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16331
-gerrit
commit 50bd20d3c64d8095087581a842b627f572c1bc94
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Aug 26 21:08:50 2016 +0530
arch/x86: Always compile postcar library in romstage
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.
The final step of moving the used and max MTRRs on to stack
is moved to a new function, that can be used outside of
postcar phase.
Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/arch/x86/Makefile.inc | 2 +-
src/arch/x86/include/arch/cpu.h | 6 ++++++
src/arch/x86/postcar_loader.c | 18 ++++++++++++------
3 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 9b16add..38a2a8c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -213,7 +213,7 @@ romstage-y += memcpy.c
romstage-y += memmove.c
romstage-y += memset.c
romstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-romstage-$(CONFIG_POSTCAR_STAGE) += postcar_loader.c
+romstage-y += postcar_loader.c
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
ifneq ($(CONFIG_ROMCC),y)
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 5c26bcf..faa2375 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -274,6 +274,12 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
uintptr_t addr, size_t size, int type);
/*
+ * Push used MTRR and Max MTRRs on to the stack
+ * and return pointer to stack top.
+ */
+void *postcar_commit_mtrrs(struct postcar_frame *pcf);
+
+/*
* Load and run a program that takes control of execution that
* tears down CAR and loads ramstage. The postcar_frame object
* indicates how to set up the frame. If caching is enabled at
diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c
index cc1d460..b5d8db0 100644
--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -84,6 +84,17 @@ void postcar_frame_add_mtrr(struct postcar_frame *pcf,
pcf->num_var_mttrs++;
}
+void *postcar_commit_mtrrs(struct postcar_frame *pcf)
+{
+ /*
+ * Place the number of used variable MTRRs on stack then max number
+ * of variable MTRRs supported in the system.
+ */
+ stack_push(pcf, pcf->num_var_mttrs);
+ stack_push(pcf, pcf->max_var_mttrs);
+ return (void *) pcf->stack;
+}
+
void run_postcar_phase(struct postcar_frame *pcf)
{
struct prog prog =
@@ -93,12 +104,7 @@ void run_postcar_phase(struct postcar_frame *pcf)
.prog = &prog,
};
- /*
- * Place the number of used variable MTRRs on stack then max number
- * of variable MTRRs supported in the system.
- */
- stack_push(pcf, pcf->num_var_mttrs);
- stack_push(pcf, pcf->max_var_mttrs);
+ postcar_commit_mtrrs(pcf);
if (prog_locate(&prog))
die("Failed to locate after CAR program.\n");