the following patch was just integrated into master:
commit b59991949580f59dbf0907881c7ea70729262e9a
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 15:15:27 2016 -0700
google/reef: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16566 for details.
-gerrit
the following patch was just integrated into master:
commit 563de15b8a4aafad162352754975158222f8de6c
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 14:50:34 2016 -0700
intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com>
See https://review.coreboot.org/16565 for details.
-gerrit
the following patch was just integrated into master:
commit 16e9d459a09ae5833776e29926207d43d2fc9a02
Author: Naresh G Solanki <naresh.solanki(a)intel.com>
Date: Thu Sep 8 22:27:04 2016 +0530
driver/intel/fsp20: move lb_framebuffer function
move lb_framebuffer function in soc/intel/apollolake
to driver/intel/fsp20 so that fsp 2.0 bases soc's can
use common lb_framebuffer function.
Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Reviewed-on: https://review.coreboot.org/16549
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/16549 for details.
-gerrit
the following patch was just integrated into master:
commit 5ff7390fcd74fe1cd94d2507cf7c04b1c1eff620
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Wed Aug 24 20:50:54 2016 +0530
kunimitsu: Add FSP 2.0 support in romstage
Populate mainboard related Memory Init Params i.e, SPD
Rcomp values, DQ and DQs values.
Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Reviewed-on: https://review.coreboot.org/16316
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16316 for details.
-gerrit
the following patch was just integrated into master:
commit 5bf42c6c23b462d9292e6854d3f334cf17e42825
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Wed Aug 24 20:48:46 2016 +0530
soc/intel/skylake: Add FSP 2.0 support in romstage
Populate SoC related Memory initialization params.
Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16315 for details.
-gerrit
the following patch was just integrated into master:
commit 69966ccb5de0addda131f313b20515bfa0cb00c8
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Sep 9 12:16:11 2016 +0530
driver/intel/fsp2_0: Make FSP-M binary XIP
If FSP_M_XIP is selected, then relocate FSP-M binary
while adding it in CBFS so that it can be executed in place.
Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-on: https://review.coreboot.org/16563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16563 for details.
-gerrit
the following patch was just integrated into master:
commit 8448ac47d2d8ade2f28e71aab6dd12e2adfce443
Author: Martin Roth <martinroth(a)google.com>
Date: Sun Sep 11 15:43:22 2016 -0600
cbmem: Exit with an errorlevel of 0 after printing help
cbmem --help should not return an error to the OS.
Change-Id: Id00091c679dbb109bc352cf8a81d67c2ae5666ec
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16574
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/16574 for details.
-gerrit
the following patch was just integrated into master:
commit fbce31a2cc560a316ed6aadac3e8e5c95a095178
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 12 11:26:45 2016 -0700
drivers/i2c/tpm: Clean up handling of command ready
The TPM driver was largely ignoring the meaning of the command
ready bit in the status register, instead just arbitrarily
sending it at the end of every receive transaction.
Instead of doing this have the command ready bit be set at the
start of a transaction, and only clear it at the end of a
transaction if it is still set, in case of failure.
Also the cr50 function to wait for status and burst count was
not waiting the full 2s that the existing driver does so that
value is increased. Also, during the probe routine a delay is
inserted after each status register read to ensure the TPM has
time to actually start up.
Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/16591 for details.
-gerrit
the following patch was just integrated into master:
commit f8a7b2c008f45e91e8bc52fbe2d4e0083dab250b
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 12 11:21:40 2016 -0700
lpss_i2c: Add Kconfig option to enable debug
It is very useful to have the ability to see I2C transactions
performed by the host firmware. This patch adds a simple
Kconfig option that will enable debug output.
Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16590
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16590 for details.
-gerrit
the following patch was just integrated into master:
commit 772555a214e023c6e3dd267d296bef23242f3638
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 12 11:20:27 2016 -0700
lpss_i2c: Change handling of controller enable/disable
This change modifies the lpss_i2c driver to behave more like
the Linux kernel driver. In particular the controller is only
enabled when processing a transaction, and is disabled after.
This means that errors in one transaction will not affect later
transactions.
Also when disabling the controller the code is supposed to wait
on the enable bit in the "enable status" register and not in
the enable control register. In order to get access to this
register the reg map was expanded to include all registers.
This was tested with the cr50 TPM driver to ensure that if a
transaction does fail that it can be successfully retried instead
of the bus being unusable.
Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16589 for details.
-gerrit