the following patch was just integrated into master:
commit 91bba828fc486881b379eeb96c7d5e2536b5906b
Author: Werner Zeh <werner.zeh(a)siemens.com>
Date: Mon Sep 12 07:54:09 2016 +0200
camelbackmountain_fsp: Select SERIRQ_CONTINUOUS_MODE
In commit 4f2754c
'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode'
the default operation mode of SERIRQ was changed from continuous to quiet.
Set the mode to continuous for this mainboard to keep the behavior unchanged.
Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
Reviewed-on: https://review.coreboot.org/16576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: York Yang <york.yang(a)intel.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16576 for details.
-gerrit
the following patch was just integrated into master:
commit 96a48f148948d614900dbc51fdec0e3a5c7a35ee
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Aug 29 15:30:23 2016 -0600
checkpatch.pl: Force raw_line to return a defined value
Fixes the warning:
Use of uninitialized value in concatenation (.) or string at
util/lint/checkpatch.pl line 4739
Change-Id: Idc3c631735a595517d77cb8b8ec67e1ac00b6685
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16357
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/16357 for details.
-gerrit
the following patch was just integrated into master:
commit ab9395f6125aa90a95b0932cb546bd494ef9194a
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Aug 29 10:39:30 2016 -0600
lint/checkpatch.pl: Pull in coreboot fixes
This pulls in two fixes that were added to coreboot's checkpatch.pl
script:
- commit 82ef8ada (src/commonlib/lz4_wrapper: Correct inline asm for
unaligned 64-bit copy):
modify checkpatch.pl to ignore spaces before opening brackets when
used in inline assembly.
- commit ebef00fa (lint/checkpatch.pl: escape \{ in perl regex to fix
warnings):
Unescaped left brace in regex is deprecated, passed through in regex;
Change-Id: Ia2c712c5b1bb5f67953a9098b5a076e31e3bd8d3
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See https://review.coreboot.org/16348 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16359
-gerrit
commit e341ebeba30efbc7897d52deb59685244c5edd7b
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Aug 29 15:40:57 2016 -0600
lint/lint-007-checkpatch: Update lint script
- Check Kconfig files as well.
- Accept a list of directories to check as a command line argument.
- Only look at src & util directories by default.
- Skip src/vendorcode.
- Remove bypass of payloads/coreinfo/util/kconfig directory, it no
longer exists.
Change-Id: Ia522d3ddc29914220bdaae36ea23ded7338c48fd
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/lint/lint-007-checkpatch | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/util/lint/lint-007-checkpatch b/util/lint/lint-007-checkpatch
index 9d9d96e..b4033e0 100755
--- a/util/lint/lint-007-checkpatch
+++ b/util/lint/lint-007-checkpatch
@@ -12,12 +12,31 @@
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
-# DESCR: Checkpatch on all .c and .h files in the tree
+# DESCR: Checkpatch on .c, .h, & Kconfig files in the tree
LC_ALL=C export LC_ALL
-util/lint/checkpatch.pl --show-types --file $( git ls-files \*.[ch] | \
- grep -v ^payloads/libpayload/util/kconfig | \
- grep -v ^payloads/libpayload/curses/PDCurses-3.4 | \
- grep -v ^payloads/coreinfo/util/kconfig | \
- grep -v ^util/kconfig \
- )
+
+# GNU BRE syntax list of files to examine
+INCLUDED_FILES='.*\.[ch]\|Kconfig.*$'
+
+EXCLUDED_DIRS="^payloads/libpayload/util/kconfig\|\
+^payloads/libpayload/curses/PDCurses\|\
+^util/kconfig\|\
+^src/vendorcode"
+
+# Space separated list of directories to test
+if [ "$1" = "" ]; then
+ INCLUDED_DIRS="src util"
+else
+ INCLUDED_DIRS="$1"
+fi
+
+# We want word splitting here, so disable the shellcheck warnings
+# shellcheck disable=SC2046,SC2086
+FILELIST=$( git ls-files $INCLUDED_DIRS | \
+ grep $INCLUDED_FILES | \
+ grep -v $EXCLUDED_DIRS )
+
+for FILE in $FILELIST; do
+ util/lint/checkpatch.pl --show-types --file --quiet "$FILE"
+done
Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16564
-gerrit
commit 99b2e433b3d4b7372dc7680661e22e0efc4d6b04
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 11:43:03 2016 -0700
soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
---
src/soc/intel/apollolake/acpi/gpio.asl | 13 +++++++++++++
src/soc/intel/apollolake/include/soc/pm.h | 6 ------
2 files changed, 13 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 5660dfa..4f3bc3e 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -174,6 +174,19 @@ scope (\_SB) {
\_SB.SPC0 (Local2, Local1)
}
}
+
+ /*
+ * Sleep button device ASL code. We are using this device to
+ * add the _PRW method for a dummy wake event to kernel so that
+ * before going to sleep kernel does not clear bit 15 in ACPI
+ * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
+ */
+ Device (SLP)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+
+ Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
+ }
}
Scope(\_GPE)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 3ee7403..2c12c8d 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -138,12 +138,6 @@
#define PCIE_GPE_EN (1 << 9)
#define SWGPE_EN (1 << 2)
-/*
- * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
- * and/or an SCI or SMI#.
- */
-#define GPIO_TIER_1_SCI (1 << 15)
-
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x1000
#define GEN_PMCON1 0x1020
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16551
-gerrit
commit f6d7b970352e5a061fad9ab79e18f0a061def026
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Thu Sep 8 22:21:54 2016 +0200
gm45/gma.c: use correct id string for fake VBT
The correct id string for gm45 is "$VBT CANTIGA ".
This can be found in the gm45 option rom:
"strings vbios.bin | grep VBT".
Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/northbridge/intel/gm45/gma.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index dbcb867..14f695e 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -741,7 +741,7 @@ static void gma_func0_init(struct device *dev)
/* Linux relies on VBT for panel info. */
generate_fake_intel_oprom(&conf->gfx, dev,
- "$VBT IRONLAKE-MOBILE");
+ "$VBT CANTIGA ");
}
}
the following patch was just integrated into master:
commit 2bf453c70e6df2136abb7b221f32709058b5b4fc
Author: Martin Roth <martinroth(a)google.com>
Date: Fri Sep 9 20:52:58 2016 -0600
southbridge/amd/sr5650/sr5650.c: Update acpi_fill_ivrs
- Update lines to make them shorter than 80 chaacters
- Update using #defines from acpi_ivrs.h
Change-Id: I1bf6cdac00e28f5b0969fd8f98e37c66f8e43110
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16568
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/16568 for details.
-gerrit
the following patch was just integrated into master:
commit 16be0337d9297ee6946fa05781c8aee707d2c16b
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Sep 8 17:53:41 2016 -0600
arch/acpi_ivrs.h: Update 8-byte IVRS entry values
I put in the decimal values for these instead of the hex values.
Instead of running them through a BCD converter, update them to use
the hex values.
Change-Id: I3fa46f055c3db113758f445f947446dd5834c126
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16567
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/16567 for details.
-gerrit
the following patch was just integrated into master:
commit d173907747ce9b1eea5dad0ca9de7b3166b757b7
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Sep 7 21:22:54 2016 -0600
amd/sr5650: Update add_ivrs_device_entries
Functionally, this should be roughly the same. The only real difference
should be removing the 4 bytes of padding from the end of the 4 byte
entries. The spec mentions a boundary for the 4 byte entries (which we
are ignoring), but doesn't mention a boundary for the 8 byte entries,
and I can't think of any other reason that the padding might be needed.
- Wrap long lines.
- Combine if statements to clean up indentation.
- Use #defines from acpi_ivrs.h to make commands easier to understand.
- Remove padding from 4 byte entries that made them 8 bytes in length.
- Set the pointer p at init, and clear the value at p if the device
we're looking at is enabled instead of setting p in every if statement.
- Look at the command type to update current and length.
- Treat malloc & free as if they were typical instead of coreboot
specific versions. Check to make sure the malloc worked and only
free on the last loop instead of every time.
Change-Id: I79dd5f9e930fad22a09d1af78f33c1d9a88b3bfe
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16532
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com>
See https://review.coreboot.org/16532 for details.
-gerrit