the following patch was just integrated into master:
commit c8ae5995bb24006949dee02148c806e6de74aa2c
Author: Shaunak Saha <shaunak.saha(a)intel.com>
Date: Fri Sep 9 11:43:03 2016 -0700
soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Reviewed-on: https://review.coreboot.org/16564
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16564 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16605
-gerrit
commit e5ea408544202af27e4c6c5e0a4dd15dec63f845
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Sep 14 17:52:15 2016 -0700
payloads/external/Memtest86Plus: Update stable to latest commit
This brings in two additional changes:
- Use OBJCOPY if available.
- Fix strstr() indent and rewrite to not call strlen() on each char.
Change-Id: Id13dfda28c545332fce8282e849f379bf50629b9
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
payloads/external/Memtest86Plus/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile
index 90ea5e8..2136495 100644
--- a/payloads/external/Memtest86Plus/Makefile
+++ b/payloads/external/Memtest86Plus/Makefile
@@ -15,7 +15,7 @@
TAG-$(CONFIG_MEMTEST_MASTER)=origin/master
NAME-$(CONFIG_MEMTEST_MASTER)=Master
-TAG-$(CONFIG_MEMTEST_STABLE)=ca352c9a6bd8c1bba16ea22cbfc7028d97bacec9
+TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb
NAME-$(CONFIG_MEMTEST_STABLE)=Stable
project_name=Memtest86+
Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16556
-gerrit
commit 13657a0534bffec1ebc60b6007b4045a51e969cf
Author: Alexander Couzens <lynxis(a)fe80.eu>
Date: Fri Sep 9 00:05:54 2016 +0200
util/release: make release archives reproducible
tar doesn't sort by default and take the order of the OS which is in
most cases the order of creation. Sort by name and set influencing
environment TZ and language to be reproducible.
Change-Id: I3d043952417000d12e81353677f1ea4aa2da4fc1
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
---
util/release/build-release | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/util/release/build-release b/util/release/build-release
index d13e038..11e7177 100755
--- a/util/release/build-release
+++ b/util/release/build-release
@@ -9,6 +9,13 @@ USERNAME=${3}
GPG_KEY_ID=${4}
set -e
+
+# set local + tz to be reproducible
+LC_ALL=C
+LANG=C
+TZ=UTC
+export LC_ALL LANG TZ
+
if [ -z "${VERSION_NAME}" ] || [ "${VERSION_NAME}" = "--help" ]; then
echo "usage: $0 <version> [commit id] [gpg key id] [username]"
echo "tags a new coreboot version and creates a tar archive"
@@ -32,8 +39,8 @@ fi
printf "${VERSION_NAME}-$(git log --pretty=%H|head -1)\n" > .coreboot-version
tstamp=$(git log --pretty=format:%ci -1)
cd ..
-tar --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude=coreboot-${VERSION_NAME}/3rdparty/blobs -cvf - coreboot-${VERSION_NAME} |xz -9 > coreboot-${VERSION_NAME}.tar.xz
-tar --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - coreboot-${VERSION_NAME}/3rdparty/blobs |xz -9 > coreboot-blobs-${VERSION_NAME}.tar.xz
+tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude=coreboot-${VERSION_NAME}/3rdparty/blobs -cvf - coreboot-${VERSION_NAME} |xz -9 > coreboot-${VERSION_NAME}.tar.xz
+tar --sort=name --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - coreboot-${VERSION_NAME}/3rdparty/blobs |xz -9 > coreboot-blobs-${VERSION_NAME}.tar.xz
if [ -n "${GPG_KEY_ID}" ]; then
gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-${VERSION_NAME}.tar.xz
gpg2 --armor --local-user ${GPG_KEY_ID} --output coreboot-blobs-${VERSION_NAME}.tar.xz.sig --detach-sig coreboot-blobs-${VERSION_NAME}.tar.xz
the following patch was just integrated into master:
commit 629ca4385996708e750c06f31d5fb4f2139cc978
Author: Fabian Kunkel <fabi(a)adv.bruhnspace.com>
Date: Tue Jul 26 22:24:31 2016 +0200
mainboard/bap/ode_e20XX: Change SATA from GEN2 to GEN3
This patch disables the SataSetMaxGen2 flag.
This flag is a power saving option,
which forces the SATA to GEN2.
Payload SeaBIOS 1.9.1, Lubuntu 16.04, Kernel 4.4.
$ dmesg | grep ahci #before patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode
$ dmesg | grep ahci #after patch
ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
Change-Id: I48361190969e6d38ddb5692f5e54b016b359fbb1
Signed-off-by: Fabian Kunkel <fabi(a)adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15906
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/15906 for details.
-gerrit
the following patch was just integrated into master:
commit 13d880fd37982e56d56ff517f3e031481b9cc566
Author: Alexander Couzens <lynxis(a)fe80.eu>
Date: Tue Sep 6 16:06:32 2016 +0200
lenovo: add ps2 spinup timeout to all H8S based boards
The h8s needs around 3s to respond to ps2 commands
Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4
Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu>
Reviewed-on: https://review.coreboot.org/16505
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/16505 for details.
-gerrit