Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16613
-gerrit
commit 70b703e873eeb1a820890661f8b18daad15cf41c
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Sep 16 11:15:49 2016 -0500
soc/intel/apollolake: cache boot media post romstage
When the boot media is memory mapped mark it as cacheable
after romstage. Otherwise the boot media is uncacheable and
all loads from it take longer. Loading FSP-S alone in ramstage
went down to 17.5ms from 54ms.
BUG=chrome-os-partner:56656
Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/apollolake/romstage.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index ebd6287..b9733de 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -130,6 +130,11 @@ asmlinkage void car_stage_entry(void)
assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram);
postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK);
+ /* Cache the memory-mapped boot media. */
+ if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
+ postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
run_postcar_phase(&pcf);
}
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16612
-gerrit
commit 38fca4f17890133de5307fba4ac65931523e63fe
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Sep 16 19:45:08 2016 +0530
kunimitsu: Remove incorrect dereferencing of pointer
In spd_util.c function mainboard_get_spd_data(), spd_file can
either be NULL or will point to the first byte of the SPD data,
and should not be dereferenced.
Change-Id: I08677976792682cc744ec509dd183eadf5e570a5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/mainboard/intel/kunimitsu/spd/spd_util.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c
index 0ce2acf..a17b519 100644
--- a/src/mainboard/intel/kunimitsu/spd/spd_util.c
+++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c
@@ -85,7 +85,7 @@ uintptr_t mainboard_get_spd_data(void)
/* Load SPD data from CBFS */
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
&spd_file_len);
- if (!(*spd_file))
+ if (!spd_file)
die("SPD data not found.");
/* make sure we have at least one SPD in the file. */
the following patch was just integrated into master:
commit fec0328c5f653233859d4aec7dae0b94acb67e97
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Wed Sep 14 14:42:25 2016 -0500
mainboard/reef: add variant support to ASL code
There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.
BUG=chrome-os-partner:56677
Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/16604 for details.
-gerrit