coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: util/lint/kconfig_lint: change warning levels and text
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16840 -gerrit commit dfdb0733a6a71b11d15006dafc13841e84fab7cd Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 15:56:27 2016 -0600 util/lint/kconfig_lint: change warning levels and text - Add an exception for MAINBOARD_POWER_ON_AFTER_POWER_FAIL when checking - With those exceptions set, we don't have anymore #define or #ifdef warnings, so turn them to errors so no more can be pushed. - Change the definition of an unused symbol from a warning to a note. There are times when unused symbols are expected. - Upgrade the warning for loading Kconfig files multiple times from a warning to an error. Change-Id: I6dcb06d4f0b099d5ccaf7643e72dd790719bdf58 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 064f3db..39a0291 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -197,8 +197,11 @@ sub check_for_ifdef { my $symbol = $3; if ( ( exists $symbols{$symbol} ) && ( $symbols{$symbol}{type} ne "string" ) ) { - show_warning( "#ifdef 'CONFIG_$symbol' used at $file:$lineno." + # TODO: Remove special check for CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL + if ($symbol ne "MAINBOARD_POWER_ON_AFTER_POWER_FAIL") { + show_error( "#ifdef 'CONFIG_$symbol' used at $file:$lineno." . " Symbols of type '$symbols{$symbol}{type}' are always defined." ); + } } } } @@ -261,7 +264,10 @@ sub check_for_def { my $symbol = $3; if ( ( exists $symbols{$symbol} ) ) { - show_warning("#define of symbol 'CONFIG_$symbol' used at $file:$lineno."); + # TODO: Remove special check for CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL + if ($symbol ne "MAINBOARD_POWER_ON_AFTER_POWER_FAIL") { + show_error("#define of symbol 'CONFIG_$symbol' used at $file:$lineno."); + } } else { show_warning( "#define 'CONFIG_$symbol' used at $file:$lineno." @@ -460,7 +466,9 @@ sub check_used_symbols { for ( my $i = 0 ; $i <= $symbols{$key}{count} ; $i++ ) { my $filename = $symbols{$key}{$i}{file}; my $line_no = $symbols{$key}{$i}{line_no}; - show_warning("Unused symbol '$key' referenced at $filename:$line_no."); + if ($show_note_output) { + print("#!!!!! Note: Unused symbol '$key' defined at $filename:$line_no."); + } } } } @@ -1162,9 +1170,9 @@ sub load_kconfig_file { #if the file exists, try to load it. elsif ( -e "$input_file" ) { - #throw a warning if the file has already been loaded. + #throw an error if the file has already been loaded. if ( exists $loaded_files{$input_file} ) { - show_warning("'$input_file' sourced at $loadfile:$loadline was already loaded by $loaded_files{$input_file}"); + show_error("'$input_file' sourced at $loadfile:$loadline was already loaded by $loaded_files{$input_file}"); } #load the file's contents and mark the file as loaded for checking later

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New patch to review for coreboot: util/lint/kconfig_lint: Check default types
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16839 -gerrit commit c771a1f56b57882ffd8fa5922ccab6eb2ef222fe Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 15:51:32 2016 -0600 util/lint/kconfig_lint: Check default types The type of the default value wasn't being checked to make sure that it matched the type of the Kconfig symbol. This makes sure that the symbol is being set to either a reasonable looking value or to another Kconfig symbol. Change-Id: Ia01bd2d8b387f319d29f0a005d55cb8e20cd3853 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index c955343..064f3db 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -329,10 +329,42 @@ sub check_defaults { next unless ( exists $symbols{$sym}{$sym_num}{default_max} ); for ( my $def_num = 0 ; $def_num <= $symbols{$sym}{$sym_num}{default_max} ; $def_num++ ) { + my $filename = $symbols{$sym}{$sym_num}{file}; + my $line_no = $symbols{$sym}{$sym_num}{default}{$def_num}{default_line_no}; + + # skip good defaults + if (! ((($symbols{$sym}{type} eq "hex") && ($symbols{$sym}{$sym_num}{default}{$def_num}{default} =~ /^0x/)) || + (($symbols{$sym}{type} eq "int") && ($symbols{$sym}{$sym_num}{default}{$def_num}{default} =~ /^[-0-9]+$/)) || + (($symbols{$sym}{type} eq "string") && ($symbols{$sym}{$sym_num}{default}{$def_num}{default} =~ /^".*"$/)) || + (($symbols{$sym}{type} eq "bool") && ($symbols{$sym}{$sym_num}{default}{$def_num}{default} =~ /^[yn]$/))) + ) { + + my ($checksym) = $symbols{$sym}{$sym_num}{default}{$def_num}{default} =~ /(\w+)/; + + if (! exists $symbols{$checksym}) { + + # verify the symbol type against the default value + if ($symbols{$sym}{type} eq "hex") { + show_error("non hex default value ($symbols{$sym}{$sym_num}{default}{$def_num}{default}) used for hex symbol $sym at $filename:$line_no."); + } elsif ($symbols{$sym}{type} eq "int") { + show_error("non int default value ($symbols{$sym}{$sym_num}{default}{$def_num}{default}) used for int symbol $sym at $filename:$line_no."); + } elsif ($symbols{$sym}{type} eq "string") { + # TODO: Remove special MAINBOARD_DIR check + if ($sym ne "MAINBOARD_DIR") { + show_error("no quotes around default value ($symbols{$sym}{$sym_num}{default}{$def_num}{default}) used for string symbol $sym at $filename:$line_no."); + } + } elsif ($symbols{$sym}{type} eq "bool") { + if ($symbols{$sym}{$sym_num}{default}{$def_num}{default} =~ /[01YN]/) { + show_warning("default value ($symbols{$sym}{$sym_num}{default}{$def_num}{default}) for bool symbol $sym uses value other than y/n at $filename:$line_no."); + } else { + show_error("non bool default value ($symbols{$sym}{$sym_num}{default}{$def_num}{default}) used for bool symbol $sym at $filename:$line_no."); + } + } + } + } + #if a default is already set, display an error if ($default_set) { - my $filename = $symbols{$sym}{$sym_num}{file}; - my $line_no = $symbols{$sym}{$sym_num}{default}{$def_num}{default_line_no}; show_warning( "Default for '$sym' referenced at $filename:$line_no will never be set" . " - overridden by default set at $default_filename:$default_line_no" ); }

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New patch to review for coreboot: google/gale/Kconfig: Change wording of Kconfig option
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16838 -gerrit commit 18ff99b05b5fd7e0a37a5d2f5ad3a82c7d50d698 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 15:27:24 2016 -0600 google/gale/Kconfig: Change wording of Kconfig option Everybody knows WHAT they're supposed to do with options, so the text "Pick this" or "Select to" are redundant. Change-Id: I327c5be755373e99ca0738593bd78e1084d4d492 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/gale/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/gale/Kconfig b/src/mainboard/google/gale/Kconfig index 5b960cd..01e2945 100644 --- a/src/mainboard/google/gale/Kconfig +++ b/src/mainboard/google/gale/Kconfig @@ -37,7 +37,7 @@ config CHROMEOS select WIPEOUT_SUPPORTED config BOARD_VARIANT_DK01 - bool "pick this to build an image for DK01" + bool "Build an image for DK01" default n config MAINBOARD_DIR

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New patch to review for coreboot: google/gale: Remove #ifdef of Kconfig bool symbol
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16837 -gerrit commit f4d0e8e7b6292292bcb82ef8080b71bdffc0e5d2 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 14:51:24 2016 -0600 google/gale: Remove #ifdef of Kconfig bool symbol Kconfig symbols of type bool are ALWAYS defined, so this code was always being included and run, which isn't what the author wanted. Change to use IS_ENABLED(), and a regular if() instead of an #ifdef. Change-Id: I72623fa27e47980c602135f4b73f371c7f50139b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/gale/verstage.c | 55 ++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/src/mainboard/google/gale/verstage.c b/src/mainboard/google/gale/verstage.c index cdc4386..1a3f5a4 100644 --- a/src/mainboard/google/gale/verstage.c +++ b/src/mainboard/google/gale/verstage.c @@ -24,34 +24,33 @@ static void ipq_setup_tpm(void) { -#ifdef CONFIG_I2C_TPM - gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, - GPIO_PULL_UP, GPIO_6MA, 1); - gpio_set(TPM_RESET_GPIO, 0); - udelay(100); - gpio_set(TPM_RESET_GPIO, 1); - - /* - * ----- Per the SLB 9615XQ1.2 spec ----- - * - * 4.7.1 Reset Timing - * - * The TPM_ACCESS_x.tpmEstablishment bit has the correct value - * and the TPM_ACCESS_x.tpmRegValidSts bit is typically set - * within 8ms after RESET# is deasserted. - * - * The TPM is ready to receive a command after less than 30 ms. - * - * -------------------------------------- - * - * I'm assuming this means "wait for 30ms" - * - * If we don't wait here, subsequent QUP I2C accesses - * to the TPM either fail or timeout. - */ - mdelay(30); - -#endif /* CONFIG_I2C_TPM */ + if (IS_ENABLED(CONFIG_I2C_TPM)) { + gpio_tlmm_config_set(TPM_RESET_GPIO, FUNC_SEL_GPIO, + GPIO_PULL_UP, GPIO_6MA, 1); + gpio_set(TPM_RESET_GPIO, 0); + udelay(100); + gpio_set(TPM_RESET_GPIO, 1); + + /* + * ----- Per the SLB 9615XQ1.2 spec ----- + * + * 4.7.1 Reset Timing + * + * The TPM_ACCESS_x.tpmEstablishment bit has the correct value + * and the TPM_ACCESS_x.tpmRegValidSts bit is typically set + * within 8ms after RESET# is deasserted. + * + * The TPM is ready to receive a command after less than 30 ms. + * + * -------------------------------------- + * + * I'm assuming this means "wait for 30ms" + * + * If we don't wait here, subsequent QUP I2C accesses + * to the TPM either fail or timeout. + */ + mdelay(30); + } } void verstage_mainboard_init(void)

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New patch to review for coreboot: src/Kconfig: Remove duplicate source of fsp1_0/Kconfig
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16836 -gerrit commit 10c1ecba3b830532aa856d64a9799fd0b8e91ab2 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 14:49:09 2016 -0600 src/Kconfig: Remove duplicate source of fsp1_0/Kconfig The FSP code was initially loaded in the chipset section, because that's where it made sense, even though the source lived in the driver tree. When the Kconfigs were updated to load files using globbing, this file got loaded twice, once in drivers and once in the chipset. Remove the initial location, and just load it in the drivers as the new FSP entries do. Change-Id: I3e7759b7b3f294ea2ae2a0c5fdba1e85da8a0699 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 91b27ce..a774124 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -443,8 +443,6 @@ source "src/superio/*/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" -# FIXME move to vendorcode -source "src/drivers/intel/fsp1_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" source "src/vboot/Kconfig"

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New patch to review for coreboot: vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16835 -gerrit commit 322c1594474889e9ea50dca79b6222e1ddd4298c Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 14:44:54 2016 -0600 vendorcode/amd/pi/Kconfig: update AGESA_BINARY_PI_LOCATION to hex The AGESA_BINARY_PI_LOCATION Kconfig symbol was declared as a string. Change it to a hex value. Change-Id: Ifd87b6c8dfcdf950aea9b15a6fea45bb72e8b4e9 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/vendorcode/amd/pi/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 892892d..0122366 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -45,7 +45,7 @@ config AGESA_BINARY_PI_FILE Specify the binary file to use for AMD platform initialization. config AGESA_BINARY_PI_LOCATION - string "AGESA PI binary address in ROM" + hex "AGESA PI binary address in ROM" default 0xFFE00000 help Specify the ROM address at which to store the binary Platform

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New patch to review for coreboot: Kconfig: Update default hex values to start with 0x
by Martin Roth 30 Sep '16

30 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16834 -gerrit commit a91e216d60b2964d848a44b7644903189faabe31 Author: Martin Roth <martinroth(a)google.com> Date: Fri Sep 30 14:43:01 2016 -0600 Kconfig: Update default hex values to start with 0x Kconfig hex values don't need to be in quotes, and should start with '0x'. If the default value isn't set this way, Kconfig will add the 0x to the start, and the entry can be added unnecessarily to the defconfig since it's "different" than what was set by the default. A check for this has been added to the Kconfig lint tool. Change-Id: I86f37340682771700011b6285e4b4af41b7e9968 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 2 +- src/console/Kconfig | 2 +- src/device/Kconfig | 4 ++-- src/drivers/i2c/tpm/Kconfig | 4 ++-- src/drivers/pc80/tpm/Kconfig | 2 +- src/drivers/spi/tpm/Kconfig | 2 +- src/ec/google/chromeec/Kconfig | 2 +- src/mainboard/asus/a8v-e_deluxe/Kconfig | 2 +- src/mainboard/asus/a8v-e_se/Kconfig | 2 +- src/mainboard/asus/k8v-x/Kconfig | 2 +- src/mainboard/asus/kcma-d8/Kconfig | 2 +- src/mainboard/asus/kfsn4-dre/Kconfig | 2 +- src/mainboard/asus/kgpe-d16/Kconfig | 2 +- src/mainboard/asus/m2v/Kconfig | 2 +- src/mainboard/google/gru/Kconfig | 4 ++-- src/mainboard/google/nyan/Kconfig | 2 +- src/mainboard/google/nyan_big/Kconfig | 2 +- src/mainboard/google/nyan_blaze/Kconfig | 2 +- src/mainboard/google/oak/Kconfig | 2 +- src/mainboard/google/peach_pit/Kconfig | 2 +- src/mainboard/google/veyron/Kconfig | 2 +- src/mainboard/hp/dl165_g6_fam10/Kconfig | 2 +- src/mainboard/msi/ms7135/Kconfig | 2 +- src/mainboard/tyan/s2912_fam10/Kconfig | 2 +- src/mainboard/winent/mb6047/Kconfig | 2 +- src/soc/intel/broadwell/Kconfig | 2 +- src/southbridge/amd/cimx/sb800/Kconfig | 10 +++++----- src/vendorcode/google/chromeos/Kconfig | 2 +- 28 files changed, 35 insertions(+), 35 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f6c022e..91b27ce 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -634,7 +634,7 @@ config IOAPIC config CACHE_ROM_SIZE_OVERRIDE hex - default 0 + default 0x0 # TODO: Can probably be removed once all chipsets have kconfig options for it. config VIDEO_MB diff --git a/src/console/Kconfig b/src/console/Kconfig index e945c25..8f74613 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -330,7 +330,7 @@ config CMOS_POST config CMOS_POST_OFFSET hex "Offset into CMOS to store POST codes" depends on CMOS_POST - default 0 + default 0x0 help If CMOS_POST is enabled then an offset into CMOS must be provided. If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value diff --git a/src/device/Kconfig b/src/device/Kconfig index b1f8dae..c7dfe9c 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -288,7 +288,7 @@ endif # EARLY_PCI_BRIDGE config SUBSYSTEM_VENDOR_ID hex "Override PCI Subsystem Vendor ID" depends on PCI - default "0x0000" + default 0x0000 help This config option will override the devicetree settings for PCI Subsystem Vendor ID. @@ -296,7 +296,7 @@ config SUBSYSTEM_VENDOR_ID config SUBSYSTEM_DEVICE_ID hex "Override PCI Subsystem Device ID" depends on PCI - default "0x0000" + default 0x0000 help This config option will override the devicetree settings for PCI Subsystem Device ID. diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index a5ab077..89e4621 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -22,12 +22,12 @@ endchoice config DRIVER_TPM_I2C_BUS hex "I2C TPM chip bus" - default 9 # FIXME, workaround for Kconfig BS + default 0x9 # FIXME, workaround for Kconfig BS depends on I2C_TPM config DRIVER_TPM_I2C_ADDR hex "I2C TPM chip address" - default 2 # FIXME, workaround for Kconfig BS + default 0x2 # FIXME, workaround for Kconfig BS depends on I2C_TPM config DRIVER_TPM_I2C_IRQ diff --git a/src/drivers/pc80/tpm/Kconfig b/src/drivers/pc80/tpm/Kconfig index 0e8a020..f32071c 100644 --- a/src/drivers/pc80/tpm/Kconfig +++ b/src/drivers/pc80/tpm/Kconfig @@ -25,7 +25,7 @@ config TPM_TIS_BASE_ADDRESS config TPM_PIRQ hex - default 0 + default 0x0 depends on LPC_TPM help This can be used to specify a PIRQ to use instead of SERIRQ, diff --git a/src/drivers/spi/tpm/Kconfig b/src/drivers/spi/tpm/Kconfig index 49ab2a6..d66d9ff 100644 --- a/src/drivers/spi/tpm/Kconfig +++ b/src/drivers/spi/tpm/Kconfig @@ -4,7 +4,7 @@ config SPI_TPM config DRIVER_TPM_SPI_BUS hex "SPI bus TPM chip is connected to" - default 0 + default 0x0 depends on SPI_TPM config DRIVER_TPM_SPI_CHIP diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index f4ff303..f809003 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -72,7 +72,7 @@ config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US config EC_GOOGLE_CHROMEEC_SPI_CHIP depends on EC_GOOGLE_CHROMEEC_SPI hex - default 0 + default 0x0 config EC_GOOGLE_CHROMEEC_BOARDNAME depends on EC_GOOGLE_CHROMEEC diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index a1c2fd9..b067047 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER config HW_MEM_HOLE_SIZEK hex - default 0 + default 0x0 config MAX_CPUS int diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index dffe9eb..0188ff9 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -39,7 +39,7 @@ config MAINBOARD_PART_NUMBER config HW_MEM_HOLE_SIZEK hex - default 0 + default 0x0 config MAX_CPUS int diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 4eb1bec..674059b 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -44,7 +44,7 @@ config AGP_APERTURE_SIZE config HW_MEM_HOLE_SIZEK hex - default 0 + default 0x0 config MAX_CPUS int diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 3c8cdcd..1542279 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -53,7 +53,7 @@ config DCACHE_RAM_SIZE config APIC_ID_OFFSET hex - default 0 + default 0x0 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 5e455e0..f40899d 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -43,7 +43,7 @@ config DCACHE_RAM_SIZE config APIC_ID_OFFSET hex - default 0 + default 0x0 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index ca1f0c8..a65cecc 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -54,7 +54,7 @@ config DCACHE_RAM_SIZE config APIC_ID_OFFSET hex - default 0 + default 0x0 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 72527be..20c2689 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -42,7 +42,7 @@ config MAINBOARD_PART_NUMBER config HW_MEM_HOLE_SIZEK hex - default 0 + default 0x0 config MAX_CPUS int diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 3150839..41e8105 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -65,7 +65,7 @@ config DRAM_SIZE_MB config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 5 + default 0x5 config BOOT_DEVICE_SPI_FLASH_BUS int @@ -73,7 +73,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS config DRIVER_TPM_I2C_BUS hex - default 0 + default 0x0 config DRIVER_TPM_I2C_ADDR hex diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index e68ad4e..9b25d5c 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -72,7 +72,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 1 + default 0x1 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index 3f94637..bcf8f5d 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -73,7 +73,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 1 + default 0x1 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index e47ebfa..0782cc0 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -74,7 +74,7 @@ config BOOT_DEVICE_SPI_FLASH_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 1 + default 0x1 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 1228cff..2674643 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -50,7 +50,7 @@ config MAINBOARD_VENDOR config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0 + default 0x0 config DRIVER_TPM_I2C_BUS hex diff --git a/src/mainboard/google/peach_pit/Kconfig b/src/mainboard/google/peach_pit/Kconfig index 125333c..be06a18 100644 --- a/src/mainboard/google/peach_pit/Kconfig +++ b/src/mainboard/google/peach_pit/Kconfig @@ -42,7 +42,7 @@ config DRAM_SIZE_MB config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 2 + default 0x2 config UART_FOR_CONSOLE int diff --git a/src/mainboard/google/veyron/Kconfig b/src/mainboard/google/veyron/Kconfig index b6a687c..1729155 100644 --- a/src/mainboard/google/veyron/Kconfig +++ b/src/mainboard/google/veyron/Kconfig @@ -54,7 +54,7 @@ config MAINBOARD_VENDOR config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0 + default 0x0 config EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US int diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index 703200d..a1f55f4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE config APIC_ID_OFFSET hex - default 0 + default 0x0 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index 50f989e..3affb6a 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -38,7 +38,7 @@ config MAX_PHYSICAL_CPUS config HT_CHAIN_UNITID_BASE hex - default 0 + default 0x0 config HT_CHAIN_END_UNITID_BASE hex diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 8a517e5..861c2e5 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -33,7 +33,7 @@ config DCACHE_RAM_SIZE config APIC_ID_OFFSET hex - default 0 + default 0x0 config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 622441e..5a3b81d 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -40,7 +40,7 @@ config MAX_PHYSICAL_CPUS config HT_CHAIN_UNITID_BASE hex - default 0 + default 0x0 config HT_CHAIN_END_UNITID_BASE hex diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 03934d2..517fd21 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -167,7 +167,7 @@ config INTEL_PCH_UART_CONSOLE config INTEL_PCH_UART_CONSOLE_NUMBER hex "Serial IO UART number to use for console" - default "0x0" + default 0x0 depends on INTEL_PCH_UART_CONSOLE config TTYS0_BASE diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig index 5748f79..a48b93a 100644 --- a/src/southbridge/amd/cimx/sb800/Kconfig +++ b/src/southbridge/amd/cimx/sb800/Kconfig @@ -39,8 +39,8 @@ config ENABLE_IDE_COMBINED_MODE config IDE_COMBINED_MODE hex - default "0x0" if ENABLE_IDE_COMBINED_MODE - default "0x1" if !ENABLE_IDE_COMBINED_MODE + default 0x0 if ENABLE_IDE_COMBINED_MODE + default 0x1 if !ENABLE_IDE_COMBINED_MODE choice prompt "SATA Mode" @@ -70,9 +70,9 @@ endchoice config SB800_SATA_MODE hex depends on (SB800_SATA_IDE || SB800_SATA_RAID || SB800_SATA_AHCI) - default "0x0" if SB800_SATA_IDE - default "0x1" if SB800_SATA_RAID - default "0x2" if SB800_SATA_AHCI + default 0x0 if SB800_SATA_IDE + default 0x1 if SB800_SATA_RAID + default 0x2 if SB800_SATA_AHCI config SB_SUPERIO_HWM bool diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 129c965..b7431b2 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -212,7 +212,7 @@ config VBOOT_KEYBLOCK_VERSION config VBOOT_KEYBLOCK_PREAMBLE_FLAGS hex "Keyblock preamble flags" - default 0 + default 0x0 endmenu # Keys

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Patch merged into coreboot/master: google/reef: Fix default values in Kconfig
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 80fa9d899c2dacf3b842b8a8cae28352bb874e62 Author: Martin Roth <martinroth(a)google.com> Date: Thu Sep 29 15:10:37 2016 -0600 google/reef: Fix default values in Kconfig These default values weren't being set with the default keyword so were ending up with different values. from the default generated config file before this change: CONFIG_DRIVER_TPM_I2C_BUS=0x9 CONFIG_DRIVER_TPM_I2C_ADDR=0x2 CONFIG_DRIVER_TPM_I2C_IRQ=-1 Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16828 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16828 for details. -gerrit

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Patch merged into coreboot/master: Kconfig: Prefix hex defaults with 0x
by gerrit＠coreboot.org 30 Sep '16

30 Sep '16

the following patch was just integrated into master: commit 311fb696cfa6644ca82dca3e1ea825401779db51 Author: Martin Roth <martinroth(a)google.com> Date: Thu Sep 29 14:46:24 2016 -0600 Kconfig: Prefix hex defaults with 0x Because these variables had "non-hexidecimal" defaults, they were updated by kconfig when writing defconfig files. Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/16827 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16827 for details. -gerrit

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New patch to review for coreboot: [WIP]soc/intel/apollolake:Implement stage cache to improve resume time
by Brandon Breitenstein 30 Sep '16

30 Sep '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16833 -gerrit commit ecce49e0f88046e21ec45a71e6d9b8771badb1c4 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Sep 30 13:57:12 2016 -0700 [WIP]soc/intel/apollolake:Implement stage cache to improve resume time This patch enables stage cache to save some time during resume. It saves ramstage in the stage cache and restores it on resume so that it does not have to reinitialize ramstage during the resume flow. Currently the stage cache is being lost on S3 entrance with this patch and it is being debugged. BUG=chrome-os-partner:56941 BRANCH=none TEST=work in progress Change-Id: I1551fd0faca536bd8c8656f0a8ec7f900aae1f72 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 3 ++- src/soc/intel/apollolake/cpu.c | 13 +++++++++++-- src/soc/intel/apollolake/include/soc/smm.h | 4 +--- src/soc/intel/apollolake/memmap.c | 30 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/romstage.c | 19 +++++++++++++++++++ 5 files changed, 63 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3a23dbd..4f3f29f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT # Misc options select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE select COLLECT_TIMESTAMPS select COMMON_FADT select GENERIC_GPIO_LIB @@ -34,7 +35,7 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE - select NO_STAGE_CACHE + # select NO_STAGE_CACHE select NO_XIP_EARLY_STAGES select PARALLEL_MP select PCIEXP_ASPM diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 86fe3e1..c4893e5 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -47,6 +47,8 @@ static const struct cpu_driver driver __cpu_driver = { * MP and SMM loading initialization. */ struct smm_relocation_attrs { + uint32_t smram_base; + uint32_t smram_size; uint32_t smbase; uint32_t smrr_base; uint32_t smrr_mask; @@ -99,19 +101,26 @@ static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, { void *smm_base; size_t smm_size; + void *handler_base; + size_t handler_size; /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); /* Initialize global tracking state. */ smm_region(&smm_base, &smm_size); + smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size); + + relo_attrs.smram_size = handler_size; + relo_attrs.smram_base = (uint32_t)handler_base; + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; - *perm_smbase = relo_attrs.smbase; - *perm_smsize = smm_size - CONFIG_SMM_RESERVED_SIZE; + *perm_smbase = relo_attrs.smram_base; + *perm_smsize = relo_attrs.smram_size; *smm_save_state_size = sizeof(em64t100_smm_state_save_area_t); } diff --git a/src/soc/intel/apollolake/include/soc/smm.h b/src/soc/intel/apollolake/include/soc/smm.h index 7a9846e..740d02b 100644 --- a/src/soc/intel/apollolake/include/soc/smm.h +++ b/src/soc/intel/apollolake/include/soc/smm.h @@ -20,6 +20,7 @@ #include <stdint.h> #include <soc/gpio.h> +#include <fsp/memmap.h> /* These helpers are for performing SMM relocation. */ void southbridge_clear_smi_status(void); @@ -35,7 +36,4 @@ void southbridge_smm_enable_smi(void); /* Mainboard handler for GPI SMIs*/ void mainboard_smi_gpi_handler(const struct gpi_status *sts); -/* Fills in the arguments for the entire SMM region covered by chipset - * protections. e.g. TSEG. */ -void smm_region(void **start, size_t *size); #endif diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index ea6f447..60d918c 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -52,3 +52,33 @@ void smm_region(void **start, size_t *size) *start = (void *)smm_region_start(); *size = smm_region_size(); } + +int smm_subregion(int sub, void **start, size_t *size) +{ + uintptr_t sub_base; + size_t sub_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + sub_base = smm_region_start(); + sub_size = smm_region_size(); + + switch (sub) { + case SMM_SUBREGION_HANDLER: + /* Handler starts at the base of TSEG. */ + sub_size -= cache_size; + break; + case SMM_SUBREGION_CACHE: + /* External cache is in the middle of TSEG. */ + sub_base += sub_size - cache_size; + sub_size = cache_size; + break; + default: + return -1; + } + + *start = (void *)sub_base; + *size = sub_size; + + return 0; +} + diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index b9733de..328ed6d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -29,6 +29,7 @@ #include <device/pci_def.h> #include <device/resource.h> #include <fsp/api.h> +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/northbridge.h> @@ -135,6 +136,24 @@ asmlinkage void car_stage_entry(void) postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + void *smm_base; + size_t smm_size; + uintptr_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uintptr_t)smm_base; + postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, + MTRR_TYPE_WRBACK); + } + run_postcar_phase(&pcf); }

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coreboot-gerrit September 2016