coreboot-gerrit August 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: src/drivers: Add required space before opening parenthesis '('
by HAOUAS Elyes 25 Aug '16

25 Aug '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16321 -gerrit commit f0906cb1ceb5679741b4cd4353e4757714b0f79e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Aug 25 20:50:50 2016 +0200 src/drivers: Add required space before opening parenthesis '(' Change-Id: I4d0087b2557862d04be54cf42f01b3223cb723ac Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/drivers/ati/ragexl/xlinit.c | 4 ++-- src/drivers/intel/fsp1_0/fsp_util.c | 2 +- src/drivers/intel/fsp1_1/ramstage.c | 2 +- src/drivers/intel/gma/intel_dp.c | 6 +++--- src/drivers/ipmi/ipmi_kcs.c | 8 ++++---- src/drivers/net/ne2k.c | 2 +- src/drivers/uart/uart8250mem.c | 6 +++--- src/drivers/usb/ehci_debug.c | 12 ++++++------ 8 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/drivers/ati/ragexl/xlinit.c b/src/drivers/ati/ragexl/xlinit.c index 3427b0e..c5d4404 100644 --- a/src/drivers/ati/ragexl/xlinit.c +++ b/src/drivers/ati/ragexl/xlinit.c @@ -528,7 +528,7 @@ static void ati_ragexl_init(struct device *dev) res = dev->resource_list; - if(res->flags & IORESOURCE_IO) { + if (res->flags & IORESOURCE_IO) { res = res->next; } @@ -542,7 +542,7 @@ static void ati_ragexl_init(struct device *dev) /* Fix this to look for the correct index. */ //if (dev->resource_list && dev->resource_list->next) res = dev->resource_list->next->next; - if(res->flags & IORESOURCE_MEM) { + if (res->flags & IORESOURCE_MEM) { info->ati_regbase = res2mmio(res, 0x400, 0); //using auxiliary register } diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index a3fef2d..b43f0df 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -303,7 +303,7 @@ static void find_fsp_hob_update_mrc(void *unused) print_hob_type_structure(0x000, FspHobListPtr); #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) - if(save_mrc_data(FspHobListPtr)) + if (save_mrc_data(FspHobListPtr)) update_mrc_cache(NULL); else printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index b4a6af1..dd1abbe 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -143,7 +143,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup) /* Mark graphics init done after SiliconInit if VBT was provided */ #if IS_ENABLED(CONFIG_GOP_SUPPORT) /* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs - * to be #if'd out instead of using if(). */ + * to be #if'd out instead of using if (). */ if (silicon_init_params.GraphicsConfigPtr) gfx_set_init_done(1); #endif diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c index 55839e1..56ee73b 100644 --- a/src/drivers/intel/gma/intel_dp.c +++ b/src/drivers/intel/gma/intel_dp.c @@ -642,7 +642,7 @@ static void ironlake_wait_panel_status(struct intel_dp *intel_dp, (unsigned long)gtt_read(PCH_PP_STATUS), (unsigned long)gtt_read(PCH_PP_CONTROL)); - for(i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000); + for (i = 0, status = gtt_read(PCH_PP_STATUS); ((status & mask) != value) && (i < 5000); status = gtt_read(PCH_PP_STATUS)){ udelay(10); } @@ -972,7 +972,7 @@ intel_dp_get_link_status(struct intel_dp *intel_dp, DP_LINK_STATUS_SIZE); printk(BIOS_SPEW, "%s:", __func__); - for(i = 0; i < /* !!sizeof(link_status) == 4*/ + for (i = 0; i < /* !!sizeof(link_status) == 4*/ DP_LINK_STATUS_SIZE; i++) printk(BIOS_SPEW, " %02x", link_status[i]); printk(BIOS_SPEW, "\n"); @@ -1308,7 +1308,7 @@ intel_dp_set_link_train(struct intel_dp *intel_dp, temp |= DP_TP_CTL_LINK_TRAIN_IDLE; gtt_write(DP_TP_CTL(port), temp); - for(i = 0; i < 10; i++){ + for (i = 0; i < 10; i++){ u32 status; status = gtt_read(DP_TP_STATUS(port)); if (status & DP_TP_STATUS_IDLE_DONE) diff --git a/src/drivers/ipmi/ipmi_kcs.c b/src/drivers/ipmi/ipmi_kcs.c index 829b2f9..e6d2e0b 100644 --- a/src/drivers/ipmi/ipmi_kcs.c +++ b/src/drivers/ipmi/ipmi_kcs.c @@ -55,7 +55,7 @@ static int wait_ibf_timeout(int port) if (!(ipmi_kcs_status(port) & IPMI_KCS_IBF)) return 0; udelay(100); - } while(timeout--); + } while (timeout--); printk(BIOS_ERR, "wait_ibf timeout!\n"); return timeout; } @@ -67,7 +67,7 @@ static int wait_obf_timeout(int port) if ((ipmi_kcs_status(port) & IPMI_KCS_OBF)) return 0; udelay(100); - } while(timeout--); + } while (timeout--); printk(BIOS_ERR, "wait_obf timeout!\n"); return timeout; @@ -160,7 +160,7 @@ static int ipmi_kcs_send_message(int port, int netfn, int lun, int cmd, return ret; } - while(len-- > 1) { + while (len-- > 1) { if ((ret = ipmi_kcs_send_data_byte(port, *msg++))) { printk(BIOS_ERR, "IPMI BYTE WRITE failed\n"); return ret; @@ -189,7 +189,7 @@ static int ipmi_kcs_read_message(int port, unsigned char *msg, int len) if (wait_ibf_timeout(port)) return 1; - for(;;) { + for (;;) { status = ipmi_kcs_status(port); if (IPMI_KCS_STATE(status) == IPMI_KCS_STATE_IDLE) diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index b59fe08..ed56006 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -153,7 +153,7 @@ unsigned long compute_ip_checksum_from_sram(unsigned short offset, unsigned shor * compute an ip style checksum. */ sum = 0; - for(i = 0; i < length; i++) { + for (i = 0; i < length; i++) { unsigned long v; v = eth_pio_read_byte((TX_START << 8)+i+offset, eth_nic_base); if (i & 1) { diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index cf58423..4e53a92 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -62,7 +62,7 @@ static int uart8250_mem_can_tx_byte(void *base) static void uart8250_mem_tx_byte(void *base, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_tx_byte(base)) + while (i-- && !uart8250_mem_can_tx_byte(base)) udelay(1); uart8250_write(base, UART8250_TBR, data); } @@ -70,7 +70,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data) static void uart8250_mem_tx_flush(void *base) { unsigned long int i = FIFO_TIMEOUT; - while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) + while (i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) udelay(1); } @@ -82,7 +82,7 @@ static int uart8250_mem_can_rx_byte(void *base) static unsigned char uart8250_mem_rx_byte(void *base) { unsigned long int i = SINGLE_CHAR_TIMEOUT; - while(i-- && !uart8250_mem_can_rx_byte(base)) + while (i-- && !uart8250_mem_can_rx_byte(base)) udelay(1); if (i) return uart8250_read(base, UART8250_RBR); diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 57a1453..cac043e 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -39,8 +39,8 @@ static int dbgp_enabled(void); # define dprintk(LEVEL, args...) \ do { if (!dbgp_enabled()) printk(LEVEL, ##args); } while (0) #else -# define dbgp_print_data(x) do {} while(0) -# define dprintk(LEVEL, args...) do {} while(0) +# define dbgp_print_data(x) do {} while (0) +# define dprintk(LEVEL, args...) do {} while (0) #endif #define DBGP_LEN_UPDATE(x, len) (((x) & ~0x0f) | ((len) & 0x0f)) @@ -460,8 +460,8 @@ try_next_port: dprintk(BIOS_INFO, "PORTSC #%d: %08x\n", i, portsc); } - if(port_map_tried && (new_debug_port != debug_port)) { - if(--playtimes) { + if (port_map_tried && (new_debug_port != debug_port)) { + if (--playtimes) { ehci_debug_select_port(debug_port); goto try_next_time; } @@ -495,7 +495,7 @@ try_next_port: cmd = read32(&ehci_regs->command); } while ((cmd & CMD_RESET) && (--loop > 0)); - if(!loop) { + if (!loop) { dprintk(BIOS_INFO, "Could not reset EHCI controller.\n"); // on some systems it works without succeeding here. // return -2; @@ -525,7 +525,7 @@ try_next_port: status = read32(&ehci_regs->status); } while ((status & STS_HALT) && (--loop > 0)); - if(!loop) { + if (!loop) { dprintk(BIOS_INFO, "EHCI could not be started.\n"); return -3; }

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New patch to review for coreboot: soc/intel/apollolake: Disable Periodic Retraining per-SKU
by Andrey Petrov 25 Aug '16

25 Aug '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16320 -gerrit commit 41ab84594430929f572a464c889f9600fb9e3a1e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Aug 25 11:06:08 2016 -0700 soc/intel/apollolake: Disable Periodic Retraining per-SKU Certain LPDDR4 models have some HW issues that can be workarounded by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=not tested yet Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/google/reef/romstage.c | 1 + src/soc/intel/apollolake/include/soc/meminit.h | 2 ++ src/soc/intel/apollolake/meminit.c | 2 ++ 3 files changed, 5 insertions(+) diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c index e8d8e16..a963095 100644 --- a/src/mainboard/google/reef/romstage.c +++ b/src/mainboard/google/reef/romstage.c @@ -110,6 +110,7 @@ static const struct lpddr4_sku skus[] = { .ch0_rank_density = LP4_8Gb_DENSITY, .ch1_rank_density = LP4_8Gb_DENSITY, .part_num = "MT53B256M32D1NP", + .per_retrn_dis = 1, }, /* K4F8E304HB-MGCH - both logical channels */ [PROTO_SKU] = { diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index c115c4a..0f95392 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -102,6 +102,8 @@ struct lpddr4_sku { int ch0_dual_rank; int ch1_dual_rank; const char *part_num; + /* Disable periodic retraining. */ + bool per_retrn_dis; }; struct lpddr4_cfg { diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c index 03e9ac4..dc770d8 100644 --- a/src/soc/intel/apollolake/meminit.c +++ b/src/soc/intel/apollolake/meminit.c @@ -254,6 +254,8 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg, sku->ch1_dual_rank, lpcfg->swizzle_config); } + + cfg->PeriodicRetrainingDisable = sku->per_retrn_dis; } void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)

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Patch set updated for coreboot: sb/amd/sb700: Add option to increase SPI speed to 33MHz
by Timothy Pearson 25 Aug '16

25 Aug '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16306 -gerrit commit 830a3dd5364dfa373490e1506ec9cb557ed3942f Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue Aug 23 15:41:05 2016 -0500 sb/amd/sb700: Add option to increase SPI speed to 33MHz Some SB700-based systems and ROMs support high speed (33MHz) SPI access instead of the power-on default 16.5MHz. Add an option to enable high speed SPI access in the bootblock, and set the default value to Disabled. This greatly decreases boot time on SB700-based systems, especiall when a large payload is in use. On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the command prompt was accessible within 20 seconds of power on, which incidentally is faster than the proprietary BIOS on the same machine could even reach the GRUB bootloader. Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Test: Booted KGPE-D16 with Linux payload --- src/southbridge/amd/sb700/Kconfig | 10 ++++++++++ src/southbridge/amd/sb700/bootblock.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 9a988a9..353c2a4 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,6 +25,16 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS +config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI + bool "Enable high speed SPI clock" + default n + help + When set, the SPI clock will run at 33MHz instead + of the compatibility mode 16.5MHz. Note that not + all ROMs are capable of 33MHz operation, so you + will need to verify this option is appropriate for + the ROM you are using. + # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 97e749c..dfa4102 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -20,6 +20,10 @@ #define IO_MEM_PORT_DECODE_ENABLE_5 0x48 #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a +#define SPI_BASE_ADDRESS 0xa0 + +#define SPI_CONTROL_1 0xc +#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000 /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -92,7 +96,37 @@ static void sb700_enable_rom(void) pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); } +static void sb700_configure_rom(void) +{ + pci_devfn_t dev; + uint32_t dword; + + dev = PCI_DEV(0, 0x14, 3); + + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { + uint32_t prev_spi_cfg; + volatile uint32_t *spi_mmio; + + /* Temporarily set up SPI access to change SPI speed */ + prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS); + dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */ + dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5); + dword |= (0x1 << 1); /* SpiRomEnable = 1 */ + pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword); + + spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1); + dword = *spi_mmio; + dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */ + dword |= (0x1 << 12); + *spi_mmio = dword; + + /* Restore previous SPI access */ + pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg); + } +} + static void bootblock_southbridge_init(void) { sb700_enable_rom(); + sb700_configure_rom(); }

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Patch set updated for coreboot: sb/amd/sb700: Add option to increase SPI speed to 33MHz
by Timothy Pearson 25 Aug '16

25 Aug '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16306 -gerrit commit 0f4cafdb69ce54e8fd89684c6c17bc5b6b650d9a Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue Aug 23 15:41:05 2016 -0500 sb/amd/sb700: Add option to increase SPI speed to 33MHz Some SB700-based systems and ROMs support high speed (33MHz) SPI access instead of the power-on default 16.5MHz. Add an option to enable high speed SPI access in the bootblock, and set the default value to Disabled. This greatly decreases boot time on SB700-based systems, especiall when a large payload is in use. On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the command prompt was accessible within 20 seconds of power on, which incidentally is faster than the proprietary BIOS on the same machine could even reach the GRUB bootloader. Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Test: Booted KGPE-D16 with Linux payload --- src/southbridge/amd/sb700/Kconfig | 10 ++++++++++ src/southbridge/amd/sb700/bootblock.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 9a988a9..353c2a4 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,6 +25,16 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS +config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI + bool "Enable high speed SPI clock" + default n + help + When set, the SPI clock will run at 33MHz instead + of the compatibility mode 16.5MHz. Note that not + all ROMs are capable of 33MHz operation, so you + will need to verify this option is appropriate for + the ROM you are using. + # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 97e749c..88ee0ac 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -20,6 +20,10 @@ #define IO_MEM_PORT_DECODE_ENABLE_5 0x48 #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a +#define SPI_BASE_ADDRESS 0xa0 + +#define SPI_CONTROL_1 0xc +#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000 /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -92,7 +96,32 @@ static void sb700_enable_rom(void) pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); } +static void sb700_configure_rom(void) +{ + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { + uint32_t prev_spi_cfg; + volatile uint32_t *spi_mmio; + + /* Temporarily set up SPI access to change SPI speed */ + prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS); + dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */ + dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5); + dword |= (0x1 << 1); /* SpiRomEnable = 1 */ + pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword); + + spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1); + dword = *spi_mmio; + dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */ + dword |= (0x1 << 12); + *spi_mmio = dword; + + /* Restore previous SPI access */ + pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg); + } +} + static void bootblock_southbridge_init(void) { sb700_enable_rom(); + sb700_configure_rom(); }

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Patch set updated for coreboot: sb/amd/sb700: Add option to increase SPI speed to 33MHz
by Timothy Pearson 25 Aug '16

25 Aug '16

Timothy Pearson (tpearson(a)raptorengineering.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16306 -gerrit commit 183f5ffcbf3dabf407a32e3ba64fae044f988063 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Tue Aug 23 15:41:05 2016 -0500 sb/amd/sb700: Add option to increase SPI speed to 33MHz Some SB700-based systems and ROMs support high speed (33MHz) SPI access instead of the power-on default 16.5MHz. Add an option to enable high speed SPI access in the bootblock, and set the default value to Disabled. This greatly decreases boot time on SB700-based systems, especiall when a large payload is in use. On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the command prompt was accessible within 20 seconds of power on, which incidentally is faster than the proprietary BIOS on the same machine could even reach the GRUB bootloader. Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Test: Booted KGPE-D16 with Linux payload --- src/southbridge/amd/sb700/Kconfig | 10 ++++++++++ src/southbridge/amd/sb700/bootblock.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 9a988a9..353c2a4 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,6 +25,16 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS +config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI + bool "Enable high speed SPI clock" + default n + help + When set, the SPI clock will run at 33MHz instead + of the compatibility mode 16.5MHz. Note that not + all ROMs are capable of 33MHz operation, so you + will need to verify this option is appropriate for + the ROM you are using. + # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index 97e749c..2fc60b8 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -20,6 +20,10 @@ #define IO_MEM_PORT_DECODE_ENABLE_5 0x48 #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a +#define SPI_BASE_ADDRESS 0xa0 + +#define SPI_CONTROL_1 0xc +#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000 /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -90,9 +94,33 @@ static void sb700_enable_rom(void) reg8 = pci_io_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6); reg8 |= (1 << 5); pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); + +static void sb700_configure_rom(void) +{ + if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { + uint32_t prev_spi_cfg; + volatile uint32_t *spi_mmio; + + /* Temporarily set up SPI access to change SPI speed */ + prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS); + dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */ + dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5); + dword |= (0x1 << 1); /* SpiRomEnable = 1 */ + pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword); + + spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1); + dword = *spi_mmio; + dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */ + dword |= (0x1 << 12); + *spi_mmio = dword; + + /* Restore previous SPI access */ + pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg); + } } static void bootblock_southbridge_init(void) { sb700_enable_rom(); + sb700_configure_rom(); }

1 0

Patch set updated for coreboot: kunimitsu: Add FSP 2.0 support in romstage
by Rizwan Qureshi 25 Aug '16

25 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16316 -gerrit commit cc6f6b7bd6e0f3dae5cb27356205b3a3ecdd399b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Aug 24 20:50:54 2016 +0530 kunimitsu: Add FSP 2.0 support in romstage Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values. Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 + src/mainboard/intel/kunimitsu/romstage_fsp20.c | 81 +++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 2aa3d95..a5789b0 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -187,6 +187,9 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 10bdd21..c966f15 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -13,9 +13,88 @@ * GNU General Public License for more details. */ +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" #include <soc/romstage.h> +#include "spd/spd.h" +#include <string.h> + +#define RCOMP_TARGET_PARAMS 0x5 void mainboard_memory_init_params(struct FSPM_UPD *mupd) { - /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ + struct FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + char *spd_file; + size_t spd_file_len; + int spd_index, spd_span; + + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ + //static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + // 100, 40, 40, 21, 40 }; + + memcpy((void*)mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy((void *)mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy((void*)mem_cfg->RcompResistor, RcompResistor, sizeof(RcompResistor)); + memcpy((void*)mem_cfg->RcompTarget, RcompTarget, sizeof(RcompTarget)); + mem_cfg->DqPinsInterleaved = 0; + + /* fill SPD Data */ + + /* PCH_MEM_CFG[3:0] */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + /* Assume same memory in both channels */ + spd_span = spd_index * SPD_LEN; + + mem_cfg->MemorySpdPtr00 = ( uint32_t )spd_file + spd_span; + mem_cfg->MemorySpdPtr10 = (uint32_t)spd_file + spd_span; + mem_cfg->MemorySpdDataLen = SPD_LEN; }

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Patch set updated for coreboot: skylake: Add FSP 2.0 support in romstage
by Rizwan Qureshi 25 Aug '16

25 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16315 -gerrit commit 6995249ca8abd99016c03c713a789edf1845f950 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Aug 24 20:48:46 2016 +0530 skylake: Add FSP 2.0 support in romstage Setup stack and MTRRs after Dram initialization. This setup code is present in FSP1.1 driver, copy and reuse stack.c. Populate SoC related Memory related params. Make sure FSP binaries are properly relocated to the base where they are placed in CBFS. i.e., Make them XIP. Minor correction in top of ram calculation. TEST=Build and boot kunimitsu, dram initialization done. ramstage is loaded. Change-Id: I8d943e29b6e118986189166d92c7891ab6642193 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 6 + src/soc/intel/skylake/chip.h | 4 + src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +- src/soc/intel/skylake/memmap.c | 19 ++- src/soc/intel/skylake/romstage/romstage_fsp20.c | 84 +++++++++- src/soc/intel/skylake/stack.c | 169 +++++++++++++++++++++ 6 files changed, 280 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index aa3da61..02b3ee8 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stack.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -104,6 +105,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake +$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_S_CBFS)-options := --xip endif # Currently used for microcode path. @@ -111,4 +114,7 @@ CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR) ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 +$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_S_CBFS)-options := --xip + endif diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a4dee51..62e28e6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -359,6 +359,10 @@ struct soc_intel_skylake_config { * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue */ u8 SendVrMbxCmd; + + /* Enable/Disable VMX feature */ + u8 VmxEnable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index d48ac67..253ee32 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -22,9 +22,16 @@ asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(struct FSPM_UPD *mupd); - void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void *setup_stack_and_mtrrs(void); +/* Board type */ + enum BoardT{ + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 96debfd..6bc0682 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -144,27 +144,38 @@ u32 top_of_32bit_ram(void) const struct device *dev; const struct soc_intel_skylake_config *config; + top_of_ram = smm_region_start(); + /* * Check if Tseg has been initialized, we will use this as a flag * to check if the MRC is done, and only then continue to read the * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before * PRMRR_MASK MSR lock bit is set. */ - if (smm_region_start() == 0) + if (top_of_ram == 0) return 0; dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); config = dev->chip_info; /* - * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved + * On Kabylake, cbmem_top is offset down from PRMRR_BASE by reserved * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB) - * for PTT if enabled. PTT is in fact not used on Skylake platforms. + * for PTT if enabled. PTT is in fact not used on Kabylake platforms. * Refer to Fsp Integration Guide for the memory mapping layout. + * If SGX is enabled, then FSP updates PRMRR base & mask msr. + * Use value from PRMRR base msr to calculate top_of_ram. + * If PRMRR base is non-zero then top_of_ram is PRMRR base. */ + prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); - top_of_ram = prmrr_base.lo; + if ( prmrr_base.lo != 0) + top_of_ram = prmrr_base.lo; + /* + * If ProbelessTrace is enabled then + * top_of_ram is top_of_ram minus TRACE_MEMORY_SIZE. + */ if (config->ProbelessTrace) top_of_ram -= TRACE_MEMORY_SIZE; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8a15a69..781bfa7 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,29 +13,101 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <arch/early_variables.h> +#include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cbmem.h> +#include <chip.h> #include <console/console.h> +#include <device/pci_def.h> #include <fsp/util.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <timestamp.h> +#include <vboot/vboot_common.h> asmlinkage void *car_stage_c_entry(void) { - bool s3wake = false; + bool s3wake; + void *top_of_stack; + struct chipset_power_state *ps; + console_init(); - /* TODO: Add fill_powerstate and determine sleep state. */ + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + + ps = fill_power_state(); + timestamp_add_now(TS_START_ROMSTAGE); + s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - return NULL; + + top_of_stack = setup_stack_and_mtrrs(); + return top_of_stack; } + static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg) { - /* TODO: Fill SoC specific Memory init Params */ -} + const struct device *dev; + const struct soc_intel_skylake_config *config; + int i; + uint32_t mask = 0; -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){ + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + config = dev->chip_info; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->EnableTraceHub = config->EnableTraceHub; + if (vboot_recovery_mode_enabled()) + m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */ + else + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; // boardtype=ULT + m_cfg->SpdProfileSelected=0; //default profile selected + m_cfg->RMT = config->Rmt; + m_cfg->DdrFreqLimit = config->DdrFreqLimit; + m_cfg->VmxEnable = config->VmxEnable; + for (i=0; i < ARRAY_SIZE(config->PcieRpEnable); i++){ + if (config->PcieRpEnable[i] == 1) + mask|=(1<<i); + } + m_cfg->PcieRpEnableMask = mask; +} +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) +{ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + struct FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg); + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg =0x01; + m_t_cfg->DidInitStat =0x01; + mainboard_memory_init_params(mupd); + + /* Reserve enough memory under TOLUD to save CBMEM header */ + mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + } __attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/stack.c b/src/soc/intel/skylake/stack.c new file mode 100644 index 0000000..d5f5350 --- /dev/null +++ b/src/soc/intel/skylake/stack.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <fsp/memmap.h> +#include <soc/romstage.h> +#include <stdlib.h> +#include <program_loading.h> +#include <soc/intel/common/util.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + uint32_t max_mtrrs; + uint32_t num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Display the MTTRs */ + soc_display_mtrrs(); + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = romstage_ram_stack_top(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + max_mtrrs = soc_get_variable_mtrr_count(NULL); + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; +#endif + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Validate the MTRR usage */ + if (num_mtrrs > max_mtrrs) { + printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d", + max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs); + die("ERROR - MTRR use count incorrect!\n"); + } + + /* + * Save the number of MTRRs to setup and clear. Return the stack + * location pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + slot = stack_push32(slot, max_mtrrs); + return slot; +}

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Patch set updated for coreboot: kunimitsu: Add FSP 2.0 support in romstage
by Rizwan Qureshi 25 Aug '16

25 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16316 -gerrit commit d3d0cf8dee7137db121836589d5d8db53246eca0 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Wed Aug 24 20:50:54 2016 +0530 kunimitsu: Add FSP 2.0 support in romstage Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values. Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 3 + src/mainboard/intel/kunimitsu/romstage_fsp20.c | 81 +++++++++++++++++++++++++- 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 2aa3d95..a5789b0 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -187,6 +187,9 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_A7" diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index 10bdd21..c966f15 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -13,9 +13,88 @@ * GNU General Public License for more details. */ +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" #include <soc/romstage.h> +#include "spd/spd.h" +#include <string.h> + +#define RCOMP_TARGET_PARAMS 0x5 void mainboard_memory_init_params(struct FSPM_UPD *mupd) { - /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ + struct FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + char *spd_file; + size_t spd_file_len; + int spd_index, spd_span; + + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 , + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 6, 5, 4, 7 }, + { 2, 3, 0, 1, 6, 7, 4, 5 } }; + + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + /*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/ + //static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { + // 100, 40, 40, 21, 40 }; + + memcpy((void*)mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); + memcpy((void *)mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy((void*)mem_cfg->RcompResistor, RcompResistor, sizeof(RcompResistor)); + memcpy((void*)mem_cfg->RcompTarget, RcompTarget, sizeof(RcompTarget)); + mem_cfg->DqPinsInterleaved = 0; + + /* fill SPD Data */ + + /* PCH_MEM_CFG[3:0] */ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + + printk(BIOS_INFO, "SPD index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + /* Assume same memory in both channels */ + spd_span = spd_index * SPD_LEN; + + mem_cfg->MemorySpdPtr00 = ( uint32_t )spd_file + spd_span; + mem_cfg->MemorySpdPtr10 = (uint32_t)spd_file + spd_span; + mem_cfg->MemorySpdDataLen = SPD_LEN; }

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Patch set updated for coreboot: kunimitsu: Add initial FSP2.0 support
by Rizwan Qureshi 25 Aug '16

25 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301 -gerrit commit a5db310db958f53ee206a801fe9fec3106a9634d Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Aug 23 13:38:19 2016 +0530 kunimitsu: Add initial FSP2.0 support Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact. Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/intel/kunimitsu/Makefile.inc | 4 ++++ src/mainboard/intel/kunimitsu/ramstage.c | 2 +- src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++ src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +- 4 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc index cafa12c..86be420 100644 --- a/src/mainboard/intel/kunimitsu/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/Makefile.inc @@ -34,3 +34,7 @@ ramstage-y += pei_data.c ramstage-y += ramstage.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y) +romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs)) +endif diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 563c715..44fb9cd 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -16,7 +16,7 @@ #include <soc/ramstage.h> #include "gpio.h" -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c new file mode 100644 index 0000000..10bdd21 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> + +void mainboard_memory_init_params(struct FSPM_UPD *mupd) +{ + /* TODO: Read and copy SPD and fill up Rcomp and DQ param */ +} diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc index 62d6fd4..0a9cb0f 100644 --- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc +++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc @@ -14,7 +14,7 @@ ## GNU General Public License for more details. ## -romstage-y += spd.c +romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c SPD_BIN = $(obj)/spd.bin

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Patch set updated for coreboot: skylake: Add FSP 2.0 support in romstage
by Rizwan Qureshi 25 Aug '16

25 Aug '16

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16315 -gerrit commit 238814060a7026a55e390c52ff1956ff3433efaa Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Aug 24 20:48:46 2016 +0530 skylake: Add FSP 2.0 support in romstage Setup stack and MTRRs after Dram initialization. This setup code is present in FSP1.1 driver, copy and reuse stack.c. Populate SoC related Memory related params. Make sure FSP binaries are properly relocated to the base where they are placed in CBFS. i.e., Make them XIP. Minor correction in top of ram calculation. TEST=Build and boot kunimitsu, dram initialization done. ramstage is loaded. Change-Id: I8d943e29b6e118986189166d92c7891ab6642193 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 6 + src/soc/intel/skylake/chip.h | 4 + src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +- src/soc/intel/skylake/memmap.c | 19 ++- src/soc/intel/skylake/romstage/romstage_fsp20.c | 84 +++++++++- src/soc/intel/skylake/stack.c | 169 +++++++++++++++++++++ 6 files changed, 280 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index aa3da61..02b3ee8 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -42,6 +42,7 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += smbus_common.c +romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stack.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -104,6 +105,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake +$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_S_CBFS)-options := --xip endif # Currently used for microcode path. @@ -111,4 +114,7 @@ CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR) ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 +$(CONFIG_FSP_M_CBFS)-options := --xip +$(CONFIG_FSP_S_CBFS)-options := --xip + endif diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index a4dee51..62e28e6 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -359,6 +359,10 @@ struct soc_intel_skylake_config { * 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue */ u8 SendVrMbxCmd; + + /* Enable/Disable VMX feature */ + u8 VmxEnable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index d48ac67..253ee32 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -22,9 +22,16 @@ asmlinkage void *car_stage_c_entry(void); void mainboard_memory_init_params(struct FSPM_UPD *mupd); - void systemagent_early_init(void); int smbus_read_byte(unsigned device, unsigned address); int early_spi_read_wpsr(u8 *sr); +void *setup_stack_and_mtrrs(void); +/* Board type */ + enum BoardT{ + BOARD_TYPE_MOBILE = 0, + BOARD_TYPE_DESKTOP = 1, + BOARD_TYPE_ULT_ULX = 5, + BOARD_TYPE_SERVER = 7 +}; #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 96debfd..6bc0682 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -144,27 +144,38 @@ u32 top_of_32bit_ram(void) const struct device *dev; const struct soc_intel_skylake_config *config; + top_of_ram = smm_region_start(); + /* * Check if Tseg has been initialized, we will use this as a flag * to check if the MRC is done, and only then continue to read the * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before * PRMRR_MASK MSR lock bit is set. */ - if (smm_region_start() == 0) + if (top_of_ram == 0) return 0; dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); config = dev->chip_info; /* - * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved + * On Kabylake, cbmem_top is offset down from PRMRR_BASE by reserved * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB) - * for PTT if enabled. PTT is in fact not used on Skylake platforms. + * for PTT if enabled. PTT is in fact not used on Kabylake platforms. * Refer to Fsp Integration Guide for the memory mapping layout. + * If SGX is enabled, then FSP updates PRMRR base & mask msr. + * Use value from PRMRR base msr to calculate top_of_ram. + * If PRMRR base is non-zero then top_of_ram is PRMRR base. */ + prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); - top_of_ram = prmrr_base.lo; + if ( prmrr_base.lo != 0) + top_of_ram = prmrr_base.lo; + /* + * If ProbelessTrace is enabled then + * top_of_ram is top_of_ram minus TRACE_MEMORY_SIZE. + */ if (config->ProbelessTrace) top_of_ram -= TRACE_MEMORY_SIZE; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8a15a69..781bfa7 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -13,29 +13,101 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <arch/early_variables.h> +#include <arch/io.h> +#include <arch/symbols.h> +#include <assert.h> +#include <cpu/x86/mtrr.h> +#include <cbmem.h> +#include <chip.h> #include <console/console.h> +#include <device/pci_def.h> #include <fsp/util.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/romstage.h> +#include <timestamp.h> +#include <vboot/vboot_common.h> asmlinkage void *car_stage_c_entry(void) { - bool s3wake = false; + bool s3wake; + void *top_of_stack; + struct chipset_power_state *ps; + console_init(); - /* TODO: Add fill_powerstate and determine sleep state. */ + + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ + systemagent_early_init(); + + ps = fill_power_state(); + timestamp_add_now(TS_START_ROMSTAGE); + s3wake = ps->prev_sleep_state == ACPI_S3; fsp_memory_init(s3wake); - return NULL; + + top_of_stack = setup_stack_and_mtrrs(); + return top_of_stack; } + static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg) { - /* TODO: Fill SoC specific Memory init Params */ -} + const struct device *dev; + const struct soc_intel_skylake_config *config; + int i; + uint32_t mask = 0; -void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){ + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); + config = dev->chip_info; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + m_cfg->IgdDvmt50PreAlloc = 2; + m_cfg->MmioSize = 0x800; /* 2GB in MB */ + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; + m_cfg->IedSize = CONFIG_IED_REGION_SIZE; + m_cfg->ProbelessTrace = config->ProbelessTrace; + m_cfg->EnableTraceHub = config->EnableTraceHub; + if (vboot_recovery_mode_enabled()) + m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */ + else + m_cfg->SaGv = config->SaGv; + m_cfg->UserBd = BOARD_TYPE_ULT_ULX; // boardtype=ULT + m_cfg->SpdProfileSelected=0; //default profile selected + m_cfg->RMT = config->Rmt; + m_cfg->DdrFreqLimit = config->DdrFreqLimit; + m_cfg->VmxEnable = config->VmxEnable; + for (i=0; i < ARRAY_SIZE(config->PcieRpEnable); i++){ + if (config->PcieRpEnable[i] == 1) + mask|=(1<<i); + } + m_cfg->PcieRpEnableMask = mask; +} +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) +{ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; + struct FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; soc_memory_init_params(m_cfg); + + /* Enable DMI Virtual Channel for ME */ + m_t_cfg->DmiVcm = 0x01; + + /* Enable Sending DID to ME */ + m_t_cfg->SendDidMsg =0x01; + m_t_cfg->DidInitStat =0x01; + mainboard_memory_init_params(mupd); + + /* Reserve enough memory under TOLUD to save CBMEM header */ + mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + } __attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/stack.c b/src/soc/intel/skylake/stack.c new file mode 100644 index 0000000..d5f5350 --- /dev/null +++ b/src/soc/intel/skylake/stack.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <fsp/memmap.h> +#include <soc/romstage.h> +#include <stdlib.h> +#include <program_loading.h> +#include <soc/intel/common/util.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + uint32_t max_mtrrs; + uint32_t num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Display the MTTRs */ + soc_display_mtrrs(); + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = romstage_ram_stack_top(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + max_mtrrs = soc_get_variable_mtrr_count(NULL); + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + alignment = mmap_region_granularity(); + aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * +0: Number of variable MTRRs to clear + */ + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; +#endif + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Validate the MTRR usage */ + if (num_mtrrs > max_mtrrs) { + printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d", + max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs); + die("ERROR - MTRR use count incorrect!\n"); + } + + /* + * Save the number of MTRRs to setup and clear. Return the stack + * location pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + slot = stack_push32(slot, max_mtrrs); + return slot; +}

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coreboot-gerrit August 2016