Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16319
-gerrit
commit b6b2f9a9775029305f88f927f93e95046594f9b9
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Thu Aug 25 09:24:15 2016 +0200
mb/intel/d945gclf: Disable combined mode to fix SATA
Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4
"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
SATA must function in "plain" mode because it does not work in
"combined" mode.
Tested on d945gclf
Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/mainboard/intel/d945gclf/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
index 823a240..aa8c441 100644
--- a/src/mainboard/intel/d945gclf/devicetree.cb
+++ b/src/mainboard/intel/d945gclf/devicetree.cb
@@ -45,7 +45,7 @@ chip northbridge/intel/i945
register "gpi13_routing" = "1"
register "gpe0_en" = "0x20000601"
- register "ide_legacy_combined" = "0x1"
+ register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ahci" = "0x0"
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16315
-gerrit
commit 8c2344ec4782c78d7acd83780df73b8132bbc391
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Wed Aug 24 20:48:46 2016 +0530
skylake: Add FSP 2.0 support in romstage
Setup stack and MTRRs after Dram initialization. This
setup code is present in FSP1.1 driver, copy and reuse
stack.c.
Populate SoC related Memory related params.
Make sure FSP binaries are properly relocated to the base where
they are placed in CBFS. i.e., Make them XIP.
Minor correction in top of ram calculation.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/soc/intel/skylake/Makefile.inc | 6 +
src/soc/intel/skylake/chip.h | 4 +
src/soc/intel/skylake/include/fsp20/soc/romstage.h | 9 +-
src/soc/intel/skylake/memmap.c | 20 ++-
src/soc/intel/skylake/romstage/romstage_fsp20.c | 84 +++++++++-
src/soc/intel/skylake/stack.c | 169 +++++++++++++++++++++
6 files changed, 281 insertions(+), 11 deletions(-)
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index aa3da61..02b3ee8 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -42,6 +42,7 @@ romstage-y += pei_data.c
romstage-y += pmutil.c
romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += smbus_common.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += stack.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
@@ -104,6 +105,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
else
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
+$(CONFIG_FSP_M_CBFS)-options := --xip
+$(CONFIG_FSP_S_CBFS)-options := --xip
endif
# Currently used for microcode path.
@@ -111,4 +114,7 @@ CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR)
ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
+$(CONFIG_FSP_M_CBFS)-options := --xip
+$(CONFIG_FSP_S_CBFS)-options := --xip
+
endif
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a4dee51..62e28e6 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -359,6 +359,10 @@ struct soc_intel_skylake_config {
* 011b - VR specific command sent for both MPS IMPV8 & PS4 exit issue
*/
u8 SendVrMbxCmd;
+
+ /* Enable/Disable VMX feature */
+ u8 VmxEnable;
+
/* Statically clock gate 8254 PIT. */
u8 clock_gate_8254;
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
index d48ac67..253ee32 100644
--- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -22,9 +22,16 @@
asmlinkage void *car_stage_c_entry(void);
void mainboard_memory_init_params(struct FSPM_UPD *mupd);
-
void systemagent_early_init(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read_wpsr(u8 *sr);
+void *setup_stack_and_mtrrs(void);
+/* Board type */
+ enum BoardT{
+ BOARD_TYPE_MOBILE = 0,
+ BOARD_TYPE_DESKTOP = 1,
+ BOARD_TYPE_ULT_ULX = 5,
+ BOARD_TYPE_SERVER = 7
+};
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 96debfd..7c14598 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -144,31 +144,43 @@ u32 top_of_32bit_ram(void)
const struct device *dev;
const struct soc_intel_skylake_config *config;
+ top_of_ram = smm_region_start();
+
/*
* Check if Tseg has been initialized, we will use this as a flag
* to check if the MRC is done, and only then continue to read the
* PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before
* PRMRR_MASK MSR lock bit is set.
*/
- if (smm_region_start() == 0)
+ if (top_of_ram == 0)
return 0;
dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));
config = dev->chip_info;
/*
- * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved
+ * On Kabylake, cbmem_top is offset down from PRMRR_BASE by reserved
* memory (128MiB) for CPU trace if enabled, then reserved memory (4KB)
- * for PTT if enabled. PTT is in fact not used on Skylake platforms.
+ * for PTT if enabled. PTT is in fact not used on Kabylake platforms.
* Refer to Fsp Integration Guide for the memory mapping layout.
+ * If SGX is enabled, then FSP updates PRMRR base & mask msr.
+ * Use value from PRMRR base msr to calculate top_of_ram.
+ * If PRMRR base is non-zero then top_of_ram is PRMRR base.
*/
+
prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);
- top_of_ram = prmrr_base.lo;
+ if ( prmrr_base.lo != 0)
+ top_of_ram = prmrr_base.lo;
+ /*
+ * If ProbelessTrace is enabled then
+ * top_of_ram is top_of_ram minus TRACE_MEMORY_SIZE.
+ */
if (config->ProbelessTrace)
top_of_ram -= TRACE_MEMORY_SIZE;
return top_of_ram;
+
}
void *cbmem_top(void)
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 8a15a69..781bfa7 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -13,29 +13,101 @@
* GNU General Public License for more details.
*/
+#include <arch/cpu.h>
+#include <arch/early_variables.h>
+#include <arch/io.h>
+#include <arch/symbols.h>
+#include <assert.h>
+#include <cpu/x86/mtrr.h>
+#include <cbmem.h>
+#include <chip.h>
#include <console/console.h>
+#include <device/pci_def.h>
#include <fsp/util.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
#include <soc/romstage.h>
+#include <timestamp.h>
+#include <vboot/vboot_common.h>
asmlinkage void *car_stage_c_entry(void)
{
- bool s3wake = false;
+ bool s3wake;
+ void *top_of_stack;
+ struct chipset_power_state *ps;
+
console_init();
- /* TODO: Add fill_powerstate and determine sleep state. */
+
+ /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+ systemagent_early_init();
+
+ ps = fill_power_state();
+ timestamp_add_now(TS_START_ROMSTAGE);
+ s3wake = ps->prev_sleep_state == ACPI_S3;
fsp_memory_init(s3wake);
- return NULL;
+
+ top_of_stack = setup_stack_and_mtrrs();
+ return top_of_stack;
}
+
static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
{
- /* TODO: Fill SoC specific Memory init Params */
-}
+ const struct device *dev;
+ const struct soc_intel_skylake_config *config;
+ int i;
+ uint32_t mask = 0;
-void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){
+ /* Set the parameters for MemoryInit */
+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ config = dev->chip_info;
+ /*
+ * Set IGD stolen size to 64MB. The FBC hardware for skylake does not
+ * have access to the bios_reserved range so it always assumes 8MB is
+ * used and so the kernel will avoid the last 8MB of the stolen window.
+ * With the default stolen size of 32MB(-8MB) there is not enough space
+ * for FBC to work with a high resolution panel.
+ */
+ m_cfg->IgdDvmt50PreAlloc = 2;
+ m_cfg->MmioSize = 0x800; /* 2GB in MB */
+ m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;
+ m_cfg->IedSize = CONFIG_IED_REGION_SIZE;
+ m_cfg->ProbelessTrace = config->ProbelessTrace;
+ m_cfg->EnableTraceHub = config->EnableTraceHub;
+ if (vboot_recovery_mode_enabled())
+ m_cfg->SaGv = 0; /* Disable SaGv in recovery mode. */
+ else
+ m_cfg->SaGv = config->SaGv;
+ m_cfg->UserBd = BOARD_TYPE_ULT_ULX; // boardtype=ULT
+ m_cfg->SpdProfileSelected=0; //default profile selected
+ m_cfg->RMT = config->Rmt;
+ m_cfg->DdrFreqLimit = config->DdrFreqLimit;
+ m_cfg->VmxEnable = config->VmxEnable;
+ for (i=0; i < ARRAY_SIZE(config->PcieRpEnable); i++){
+ if (config->PcieRpEnable[i] == 1)
+ mask|=(1<<i);
+ }
+ m_cfg->PcieRpEnableMask = mask;
+}
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd)
+{
struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ struct FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
soc_memory_init_params(m_cfg);
+
+ /* Enable DMI Virtual Channel for ME */
+ m_t_cfg->DmiVcm = 0x01;
+
+ /* Enable Sending DID to ME */
+ m_t_cfg->SendDidMsg =0x01;
+ m_t_cfg->DidInitStat =0x01;
+
mainboard_memory_init_params(mupd);
+
+ /* Reserve enough memory under TOLUD to save CBMEM header */
+ mupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size();
+
}
__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd)
diff --git a/src/soc/intel/skylake/stack.c b/src/soc/intel/skylake/stack.c
new file mode 100644
index 0000000..d5f5350
--- /dev/null
+++ b/src/soc/intel/skylake/stack.c
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <fsp/memmap.h>
+#include <soc/romstage.h>
+#include <stdlib.h>
+#include <program_loading.h>
+#include <soc/intel/common/util.h>
+
+static inline void *stack_push32(void *stack, uint32_t value)
+{
+ uint32_t *stack32 = stack;
+
+ stack32 = &stack32[-1];
+ *stack32 = value;
+ return stack32;
+}
+
+/*
+ * setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use.
+ */
+void *setup_stack_and_mtrrs(void)
+{
+ size_t alignment;
+ uint32_t aligned_ram;
+ uint32_t mtrr_mask_upper;
+ uint32_t max_mtrrs;
+ uint32_t num_mtrrs;
+ uint32_t *slot;
+ unsigned long top_of_stack;
+
+ /* Display the MTTRs */
+ soc_display_mtrrs();
+
+ /* Top of stack needs to be aligned to a 8-byte boundary. */
+ top_of_stack = romstage_ram_stack_top();
+ slot = (void *)top_of_stack;
+ num_mtrrs = 0;
+ max_mtrrs = soc_get_variable_mtrr_count(NULL);
+
+ /*
+ * The upper bits of the MTRR mask need to set according to the number
+ * of physical address bits.
+ */
+ mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
+ alignment = mmap_region_granularity();
+ aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment);
+
+ /*
+ * The order for each MTRR is value then base with upper 32-bits of
+ * each value coming before the lower 32-bits. The reasoning for
+ * this ordering is to create a stack layout like the following:
+ *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+ /*
+ * +-------------------------+ Top of RAM (aligned)
+ * | System Management Mode |
+ * | code and data | Length: CONFIG_TSEG_SIZE
+ * | (TSEG) |
+ * +-------------------------+ SMM base (aligned)
+ * | |
+ * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
+ * | |
+ * +-------------------------+ top_of_ram (aligned)
+ * | |
+ * | CBMEM Root |
+ * | |
+ * +-------------------------+
+ * | |
+ * | FSP Reserved Memory |
+ * | |
+ * +-------------------------+
+ * | |
+ * | Various CBMEM Entries |
+ * | |
+ * +-------------------------+ top_of_stack (8 byte aligned)
+ * | |
+ * | stack (CBMEM Entry) |
+ * | |
+ * +-------------------------+
+ */
+
+ /*
+ * Cache the stack and the other CBMEM entries as well as part or all
+ * of the FSP reserved memory region.
+ */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+
+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
+ void *smm_base;
+ size_t smm_size;
+ uint32_t tseg_base;
+
+ /*
+ * Cache the TSEG region at the top of ram. This region is not
+ * restricted to SMM mode until SMM has been relocated. By setting
+ * the region to cacheable it provides faster access when relocating
+ * the SMM handler as well as using the TSEG region for other purposes.
+ */
+ smm_region(&smm_base, &smm_size);
+ tseg_base = (uint32_t)smm_base;
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
+ num_mtrrs++;
+#endif
+
+ /* Cache the ROM as WP just below 4GiB. */
+ slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
+ slot = stack_push32(slot, 0); /* upper base */
+ slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
+ num_mtrrs++;
+
+ /* Validate the MTRR usage */
+ if (num_mtrrs > max_mtrrs) {
+ printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d",
+ max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs);
+ die("ERROR - MTRR use count incorrect!\n");
+ }
+
+ /*
+ * Save the number of MTRRs to setup and clear. Return the stack
+ * location pointing to the number of MTRRs.
+ */
+ slot = stack_push32(slot, num_mtrrs);
+ slot = stack_push32(slot, max_mtrrs);
+ return slot;
+}
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301
-gerrit
commit fcda24bd6cb2ff7199556a1df0902cb5355b9825
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 13:38:19 2016 +0530
kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.
Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/mainboard/intel/kunimitsu/Makefile.inc | 5 +++++
src/mainboard/intel/kunimitsu/ramstage.c | 2 +-
src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
4 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index cafa12c..3f58061 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -34,3 +34,8 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
+endif
+
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..44fb9cd 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
new file mode 100644
index 0000000..10bdd21
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* TODO: Read and copy SPD and fill up Rcomp and DQ param */
+}
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 62d6fd4..0a9cb0f 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
-romstage-y += spd.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16301
-gerrit
commit 47d5f6a3b50451b5f45a9432003165cdbd1e4594
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 13:38:19 2016 +0530
kunimitsu: Add initial FSP2.0 support
Add placeholders for functions required when skylake
uses FSP2.0 driver, keeping the fsp1.1 flow intact.
Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/mainboard/intel/kunimitsu/Makefile.inc | 5 +++++
src/mainboard/intel/kunimitsu/ramstage.c | 2 +-
src/mainboard/intel/kunimitsu/romstage_fsp20.c | 21 +++++++++++++++++++++
src/mainboard/intel/kunimitsu/spd/Makefile.inc | 2 +-
4 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index cafa12c..3f58061 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -34,3 +34,8 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-srcs := $(subst $(MAINBOARDDIR)/romstage.c,$(MAINBOARDDIR)/romstage_fsp20.c,$(romstage-srcs))
+endif
+
diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
index 563c715..44fb9cd 100644
--- a/src/mainboard/intel/kunimitsu/ramstage.c
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -16,7 +16,7 @@
#include <soc/ramstage.h>
#include "gpio.h"
-void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
/* Configure pads prior to SiliconInit() in case there's any
* dependencies during hardware initialization. */
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
new file mode 100644
index 0000000..10bdd21
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* TODO: Read and copy SPD and fill up Rcomp and DQ param */
+}
diff --git a/src/mainboard/intel/kunimitsu/spd/Makefile.inc b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
index 62d6fd4..0a9cb0f 100644
--- a/src/mainboard/intel/kunimitsu/spd/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/spd/Makefile.inc
@@ -14,7 +14,7 @@
## GNU General Public License for more details.
##
-romstage-y += spd.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += spd.c
SPD_BIN = $(obj)/spd.bin
Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16267
-gerrit
commit 7454cf199264a6a93fc1a5fdd1c6096dee56d3e6
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Tue Aug 23 14:31:23 2016 +0530
skylake: Add initial FSP2.0 support
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.
The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
Also add monotonic_timer.c to verstage.
With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/soc/intel/skylake/Kconfig | 1 +
src/soc/intel/skylake/Makefile.inc | 13 +-
src/soc/intel/skylake/chip_fsp20.c | 30 +++++
src/soc/intel/skylake/igd.c | 29 +----
src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 36 ++++++
src/soc/intel/skylake/include/fsp11/soc/romstage.h | 30 +++++
src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 39 ++++++
src/soc/intel/skylake/include/fsp20/soc/romstage.h | 30 +++++
src/soc/intel/skylake/include/soc/ramstage.h | 31 -----
src/soc/intel/skylake/include/soc/romstage.h | 30 -----
src/soc/intel/skylake/include/soc/smm.h | 1 -
src/soc/intel/skylake/include/soc/vr_config.h | 9 +-
src/soc/intel/skylake/memmap.c | 1 -
src/soc/intel/skylake/opregion.c | 49 ++++++++
src/soc/intel/skylake/reset.c | 32 +++++
src/soc/intel/skylake/romstage/Makefile.inc | 5 +-
src/soc/intel/skylake/romstage/car_stage.S | 131 +++++++++++++++++++++
src/soc/intel/skylake/romstage/romstage_fsp20.c | 44 +++++++
src/soc/intel/skylake/vr_config.c | 27 +++--
19 files changed, 460 insertions(+), 108 deletions(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 6171c41..edf5db3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
select RTC
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON_LPSS_I2C
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index 716c3d5..aa3da61 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -40,12 +40,14 @@ romstage-y += pch.c
romstage-y += pcr.c
romstage-y += pei_data.c
romstage-y += pmutil.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
romstage-y += smbus_common.c
romstage-y += tsc_freq.c
romstage-$(CONFIG_UART_DEBUG) += uart_debug.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
-ramstage-y += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += chip_fsp20.c
ramstage-y += cpu.c
ramstage-y += cpu_info.c
ramstage-y += dsp.c
@@ -59,12 +61,14 @@ ramstage-y += lpc.c
ramstage-y += me_status.c
ramstage-y += memmap.c
ramstage-y += monotonic_timer.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += opregion.c
ramstage-y += pch.c
ramstage-y += pcie.c
ramstage-y += pcr.c
ramstage-y += pei_data.c
ramstage-y += pmc.c
ramstage-y += pmutil.c
+ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
ramstage-y += ramstage.c
ramstage-y += sd.c
ramstage-y += smbus.c
@@ -93,7 +97,14 @@ smm-$(CONFIG_UART_DEBUG) += uart_debug.c
CPPFLAGS_common += -I$(src)/soc/intel/skylake
CPPFLAGS_common += -I$(src)/soc/intel/skylake/include
+
+ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y)
+CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp11
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake
+else
+CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20
+CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake
+endif
# Currently used for microcode path.
CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(MAINBOARD_DIR)
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
new file mode 100644
index 0000000..215530c
--- /dev/null
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <chip.h>
+#include <bootstate.h>
+#include <device/pci.h>
+#include <fsp/api.h>
+
+/* UPD parameters to be initialized before SiliconInit */
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd)
+{
+}
+
+struct pci_operations soc_pci_ops = {
+ /* TODO: Add set subsystem id function */
+};
+
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index 3e29ab0..969f386 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -24,7 +24,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <drivers/intel/gma/i915_reg.h>
-#include <fsp/gop.h>
#include <soc/acpi.h>
#include <soc/cpu.h>
#include <soc/pm.h>
@@ -117,35 +116,10 @@ static void igd_init(struct device *dev)
}
/* Initialize IGD OpRegion, called from ACPI code */
-static int init_igd_opregion(igd_opregion_t *opregion)
+static int update_igd_opregion(igd_opregion_t *opregion)
{
- const optionrom_vbt_t *vbt;
- uint32_t vbt_len;
u16 reg16;
- memset(opregion, 0, sizeof(igd_opregion_t));
-
- /* Read VBT table from flash */
- vbt = fsp_get_vbt(&vbt_len);
- if (!vbt)
- die("vbt data not found");
-
- memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
- sizeof(IGD_OPREGION_SIGNATURE) - 1);
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
- memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
- sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
- sizeof(opregion->vbt.gvd1));
-
- /* Size, in KB, of the entire OpRegion structure (including header)*/
- opregion->header.size = sizeof(igd_opregion_t) / KiB;
- opregion->header.version = IGD_OPREGION_VERSION;
-
- /* We just assume we're mobile for now */
- opregion->header.mailboxes = MAILBOXES_MOBILE;
-
- /* TODO Initialize Mailbox 1 */
-
/* Initialize Mailbox 3 */
opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
@@ -189,6 +163,7 @@ static unsigned long write_acpi_igd_opregion(device_t device,
printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
opregion = (igd_opregion_t *)current;
init_igd_opregion(opregion);
+ update_igd_opregion(opregion);
current += sizeof(igd_opregion_t);
current = acpi_align_current(current);
diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
new file mode 100644
index 0000000..e469554
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+#include <fsp/gop.h>
+#include <fsp/ramstage.h>
+#include <fsp/soc_binding.h>
+
+#define FSP_SIL_UPD SILICON_INIT_UPD
+#define FSP_MEM_UPD MEMORY_INIT_UPD
+
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+int init_igd_opregion(igd_opregion_t *igd_opregion);
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
new file mode 100644
index 0000000..6c40bd6
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/romstage.h>
+
+void systemagent_early_init(void);
+void intel_early_me_status(void);
+void enable_smbus(void);
+int smbus_read_byte(unsigned device, unsigned address);
+
+int early_spi_read_wpsr(u8 *sr);
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
new file mode 100644
index 0000000..3a9d96b
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <chip.h>
+#include <device/device.h>
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/intel/common/opregion.h>
+
+#define FSP_SIL_UPD struct FSP_S_CONFIG
+#define FSP_MEM_UPD struct FSP_M_CONFIG
+
+void intel_silicon_init(void);
+void mainboard_silicon_init_params(struct FSP_S_CONFIG *params);
+void pch_enable_dev(device_t dev);
+void soc_init_pre_device(void *chip_info);
+void soc_init_cpus(device_t dev);
+const char *soc_acpi_name(struct device *dev);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif
diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
new file mode 100644
index 0000000..d48ac67
--- /dev/null
+++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <arch/cpu.h>
+#include <fsp/api.h>
+
+asmlinkage void *car_stage_c_entry(void);
+void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+
+void systemagent_early_init(void);
+int smbus_read_byte(unsigned device, unsigned address);
+int early_spi_read_wpsr(u8 *sr);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/ramstage.h b/src/soc/intel/skylake/include/soc/ramstage.h
deleted file mode 100644
index 55f9972..0000000
--- a/src/soc/intel/skylake/include/soc/ramstage.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RAMSTAGE_H_
-#define _SOC_RAMSTAGE_H_
-
-#include <chip.h>
-#include <device/device.h>
-#include <fsp/ramstage.h>
-
-void pch_enable_dev(device_t dev);
-void soc_init_pre_device(void *chip_info);
-void soc_init_cpus(device_t dev);
-const char *soc_acpi_name(struct device *dev);
-
-extern struct pci_operations soc_pci_ops;
-
-#endif
diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h
deleted file mode 100644
index 6c40bd6..0000000
--- a/src/soc/intel/skylake/include/soc/romstage.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015-2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_ROMSTAGE_H_
-#define _SOC_ROMSTAGE_H_
-
-#include <fsp/romstage.h>
-
-void systemagent_early_init(void);
-void intel_early_me_status(void);
-void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
-
-int early_spi_read_wpsr(u8 *sr);
-void mainboard_fill_spd_data(struct pei_data *pei_data);
-
-#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/smm.h b/src/soc/intel/skylake/include/soc/smm.h
index fa8da46..1beaaa4 100644
--- a/src/soc/intel/skylake/include/soc/smm.h
+++ b/src/soc/intel/skylake/include/soc/smm.h
@@ -20,7 +20,6 @@
#include <stdint.h>
#include <cpu/x86/msr.h>
#include <fsp/memmap.h>
-#include <fsp/romstage.h>
#include <soc/gpio.h>
struct ied_header {
diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h
index d70fd21..1c19b88 100644
--- a/src/soc/intel/skylake/include/soc/vr_config.h
+++ b/src/soc/intel/skylake/include/soc/vr_config.h
@@ -19,7 +19,11 @@
#ifndef _SOC_VR_CONFIG_H_
#define _SOC_VR_CONFIG_H_
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
#include <fsp/soc_binding.h>
+#else
+#include <fsp/api.h>
+#endif
struct vr_config {
@@ -74,7 +78,6 @@ enum vr_domain{
NUM_VR_DOMAINS
};
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
- const struct vr_config *cfg);
-
+void fill_vr_domain_config(void *params,
+ int domain, const struct vr_config *cfg);
#endif
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index 6af1371..96debfd 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -21,7 +21,6 @@
#include <device/pci.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
-#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/systemagent.h>
#include <stdlib.h>
diff --git a/src/soc/intel/skylake/opregion.c b/src/soc/intel/skylake/opregion.c
new file mode 100644
index 0000000..31987cb
--- /dev/null
+++ b/src/soc/intel/skylake/opregion.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/ramstage.h>
+#include <fsp/gop.h>
+#include <stdlib.h>
+#include <string.h>
+
+int init_igd_opregion(igd_opregion_t *opregion)
+{
+ const optionrom_vbt_t *vbt;
+ uint32_t vbt_len;
+
+ memset(opregion, 0, sizeof(igd_opregion_t));
+
+ /* Read VBT table from flash */
+ vbt = fsp_get_vbt(&vbt_len);
+ if (!vbt)
+ die("vbt data not found");
+
+ memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
+ sizeof(IGD_OPREGION_SIGNATURE) - 1);
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
+ memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
+ sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
+ sizeof(opregion->vbt.gvd1));
+
+ /* Size, in KB, of the entire OpRegion structure (including header)*/
+ opregion->header.size = sizeof(igd_opregion_t) / KiB;
+ opregion->header.version = IGD_OPREGION_VERSION;
+
+ /* We just assume we're mobile for now */
+ opregion->header.mailboxes = MAILBOXES_MOBILE;
+
+ return 0;
+}
diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c
new file mode 100644
index 0000000..ab251ce
--- /dev/null
+++ b/src/soc/intel/skylake/reset.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <reset.h>
+
+void chipset_handle_reset(enum fsp_status status)
+{
+ switch(status) {
+ case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
+ printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
+ hard_reset();
+ break;
+ default:
+ printk(BIOS_ERR, "unhandled reset type %x\n", status);
+ die("unknown reset type");
+ break;
+ }
+}
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 31a452f..e552c39 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,7 +1,8 @@
-
verstage-y += power_state.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += car_stage.S
romstage-y += power_state.c
-romstage-y += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c
romstage-y += spi.c
romstage-y += systemagent.c
diff --git a/src/soc/intel/skylake/romstage/car_stage.S b/src/soc/intel/skylake/romstage/car_stage.S
new file mode 100644
index 0000000..c6401fa
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/car_stage.S
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <rules.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/post_code.h>
+
+.section ".text"
+.global car_stage_entry
+
+car_stage_entry:
+
+ /* Enter the C code */
+ call car_stage_c_entry
+
+/*
+ * Car teardown
+ */
+ /*
+ * eax: New stack address
+ */
+
+ /* Switch to the stack in RAM */
+ movl %eax, %esp
+
+ #include <soc/car_teardown.S>
+
+ /* Display the MTRRs */
+ call soc_display_mtrrs
+
+ /*
+ * The stack contents are initialized in src/soc/intel/common/stack.c
+ * to be the following:
+ *
+ * *
+ * *
+ * *
+ * +36: MTRR mask 1 63:32
+ * +32: MTRR mask 1 31:0
+ * +28: MTRR base 1 63:32
+ * +24: MTRR base 1 31:0
+ * +20: MTRR mask 0 63:32
+ * +16: MTRR mask 0 31:0
+ * +12: MTRR base 0 63:32
+ * +8: MTRR base 0 31:0
+ * +4: Number of MTRRs to setup (described above)
+ * +0: Number of variable MTRRs to clear
+ */
+
+ /* Clear all of the variable MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+ clr %eax
+ clr %edx
+
+1:
+ testl %ebx, %ebx
+ jz 1f
+ wrmsr /* Write MTRR base. */
+ inc %ecx
+ wrmsr /* Write MTRR mask. */
+ inc %ecx
+ dec %ebx
+ jmp 1b
+
+1:
+ /* Get number of MTRRs. */
+ popl %ebx
+ movl $MTRR_PHYS_BASE(0), %ecx
+2:
+ testl %ebx, %ebx
+ jz 2f
+
+ /* Low 32 bits of MTRR base. */
+ popl %eax
+ /* Upper 32 bits of MTRR base. */
+ popl %edx
+ /* Write MTRR base. */
+ wrmsr
+ inc %ecx
+ /* Low 32 bits of MTRR mask. */
+ popl %eax
+ /* Upper 32 bits of MTRR mask. */
+ popl %edx
+ /* Write MTRR mask. */
+ wrmsr
+ inc %ecx
+
+ dec %ebx
+ jmp 2b
+2:
+
+ post_code(0x39)
+
+ /* And enable cache again after setting MTRRs. */
+ movl %cr0, %eax
+ andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
+ movl %eax, %cr0
+
+ post_code(0x3a)
+
+ /* Enable MTRR. */
+ movl $MTRR_DEF_TYPE_MSR, %ecx
+ rdmsr
+ orl $MTRR_DEF_TYPE_EN, %eax
+ wrmsr
+
+ post_code(0x3b)
+
+ /* Invalidate the cache again. */
+ invd
+
+__main:
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
+
+ call copy_and_run
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
new file mode 100644
index 0000000..8a15a69
--- /dev/null
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/romstage.h>
+
+asmlinkage void *car_stage_c_entry(void)
+{
+ bool s3wake = false;
+ console_init();
+ /* TODO: Add fill_powerstate and determine sleep state. */
+ fsp_memory_init(s3wake);
+ return NULL;
+}
+static void soc_memory_init_params(struct FSP_M_CONFIG *m_cfg)
+{
+ /* TODO: Fill SoC specific Memory init Params */
+}
+
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd){
+
+ struct FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+
+ soc_memory_init_params(m_cfg);
+ mainboard_memory_init_params(mupd);
+}
+
+__attribute__((weak)) void mainboard_memory_init_params(struct FSPM_UPD *mupd)
+{
+ /* Do nothing */
+}
diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c
index 40223e3..17ccd7d 100644
--- a/src/soc/intel/skylake/vr_config.c
+++ b/src/soc/intel/skylake/vr_config.c
@@ -14,6 +14,8 @@
*
*/
+#include <fsp/api.h>
+#include <soc/ramstage.h>
#include <soc/vr_config.h>
/* Default values for domain configuration. PSI3 and PSI4 are disabled. */
@@ -80,9 +82,10 @@ static const struct vr_config default_configs[NUM_VR_DOMAINS] = {
},
};
-void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
- const struct vr_config *chip_cfg)
+void fill_vr_domain_config(void *params,
+ int domain, const struct vr_config *chip_cfg)
{
+ FSP_SIL_UPD *vr_params = (FSP_SIL_UPD *)params;
const struct vr_config *cfg;
if (domain < 0 || domain >= NUM_VR_DOMAINS)
@@ -94,14 +97,14 @@ void fill_vr_domain_config(SILICON_INIT_UPD *params, int domain,
else
cfg = &default_configs[domain];
- params->VrConfigEnable[domain] = cfg->vr_config_enable;
- params->Psi1Threshold[domain] = cfg->psi1threshold;
- params->Psi2Threshold[domain] = cfg->psi2threshold;
- params->Psi3Threshold[domain] = cfg->psi3threshold;
- params->Psi3Enable[domain] = cfg->psi3enable;
- params->Psi4Enable[domain] = cfg->psi4enable;
- params->ImonSlope[domain] = cfg->imon_slope;
- params->ImonOffset[domain] = cfg->imon_offset;
- params->IccMax[domain] = cfg->icc_max;
- params->VrVoltageLimit[domain] = cfg->voltage_limit;
+ vr_params->VrConfigEnable[domain] = cfg->vr_config_enable;
+ vr_params->Psi1Threshold[domain] = cfg->psi1threshold;
+ vr_params->Psi2Threshold[domain] = cfg->psi2threshold;
+ vr_params->Psi3Threshold[domain] = cfg->psi3threshold;
+ vr_params->Psi3Enable[domain] = cfg->psi3enable;
+ vr_params->Psi4Enable[domain] = cfg->psi4enable;
+ vr_params->ImonSlope[domain] = cfg->imon_slope;
+ vr_params->ImonOffset[domain] = cfg->imon_offset;
+ vr_params->IccMax[domain] = cfg->icc_max;
+ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit;
}