coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/reef: Add DA7219 support in acpi
by HARSHAPRIYA N 01 Jul '16

01 Jul '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15436 -gerrit commit 9a22b0693a257c2e41580aaab9b2a145d6ae6063 Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Thu Jun 16 15:05:02 2016 -0700 google/reef: Add DA7219 support in acpi Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/acpi/mainboard.asl | 61 ++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 5471488..ca6dace 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -15,6 +15,7 @@ #include "acpi/superio.asl" #include "../gpio.h" +#include <on_board.h> Scope (\_SB) { @@ -84,3 +85,63 @@ Scope (\_SB.PCI0.LPCB) #include <drivers/pc80/tpm/acpi/tpm.asl> #include "ec.asl" } + +Scope (\_SB.PCI0.I2C0) +{ + /* Headphone Codec */ + Device (HPDA) + { + Name (_HID, "DLGS7219") + Name (_DDN, "Dialog DA7219 Codec") + Name (_UID, 1) + Name (_S0W, 4) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "dlg,micbias-lvl", 2600 }, + Package () { "dlg,mic-amp-in-sel", "diff" }, + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () {"da7219_aad", "DAAD"}, + } + }) + + Name (DAAD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "dlg,btn-cfg", 50 }, + Package () { "dlg,mic-det-thr", 500 }, + Package () { "dlg,jack-ins-deb", 20 }, + Package () { "dlg,jack-det-rate", "32ms_64ms" }, + Package () { "dlg,jack-rem-deb", 1 }, + Package () { "dlg,a-d-btn-thr", 0xa }, + Package () { "dlg,d-b-btn-thr", 0x16 }, + Package () { "dlg,b-c-btn-thr", 0x21 }, + Package () { "dlg,c-mic-btn-thr", 0x3E }, + Package () { "dlg,btn-avg", 4 }, + Package () { "dlg,adc-1bit-rpt", 1 }, + } + }) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_HP_MIC_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C0", + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_HP_MIC_CODEC_IRQ + } + }) + + Method (_STA) + { + Return (0xF) + } + } +}

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Patch set updated for coreboot: google/reef: Add Maxim98357a support
by HARSHAPRIYA N 01 Jul '16

01 Jul '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15435 -gerrit commit 9b09a399315f8197373676cff0f423c092bd63f8 Author: Harsha Priya <harshapriya.n(a)intel.com> Date: Fri Jun 24 17:13:54 2016 -0700 google/reef: Add Maxim98357a support Adds Maxim98357a support for reef using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/devicetree.cb | 7 ++++++- src/soc/intel/apollolake/Kconfig | 1 + 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d64598d..bce6dce 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -45,4 +45,7 @@ config UART_FOR_CONSOLE int default 2 +config DRIVERS_GENERIC_MAX98357A + default y + endif # BOARD_GOOGLE_REEF diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index d2b295f..4a3c8a3 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -46,7 +46,12 @@ chip soc/intel/apollolake device pci 0d.1 on end # - PMC device pci 0d.2 on end # - SPI device pci 0d.3 on end # - Shared SRAM - device pci 0e.0 on end # - Audio + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(114)" + device generic 0 on end + end + end device pci 11.0 on end # - ISH device pci 12.0 off end # - SATA device pci 13.0 off end # - Root Port 2 - PCIe-A 0 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 98ce7d8..9317827 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -50,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select SOC_INTEL_COMMON_GFX_OPREGION select ADD_VBT_DATA_FILE + select DRIVERS_GENERIC_MAX98357A config TPM_ON_FAST_SPI bool

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Patch merged into coreboot/master: AGESA boards: Fix split to romstage and ramstage
by gerrit＠coreboot.org 01 Jul '16

01 Jul '16

the following patch was just integrated into master: commit 6aa45c090bf8f52fd531f24d3347fdbf70f3b7a8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jun 24 16:37:05 2016 +0300 AGESA boards: Fix split to romstage and ramstage Boards broken with commit: 062ef1c AGESA boards: Split dispatcher to romstage and ramstage Boot failure with asus/f2a85-m witnessed around MemMS3Save() call, message "Save memory S3 data in heap" in verbose agesa logs was replaced by a system reset. Default stubs for MemS3ResumeConstructNBBlock() returned TRUE without initializing the block contents. This would not work for case with multiple NB support built into same firmware. MemMCreateS3NbBlock() then returned with S3NBPtr!=NULL with uninitialized data and MemMContextSave() referenced those as invalid pointers. There is no reason to prevent booting in the case S3 resume data is not passed to ramstage, so remove the ASSERT(). It only affects builds with IDSOPT_IDS_ENABLED=TRUE anyways. Change-Id: I8fd1e308ceab2b6f4b4c90f0f712934c2918d92d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/15344 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See https://review.coreboot.org/15344 for details. -gerrit

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New patch to review for coreboot: apollolake: Add Audio DSP device
by HARSHAPRIYA N 01 Jul '16

01 Jul '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15528 -gerrit commit 82e4fa14a5a9f9266486a838a6bf647d400490ca Author: Harsha Priya <harshapriya.n(a)intel.com> Date: Fri Jul 1 11:53:05 2016 -0700 apollolake: Add Audio DSP device Add the Audio DSP device for apollolake as a PCI driver with a static scan_bus handler so generic devices can be declared under it. This is for devices like the Maxim 98357A which is connected on the I2S bus for data but has no control channel bus and instead just has a GPIO for channel selection and power down control and needs to describe that GPIO connection to the OS via ACPI. Change-Id: Icb97ccf7d6a9034877614d49166bc9e4fe659b12 --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/dsp.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7326f14..ae12b08 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -43,6 +43,7 @@ smm-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c +ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/dsp.c b/src/soc/intel/apollolake/dsp.c new file mode 100644 index 0000000..ae4723b --- /dev/null +++ b/src/soc/intel/apollolake/dsp.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static struct device_operations dsp_dev_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_static_bus, +}; + +static const struct pci_driver apollolake_dsp __pci_driver = { + .ops = &dsp_dev_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x5a98 +}; + +

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Patch set updated for coreboot: google/reef: Make the device address more readable
by HARSHAPRIYA N 01 Jul '16

01 Jul '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15434 -gerrit commit d3ea0deab9b65a152fd18d92596adea06fb4c823 Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Thu Jun 16 14:40:17 2016 -0700 google/reef: Make the device address more readable Using central header file to include device address and interrupt line to avoid confusion. Change-Id: Ie0eae6e88db29ab9dc628f8c3fc0178b085b5536 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/on_board.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/mainboard/google/reef/on_board.h b/src/mainboard/google/reef/on_board.h new file mode 100644 index 0000000..3c2af96 --- /dev/null +++ b/src/mainboard/google/reef/on_board.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _ON_BOARD_H_ +#define _ON_BOARD_H_ + +#include <soc/gpio_defs.h> + +#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a +#define BOARD_HP_MIC_CODEC_IRQ 0x5b + +#endif /* _ON_BOARD_H_ */

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Patch set updated for coreboot: cbgfx: Use memset() for faster screen clearing if possible
by Julius Werner 01 Jul '16

01 Jul '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15524 -gerrit commit af4a9748381fe282c0b9c01bfaad49676a6b221a Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jun 30 22:34:57 2016 -0700 cbgfx: Use memset() for faster screen clearing if possible cbgfx currently makes a separate function call (recomputing some values) for every single pixel it draws. While we mostly don't care that much about display speed, this can become an issue if you're trying to paint the whole screen white on a lowly-clocked Cortex-A53. As a simple solution for these extreme cases, we can build a fast path into clear_screen() that just memset()s the whole framebuffer if the color and pixel format allow it. BUG=chrome-os-partner:54416 TEST=Screen drawing speed on Kevin visibly improves (from 2.5s to 3ms). Change-Id: I22f032afbb86b96fa5a0cbbdce8526a905c67b58 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- payloads/libpayload/drivers/video/graphics.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/payloads/libpayload/drivers/video/graphics.c b/payloads/libpayload/drivers/video/graphics.c index 01e3565..943f8ed 100644 --- a/payloads/libpayload/drivers/video/graphics.c +++ b/payloads/libpayload/drivers/video/graphics.c @@ -223,16 +223,24 @@ int clear_canvas(const struct rgb_color *rgb) int clear_screen(const struct rgb_color *rgb) { - uint32_t color; - struct vector p; - if (cbgfx_init()) return CBGFX_ERROR_INIT; - color = calculate_color(rgb); - for (p.y = 0; p.y < screen.size.height; p.y++) - for (p.x = 0; p.x < screen.size.width; p.x++) - set_pixel(&p, color); + struct vector p; + uint32_t color = calculate_color(rgb); + const int bpp = fbinfo->bits_per_pixel; + const int bpl = fbinfo->bytes_per_line; + + /* If all significant bytes in color are equal, fastpath through memset. + * We assume that for 32bpp the high byte gets ignored anyway. */ + if ((((color >> 8) & 0xff) == (color & 0xff)) && (bpp == 16 || + (((color >> 16) & 0xff) == (color & 0xff)))) { + memset(fbaddr, color & 0xff, screen.size.height * bpl); + } else { + for (p.y = 0; p.y < screen.size.height; p.y++) + for (p.x = 0; p.x < screen.size.width; p.x++) + set_pixel(&p, color); + } return CBGFX_SUCCESS; }

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Patch set updated for coreboot: soc/intel/apollolake: Add GPE routing code
by Shaunak Saha 01 Jul '16

01 Jul '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15324 -gerrit commit 38e04f1274ab3daadb63f39d1e415c5e77d930a3 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Tue Jun 7 02:06:28 2016 -0700 soc/intel/apollolake: Add GPE routing code This patch adds the basic framework for SCI to GPE routing code. BUG = chrome-os-partner:53438 TEST = Toogle pch_sci_l from ec console using gpioset command and see that the sci counter increases in /sys/firmware/acpi/interrupt and also 9 in /proc/interrupts. Change-Id: I3b3198276530bf6513d94e9bea02ab9751212adf Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.h | 6 ++ src/soc/intel/apollolake/gpio.c | 68 +++++++++++++++ src/soc/intel/apollolake/include/soc/gpe.h | 102 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio.h | 11 +++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 22 +++++ src/soc/intel/apollolake/include/soc/pm.h | 19 ++++- src/soc/intel/apollolake/pmc.c | 68 +++++++++++++++ 7 files changed, 293 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index ef82c53..5571672 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_CHIP_H_ #define _SOC_APOLLOLAKE_CHIP_H_ +#include <soc/pm.h> + #define CLKREQ_DISABLED 0xf /* Serial IRQ control. SERIRQ_QUIET is the default (0). */ @@ -79,6 +81,10 @@ struct soc_intel_apollolake_config { /* Integrated Sensor Hub */ uint8_t integrated_sensor_hub_enable; + + uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ + uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ + uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c index d0ef648..76dbbad 100644 --- a/src/soc/intel/apollolake/gpio.c +++ b/src/soc/intel/apollolake/gpio.c @@ -19,6 +19,7 @@ #include <gpio.h> #include <soc/gpio.h> #include <soc/iosf.h> +#include <soc/pm.h> /* This list must be in order, from highest pad numbers, to lowest pad numbers*/ static const struct pad_community { @@ -132,3 +133,70 @@ const char *gpio_acpi_path(gpio_t gpio_num) return NULL; } + +/* Helper function to map PMC register groups to tier1 sci groups */ +static int pmc_gpe_route_to_gpio(int route) +{ + switch(route) { + case PMC_GPE_SW_31_0: + return GPIO_GPE_SW_31_0; + case PMC_GPE_SW_63_32: + return GPIO_GPE_SW_63_32; + case PMC_GPE_NW_31_0: + return GPIO_GPE_NW_31_0; + case PMC_GPE_NW_63_32: + return GPIO_GPE_NW_63_32; + case PMC_GPE_NW_95_64: + return GPIO_GPE_NW_95_64; + case PMC_GPE_N_31_0: + return GPIO_GPE_N_31_0; + case PMC_GPE_N_63_32: + return GPIO_GPE_N_63_32; + case PMC_GPE_W_31_0: + return GPIO_GPE_W_31_0; + default: + return -1; + } +} + +void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d) +{ + int i; + uint32_t misccfg_mask; + uint32_t misccfg_value; + uint32_t value; + + /* Get the group here for community specific MISCCFG register. + * If any of these returns -1 then there is some error in devicetree + * where the group is probably hardcoded and does not comply with the + * PMC group defines. So we return from here and MISCFG is set to + * default. + */ + gpe0b = pmc_gpe_route_to_gpio(gpe0b); + if(gpe0b == -1) + return; + gpe0c = pmc_gpe_route_to_gpio(gpe0c); + if(gpe0c == -1) + return; + gpe0d = pmc_gpe_route_to_gpio(gpe0d); + if(gpe0d == -1) + return; + + misccfg_value = gpe0b << MISCCFG_GPE0_DW0_SHIFT; + misccfg_value |= gpe0c << MISCCFG_GPE0_DW1_SHIFT; + misccfg_value |= gpe0d << MISCCFG_GPE0_DW2_SHIFT; + + /* Program GPIO_MISCCFG */ + misccfg_mask = ~(MISCCFG_GPE0_DW2_MASK | + MISCCFG_GPE0_DW1_MASK | + MISCCFG_GPE0_DW0_MASK); + + for (i = 0; i < ARRAY_SIZE(gpio_communities); i++) { + const struct pad_community *comm = &gpio_communities[i]; + + value = iosf_read(comm->port, GPIO_MISCCFG); + value &= misccfg_mask; + value |= misccfg_value; + iosf_write(comm->port, GPIO_MISCCFG, value); + } +} diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h index 8abbad8..5482ed3 100644 --- a/src/soc/intel/apollolake/include/soc/gpe.h +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -34,4 +34,106 @@ #define GPE0A_SMB_WAK_STS 16 #define GPE0A_SATA_PME_STS 17 +/* Group DW0 is reserved in Apollolake */ + +/* GPE_63_32 */ +#define GPE0_DW1_00 32 +#define GPE0_DW1_01 33 +#define GPE0_DW1_02 34 +#define GPE0_DW1_03 36 +#define GPE0_DW1_04 36 +#define GPE0_DW1_05 37 +#define GPE0_DW1_06 38 +#define GPE0_DW1_07 39 +#define GPE0_DW1_08 40 +#define GPE0_DW1_09 41 +#define GPE0_DW1_10 42 +#define GPE0_DW1_11 43 +#define GPE0_DW1_12 44 +#define GPE0_DW1_13 45 +#define GPE0_DW1_14 46 +#define GPE0_DW1_15 47 +#define GPE0_DW1_16 48 +#define GPE0_DW1_17 49 +#define GPE0_DW1_18 50 +#define GPE0_DW1_19 51 +#define GPE0_DW1_20 52 +#define GPE0_DW1_21 53 +#define GPE0_DW1_22 54 +#define GPE0_DW1_23 55 +#define GPE0_DW1_24 56 +#define GPE0_DW1_25 57 +#define GPE0_DW1_26 58 +#define GPE0_DW1_27 59 +#define GPE0_DW1_28 60 +#define GPE0_DW1_29 61 +#define GPE0_DW1_30 62 +#define GPE0_DW1_31 63 +/* GPE_95_64 */ +#define GPE0_DW2_00 64 +#define GPE0_DW2_01 65 +#define GPE0_DW2_02 66 +#define GPE0_DW2_03 67 +#define GPE0_DW2_04 68 +#define GPE0_DW2_05 69 +#define GPE0_DW2_06 70 +#define GPE0_DW2_07 71 +#define GPE0_DW2_08 72 +#define GPE0_DW2_09 73 +#define GPE0_DW2_10 74 +#define GPE0_DW2_11 75 +#define GPE0_DW2_12 76 +#define GPE0_DW2_13 77 +#define GPE0_DW2_14 78 +#define GPE0_DW2_15 79 +#define GPE0_DW2_16 80 +#define GPE0_DW2_17 81 +#define GPE0_DW2_18 82 +#define GPE0_DW2_19 83 +#define GPE0_DW2_20 84 +#define GPE0_DW2_21 85 +#define GPE0_DW2_22 86 +#define GPE0_DW2_23 87 +#define GPE0_DW2_24 88 +#define GPE0_DW2_25 89 +#define GPE0_DW2_26 90 +#define GPE0_DW2_27 91 +#define GPE0_DW2_28 92 +#define GPE0_DW2_29 93 +#define GPE0_DW2_30 94 +#define GPE0_DW2_31 95 +/* GPE_127_96 */ +#define GPE0_DW3_00 96 +#define GPE0_DW3_01 97 +#define GPE0_DW3_02 98 +#define GPE0_DW3_03 99 +#define GPE0_DW3_04 100 +#define GPE0_DW3_05 101 +#define GPE0_DW3_06 102 +#define GPE0_DW3_07 103 +#define GPE0_DW3_08 104 +#define GPE0_DW3_09 105 +#define GPE0_DW3_10 106 +#define GPE0_DW3_11 107 +#define GPE0_DW3_12 108 +#define GPE0_DW3_13 109 +#define GPE0_DW3_14 110 +#define GPE0_DW3_15 111 +#define GPE0_DW3_16 112 +#define GPE0_DW3_17 113 +#define GPE0_DW3_18 114 +#define GPE0_DW3_19 115 +#define GPE0_DW3_20 116 +#define GPE0_DW3_21 117 +#define GPE0_DW3_22 118 +#define GPE0_DW3_23 119 +#define GPE0_DW3_24 120 +#define GPE0_DW3_25 121 +#define GPE0_DW3_26 122 +#define GPE0_DW3_27 123 +#define GPE0_DW3_28 124 +#define GPE0_DW3_29 125 +#define GPE0_DW3_30 126 +#define GPE0_DW3_31 127 + #endif diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h index c9d32cc..763cdef 100644 --- a/src/soc/intel/apollolake/include/soc/gpio.h +++ b/src/soc/intel/apollolake/include/soc/gpio.h @@ -99,5 +99,16 @@ struct pad_config { void gpio_configure_pad(const struct pad_config *cfg); void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads); +/* + * Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG + * are passed which is then mapped to proper groups for MISCCFG. This basically + * sets the MISCCFG register bits: + * dw0 = gpe0_route[11:8]. This is ACPI GPE0b. + * dw1 = gpe0_route[15:12]. This is ACPI GPE0c. + * dw2 = gpe0_route[19:16]. This is ACPI GPE0d. + */ +void gpio_route_gpe(uint8_t gpe0b, uint8_t gpe0c, uint8_t gpe0d); + #endif /* __ACPI__ */ + #endif /* _SOC_APOLLOLAKE_GPIO_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 30c4bdb..c6e2c3c 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -23,6 +23,28 @@ #ifndef _SOC_APOLLOLAKE_GPIO_DEFS_H_ #define _SOC_APOLLOLAKE_GPIO_DEFS_H_ +/* + * Miscellaneous Configuration register(MISCCFG).These are community specific + * registers and are meant to house miscellaneous configuration fields per + * community. There are 8 GPIO groups: GPP_0 -> GPP_8 (Group 3 is absent) + */ +#define GPIO_MISCCFG 0x10 /* Miscellaneous Configuration offset */ +#define GPIO_GPE_SW_31_0 0 /* SOUTHWEST GPIO# 0 ~ 31 belong to GROUP0 */ +#define GPIO_GPE_SW_63_32 1 /* SOUTHWEST GPIO# 32 ~ 42 belong to GROUP1 */ +#define GPIO_GPE_W_31_0 2 /* WEST GPIO# 0 ~ 25 belong to GROUP2 */ +#define GPIO_GPE_NW_31_0 4 /* NORTHWEST GPIO# 0 ~ 17 belong to GROUP4 */ +#define GPIO_GPE_NW_63_32 5 /* NORTHWEST GPIO# 32 ~ 63 belong to GROUP5 */ +#define GPIO_GPE_NW_95_64 6 /* NORTHWEST GPIO# 64 ~ 76 belong to GROUP6 */ +#define GPIO_GPE_N_31_0 7 /* NORTH GPIO# 0 ~ 31 belong to GROUP7 */ +#define GPIO_GPE_N_63_32 8 /* NORTH GPIO# 32 ~ 61 belong to GROUP8 */ + +#define MISCCFG_GPE0_DW0_SHIFT 8 +#define MISCCFG_GPE0_DW0_MASK (0xf << MISCCFG_GPE0_DW0_SHIFT) +#define MISCCFG_GPE0_DW1_SHIFT 12 +#define MISCCFG_GPE0_DW1_MASK (0xf << MISCCFG_GPE0_DW1_SHIFT) +#define MISCCFG_GPE0_DW2_SHIFT 16 +#define MISCCFG_GPE0_DW2_MASK (0xf << MISCCFG_GPE0_DW2_SHIFT) + #define PAD_CFG0_TX_STATE (1 << 0) #define PAD_CFG0_RX_STATE (1 << 1) #define PAD_CFG0_TX_DISABLE (1 << 8) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 72f74a6..99f922f 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -129,9 +129,22 @@ # define RPS (1 << 2) #define GEN_PMCON3 0x1028 #define ETR 0x1048 -# define CF9_LOCK (1 << 31) -# define CF9_GLB_RST (1 << 20) - +# define CF9_LOCK (1 << 31) +# define CF9_GLB_RST (1 << 20) +#define GPIO_GPE_CFG 0x1050 +#define GPE0_DWX_MASK 0xf +#define GPE0_DW1_SHIFT 4 +#define GPE0_DW2_SHIFT 8 +#define GPE0_DW3_SHIFT 12 + +#define PMC_GPE_SW_31_0 0 +#define PMC_GPE_SW_63_32 1 +#define PMC_GPE_NW_31_0 3 +#define PMC_GPE_NW_63_32 4 +#define PMC_GPE_NW_95_64 5 +#define PMC_GPE_N_31_0 6 +#define PMC_GPE_N_63_32 7 +#define PMC_GPE_W_31_0 9 /* Generic sleep state types */ #define SLEEP_STATE_S0 0 diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index c88e14c..94040c3 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -18,8 +18,13 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <console/console.h> #include <soc/iomap.h> #include <soc/pci_ids.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include "chip.h" /* * The ACPI IO BAR (offset 0x20) is not PCI compliant. We've observed cases @@ -58,10 +63,73 @@ static void set_resources(device_t dev) report_resource_stored(dev, res, " ACPI BAR"); } +static void pmc_gpe_init(void) +{ + uint32_t gpio_cfg = 0; + uint32_t gpio_cfg_reg; + uint8_t dw1, dw2, dw3; + const struct soc_intel_apollolake_config *config; + + struct device *dev = NB_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + uintptr_t pmc_bar = get_pmc_mmio_bar(); + + const uint32_t gpio_cfg_mask = + (GPE0_DWX_MASK << GPE0_DW1_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW2_SHIFT) | + (GPE0_DWX_MASK << GPE0_DW3_SHIFT); + + /* Assign to local variable */ + dw1 = config->gpe0_dw1; + dw2 = config->gpe0_dw2; + dw3 = config->gpe0_dw3; + + /* Making sure that bad values don't bleed into the other fields */ + dw1 &= GPE0_DWX_MASK; + dw2 &= GPE0_DWX_MASK; + dw3 &= GPE0_DWX_MASK; + + /* Route the GPIOs to the GPE0 block. Determine that all values + * are different, and if they aren't use the reset values. + * DW0 is reserved/unused */ + if (dw1 == dw2 || dw2 == dw3) { + printk(BIOS_INFO, "PMC: Using default GPE route.\n"); + gpio_cfg = read32((void *)pmc_bar + GPIO_GPE_CFG); + + dw1 = (gpio_cfg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK; + dw2 = (gpio_cfg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK; + dw3 = (gpio_cfg >> GPE0_DW3_SHIFT) & GPE0_DWX_MASK; + } else { + gpio_cfg |= (uint32_t)dw1 << GPE0_DW1_SHIFT; + gpio_cfg |= (uint32_t)dw2 << GPE0_DW2_SHIFT; + gpio_cfg |= (uint32_t)dw3 << GPE0_DW3_SHIFT; + } + + gpio_cfg_reg = read32((void *)pmc_bar + GPIO_GPE_CFG) & ~gpio_cfg_mask; + gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask; + + write32((void *)pmc_bar + GPIO_GPE_CFG, gpio_cfg_reg); + + /* Set the routes in the GPIO communities as well. */ + gpio_route_gpe(dw1, dw2, dw3); +} + +static void pmc_init(struct device *dev) +{ + /* Set up GPE configuration */ + pmc_gpe_init(); +} + static const struct device_operations device_ops = { .read_resources = read_resources, .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, + .init = &pmc_init, }; static const struct pci_driver pmc __pci_driver = {

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Patch set updated for coreboot: acpi_device: Have acpi_device_scope() use a separate buffer
by Duncan Laurie 01 Jul '16

01 Jul '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15521 -gerrit commit 1f540a06d8184636e4ccb0c847e6db91b79855f0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jun 30 14:37:37 2016 -0700 acpi_device: Have acpi_device_scope() use a separate buffer Have the different acpi_device_ path functions use a different static buffer so they can be called interchangeably. Change-Id: I270a80f66880861d5847bd586a16a73f8f1e2511 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/acpi_device.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 69d44f3..1f0ab37 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -121,10 +121,15 @@ const char *acpi_device_path(struct device *dev) /* Return the path of the parent device as the ACPI Scope for this device */ const char *acpi_device_scope(struct device *dev) { + static char buf[DEVICE_PATH_MAX] = {}; + if (!dev || !dev->bus || !dev->bus->dev) return NULL; - return acpi_device_path(dev->bus->dev); + if (acpi_device_path_fill(dev->bus->dev, buf, sizeof(buf), 0) <= 0) + return NULL; + + return buf; } /* Concatentate the device path and provided name suffix */

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New patch to review for coreboot: reef: Enable I2C TPM
by Duncan Laurie 01 Jul '16

01 Jul '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15527 -gerrit commit c8c8ed3c150f56a9b863805df70fe11664dc4176 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jun 30 14:50:04 2016 -0700 reef: Enable I2C TPM Enable I2C bus 2 for TPM at address 0x50. This is needed in verstage so enable the pads and the I2C controller early. Change-Id: Ib696ace0274344ae3f527d883f56fae59dc41590 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 9 +++++++++ src/mainboard/google/reef/devicetree.cb | 3 +++ src/mainboard/google/reef/gpio.h | 3 +++ 3 files changed, 15 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 194a6ba..603866a 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -28,6 +28,15 @@ config CHROMEOS config DRIVERS_I2C_GENERIC default y +config I2C_TPM + default y + +config DRIVER_TPM_I2C_ADDR + default 0x50 + +config DRIVER_TPM_I2C_BUS + default 0x2 + config MAINBOARD_DIR string default google/reef diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb index e0831f4..f18caa8 100644 --- a/src/mainboard/google/reef/devicetree.cb +++ b/src/mainboard/google/reef/devicetree.cb @@ -36,6 +36,9 @@ chip soc/intel/apollolake # 0x1C[6:0] stands for 28*125 = 3500 pSec delay for HS200 register "emmc_rx_cmd_data_cntl2" = "0x1001C" + # I2C bus for TPM needed in verstage + register "i2c[2].early_init" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index bd491b4..d95d11b 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -341,6 +341,9 @@ static const struct pad_config gpio_table[] = { /* GPIOs needed prior to ramstage. */ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPIO_75, UP_20K, DEEP), /* I2S1_BCLK -- PCH_WP */ + /* I2C2 - TPM */ + PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */ + PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */ }; #endif /* __ACPI__ */

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Patch set updated for coreboot: soc/intel/apollolake: Add function to translate device into ACPI name
by Duncan Laurie 01 Jul '16

01 Jul '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15479 -gerrit commit f214b8b0eda6c4c9baae5b6a3b6891d796a2fb27 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 27 10:51:17 2016 -0700 soc/intel/apollolake: Add function to translate device into ACPI name Add support for the soc_acpi_name() handler in the device operations structure to translate a device path into ACPI name. In order to make this more complete add some missing devices in include/soc/pci_devs.h. Change-Id: I517bc86d8d9fe70bfa0fc4eb3828681887239587 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/apollolake/chip.c | 67 +++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pci_devs.h | 13 +++++ 2 files changed, 80 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b2afc4a..68459e6 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -39,6 +39,72 @@ static void *vbt; static struct region_device vbt_rdev; +static const char *soc_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + /* DSDT: acpi/northbridge.asl */ + case NB_DEVFN: + return "MCHC"; + /* DSDT: acpi/lpc.asl */ + case LPC_DEVFN: + return "LPCB"; + /* DSDT: acpi/xhci.asl */ + case XHCI_DEVFN: + return "XHCI"; + /* DSDT: acpi/pch_hda.asl */ + case HDA_DEVFN: + return "HDAS"; + /* DSDT: acpi/lpss.asl */ + case LPSS_DEVFN_UART0: + return "URT1"; + case LPSS_DEVFN_UART1: + return "URT2"; + case LPSS_DEVFN_UART2: + return "URT3"; + case LPSS_DEVFN_UART3: + return "URT4"; + case LPSS_DEVFN_SPI0: + return "SPI1"; + case LPSS_DEVFN_SPI1: + return "SPI2"; + case LPSS_DEVFN_SPI2: + return "SPI3"; + case LPSS_DEVFN_PWM: + return "PWM"; + case LPSS_DEVFN_I2C0: + return "I2C0"; + case LPSS_DEVFN_I2C1: + return "I2C1"; + case LPSS_DEVFN_I2C2: + return "I2C2"; + case LPSS_DEVFN_I2C3: + return "I2C3"; + case LPSS_DEVFN_I2C4: + return "I2C4"; + case LPSS_DEVFN_I2C5: + return "I2C5"; + case LPSS_DEVFN_I2C6: + return "I2C6"; + case LPSS_DEVFN_I2C7: + return "I2C7"; + /* Storage */ + case SDCARD_DEVFN: + return "SDCD"; + case EMMC_DEVFN: + return "EMMC"; + case SDIO_DEVFN: + return "SDIO"; + } + + return NULL; +} + static void pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); @@ -51,6 +117,7 @@ static struct device_operations pci_domain_ops = { .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .acpi_name = &soc_acpi_name, }; static struct device_operations cpu_bus_ops = { diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 88a7a07..f29784d 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -35,8 +35,16 @@ #define NB_DEV_ROOT _PCI_DEV(0x0, 0) #define P2SB_DEV _PCI_DEV(0xd, 0) +#define P2SB_DEVFN _PCI_DEVFN(0xd, 0) + #define PMC_DEV _PCI_DEV(0xd, 1) +#define PMC_DEVFN _PCI_DEVFN(0xd, 1) + #define SPI_DEV _PCI_DEV(0xd, 2) +#define SPI_DEVFN _PCI_DEVFN(0xd, 2) + +#define HDA_DEV _PCI_DEV(0xe, 0) +#define HDA_DEVFN _PCI_DEVFN(0xe, 0) #define ISH_DEV _PCI_DEV(0x11, 0) #define ISH_DEVFN _PCI_DEVFN(0x11, 0) @@ -86,6 +94,10 @@ #define LPSS_DEVFN_SPI1 _LPSS_PCI_DEVFN(SPI, 1) #define LPSS_DEVFN_SPI2 _LPSS_PCI_DEVFN(SPI, 2) +/* LPSS PWM */ +#define LPSS_DEV_SLOT_PWM 0x1a +#define LPSS_DEVFN_PWM _LPSS_PCI_DEVFN(PWM, 0) + #define SDCARD_DEV _PCI_DEV(0x1b, 0) #define SDCARD_DEVFN _PCI_DEVFN(0x1b, 0) @@ -100,4 +112,5 @@ #define SMBUS_DEV _PCI_DEV(0x1f, 1) #define SMBUS_DEVFN _PCI_DEVFN(0x1f, 1) + #endif

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coreboot-gerrit July 2016