coreboot-gerrit July 2016

coreboot-gerrit@coreboot.org

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1820 discussions

Patch merged into coreboot/master: lib: remove ulzma()
by gerrit＠coreboot.org 01 Jul '16

01 Jul '16

the following patch was just integrated into master: commit 8f9c866caf6e617eda26ef3caeff6a4b5bb91e9b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 1 10:06:29 2016 -0500 lib: remove ulzma() That function is no longer used. All users have been updated to use the ulzman() function which specifies lengths for the input and output buffers. Change-Id: Ie630172be914a88ace010ec3ff4ff97da414cb5e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/15526 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> See https://review.coreboot.org/15526 for details. -gerrit

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New patch to review for coreboot: soc/intel/apollolake: handle p2sb quirks
by Aaron Durbin 01 Jul '16

01 Jul '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15530 -gerrit commit 9e3244dd4f070df88446c9fd1a149066ad76aaa8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jul 1 16:36:03 2016 -0500 soc/intel/apollolake: handle p2sb quirks The P2SB device is device 0xd and function 0. If hidden that causes the latter pci devices on function >= 1 to not be probed in the kernel. This is also a problem for coreboot if the P2SB device is hidden by FSP. That means the coreboot driver won't be ran. Therefore, provide hide and unhide functions for the P2SB device. The other quirk is to allow the GPIO devices to work correctly. Those devices are ACPI devices. However, their resources are sub-regions within the P2SB BAR. Sadly, linux doesn't handle ACPI devices being children of PCI devices. This leads to resource conflict errors when the P2SB device is visible. For the time being keep the P2SB device hidden, but also ensure the resources it is using are accounted for and reserved. The fallout of that is the PMC and SPI device are no longer probed by the kernel. BUG=chrome-os-partner:53017 TEST=Ensured P2SB device is visible and pci resources are allocated correctly for the devices. Change-Id: I24e59bbde74310e1ce8425b344a3ad0b88702153 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 14 +++++- src/soc/intel/apollolake/include/soc/iomap.h | 3 ++ src/soc/intel/apollolake/include/soc/p2sb.h | 23 +++++++++ src/soc/intel/apollolake/p2sb.c | 74 ++++++++++++++++++++++++++++ 5 files changed, 114 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 030e35c..11f82f9 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -50,6 +50,7 @@ ramstage-y += lpc.c ramstage-y += lpc_lib.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += p2sb.c ramstage-y += uart.c ramstage-y += nhlt.c ramstage-y += northbridge.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b2afc4a..bb5f2bd 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -33,6 +33,7 @@ #include <soc/pci_devs.h> #include <spi-generic.h> #include <soc/pm.h> +#include <soc/p2sb.h> #include "chip.h" @@ -86,6 +87,14 @@ static void soc_init(void *data) range_entry_init(&range, 0x200000, 4ULL*GiB, 0); fsp_silicon_init(&range); + /* + * Keep the P2SB device visible so it and the other devices are + * visible in coreboot for driver support and PCI resource allocation. + * There is a UPD setting for this, but it's more consistent to use + * hide and unhide symmetrically. + */ + p2sb_unhide(); + /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } @@ -279,8 +288,11 @@ static void fsp_notify_dummy(void *arg) fsp_handle_reset(ret); } /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ - if (ph == READY_TO_BOOT) + if (ph == READY_TO_BOOT) { fsp_notify_dummy((void *)END_OF_FIRMWARE); + /* Hide the P2SB device to align with previous behavior. */ + p2sb_hide(); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 716c2a6..033ebb8 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -18,7 +18,10 @@ #ifndef _SOC_APOLLOLAKE_IOMAP_H_ #define _SOC_APOLLOLAKE_IOMAP_H_ +#include <commonlib/helpers.h> + #define P2SB_BAR CONFIG_IOSF_BASE_ADDRESS +#define P2SB_SIZE (16 * MiB) #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) diff --git a/src/soc/intel/apollolake/include/soc/p2sb.h b/src/soc/intel/apollolake/include/soc/p2sb.h new file mode 100644 index 0000000..a0bcc67 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/p2sb.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_P2SB_H_ +#define _SOC_APOLLOLAKE_P2SB_H_ + +void p2sb_unhide(void); +void p2sb_hide(void); + +#endif /* _SOC_APOLLOLAKE_P2SB_H_ */ diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c new file mode 100644 index 0000000..7834e38 --- /dev/null +++ b/src/soc/intel/apollolake/p2sb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <rules.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <soc/p2sb.h> + +#define P2SB_E0 0xe0 +#define HIDE_BIT (1 << 0) + +static void p2sb_set_hide_bit(int hide) +{ + struct device *dev; + const uint16_t reg = P2SB_E0 + 1; + const uint8_t mask = HIDE_BIT; + uint8_t val; + + dev = P2SB_DEV; + + val = pci_read_config8(dev, reg); + val &= ~mask; + if (hide) + val |= mask; + pci_write_config8(dev, reg, val); +} + +void p2sb_unhide(void) +{ + p2sb_set_hide_bit(0); +} + +void p2sb_hide(void) +{ + p2sb_set_hide_bit(HIDE_BIT); +} + +static void read_resources(struct device *dev) +{ + /* + * There's only one resource on the P2SB device. It's also already + * manually set to a fixed address in earlier boot stages. + */ + mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = DEVICE_NOOP, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_P2SB, +};

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Patch set updated for coreboot: google/reef: Add DA7219 support in acpi
by HARSHAPRIYA N 01 Jul '16

01 Jul '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15436 -gerrit commit d3638dea74cea6c66480e82467ee125928f6a2b3 Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Thu Jun 16 15:05:02 2016 -0700 google/reef: Add DA7219 support in acpi Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/acpi/mainboard.asl | 60 ++++++++++++++++++++++++++++ src/mainboard/google/reef/gpio.h | 3 ++ 2 files changed, 63 insertions(+) diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 5471488..e56bac4 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -84,3 +84,63 @@ Scope (\_SB.PCI0.LPCB) #include <drivers/pc80/tpm/acpi/tpm.asl> #include "ec.asl" } + +Scope (\_SB.PCI0.I2C0) +{ + /* Headphone Codec */ + Device (HPDA) + { + Name (_HID, "DLGS7219") + Name (_DDN, "Dialog DA7219 Codec") + Name (_UID, 1) + Name (_S0W, 4) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "dlg,micbias-lvl", 2600 }, + Package () { "dlg,mic-amp-in-sel", "diff" }, + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () {"da7219_aad", "DAAD"}, + } + }) + + Name (DAAD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "dlg,btn-cfg", 50 }, + Package () { "dlg,mic-det-thr", 500 }, + Package () { "dlg,jack-ins-deb", 20 }, + Package () { "dlg,jack-det-rate", "32ms_64ms" }, + Package () { "dlg,jack-rem-deb", 1 }, + Package () { "dlg,a-d-btn-thr", 0xa }, + Package () { "dlg,d-b-btn-thr", 0x16 }, + Package () { "dlg,b-c-btn-thr", 0x21 }, + Package () { "dlg,c-mic-btn-thr", 0x3E }, + Package () { "dlg,btn-avg", 4 }, + Package () { "dlg,adc-1bit-rpt", 1 }, + } + }) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_HP_MIC_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C0", + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + BOARD_HP_MIC_CODEC_IRQ + } + }) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index bd491b4..91e8bb1 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -21,6 +21,9 @@ /* Input device interrupt configuration */ #define TOUCHPAD_INT GPIO_18_IRQ +#define BOARD_HP_MIC_CODEC_IRQ GPIO_116_IRQ +#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a + #ifndef __ACPI__ /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'

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Patch set updated for coreboot: google/reef: Add DA7219 support in acpi
by HARSHAPRIYA N 01 Jul '16

01 Jul '16

HARSHAPRIYA N (harshapriya.n(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15436 -gerrit commit 341d6349fcee1d7f25629963aedb83b141d5442c Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Thu Jun 16 15:05:02 2016 -0700 google/reef: Add DA7219 support in acpi Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/acpi/mainboard.asl | 60 ++++++++++++++++++++++++++++ src/mainboard/google/reef/gpio.h | 2 + 2 files changed, 62 insertions(+) diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 5471488..b5bf3e6 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -84,3 +84,63 @@ Scope (\_SB.PCI0.LPCB) #include <drivers/pc80/tpm/acpi/tpm.asl> #include "ec.asl" } + +Scope (\_SB.PCI0.I2C0) +{ + /* Headphone Codec */ + Device (HPDA) + { + Name (_HID, "DLGS7219") + Name (_DDN, "Dialog DA7219 Codec") + Name (_UID, 1) + Name (_S0W, 4) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "dlg,micbias-lvl", 2600 }, + Package () { "dlg,mic-amp-in-sel", "diff" }, + }, + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package () { + Package () {"da7219_aad", "DAAD"}, + } + }) + + Name (DAAD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "dlg,btn-cfg", 50 }, + Package () { "dlg,mic-det-thr", 500 }, + Package () { "dlg,jack-ins-deb", 20 }, + Package () { "dlg,jack-det-rate", "32ms_64ms" }, + Package () { "dlg,jack-rem-deb", 1 }, + Package () { "dlg,a-d-btn-thr", 0xa }, + Package () { "dlg,d-b-btn-thr", 0x16 }, + Package () { "dlg,b-c-btn-thr", 0x21 }, + Package () { "dlg,c-mic-btn-thr", 0x3E }, + Package () { "dlg,btn-avg", 4 }, + Package () { "dlg,adc-1bit-rpt", 1 }, + } + }) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_HP_MIC_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C0", + ) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + GPIO_116_IRQ + } + }) + + Method (_STA) + { + Return (0xF) + } + } +} diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h index bd491b4..2c8a0d0 100644 --- a/src/mainboard/google/reef/gpio.h +++ b/src/mainboard/google/reef/gpio.h @@ -21,6 +21,8 @@ /* Input device interrupt configuration */ #define TOUCHPAD_INT GPIO_18_IRQ +#define BOARD_HP_MIC_CODEC_I2C_ADDR 0x1a + #ifndef __ACPI__ /* * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'

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Patch set updated for coreboot: arch/riscv: Change all eret instructions to mret
by Ronald G. Minnich 01 Jul '16

01 Jul '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15290 -gerrit commit d06a48c5e28950dee35f3ac65f24a4b045ba15a2 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:53 2016 +0200 arch/riscv: Change all eret instructions to mret Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/boot.c | 2 +- src/arch/riscv/trap_util.S | 4 ++-- src/arch/riscv/virtual_memory.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 96526bf..d322e59 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -25,7 +25,7 @@ void arch_prog_run(struct prog *prog) if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); write_csr(mepc, doit); - asm volatile("eret"); + asm volatile("mret"); } else { doit(prog_entry_arg(prog)); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 0118ffc..6608328 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -124,9 +124,9 @@ trap_entry: supervisor_call_return: csrr a0, mscratch restore_regs - eret # go back into supervisor call + mret # go back into supervisor call .global machine_call_return machine_call_return: csrr a0, mscratch restore_regs - eret # go back into machine call + mret # go back into machine call diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 64ea2b1..d9727d1 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -31,7 +31,7 @@ void walk_page_table(void) { void enter_supervisor(void) { // enter supervisor mode - asm volatile("la t0, 1f; csrw mepc, t0; eret; 1:" ::: "t0"); + asm volatile("la t0, 1f; csrw mepc, t0; mret; 1:" ::: "t0"); } void flush_tlb(void)

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Patch set updated for coreboot: spike-riscv: Remove HTIF related code
by Ronald G. Minnich 01 Jul '16

01 Jul '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15289 -gerrit commit 98e0ddb8857be8e38b7f2f207d9f43baa926e282 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:51 2016 +0200 spike-riscv: Remove HTIF related code The HTIF is deprecated and the newest RISC-V binutils don't know the mtohost/mfromhost CSRs anymore. The SBI implementation still needs to be restructured. Change-Id: I13f01e45b714f1bd919e27b84aff8db772504b1f Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/spike_util.c | 110 ++--------------------- 1 file changed, 7 insertions(+), 103 deletions(-) diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c index fca7d56..358cb44 100644 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ b/src/mainboard/emulation/spike-riscv/spike_util.c @@ -55,14 +55,7 @@ uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p) uintptr_t mcall_send_ipi(uintptr_t recipient) { - //if (recipient >= num_harts) - //return -1; - - if (atomic_swap(&OTHER_HLS(recipient)->ipi_pending, 1) == 0) { - mb(); - write_csr(send_ipi, recipient); - } - + die("mcall_send_ipi is currently not implemented"); return 0; } @@ -79,50 +72,26 @@ uintptr_t mcall_clear_ipi(void) uintptr_t mcall_shutdown(void) { - while (1) write_csr(mtohost, 1); + die("mcall_shutdown is currently not implemented"); return 0; } uintptr_t mcall_set_timer(unsigned long long when) { - write_csr(mtimecmp, when); - clear_csr(mip, MIP_STIP); - set_csr(mie, MIP_MTIP); + die("mcall_set_timer is currently not implemented"); return 0; } uintptr_t mcall_dev_req(sbi_device_message *m) { - if ((m->dev > 0xFFU) | (m->cmd > 0xFFU) | (m->data > 0x0000FFFFFFFFFFFFU)) return -EINVAL; - - while (swap_csr(mtohost, TOHOST_CMD(m->dev, m->cmd, m->data)) != 0); - - m->sbi_private_data = (uintptr_t)HLS()->device_request_queue_head; - HLS()->device_request_queue_head = m; - HLS()->device_request_queue_size++; - + die("mcall_dev_req is currently not implemented"); return 0; } uintptr_t mcall_dev_resp(void) { - htif_interrupt(0, 0); - - sbi_device_message* m = HLS()->device_response_queue_head; - if (m) { - //printm("resp %p\n", m); - sbi_device_message* next = (void*)atomic_read(&m->sbi_private_data); - HLS()->device_response_queue_head = next; - if (!next) { - HLS()->device_response_queue_tail = 0; - - // only clear SSIP if no other events are pending - clear_csr(mip, MIP_SSIP); - mb(); - if (HLS()->ipi_pending) set_csr(mip, MIP_SSIP); - } - } - return (uintptr_t)m; + die("mcall_dev_resp is currently not implemented"); + return 0; } uintptr_t mcall_hart_id(void) @@ -136,74 +105,9 @@ void hls_init(uint32_t hart_id) HLS()->hart_id = hart_id; } -uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs) { - uintptr_t fromhost = swap_csr(mfromhost, 0); - if (!fromhost) - return 0; - - uintptr_t dev = FROMHOST_DEV(fromhost); - uintptr_t cmd = FROMHOST_CMD(fromhost); - uintptr_t data = FROMHOST_DATA(fromhost); - - sbi_device_message* m = HLS()->device_request_queue_head; - sbi_device_message* prev = 0x0; - unsigned long i, n; - for (i = 0, n = HLS()->device_request_queue_size; i < n; i++) { - /* - if (!supervisor_paddr_valid(m, sizeof(*m)) - && EXTRACT_FIELD(read_csr(mstatus), MSTATUS_PRV1) != PRV_M) - panic("htif: page fault"); - */ - - sbi_device_message* next = (void*)m->sbi_private_data; - if (m->dev == dev && m->cmd == cmd) { - m->data = data; - - // dequeue from request queue - if (prev) - prev->sbi_private_data = (uintptr_t)next; - else - HLS()->device_request_queue_head = next; - HLS()->device_request_queue_size = n-1; - m->sbi_private_data = 0; - - // enqueue to response queue - if (HLS()->device_response_queue_tail) - { - HLS()->device_response_queue_tail->sbi_private_data = (uintptr_t)m; - } - else - { - HLS()->device_response_queue_head = m; - } - HLS()->device_response_queue_tail = m; - - // signal software interrupt - set_csr(mip, MIP_SSIP); - return 0; - } - - prev = m; - m = (void*)atomic_read(&m->sbi_private_data); - } - //HLT(); - return 0; - //panic("htif: no record"); -} - uintptr_t mcall_console_putchar(uint8_t ch) { - while (swap_csr(mtohost, TOHOST_CMD(1, 1, ch)) != 0); - while (1) { - uintptr_t fromhost = read_csr(mfromhost); - if (FROMHOST_DEV(fromhost) != 1 || FROMHOST_CMD(fromhost) != 1) { - if (fromhost) - htif_interrupt(0, 0); - continue; - } - write_csr(mfromhost, 0); - break; - } + do_putchar(ch); return 0; }

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Patch set updated for coreboot: util/riscvtools: Provide a tohost symbol so Spike doesn't hang
by Ronald G. Minnich 01 Jul '16

01 Jul '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15288 -gerrit commit 2d321144ed66509ec2337d300231fcf765257e27 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Jun 30 22:58:52 2016 +0200 util/riscvtools: Provide a tohost symbol so Spike doesn't hang See https://github.com/riscv/riscv-isa-sim/issues/54 for more information. Change-Id: I8cda8dc07866d395eb3ce5d94df8232840fa8b82 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/riscvtools/spike-elf.ld | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/riscvtools/spike-elf.ld b/util/riscvtools/spike-elf.ld index 341a16f..44114f7 100644 --- a/util/riscvtools/spike-elf.ld +++ b/util/riscvtools/spike-elf.ld @@ -8,4 +8,8 @@ SECTIONS .data : { *(.data) } + + tohost = .; + . = . + 8; + fromhost = .; }

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Patch set updated for coreboot: [WIP] spike-riscv: Register RAM resource at 0x80000000
by Ronald G. Minnich 01 Jul '16

01 Jul '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15511 -gerrit commit 2808a4aa0d685bc790fe78e832e8ca0fd65057b3 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:32 2016 +0200 [WIP] spike-riscv: Register RAM resource at 0x80000000 Without this patch, the CBFS loader won't load segments into the RAM. Change-Id: If05c8edb51f9fe2f7af84178826f93b193cfd8a9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/mainboard.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/mainboard/emulation/spike-riscv/mainboard.c b/src/mainboard/emulation/spike-riscv/mainboard.c index 111e9b1..5a481f3 100644 --- a/src/mainboard/emulation/spike-riscv/mainboard.c +++ b/src/mainboard/emulation/spike-riscv/mainboard.c @@ -19,13 +19,22 @@ static void mainboard_enable(device_t dev) { + /* + * Size of the emulated system RAM. On hardware, this would be external + * DDR memory. + * + * TODO: Get this size from the hardware-supplied configuration string. + */ + const size_t ram_size = 1*GiB; if (!dev) { printk(BIOS_EMERG, "No dev0; die\n"); while (1); } - ram_resource(dev, 0, 2048, 32768); + /* TODO: move to src/arch/riscv? */ + ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB); + cbmem_recovery(0); }

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New patch to review for coreboot: marvell/mvmap2315: add IPC driver
by hakim giydan 01 Jul '16

01 Jul '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15529 -gerrit commit ea6cbf0964c8f369621282a69b05c157038638c5 Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Fri Jul 1 12:07:57 2016 -0700 marvell/mvmap2315: add IPC driver IPC is the interface between the SP and the MCU Change-Id: I003f6929b00476d46be931773cd35418fe6622a6 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- src/soc/marvell/mvmap2315/Makefile.inc | 1 + src/soc/marvell/mvmap2315/include/soc/addressmap.h | 4 + src/soc/marvell/mvmap2315/include/soc/gic.h | 2 + src/soc/marvell/mvmap2315/include/soc/ipc.h | 115 ++++++++++++++++ src/soc/marvell/mvmap2315/ipc.c | 151 +++++++++++++++++++++ src/soc/marvell/mvmap2315/power.c | 12 +- src/soc/marvell/mvmap2315/romstage.c | 9 +- 7 files changed, 290 insertions(+), 4 deletions(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index 0e10a94..48ce8c0 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += bootrom.c romstage-y += cbmem.c romstage-y += clock.c romstage-y += gic.c +romstage-y += ipc.c romstage-y += media.c romstage-y += monotonic_timer.c romstage-y += pinconfig.c diff --git a/src/soc/marvell/mvmap2315/include/soc/addressmap.h b/src/soc/marvell/mvmap2315/include/soc/addressmap.h index a54403e..2ecfab0 100644 --- a/src/soc/marvell/mvmap2315/include/soc/addressmap.h +++ b/src/soc/marvell/mvmap2315/include/soc/addressmap.h @@ -36,6 +36,10 @@ enum { MVMAP2315_PADWRAP_BASE = 0xE0140000, MVMAP2315_WDT0_BASE = 0XE1010000, MVMAP2315_TIMER0_BASE = 0xE1020000, + MVMAP2315_IPC_SP_BASE = 0xED0C2000, + MVMAP2315_IPC_MCU_BASE = 0xED0C2100, + MVMAP2315_IPC_BUFFER_SP_BASE = 0xEE03FF0C, + MVMAP2315_IPC_BUFFER_MCU_BASE = 0xEE03FF8C, MVMAP2315_MPMU_CLK_BASE = 0xEF000800, MVMAP2315_A2BUS_BANKED_REGS_BASE = 0xF0000000, MVMAP2315_A2BUS_ALIAS6_REGS_BASE = 0xF0002000, diff --git a/src/soc/marvell/mvmap2315/include/soc/gic.h b/src/soc/marvell/mvmap2315/include/soc/gic.h index 520ea51..310680f 100644 --- a/src/soc/marvell/mvmap2315/include/soc/gic.h +++ b/src/soc/marvell/mvmap2315/include/soc/gic.h @@ -19,6 +19,8 @@ #include <stdlib.h> #include <types.h> +#include <soc/addressmap.h> + #define MVMAP2315_BCM_GICC_EN0 BIT(0) #define MVMAP2315_BCM_GICD_FIQ_EN BIT(3) struct mvmap2315_bcm_gicc_regs { diff --git a/src/soc/marvell/mvmap2315/include/soc/ipc.h b/src/soc/marvell/mvmap2315/include/soc/ipc.h new file mode 100644 index 0000000..85b1d88 --- /dev/null +++ b/src/soc/marvell/mvmap2315/include/soc/ipc.h @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MARVELL_MVMAP2315_IPC_H__ +#define __SOC_MARVELL_MVMAP2315_IPC_H__ + +#include <stdlib.h> +#include <stdint.h> +#include <types.h> + +#include <soc/addressmap.h> + +#define MVMAP2315_IPC_MSG_BUFFER_OFFSET 0xCE000000 +#define MVMAP2315_IPC_MSG_IRQ_SENT BIT(0) +#define MVMAP2315_IPC_MSG_IRQ_RECEIVED BIT(0) +#define MVMAP2315_IPC_MSG_IRQ_ACK BIT(3) +#define MVMAP2315_IPC_MSG_IRQ_MCU_MSG BIT(6) + +struct ipc_mcu_hash_msg { + u8 protocol_version; + u8 checksum; + u16 command_id; + u8 command_version; + u8 reserved; + u16 length; + u8 hash_subcommand; + u8 hash_type; + u8 nonce_size; + u8 reserved0; + u32 offset; + u32 size; + u8 nonce_data[64]; +}; + +struct ipc_mcu_power_msg { + u8 protocol_version; + u8 checksum; + u16 command_id; + u8 command_version; + u8 reserved; + u16 length; + u8 power_status; +}; + +struct ipc_mcu_hash_reply_msg { + u8 protocol_version; + u8 checksum; + u16 result; + u16 length; + u8 status; + u8 type; + u8 digest_size; + u8 reserved0; + u32 offset; + u32 size; + u8 digest_data[64]; +}; + +struct mvmap2315_ipc_regs { + u32 ipc_isrr; + u32 ipc_wdr_0; + u32 ipc_wdr_1; + u32 ipc_isrw; + u32 ipc_icr; + u32 ipc_iir; + u32 ipc_rdr_0; + u32 ipc_rdr_1; + u32 ipc_maj_mid_rev; + u32 ipc_cfg_rev; + u32 ipc_dummy; +}; + +check_member(mvmap2315_ipc_regs, ipc_dummy, 0x28); +static struct mvmap2315_ipc_regs * const mvmap2315_ipc_sp + = (void *)MVMAP2315_IPC_SP_BASE; +static struct mvmap2315_ipc_regs * const mvmap2315_ipc_mcu + = (void *)MVMAP2315_IPC_MCU_BASE; +enum hash_responses { + ABORT = 0x0, + FINISHED = 0x1, + BUSY = 0x2 +}; + +enum hash_subcommands { + GET_HASH = 0x0, + ABORT_HASH = 0x1, + START_HASH = 0x2, + SYNC_HASH = 0x3 +}; + +enum msg_types { + MSG_READY = 1, + MSG_RECEIVED = 8, + MSG_READY_RECEIVED = 9, +}; + +u8 checksum8(u8 *addr, u32 length); +void wait_for_ipc_msg(void); +void *extract_ipc_msg(void); +void send_ipc_msg(u32 msg_buffer_addr, u32 size); +int ipc_mcu_hash_msg_cmd(u8 subcommand); + +#endif /* __SOC_MARVELL_MVMAP2315_IPC_H__ */ diff --git a/src/soc/marvell/mvmap2315/ipc.c b/src/soc/marvell/mvmap2315/ipc.c new file mode 100644 index 0000000..81d5a6c --- /dev/null +++ b/src/soc/marvell/mvmap2315/ipc.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/gic.h> +#include <soc/ipc.h> +#include <string.h> + +u8 checksum8(u8 *addr, u32 length) +{ + u8 checksum = 0; + + while (length) { + checksum += *addr; + addr++; + --length; + } + return ~checksum + 1; +} + +void wait_for_ipc_msg(void) +{ + while (!(read32(&mvmap2315_bcm_gicd->ispendr2) & + MVMAP2315_IPC_MSG_IRQ_MCU_MSG)) + ; + + printk(BIOS_DEBUG, "MCU msg IRQ Found\n"); +} + +void *extract_ipc_msg(void) +{ + u32 iir; + u32 msg_buffer; + u32 reg; + + write32(&mvmap2315_ipc_sp->ipc_dummy, 0xA5A5A5A5); + + iir = read32(&mvmap2315_ipc_sp->ipc_iir); + printk(BIOS_DEBUG, "MCU msg IIR is: %d\n", iir); + + switch (iir) { + case MSG_READY: + + msg_buffer = read32(&mvmap2315_ipc_sp->ipc_rdr_0) + + MVMAP2315_IPC_MSG_BUFFER_OFFSET; + + reg = read32(&mvmap2315_ipc_sp->ipc_icr); + reg |= MVMAP2315_IPC_MSG_IRQ_RECEIVED; + write32(&mvmap2315_ipc_sp->ipc_icr, reg); + + reg = read32(&mvmap2315_ipc_sp->ipc_isrw); + reg |= MVMAP2315_IPC_MSG_IRQ_ACK; + write32(&mvmap2315_ipc_sp->ipc_isrw, reg); + + break; + + case MSG_RECEIVED: + + msg_buffer = 0; + + reg = read32(&mvmap2315_ipc_sp->ipc_icr); + reg |= MVMAP2315_IPC_MSG_IRQ_ACK; + write32(&mvmap2315_ipc_sp->ipc_icr, reg); + + break; + + case MSG_READY_RECEIVED: + + msg_buffer = read32(&mvmap2315_ipc_sp->ipc_rdr_0) + + MVMAP2315_IPC_MSG_BUFFER_OFFSET; + + reg = read32(&mvmap2315_ipc_sp->ipc_icr); + reg |= (MVMAP2315_IPC_MSG_IRQ_ACK | + MVMAP2315_IPC_MSG_IRQ_RECEIVED); + write32(&mvmap2315_ipc_sp->ipc_icr, reg); + + reg = read32(&mvmap2315_ipc_sp->ipc_isrw); + reg |= MVMAP2315_IPC_MSG_IRQ_ACK; + write32(&mvmap2315_ipc_sp->ipc_isrw, reg); + + break; + + default: + write32(&mvmap2315_ipc_sp->ipc_iir, iir); + + break; + } + + return (void *)msg_buffer; +} + +void send_ipc_msg(u32 msg_buffer_addr, u32 size) +{ + u32 reg; + + write32(&mvmap2315_ipc_sp->ipc_wdr_0, msg_buffer_addr); + + reg = read32(&mvmap2315_ipc_sp->ipc_isrw); + reg |= MVMAP2315_IPC_MSG_IRQ_SENT; + write32(&mvmap2315_ipc_sp->ipc_isrw, reg); +} + +int ipc_mcu_hash_msg_cmd(u8 subcommand) +{ + struct ipc_mcu_hash_msg *mcu_hash_msg + = (void *)MVMAP2315_IPC_BUFFER_MCU_BASE; + struct ipc_mcu_hash_reply_msg *mcu_hash_reply_msg; + u32 *ipc_buff; + + /* setting hash msg parameters */ + mcu_hash_msg->protocol_version = 0x3; + mcu_hash_msg->command_id = 0x2A; + mcu_hash_msg->reserved = 0x0; + mcu_hash_msg->length = 76; + mcu_hash_msg->checksum = 0; + mcu_hash_msg->hash_subcommand = subcommand; + mcu_hash_msg->hash_type = 0; + mcu_hash_msg->nonce_size = 0; + mcu_hash_msg->reserved0 = 0; + mcu_hash_msg->offset = 0; + mcu_hash_msg->size = 32; + mcu_hash_msg->checksum = checksum8((u8 *)mcu_hash_msg, + sizeof(struct ipc_mcu_hash_msg)); + + send_ipc_msg((u32)mcu_hash_msg, sizeof(struct ipc_mcu_hash_msg)); + + wait_for_ipc_msg(); + + ipc_buff = extract_ipc_msg(); + + mcu_hash_reply_msg = (void *)ipc_buff; + + wait_for_ipc_msg(); + + ipc_buff = extract_ipc_msg(); + + return mcu_hash_reply_msg->status; +} diff --git a/src/soc/marvell/mvmap2315/power.c b/src/soc/marvell/mvmap2315/power.c index 772715d..dd71b9b 100644 --- a/src/soc/marvell/mvmap2315/power.c +++ b/src/soc/marvell/mvmap2315/power.c @@ -21,6 +21,7 @@ #include <soc/clock.h> #include <soc/power.h> #include <soc/pwr_types.h> +#include <soc/ipc.h> static void enable_sys_power(void) { @@ -126,5 +127,14 @@ void full_boot(void) u32 get_boot_path(void) { - return FULL_BOOT; + struct ipc_mcu_power_msg *power_status_msg; + u32 *ipc_buff; + + wait_for_ipc_msg(); + + ipc_buff = extract_ipc_msg(); + + power_status_msg = (void *)ipc_buff; + + return power_status_msg->power_status; } diff --git a/src/soc/marvell/mvmap2315/romstage.c b/src/soc/marvell/mvmap2315/romstage.c index 0e32020..7d84651 100644 --- a/src/soc/marvell/mvmap2315/romstage.c +++ b/src/soc/marvell/mvmap2315/romstage.c @@ -24,6 +24,7 @@ #include <soc/bootrom.h> #include <soc/clock.h> #include <soc/gic.h> +#include <soc/ipc.h> #include <soc/monotonic_timer.h> #include <soc/power.h> #include <soc/romstage.h> @@ -82,13 +83,15 @@ void main(void) printk(BIOS_INFO, "loading and validating MCU FIRMWARE\n"); load_and_validate_image(&bdb_info, MCU_FIRMWARE); mcu_start(); + boot_path = get_boot_path(); } else { printk(BIOS_INFO, "low power restart. skip MCU code load\n"); - printk(BIOS_INFO, "TODO: check MCU Firmware hash\n"); + printk(BIOS_INFO, "checking MCU Firmware hash\n"); + ipc_mcu_hash_msg_cmd(GET_HASH); + printk(BIOS_INFO, "comparison not currently implemented\n"); + boot_path = get_boot_path(); } - boot_path = get_boot_path(); - switch (boot_path) { case NO_BOOT: no_boot();

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Patch merged into coreboot/master: Kconfig: Show DEBUG_BOOT_STATE in the Debug menu
by gerrit＠coreboot.org 01 Jul '16

01 Jul '16

the following patch was just integrated into master: commit fc04f9b5ee911bb622d5acbad5056b77af4e4ec7 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Jun 29 21:59:32 2016 +0200 Kconfig: Show DEBUG_BOOT_STATE in the Debug menu Change-Id: I22441ee0d19aa1b2e2f40278ce30092c86e0adc9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/15522 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15522 for details. -gerrit

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coreboot-gerrit July 2016