coreboot-gerrit April 2016

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Patch set updated for coreboot: buildgcc: Update Python to 3.5.1
by Stefan Reinauer 22 Apr '16

22 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14463 -gerrit commit 42af45ee578a1f660e62ada7d5a37051d08567c4 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 21 19:29:03 2016 -0700 buildgcc: Update Python to 3.5.1 Change-Id: I57f935b94ab0db2e9ff9434fb496d470bb4ec987 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/Python-3.4.3.tar.xz.cksum | 1 - util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 088c904..e9ce774 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.26 GDB_VERSION=7.11 IASL_VERSION=20160318 -PYTHON_VERSION=3.4.3 +PYTHON_VERSION=3.5.1 EXPAT_VERSION=2.1.1 # CLANG version number CLANG_VERSION=3.8.0 diff --git a/util/crossgcc/sum/Python-3.4.3.tar.xz.cksum b/util/crossgcc/sum/Python-3.4.3.tar.xz.cksum deleted file mode 100644 index 7f7273e..0000000 --- a/util/crossgcc/sum/Python-3.4.3.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7ca5cd664598bea96eec105aa6453223bb6b4456 tarballs/Python-3.4.3.tar.xz diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum new file mode 100644 index 0000000..58affb0 --- /dev/null +++ b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum @@ -0,0 +1 @@ +0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz

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Patch set updated for coreboot: soc/intel/apollolake: Add PMC_INT defination
by Lijian Zhao 22 Apr '16

22 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14476 -gerrit commit 822554c2582b51df0c4b799d535cc538f5e35ad9 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:12:13 2016 -0700 soc/intel/apollolake: Add PMC_INT defination PMC_INT is using direct irq 40, the defination is missing in previous commit. Change-Id: Ib67ee50f6c1cf9a2b8170d3123a0776ecb30b7eb Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/soc_int.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 83a831f..7db23ee 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -51,6 +51,7 @@ #define SPI2_INT 37 #define UFS_INT 38 #define EMMC_INT 39 +#define PMC_INT 40 #define SDIO_INT 42 #endif /* _SOC_INT_DEFINE_ASL_ */

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Patch set updated for coreboot: buildgcc: Update Python to 3.5.1
by Stefan Reinauer 22 Apr '16

22 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14463 -gerrit commit df39a801c6c03cc7516b60340597d3409f985e3e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 21 19:29:03 2016 -0700 buildgcc: Update Python to 3.5.1 Change-Id: I57f935b94ab0db2e9ff9434fb496d470bb4ec987 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/Python-3.4.3.tar.xz.cksum | 1 - util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 088c904..e9ce774 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.26 GDB_VERSION=7.11 IASL_VERSION=20160318 -PYTHON_VERSION=3.4.3 +PYTHON_VERSION=3.5.1 EXPAT_VERSION=2.1.1 # CLANG version number CLANG_VERSION=3.8.0 diff --git a/util/crossgcc/sum/Python-3.4.3.tar.xz.cksum b/util/crossgcc/sum/Python-3.4.3.tar.xz.cksum deleted file mode 100644 index 7f7273e..0000000 --- a/util/crossgcc/sum/Python-3.4.3.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7ca5cd664598bea96eec105aa6453223bb6b4456 tarballs/Python-3.4.3.tar.xz diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum new file mode 100644 index 0000000..58affb0 --- /dev/null +++ b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum @@ -0,0 +1 @@ +0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz

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Patch set updated for coreboot: buildgcc: Drop --target from python and expat
by Stefan Reinauer 22 Apr '16

22 Apr '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14464 -gerrit commit 15ab83781e92a251d9280be3e59bc0f16489075a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Apr 21 19:29:51 2016 -0700 buildgcc: Drop --target from python and expat Both packages are not using the target architecture. Drop it, and remove them from package_uses_targetarch Change-Id: I58efde4cb7cc39e7e3c31527eb7682e318928100 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e9ce774..c138473 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -289,8 +289,7 @@ is_package_enabled() package_uses_targetarch() { - if [ "$1" = "GCC" ] || [ "$1" = "GDB" ] || [ "$1" = "BINUTILS" ] || \ - [ "$1" = "PYTHON" ] || [ "$1" = "EXPAT" ]; then + if [ "$1" = "GCC" ] || [ "$1" = "GDB" ] || [ "$1" = "BINUTILS" ]; then true else false @@ -511,7 +510,7 @@ build_GCC() { build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ - --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed + --prefix=$TARGETDIR || touch .failed $MAKE || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -520,7 +519,7 @@ build_EXPAT() { build_PYTHON() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$TARGETDIR \ - --target=${TARGETARCH} || touch .failed + || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed

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New patch to review for coreboot: soc/intel/apollolake: Add PMC_INT defination
by Lijian Zhao 22 Apr '16

22 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14476 -gerrit commit 81fd3b9cdc4706010afb366a79cec5bac86956ec Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:12:13 2016 -0700 soc/intel/apollolake: Add PMC_INT defination PMC_INT is using direct irq 40, the defination is missing in previous commit. Change-Id: Ib67ee50f6c1cf9a2b8170d3123a0776ecb30b7eb Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/soc_int.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 83a831f..7db23ee 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -51,6 +51,7 @@ #define SPI2_INT 37 #define UFS_INT 38 #define EMMC_INT 39 +#define PMC_INT 40 #define SDIO_INT 42 #endif /* _SOC_INT_DEFINE_ASL_ */

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Patch merged into coreboot/master: drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ scheme
by gerrit＠coreboot.org 22 Apr '16

22 Apr '16

the following patch was just integrated into master: commit c6400e974e7b50d1b679faeae0d812da133daece Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Apr 19 09:55:19 2016 -0700 drivers/ricoh: Fully switch to src/drivers/[X]/[Y]/ scheme The previous commit removed Kconfig, but not Makefile.inc Change-Id: If46a0a3e253eea9d286d8ab3b1a6ab67ef678ee4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14419 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14419 for details. -gerrit

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New patch to review for coreboot: soc/intel/apollolake: Including PCI IRQ into ASL
by Lijian Zhao 22 Apr '16

22 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14475 -gerrit commit 3ea1ce3235c9cd4bfb5381bead511bbdf2de2f24 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:02:36 2016 -0700 soc/intel/apollolake: Including PCI IRQ into ASL Including pci irq defination into southbridge ASL files. Change-Id: I942ada5fe165736c32ea85899c2f3657c39aa53f --- src/soc/intel/apollolake/acpi/southbridge.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index cc52676..46d7013 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,3 +17,6 @@ /* LPSS device */ #include "lpss.asl" + +/* PCI IRQ assignment */ +#include "pci_irqs.asl"

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Patch set updated for coreboot: soc/intel/quark: Remove UPD parameters
by Leroy P Leahy 22 Apr '16

22 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14451 -gerrit commit b5a07ccc53d23df79ddf05af92672eb51f239389 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Mar 11 07:55:24 2016 -0800 soc/intel/quark: Remove UPD parameters Remove the UPD parameters to match QuarkFsp code. TEST=Build and run on Galileo Gen2 Change-Id: Ie4639d1f087cc2bc4387aa691eb66b640fe8faf9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/chip.c | 20 +------------------- src/soc/intel/quark/romstage/romstage.c | 16 ---------------- 2 files changed, 1 insertion(+), 35 deletions(-) diff --git a/src/soc/intel/quark/chip.c b/src/soc/intel/quark/chip.c index eb326d7..7ea8a06 100644 --- a/src/soc/intel/quark/chip.c +++ b/src/soc/intel/quark/chip.c @@ -55,29 +55,11 @@ struct chip_operations soc_intel_quark_ops = { .enable_dev = chip_enable_dev, }; -void soc_silicon_init_params(SILICON_INIT_UPD *params) +void soc_silicon_init_params(SILICON_INIT_UPD *upd) { - struct soc_intel_quark_config *config; - device_t dev; - - /* Locate the configuration data from devicetree.cb */ - dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { - printk(BIOS_ERR, - "Error! Device (PCI:0:%02x.%01x) not found, " - "soc_silicon_init_params!\n", PCI_DEVICE_NUMBER_QNC_LPC, - PCI_FUNCTION_NUMBER_QNC_LPC); - return; - } - config = dev->chip_info; - - /* Set the parameters for SiliconInit */ -// printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new) { - /* Display the parameters for SiliconInit */ -// printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); } diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 5bedb25..93fb24b 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -81,13 +81,6 @@ void soc_memory_init_params(struct romstage_params *params, } config = dev->chip_info; - /* Set the parameters for MemoryInit */ - printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); - upd->PcdSmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? - config->PcdSmmTsegSize : 0; - upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; - upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; - /* Display the ROM shadow data */ hexdump((void *)0x000ffff0, 0x10); } @@ -116,13 +109,4 @@ void soc_after_ram_init(struct romstage_params *params) void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new) { - /* Display the parameters for MemoryInit */ - printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); - fsp_display_upd_value("PcdSmmTsegSize", 2, - old->PcdSmmTsegSize, new->PcdSmmTsegSize); - fsp_display_upd_value("PcdPlatformDataBaseAddress", 4, - old->PcdPlatformDataBaseAddress, - new->PcdPlatformDataBaseAddress); - fsp_display_upd_value("PcdPlatformDataMaxLen", 4, - old->PcdPlatformDataMaxLen, new->PcdPlatformDataMaxLen); }

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Patch set updated for coreboot: coreboot_tables: Extend serial port description
by Leroy P Leahy 22 Apr '16

22 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14111 -gerrit commit 2df189081971049c6e62a9cd793204eb4a40581b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Mar 16 10:21:59 2016 -0700 coreboot_tables: Extend serial port description Extend the serial port description to include the input clock frequency and an identifier for the serial port. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Add an ID field that may specify the PCI vendor and device ID values which are required for CorebootPayloadPkg to initialize PCI based UARTs. A Kconfig value provides the default for this field to prevent breaking existing coreboot implementations. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I05a7e864afcd930916658e3efed53ff2efd403ec Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 2 ++ src/commonlib/include/commonlib/coreboot_tables.h | 2 ++ src/drivers/uart/Kconfig | 7 +++++++ src/drivers/uart/oxpcie_early.c | 2 ++ src/drivers/uart/pl011.c | 8 ++++++++ src/drivers/uart/uart8250io.c | 6 ++++-- src/drivers/uart/uart8250mem.c | 5 ++++- src/lib/coreboot_table.c | 2 ++ src/soc/intel/quark/Kconfig | 5 +++++ 9 files changed, 36 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 276f25f..06d1768 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -121,6 +121,8 @@ struct cb_serial { u32 baseaddr; u32 baud; u32 regwidth; + u32 input_hertz; + u32 id; }; #define CB_TAG_CONSOLE 0x00010 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..3839028 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -173,6 +173,8 @@ struct lb_serial { uint32_t baseaddr; uint32_t baud; uint32_t regwidth; + uint32_t input_hertz; + uint32_t id; }; #define LB_TAG_CONSOLE 0x0010 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index f4ad011..25dc980 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -41,3 +41,10 @@ config DRIVERS_UART_PL011 bool default n select HAVE_UART_SPECIAL + +config UART_DEVICE_ID + hex + default 0 + help + ID to help the payload identify the proper UART + diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index eb91d31..479408b 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -92,6 +92,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index aa55c68..cfd6f32 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -48,8 +48,16 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } + +__attribute__((weak)) unsigned int uart_platform_refclk(void) +{ + return 0; /* Unknown input frequency */ +} + #endif diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 63bc42f..683b7dd 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -30,8 +30,8 @@ /* Nominal values only, good for the range of choices Kconfig offers for * set of standard baudrates. */ -#define BAUDRATE_REFCLK (115200) -#define BAUDRATE_OVERSAMPLE (1) +#define BAUDRATE_REFCLK (115200 * 16) +#define BAUDRATE_OVERSAMPLE (16) /* Expected character delay at 1200bps is 9ms for a working UART * and no flow-control. Assume UART as stuck if shift register @@ -139,6 +139,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = BAUDRATE_REFCLK; + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..9c1f622 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -117,7 +117,8 @@ void uart_init(int idx) return; unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16); + div = uart_baudrate_divisor(default_baudrate(), + uart_platform_refclk(), 16); uart8250_mem_init(base, div); } @@ -156,6 +157,8 @@ void uart_fill_lb(void *data) serial.regwidth = sizeof(uint32_t); else serial.regwidth = sizeof(uint8_t); + serial.input_hertz = uart_platform_refclk(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 58c6f48..817cbc5 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -118,6 +118,8 @@ void lb_add_serial(struct lb_serial *new_serial, void *data) serial->baseaddr = new_serial->baseaddr; serial->baud = new_serial->baud; serial->regwidth = new_serial->regwidth; + serial->input_hertz = new_serial->input_hertz; + serial->id = new_serial->id; } void lb_add_console(uint16_t consoletype, void *data) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index aab509a..d71af30 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -59,6 +59,11 @@ config TTYS0_LCS depends on ENABLE_BUILTIN_HSUART1 default 3 +config UART_DEVICE_ID + hex + depends on ENABLE_BUILTIN_HSUART1 + default 0x09368086 + ##### # Debug support # The following options provide debug support for the Quark coreboot

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Patch set updated for coreboot: soc/intel/quark/romstage: Increase size of FSP
by Leroy P Leahy 22 Apr '16

22 Apr '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14453 -gerrit commit 4332e911a2fc759c50c4999ae3bc10b21a0d1dfe Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Apr 19 14:17:46 2016 -0700 soc/intel/quark/romstage: Increase size of FSP Increase the size of FSP to 320 KiB. The debug build of QuarkFspPkg with GCC 4.8.4 is just over the 256 KiB limit. TEST=Build and run on Galileo Gen2 Change-Id: I817ab310e6de145db37174ebf2b9d661167acb01 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/esram_init.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc index b899741..5cc3f0d 100644 --- a/src/soc/intel/quark/romstage/esram_init.inc +++ b/src/soc/intel/quark/romstage/esram_init.inc @@ -457,7 +457,7 @@ esram_init_done: /* Copy FSP image to eSRAM and call it. */ /* TODO: FSP location/size could be got in a routine. */ cld - movl $(0x00040000), %ecx /* 256K DWORDs = 64K */ + movl $(0x00050000), %ecx shrl $2, %ecx movl $CONFIG_FSP_LOC, %esi /* The source address. */ movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */

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coreboot-gerrit April 2016