coreboot-gerrit March 2016

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New patch to review for coreboot: TPM: add measurement code
by Georg Wicherski 11 Mar '16

11 Mar '16

Georg Wicherski (gw(a)oxff.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14038 -gerrit commit a197677796180fb7309129f72fbb5594dc983211 Author: Georg Wicherski <gw(a)oxff.net> Date: Fri Mar 11 17:53:01 2016 +0100 TPM: add measurement code WORK IN PROGRESS Measure ramstage and payload, extend PCRs. Change-Id: I1c15108e4a27e9929ae02c6409c3cae0bda073a5 --- src/drivers/tpm/lpc/Kconfig | 30 ++++++ src/include/tpm/tspi.h | 14 +++ src/lib/prog_loaders.c | 13 ++- src/lib/tpm/Makefile.inc | 5 + src/lib/tpm/sha1.c | 222 ++++++++++++++++++++++++++++++++++++++++++++ src/lib/tpm/tspi.c | 41 +++++++- 6 files changed, 319 insertions(+), 6 deletions(-) diff --git a/src/drivers/tpm/lpc/Kconfig b/src/drivers/tpm/lpc/Kconfig index ec17782..6015eca 100644 --- a/src/drivers/tpm/lpc/Kconfig +++ b/src/drivers/tpm/lpc/Kconfig @@ -13,6 +13,36 @@ config LPC_TPM If unsure, say N. +config TPM_MEASURE + bool "Enable TPM PCR measurements" + depends on LPC_TPM + default n + help + Add code to compute SHA1 digests on coreboot components and the + payload; extend appropriate PCRs with these digests. + + If unsure, say N. + +config TPM_MEASURE_RAMSTAGE + bool "Measure the coreboot ramstage" + depends on TPM_MEASURE + default n + help + Compute SHA1 digest on the ramstage after loading it. Extend PCR[0] + with the digest. + + If unsure, say N. + +config TPM_MEASURE_PAYLOAD + bool "Measure the coreboot payload" + depends on TPM_MEASURE + default n + help + Compute SHA1 digest on the payload as it is found in memory just + before mirroring it. Extend PCR[4] with the digest. + + If unsure, say N. + config TPM_READ_INIT_PCRS bool "Read PCR values after initialization" depends on LPC_TPM diff --git a/src/include/tpm/tspi.h b/src/include/tpm/tspi.h index ba2f119..26987cf 100644 --- a/src/include/tpm/tspi.h +++ b/src/include/tpm/tspi.h @@ -17,10 +17,24 @@ #ifndef TPM_TSPI_H #define TPM_TSPI_H +#include <stdint.h> +#include <program_loading.h> + /** * TSPI Implementation for coreboot without vboot2 */ void init_tpm(int s3resume); +/** + * Compute SHA1 digest on program memory contents and + * extend requested PCR with the digest. + */ +void measure_prog(struct prog *program, int pcr, const char *measured_thing); + + +#define SHA1_BLOCK_LENGTH 64 +#define SHA1_DIGEST_LENGTH 20 +u8 *sha1(const u8 *data, unsigned long len, u8 *buf); + #endif /* TPM_TSPI_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 14e1299..c21613e 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -28,6 +28,7 @@ #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> +#include <tpm/tspi.h> /* Only can represent up to 1 byte less than size_t. */ const struct mem_region_device addrspace_32bit = MEM_REGION_DEV_INIT(0, ~0UL); @@ -53,7 +54,7 @@ void run_romstage(void) if (prog_locate(&romstage)) goto fail; - + timestamp_add_now(TS_START_COPYROM); if (cbfs_prog_stage_load(&romstage)) @@ -115,8 +116,12 @@ void run_ramstage(void) if (prog_locate(&ramstage)) goto fail; - timestamp_add_now(TS_START_COPYRAM); + if (IS_ENABLED(CONFIG_TPM_MEASURE_RAMSTAGE)) { + measure_prog(&ramstage, 0, __func__); + } + timestamp_add_now(TS_START_COPYRAM); + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; @@ -151,6 +156,10 @@ void payload_load(void) if (prog_locate(payload)) goto out; + + if (IS_ENABLED(CONFIG_TPM_MEASURE_PAYLOAD)) { + measure_prog(payload, 4, __func__); + } mirror_payload(payload); diff --git a/src/lib/tpm/Makefile.inc b/src/lib/tpm/Makefile.inc index 81a3eb9..60bdfa2 100644 --- a/src/lib/tpm/Makefile.inc +++ b/src/lib/tpm/Makefile.inc @@ -1,10 +1,15 @@ ifneq ($(CONFIG_CHROMEOS),y) romstage-$(CONFIG_LPC_TPM) += tss.c tspi.c ramstage-$(CONFIG_LPC_TPM) += tss.c tspi.c +bootblock-$(CONFIG_LPC_TPM) += tss.c tspi.c else romstage-$(CONFIG_LPC_TPM) += tspi.c endif +bootblock-$(CONFIG_TPM_MEASURE) += sha1.c +romstage-$(CONFIG_TPM_MEASURE) += sha1.c +ramstage-$(CONFIG_TPM_MEASURE) += sha1.c + ifeq ($(MOCK_TPM),1) libverstage-y += mocked_tss.c else diff --git a/src/lib/tpm/sha1.c b/src/lib/tpm/sha1.c new file mode 100644 index 0000000..6e649b4 --- /dev/null +++ b/src/lib/tpm/sha1.c @@ -0,0 +1,222 @@ +/* + * This file was copied from the libpayload project. + * + * It has originally been taken from the OpenBSD project. + */ + +/* $OpenBSD: sha1.c,v 1.20 2005/08/08 08:05:35 espie Exp $ */ + +/* + * SHA-1 in C + * By Steve Reid <steve(a)edmweb.com> + * 100% Public Domain + * + * Test Vectors (from FIPS PUB 180-1) + * "abc" + * A9993E36 4706816A BA3E2571 7850C26C 9CD0D89D + * "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" + * 84983E44 1C3BD26E BAAE4AA1 F95129E5 E54670F1 + * A million repetitions of "a" + * 34AA973C D4C4DAA4 F61EEB2B DBAD2731 6534016F + */ + +#include <tpm/tspi.h> +#include <string.h> + +typedef u8 u_int8_t; +typedef u32 u_int32_t; +typedef u64 u_int64_t; +typedef unsigned int u_int; + +typedef struct { + u32 state[5]; + u64 count; + u8 buffer[SHA1_BLOCK_LENGTH]; +} SHA1_CTX; + + +#define LITTLE_ENDIAN 1234 +#define BIG_ENDIAN 4321 + +#if CONFIG_LITTLE_ENDIAN +#define BYTE_ORDER LITTLE_ENDIAN +#else +#define BYTE_ORDER BIG_ENDIAN +#endif + +#define rol(value, bits) (((value) << (bits)) | ((value) >> (32 - (bits)))) + +/* + * blk0() and blk() perform the initial expand. + * I got the idea of expanding during the round function from SSLeay + */ +#if BYTE_ORDER == LITTLE_ENDIAN +# define blk0(i) (block->l[i] = (rol(block->l[i],24)&0xFF00FF00) \ + |(rol(block->l[i],8)&0x00FF00FF)) +#else +# define blk0(i) block->l[i] +#endif +#define blk(i) (block->l[i&15] = rol(block->l[(i+13)&15]^block->l[(i+8)&15] \ + ^block->l[(i+2)&15]^block->l[i&15],1)) + +/* + * (R0+R1), R2, R3, R4 are the different operations (rounds) used in SHA1 + */ +#define R0(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk0(i)+0x5A827999+rol(v,5);w=rol(w,30); +#define R1(v,w,x,y,z,i) z+=((w&(x^y))^y)+blk(i)+0x5A827999+rol(v,5);w=rol(w,30); +#define R2(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0x6ED9EBA1+rol(v,5);w=rol(w,30); +#define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30); +#define R4(v,w,x,y,z,i) z+=(w^x^y)+blk(i)+0xCA62C1D6+rol(v,5);w=rol(w,30); + +/* + * Hash a single 512-bit block. This is the core of the algorithm. + */ +static void +SHA1Transform(u_int32_t state[5], const u_int8_t buffer[SHA1_BLOCK_LENGTH]) +{ + u_int32_t a, b, c, d, e; + u_int8_t workspace[SHA1_BLOCK_LENGTH]; + typedef union { + u_int8_t c[64]; + u_int32_t l[16]; + } CHAR64LONG16; + CHAR64LONG16 *block = (CHAR64LONG16 *)workspace; + + (void)memcpy(block, buffer, SHA1_BLOCK_LENGTH); + + /* Copy context->state[] to working vars */ + a = state[0]; + b = state[1]; + c = state[2]; + d = state[3]; + e = state[4]; + + /* 4 rounds of 20 operations each. Loop unrolled. */ + R0(a,b,c,d,e, 0); R0(e,a,b,c,d, 1); R0(d,e,a,b,c, 2); R0(c,d,e,a,b, 3); + R0(b,c,d,e,a, 4); R0(a,b,c,d,e, 5); R0(e,a,b,c,d, 6); R0(d,e,a,b,c, 7); + R0(c,d,e,a,b, 8); R0(b,c,d,e,a, 9); R0(a,b,c,d,e,10); R0(e,a,b,c,d,11); + R0(d,e,a,b,c,12); R0(c,d,e,a,b,13); R0(b,c,d,e,a,14); R0(a,b,c,d,e,15); + R1(e,a,b,c,d,16); R1(d,e,a,b,c,17); R1(c,d,e,a,b,18); R1(b,c,d,e,a,19); + R2(a,b,c,d,e,20); R2(e,a,b,c,d,21); R2(d,e,a,b,c,22); R2(c,d,e,a,b,23); + R2(b,c,d,e,a,24); R2(a,b,c,d,e,25); R2(e,a,b,c,d,26); R2(d,e,a,b,c,27); + R2(c,d,e,a,b,28); R2(b,c,d,e,a,29); R2(a,b,c,d,e,30); R2(e,a,b,c,d,31); + R2(d,e,a,b,c,32); R2(c,d,e,a,b,33); R2(b,c,d,e,a,34); R2(a,b,c,d,e,35); + R2(e,a,b,c,d,36); R2(d,e,a,b,c,37); R2(c,d,e,a,b,38); R2(b,c,d,e,a,39); + R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); + R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); + R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); + R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); + R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); + R4(a,b,c,d,e,60); R4(e,a,b,c,d,61); R4(d,e,a,b,c,62); R4(c,d,e,a,b,63); + R4(b,c,d,e,a,64); R4(a,b,c,d,e,65); R4(e,a,b,c,d,66); R4(d,e,a,b,c,67); + R4(c,d,e,a,b,68); R4(b,c,d,e,a,69); R4(a,b,c,d,e,70); R4(e,a,b,c,d,71); + R4(d,e,a,b,c,72); R4(c,d,e,a,b,73); R4(b,c,d,e,a,74); R4(a,b,c,d,e,75); + R4(e,a,b,c,d,76); R4(d,e,a,b,c,77); R4(c,d,e,a,b,78); R4(b,c,d,e,a,79); + + /* Add the working vars back into context.state[] */ + state[0] += a; + state[1] += b; + state[2] += c; + state[3] += d; + state[4] += e; + + /* Wipe variables */ + a = b = c = d = e = 0; +} + + +/* + * SHA1Init - Initialize new context + */ +static void +SHA1Init(SHA1_CTX *context) +{ + + /* SHA1 initialization constants */ + context->count = 0; + context->state[0] = 0x67452301; + context->state[1] = 0xEFCDAB89; + context->state[2] = 0x98BADCFE; + context->state[3] = 0x10325476; + context->state[4] = 0xC3D2E1F0; +} + + +/* + * Run your data through this. + */ +static void +SHA1Update(SHA1_CTX *context, const u_int8_t *data, unsigned long len) +{ + size_t i, j; + + j = (size_t)((context->count >> 3) & 63); + context->count += (len << 3); + if ((j + len) > 63) { + (void)memcpy(&context->buffer[j], data, (i = 64-j)); + SHA1Transform(context->state, context->buffer); + for ( ; i + 63 < len; i += 64) + SHA1Transform(context->state, (u_int8_t *)&data[i]); + j = 0; + } else { + i = 0; + } + (void)memcpy(&context->buffer[j], &data[i], len - i); +} + + +/* + * Add padding and return the message digest. + */ +static void +SHA1Pad(SHA1_CTX *context) +{ + u_int8_t finalcount[8]; + u_int i; + + for (i = 0; i < 8; i++) { + finalcount[i] = (u_int8_t)((context->count >> + ((7 - (i & 7)) * 8)) & 255); /* Endian independent */ + } + SHA1Update(context, (u_int8_t *)"\200", 1); + while ((context->count & 504) != 448) + SHA1Update(context, (u_int8_t *)"\0", 1); + SHA1Update(context, finalcount, 8); /* Should cause a SHA1Transform() */ +} + +static void +SHA1Final(u_int8_t digest[SHA1_DIGEST_LENGTH], SHA1_CTX *context) +{ + u_int i; + + SHA1Pad(context); + if (digest) { + for (i = 0; i < SHA1_DIGEST_LENGTH; i++) { + digest[i] = (u_int8_t) + ((context->state[i>>2] >> ((3-(i & 3)) * 8) ) & 255); + } + memset(context, 0, sizeof(*context)); + } +} + +/** + * Compute the SHA-1 hash of the given data as specified by the 'data' and + * 'len' arguments, and place the result -- 160 bits (20 bytes) -- into the + * specified output buffer 'buf'. + * + * @param data Pointer to the input data that shall be hashed. + * @param len Length of the input data (in bytes). + * @param buf Buffer which will hold the resulting hash (must be at + * least 20 bytes in size). + * @return Pointer to the output buffer where the hash is stored. + */ +u8 *sha1(const u8 *data, unsigned long len, u8 *buf) +{ + SHA1_CTX ctx; + + SHA1Init(&ctx); + SHA1Update(&ctx, data, len); + SHA1Final(buf, &ctx); + + return buf; +} diff --git a/src/lib/tpm/tspi.c b/src/lib/tpm/tspi.c index 0d9c6aa..1f2c579 100644 --- a/src/lib/tpm/tspi.c +++ b/src/lib/tpm/tspi.c @@ -19,14 +19,13 @@ #include <reset.h> #include <tpm/tss.h> -#define TPM_PCR_DIGEST_LENGTH 20 #include <tpm/tspi.h> static inline void _debug_init_pcrs(void) { uint32_t result; int pcr_index; - uint8_t digest[TPM_PCR_DIGEST_LENGTH]; + uint8_t digest[SHA1_DIGEST_LENGTH]; for (pcr_index = 0; pcr_index < 24; ++pcr_index) { int digest_offset; @@ -43,11 +42,11 @@ static inline void _debug_init_pcrs(void) printk(BIOS_SPEW, "TPM: PCR %i value is ", pcr_index); for (digest_offset = 0; - digest_offset < TPM_PCR_DIGEST_LENGTH; + digest_offset < SHA1_DIGEST_LENGTH; ++digest_offset) { printk(BIOS_SPEW, "%02x%c", digest[digest_offset], - digest_offset < TPM_PCR_DIGEST_LENGTH - 1 ? + digest_offset < SHA1_DIGEST_LENGTH - 1 ? ':' : '\n'); } } @@ -125,3 +124,37 @@ void init_tpm(int s3resume) hard_reset(); } } + + +void measure_prog(struct prog *program, int pcr, const char *measured_thing) +{ + uint8_t digest[SHA1_DIGEST_LENGTH]; + const uint8_t * start; + size_t size; + + start = prog_start(program); + size = prog_size(program); + + sha1(start, size, digest); + + printk(BIOS_DEBUG, "TPM: Digest for program \"%s\" " + "at %p (%lx bytes): ", + measured_thing, start, size); + for(size = 0; size < SHA1_DIGEST_LENGTH; ++size) { + printk(BIOS_SPEW, "%02x%c", + digest[size], + size < SHA1_DIGEST_LENGTH - 1 ? + ':' : '\n'); + } + + if (tlcl_extend(pcr, digest, digest) == TPM_SUCCESS) { + printk(BIOS_DEBUG, "TPM: PCR[%i] after extension: ", pcr); + + for(size = 0; size < SHA1_DIGEST_LENGTH; ++size) { + printk(BIOS_SPEW, "%02x%c", + digest[size], + size < SHA1_DIGEST_LENGTH - 1 ? + ':' : '\n'); + } + } +}

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Patch set updated for coreboot: lenovo: add config ONBOARD_VGA_IS_PRIMARY
by Patrick Rudolph 11 Mar '16

11 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14031 -gerrit commit fb5e213db271737b738bd963535ca0c7c04aae0b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Mar 10 20:50:42 2016 +0100 lenovo: add config ONBOARD_VGA_IS_PRIMARY Fix for the T4xx and T5xx series. It does not apply to X2xx/X6x series as those have only one GPU, which is always connected to the display. The T6x series needs special care not handled with this patch. Without ONBOARD_VGA_IS_PRIMARY the onboard GPU would be deactivated in case a dedicated GPU is found and active, leaving the system without a working display. Change-Id: I94d1700e9afb75de83a4f2ed1ff53ba3b0559ae1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/lenovo/t400/Kconfig | 4 ++++ src/mainboard/lenovo/t420s/Kconfig | 4 ++++ src/mainboard/lenovo/t430s/Kconfig | 4 ++++ src/mainboard/lenovo/t520/Kconfig | 4 ++++ src/mainboard/lenovo/t530/Kconfig | 4 ++++ 5 files changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 0eac311..d74a813 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -51,4 +51,8 @@ config CBFS_SIZE hex default 0x200000 +config ONBOARD_VGA_IS_PRIMARY + bool + default y + endif # BOARD_LENOVO_T400 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index dc279027..fbfbef5 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -70,4 +70,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21d2 +config ONBOARD_VGA_IS_PRIMARY + bool + default y + endif # BOARD_LENOVO_T420S diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 4e55eda..3f5d4f4 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -67,4 +67,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21fb +config ONBOARD_VGA_IS_PRIMARY + bool + default y + endif # BOARD_LENOVO_T430S diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d5cee9e..55a22ba 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -70,4 +70,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21cf +config ONBOARD_VGA_IS_PRIMARY + bool + default y + endif # BOARD_LENOVO_T520 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 257621f..3a34a9a 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -68,4 +68,8 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex default 0x21fa +config ONBOARD_VGA_IS_PRIMARY + bool + default y + endif # BOARD_LENOVO_T530

1 0

New patch to review for coreboot: coreinfo: Remove the LAR module
by Jonathan Neuschäfer 11 Mar '16

11 Mar '16

Jonathan Neuschäfer just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14037 -gerrit commit 3036ba4a06d7ea0cf26281a258a66e5d5e06c9e4 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Mar 11 17:30:14 2016 +0100 coreinfo: Remove the LAR module Since libpayload's LAR support was dropped in If6e36569cd, this module doesn't compile anymore. Change-Id: I98f25613a1728e94704d9e9ccb65fd6ba33968b9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- payloads/coreinfo/Kconfig | 6 -- payloads/coreinfo/Makefile | 2 +- payloads/coreinfo/coreinfo.c | 4 -- payloads/coreinfo/lar_module.c | 140 ----------------------------------------- 4 files changed, 1 insertion(+), 151 deletions(-) diff --git a/payloads/coreinfo/Kconfig b/payloads/coreinfo/Kconfig index f1d1bf9..e71599c 100644 --- a/payloads/coreinfo/Kconfig +++ b/payloads/coreinfo/Kconfig @@ -98,12 +98,6 @@ config MODULE_RAMDUMP bool "Enable the RAM dump module" default y -config MODULE_LAR - bool "Enable the coreboot v3 LAR module" - help - LAR support must also be enabled in libpayload. - default n - config MODULE_CBFS bool "Enable the coreboot CBFS module" default y diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index c9f5c10..cc59339 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -55,7 +55,7 @@ OBJCOPY ?= objcopy INCLUDES = -I$(obj) -include $(LIBPAYLOAD_DIR)/libpayload/include/kconfig.h OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ - nvram_module.o bootlog_module.o ramdump_module.o lar_module.o \ + nvram_module.o bootlog_module.o ramdump_module.o \ multiboot_module.o cbfs_module.o coreinfo.o OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) TARGET = $(obj)/coreinfo.elf diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 41b5f12..7bc9304 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -24,7 +24,6 @@ extern struct coreinfo_module multiboot_module; extern struct coreinfo_module nvram_module; extern struct coreinfo_module bootlog_module; extern struct coreinfo_module ramdump_module; -extern struct coreinfo_module lar_module; extern struct coreinfo_module cbfs_module; struct coreinfo_module *system_modules[] = { @@ -52,9 +51,6 @@ struct coreinfo_module *firmware_modules[] = { #if IS_ENABLED(CONFIG_MODULE_BOOTLOG) &bootlog_module, #endif -#if IS_ENABLED(CONFIG_MODULE_LAR) - &lar_module, -#endif #if IS_ENABLED(CONFIG_MODULE_CBFS) &cbfs_module, #endif diff --git a/payloads/coreinfo/lar_module.c b/payloads/coreinfo/lar_module.c deleted file mode 100644 index 2cfd762..0000000 --- a/payloads/coreinfo/lar_module.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * This file is part of the coreinfo project. - * - * Copyright (C) 2008 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "coreinfo.h" - -#if IS_ENABLED(CONFIG_MODULE_LAR) - -static struct LAR *lar; -static int lcount, selected; -static char **lnames; -static const char *compression_table[4] = {"none", "LZMA", "NRV2B", "zeroes"}; - -static int lar_module_init(void) -{ - int index = 0; - struct larent *larent; - - lar = openlar(NULL); - - if (lar == NULL) - return 0; - - while ((larent = readlar(lar))) - lcount++; - - lnames = malloc(lcount * sizeof(char *)); - - if (lnames == NULL) - return 0; - - rewindlar(lar); - - while ((larent = readlar(lar))) - lnames[index++] = strdup((const char *) larent->name); - - return 0; -} - -static int lar_module_redraw(WINDOW *win) -{ - int i, row = 2; - struct larstat stat; - - print_module_title(win, "LAR Listing"); - - if (lar == 0) { - mvwprintw(win, 11, 61 / 2, "Bad or missing LAR"); - return 0; - } - - /* Draw a line down the middle. */ - for (i = 2; i < 21; i++) - mvwaddch(win, i, 30, ACS_VLINE); - - /* Draw the names down the left side. */ - for (i = 0; i < lcount; i++) { - if (i == selected) - wattrset(win, COLOR_PAIR(3) | A_BOLD); - else - wattrset(win, COLOR_PAIR(2)); - - mvwprintw(win, 2 + i, 1, "%.25s", lnames[i]); - } - - /* Get the information for the LAR. */ - if (larstat(lar, lnames[selected], &stat)) { - printf("larstat failed\n"); - return 0; - } - - wattrset(win, COLOR_PAIR(2)); - - mvwprintw(win, row++, 32, "Offset: 0x%x", stat.offset); - - if (stat.compression) { - mvwprintw(win, row++, 32, "Compression: %s", - compression_table[stat.compression]); - mvwprintw(win, row++, 32, "Compressed length: %d", stat.len); - mvwprintw(win, row++, 32, "Compressed checksum: 0x%x", - stat.compchecksum); - } - - mvwprintw(win, row++, 32, "Length: %d", stat.reallen); - mvwprintw(win, row++, 32, "Checksum: 0x%x", stat.checksum); - mvwprintw(win, row++, 32, "Load address: 0x%llx", stat.loadaddress); - mvwprintw(win, row++, 32, "Entry point: 0x%llx", stat.entry); - - return 0; -} - -static int lar_module_handle(int key) -{ - int ret = 0; - - if (lar == NULL) - return 0; - - switch (key) { - case KEY_DOWN: - if (selected + 1 < lcount) { - selected++; - ret = 1; - } - break; - case KEY_UP: - if (selected > 0) { - selected--; - ret = 1; - } - break; - } - - return ret; -} - -struct coreinfo_module lar_module = { - .name = "LAR", - .init = lar_module_init, - .redraw = lar_module_redraw, - .handle = lar_module_handle -}; - -#else - -struct coreinfo_module lar_module = { -}; - -#endif

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Patch merged into coreboot/master: crossgcc/Makefile.inc: Add target for jenkins toolchain test build
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 2114880f66ce567bb507b26218f9e88241348ec1 Author: Martin Roth <martinroth(a)google.com> Date: Tue Mar 8 09:27:45 2016 -0700 crossgcc/Makefile.inc: Add target for jenkins toolchain test build We've recently added a jenkins test builder for the coreboot toolchain. This patch allows what it builds to be controlled from the makefiles checked into git instead of by a rule on the builder itself. Change-Id: I65f70bac5ab97ecb27aae93ee370b26a2ab1f9c0 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13954 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13954 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Require minumum training quality for both read and write
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 2e1f73181a770f1c3a8ea5bc1b72bac3732c5c76 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 16:44:39 2016 -0600 nb/amd/mct_ddr3: Require minumum training quality for both read and write The existing MCT code proceeded to the next DRAM training phase if the minimum lane quality standard passed for either the read or write direction. Ensure that both pass for a given set of delay values before proceeding to the next training phase. Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13993 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13993 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 50583f0e1f82f6863762c75acf01c26e163bf2da Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 18:40:28 2016 -0600 nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency must be calculated prior to DQS position training, however the read latency calculations use read DQS delay values that have not been set prior to DQS position training. Set the read DQS delay values to 1UI (i.e worst case) before calculating the read latency prior to DQS position training. Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13995 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13995 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 8eb221deafcdba4311979e09020335b3cc4722f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 7 14:30:47 2016 -0600 nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks A couple of arrays were not properly initialized. This did not appear to affect operation of the codebase however it led to some ugly values being displayed when debugging was turned on. Also bounds check an array index; as before this did not appear to affect operation but was a potential point of failure. Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13934 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13934 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit bbfcf625124da70f67675f2f85aec44ecda00b3e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Mar 7 09:10:31 2016 -0600 nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13931 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13931 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Avoid hardcoding CAR region size for FSPM
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 7109304cf241e22923d83344050eb6b30b31484d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Mar 8 21:59:01 2016 -0800 soc/intel/apollolake: Avoid hardcoding CAR region size for FSPM Instead of having to supply CAR memory region during compilation time it is possible to determine it in runtime. FSP2.0 blobs carry a copy of UPD structure pre-populated with 'default' values. The default value for StackSize is actually the real value blob needs. Change-Id: I298e07bb12470ce659f63846ab096189138e594f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14001 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14001 for details. -gerrit

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Patch merged into coreboot/master: payloads/seabios: Update version number in Kconfig
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 468dc3332531510b0bf0708ecc446732fb0b8b2c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Mar 9 18:36:46 2016 +0100 payloads/seabios: Update version number in Kconfig Fix up commit 4f66648c (payloads/seabios: Upgrade stable from 1.9.0 to 1.9.1), forgetting to update the version number displayed in the Kconfig menu, by updating the string to 1.9.1. Change-Id: Idb395d0ea65bcf91c7c9645fd76d428936e91587 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: https://review.coreboot.org/14010 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14010 for details. -gerrit

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coreboot-gerrit March 2016