coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/intel/apollolake: Avoid UART BAR relocation at ramstage
by gerrit＠coreboot.org 10 Mar '16

10 Mar '16

the following patch was just integrated into master: commit 1e70cda320df24e477d8ee80a88e9add2eb535c9 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Mar 8 16:12:06 2016 -0800 soc/intel/apollolake: Avoid UART BAR relocation at ramstage UART bar gets overwritten during resource allocation stage. As result the serial driver ends up using stale BAR so serial output does not work. This driver simply tells resource allocator not to change BAR of UART device. Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13997 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13997 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Add ids of internal SoC PCI devices
by gerrit＠coreboot.org 10 Mar '16

10 Mar '16

the following patch was just integrated into master: commit e953dce7c463824a607cca6d845615e87d0dda6e Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Mar 8 15:57:53 2016 -0800 soc/intel/apollolake: Add ids of internal SoC PCI devices Change-Id: I6a632ca7d4a19c4973c41bb102f97e0836f27a5e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13996 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13996 for details. -gerrit

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Patch merged into coreboot/master: mainboard/intel/apollolake_rvp: Populate static devicetree
by gerrit＠coreboot.org 10 Mar '16

10 Mar '16

the following patch was just integrated into master: commit ffc51d475a428c01fc57977b75de328f6f818aa0 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Sun Mar 6 22:19:31 2016 -0800 mainboard/intel/apollolake_rvp: Populate static devicetree Add configuration in accordance to "PCI Configuration Matrix". Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13926 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13926 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Add chip initialization
by gerrit＠coreboot.org 10 Mar '16

10 Mar '16

the following patch was just integrated into master: commit 70efecd4a21c4adc7cbfb5fcdbc8b9bfedbaa270 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 4 21:41:13 2016 -0800 soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13911 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13911 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Add chip initialization
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13911 -gerrit commit a75c846de88036d9ef3f2393325b53e2efa26d75 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 4 21:41:13 2016 -0800 soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 113 ++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 32 ++++++++++ 3 files changed, 146 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b31f12..1b2efdf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += cpu.c +ramstage-y += chip.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c new file mode 100644 index 0000000..2374a88 --- /dev/null +++ b/src/soc/intel/apollolake/chip.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <soc/cpu.h> +#include <soc/pci_devs.h> + +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = apollolake_init_cpus, + .scan_bus = NULL, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + struct range_entry range; + + /* TODO: tigten this resource range */ + /* TODO: fix for S3 resume, as this would corrupt OS memory */ + range_entry_init(&range, 0x200000, 4ULL*GiB, 0); + fsp_silicon_init(&range); +} + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ + struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; + static struct soc_intel_apollolake_config *cfg; + + /* Load VBT before devicetree-specific config. */ + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + + struct device *dev = NB_DEV_ROOT; + if (!dev && !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; + silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; + silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; + silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; + silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; + silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; +} + +struct chip_operations soc_intel_apollolake_ops = { + CHIP_NAME("Intel Apollolake SOC") + .enable_dev = &enable_dev, + .init = &soc_init +}; + +static void fsp_notify_dummy(void *arg) +{ + + enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; + + if (fsp_notify(ph) != FSP_SUCCESS) + printk(BIOS_CRIT, "FspNotify failed!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h new file mode 100644 index 0000000..026fdda --- /dev/null +++ b/src/soc/intel/apollolake/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CHIP_H_ +#define _SOC_APOLLOLAKE_CHIP_H_ + +#define CLKREQ_DISABLED 0xf + +struct soc_intel_apollolake_config { + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + uint8_t pcie_rp0_clkreq_pin; + uint8_t pcie_rp1_clkreq_pin; + uint8_t pcie_rp2_clkreq_pin; + uint8_t pcie_rp3_clkreq_pin; + uint8_t pcie_rp4_clkreq_pin; + uint8_t pcie_rp5_clkreq_pin; +}; + +#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch merged into coreboot/master: soc/apollolake: Enable all CPU cores using the parallel MP lib
by gerrit＠coreboot.org 10 Mar '16

10 Mar '16

the following patch was just integrated into master: commit 9d903a1dd352ce16c6e6feee5f63e3b21c821111 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Fri Mar 4 21:33:04 2016 -0800 soc/apollolake: Enable all CPU cores using the parallel MP lib This is the minimal setup needed to get all CPU cores enabled. That includes sending an IPI to APs and setting up MTRRs. Microcode updates are not performed for two reasons: * CSE (Converged Security Engine) upgrades the microcode before releasing reset * Microcode update files are not available at this point in time Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/13910 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13910 for details. -gerrit

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Populate static devicetree
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13926 -gerrit commit 214cd394628c5d898f054f90e7edbb2a4b68cd6b Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Sun Mar 6 22:19:31 2016 -0800 mainboard/intel/apollolake_rvp: Populate static devicetree Add configuration in accordance to "PCI Configuration Matrix". Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/devicetree.cb | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index d624bc0..746aaf3 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -1,9 +1,56 @@ chip soc/intel/apollolake + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + device cpu_cluster 0 on device lapic 0 on end end device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS end end

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Patch set updated for coreboot: soc/intel/apollolake: Add chip initialization
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13911 -gerrit commit 990ee5de8e319a3bd14a8849fa34454b21b49037 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Mar 4 21:41:13 2016 -0800 soc/intel/apollolake: Add chip initialization Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 113 ++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 32 ++++++++++ 3 files changed, 146 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3b31f12..1b2efdf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += mmap_boot.c smm-y += placeholders.c ramstage-y += cpu.c +ramstage-y += chip.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c new file mode 100644 index 0000000..2374a88 --- /dev/null +++ b/src/soc/intel/apollolake/chip.c @@ -0,0 +1,113 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <soc/cpu.h> +#include <soc/pci_devs.h> + +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = apollolake_init_cpus, + .scan_bus = NULL, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void soc_init(void *data) +{ + struct range_entry range; + + /* TODO: tigten this resource range */ + /* TODO: fix for S3 resume, as this would corrupt OS memory */ + range_entry_init(&range, 0x200000, 4ULL*GiB, 0); + fsp_silicon_init(&range); +} + +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) +{ + struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig; + static struct soc_intel_apollolake_config *cfg; + + /* Load VBT before devicetree-specific config. */ + silconfig->GraphicsConfigPtr = fsp_load_vbt(); + + struct device *dev = NB_DEV_ROOT; + if (!dev && !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; + silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; + silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; + silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; + silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; + silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; +} + +struct chip_operations soc_intel_apollolake_ops = { + CHIP_NAME("Intel Apollolake SOC") + .enable_dev = &enable_dev, + .init = &soc_init +}; + +static void fsp_notify_dummy(void *arg) +{ + + enum fsp_notify_phase ph = (enum fsp_notify_phase) arg; + + if (fsp_notify(ph) != FSP_SUCCESS) + printk(BIOS_CRIT, "FspNotify failed!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy, + (void *) AFTER_PCI_ENUM); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy, + (void *) READY_TO_BOOT); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy, + (void *) READY_TO_BOOT); diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h new file mode 100644 index 0000000..026fdda --- /dev/null +++ b/src/soc/intel/apollolake/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CHIP_H_ +#define _SOC_APOLLOLAKE_CHIP_H_ + +#define CLKREQ_DISABLED 0xf + +struct soc_intel_apollolake_config { + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + uint8_t pcie_rp0_clkreq_pin; + uint8_t pcie_rp1_clkreq_pin; + uint8_t pcie_rp2_clkreq_pin; + uint8_t pcie_rp3_clkreq_pin; + uint8_t pcie_rp4_clkreq_pin; + uint8_t pcie_rp5_clkreq_pin; +}; + +#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch set updated for coreboot: soc/apollolake: Enable all CPU cores using the parallel MP lib
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13910 -gerrit commit 0e568707d083c6f33f84e924500dc9fe30939ac5 Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Fri Mar 4 21:33:04 2016 -0800 soc/apollolake: Enable all CPU cores using the parallel MP lib This is the minimal setup needed to get all CPU cores enabled. That includes sending an IPI to APs and setting up MTRRs. Microcode updates are not performed for two reasons: * CSE (Converged Security Engine) upgrades the microcode before releasing reset * Microcode update files are not available at this point in time Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 2 + src/soc/intel/apollolake/cpu.c | 97 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 6 ++ 3 files changed, 105 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index dd2213e..3b31f12 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S @@ -24,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += cpu.c ramstage-y += placeholders.c ramstage-y += gpio.c ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c new file mode 100644 index 0000000..0724439 --- /dev/null +++ b/src/soc/intel/apollolake/cpu.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/cpu.h> + +static struct device_operations cpu_dev_ops = { + .init = DEVICE_NOOP, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, + { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) +{ + msr_t msr; + msr = rdmsr(MSR_CORE_THREAD_COUNT); + *num_virt = (msr.lo >> 0) & 0xffff; + *num_phys = (msr.lo >> 16) & 0xffff; +} + +/* + * Do essential initialization tasks before APs can be fired up + * + * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This + * creates the MTRR solution that the APs will use. Otherwise APs will try to + * apply the incomplete solution as the BSP is calculating it. + */ +static void bsp_pre_mp_setup(void) +{ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +/* + * CPU initialization recipe + * + * Note that no microcode update is passed to the init function. CSE updates + * the microcode on all cores before releasing them from reset. That means that + * the BSP and all APs will come up with the same microcode revision. + */ +static struct mp_flight_record flight_plan[] = { + /* NOTE: MTRR solution must be calculated before firing up the APs */ + MP_FR_NOBLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), +}; + +void apollolake_init_cpus(device_t dev) +{ + unsigned int num_virt_cores, num_phys_cores; + + /* Pre-flight check */ + bsp_pre_mp_setup(); + + /* Find CPU topology */ + read_cpu_topology(&num_phys_cores, &num_virt_cores); + printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", + num_phys_cores, num_virt_cores); + + /* Systems check */ + struct mp_params flight_data_recorder = { + .num_cpus = num_virt_cores, + .parallel_microcode_load = 0, + .microcode_pointer = NULL, + .adjust_apic_id = NULL, + .flight_plan = flight_plan, + .num_records = ARRAY_SIZE(flight_plan), + }; + + /* Clear for take-off */ + if (mp_init(dev->link_list, &flight_data_recorder) < 0) + printk(BIOS_ERR, "MP initialization failure.\n"); +} diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 870f474..765be70 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -14,12 +14,18 @@ #define _SOC_APOLLOLAKE_CPU_H_ #include <cpu/x86/msr.h> +#include <device/device.h> #define CPUID_APOLLOLAKE_A0 0x506c8 +#define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 +#define MSR_CORE_THREAD_COUNT 0x35 #define BASE_CLOCK_MHZ 100 +void apollolake_init_cpus(struct device *dev); + + #endif /* _SOC_APOLLOLAKE_CPU_H_ */

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Patch set updated for coreboot: cbmem: Add utility to get memory region occupied by cbmem
by Andrey Petrov 10 Mar '16

10 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13363 -gerrit commit cedb8c6abb3ca313c20b9132a2b5e7a821b24299 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Nov 16 13:26:33 2015 -0800 cbmem: Add utility to get memory region occupied by cbmem Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/include/cbmem.h | 2 ++ src/lib/imd_cbmem.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efaa44f..2e947a1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -109,6 +109,8 @@ int cbmem_recovery(int s3resume); void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +/* Get location and size of CBMEM region in memory */ +void cbmem_region_used(uintptr_t *base, size_t *size); /* Indicate to each hook if cbmem is being recovered or not. */ typedef void (* const cbmem_init_hook_t)(int is_recovery); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 49faad9..e75c538 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -263,12 +263,19 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } +void cbmem_region_used(uintptr_t *base, size_t *size) +{ + void *baseptr; + imd_region_used(cbmem_get_imd(), &baseptr, size); + *base = (uintptr_t)baseptr; +} + void cbmem_add_bootmem(void) { void *base = NULL; size_t size = 0; - imd_region_used(cbmem_get_imd(), &base, &size); + cbmem_region_used(base, &size); bootmem_add_range((uintptr_t)base, size, LB_MEM_TABLE); }

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coreboot-gerrit March 2016