coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

New patch to review for coreboot: intel/fsp_baytrail: Enable LPSS in ACPI mode
by Ben Gardner 11 Mar '16

11 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14042 -gerrit commit 67b3ee13903965b55e31a296f04c09c737f9cf36 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Mar 11 16:29:54 2016 -0600 intel/fsp_baytrail: Enable LPSS in ACPI mode This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would result in unusable devices, as the resources were set to 0 and the devices were disabled. lpss.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode set to disable and the devicetree set to default. Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560 Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/lpss.c | 202 ++++++++++++++++++++++++++++++++ 2 files changed, 203 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 41672e6..805ae68 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -49,6 +49,7 @@ romstage-y += reset.c ramstage-y += reset.c ramstage-y += cpu.c ramstage-y += acpi.c +ramstage-y += lpss.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c new file mode 100644 index 0000000..427fc6d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/lpss.c @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iosf.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#include "chip.h" + +static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, + LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpss_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} + +static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +{ + struct reg_script ops[] = { + REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, + ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), + LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), + REG_SCRIPT_END, + }; + + reg_script_run_on_dev(dev, ops); +} + +static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +{ + *iosf_reg = -1; + *nvs_index = -1; +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_ + + switch (dev->path.pci.devfn) { + SET_IOSF_REG(SIO_DMA1); + break; + SET_IOSF_REG(I2C1); + break; + SET_IOSF_REG(I2C2); + break; + SET_IOSF_REG(I2C3); + break; + SET_IOSF_REG(I2C4); + break; + SET_IOSF_REG(I2C5); + break; + SET_IOSF_REG(I2C6); + break; + SET_IOSF_REG(I2C7); + break; + SET_IOSF_REG(SIO_DMA2); + break; + SET_IOSF_REG(PWM1); + break; + SET_IOSF_REG(PWM2); + break; + SET_IOSF_REG(HSUART1); + break; + SET_IOSF_REG(HSUART2); + break; + SET_IOSF_REG(SPI); + break; + } +} + +static void i2c_disable_resets(device_t dev) +{ + /* Release the I2C devices from reset. */ + static const struct reg_script ops[] = { + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), + REG_SCRIPT_END, + }; + +#define CASE_I2C(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1): + CASE_I2C(I2C2): + CASE_I2C(I2C3): + CASE_I2C(I2C4): + CASE_I2C(I2C5): + CASE_I2C(I2C6): + CASE_I2C(I2C7): + printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); + reg_script_run_on_dev(dev, ops); + break; + default: + return; + } +} + +static void lpss_init(device_t dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + int iosf_reg, nvs_index; + + dev_ctl_reg(dev, &iosf_reg, &nvs_index); + + if (iosf_reg < 0) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", + slot, func); + return; + } + dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); + + if (config->PcdLpssSioEnablePciMode == LPSS_PCI_MODE_DISABLE) + dev_enable_acpi_mode(dev, iosf_reg, nvs_index); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpss_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + SIO_DMA1_DEVID, + I2C1_DEVID, + I2C2_DEVID, + I2C3_DEVID, + I2C4_DEVID, + I2C5_DEVID, + I2C6_DEVID, + I2C7_DEVID, + SIO_DMA2_DEVID, + PWM1_DEVID, + PWM2_DEVID, + HSUART1_DEVID, + HSUART2_DEVID, + SPI_DEVID, + 0, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

1 0

Patch set updated for coreboot: abuild: Add option of starting with an existing defconfig file
by Martin Roth 11 Mar '16

11 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14016 -gerrit commit 3e457c62e9f382ce8fb2b93b5bb1ba4428427f01 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 9 13:12:10 2016 -0700 abuild: Add option of starting with an existing defconfig file We want to start testing builds with additional Kconfig options to try to get more coverage. This will allow us to enable various options to test without having to add each individual option to the abuild script. Change-Id: I9bb2bb6f38589e3bcc1282dc4cad51cf6f5149aa Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/abuild/abuild | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index ffa16b5..a2a428b 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -410,6 +410,7 @@ Options:\n" [-o|--outdir <path>] store build results in path (defaults to $TARGET) [-L|--clang] Use clang + [-K|--kconfig <name>] Prepend file to generated Kconfig [-x|--chromeos] Build with CHROMEOS enabled Skip boards without Chrome OS support [-X|--xmlfile <name>] set JUnit XML log file filename @@ -456,11 +457,11 @@ cmdline="$* -c 1" getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,verbose,quiet,help,all,target:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,clean,outdir:,chromeos,xmlfile: -o Vvqhat:p:c:sJCl:rP:uyBLzo:xX: -- "$@"` || exit 1 + args=`getopt -l version,verbose,quiet,help,all,target:,payloads:,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang,clean,outdir:,chromeos,xmlfile:,kconfig: -o Vvqhat:p:c:sJCl:rP:uyBLzo:xX:K: -- "$@"` || exit 1 eval set -- $args else # Detected non-GNU getopt - args=`getopt Vvqhat:p:c:sJCl:rP:uyBLzo:xX: $*` + args=`getopt Vvqhat:p:c:sJCl:rP:uyBLzo:xX:K: $*` set -- $args fi @@ -538,6 +539,11 @@ while true ; do configoptions="${configoptions}CONFIG_CHROMEOS=y\n" ;; -X|--xmlfile) shift; XMLFILE=$1; REAL_XMLFILE=$1; shift;; + -K|--kconfig) shift + testclass=="$(basename $1 | tr '.' '_' )" + customizing="${customizing}, $1 config" + configoptions="$(cat "$1")${configoptions}\n" + shift;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;;

1 0

New patch to review for coreboot: intel/fsp_baytrail: Fix LPE initialization and enable ACPI mode
by Ben Gardner 11 Mar '16

11 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14041 -gerrit commit c3a28af5a284f29327f03938155ba4881f646232 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Mar 11 15:20:32 2016 -0600 intel/fsp_baytrail: Fix LPE initialization and enable ACPI mode This change properly assigns resources to the LPE (Low Power Engine for Audio) and enables ACPI mode. lpe.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting LpeAcpiModeEnable=LPE_ACPI_MODE_ENABLED and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ Change-Id: I3fff9aa158bde88e571082642d4f985a5ae1976e Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/chip.h | 4 + src/soc/intel/fsp_baytrail/lpe.c | 185 ++++++++++++++++++++++++++++++++ 3 files changed, 190 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 41672e6..65eb55f 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -49,6 +49,7 @@ romstage-y += reset.c ramstage-y += reset.c ramstage-y += cpu.c ramstage-y += acpi.c +ramstage-y += lpe.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index 35dafa9..156a084 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -342,6 +342,10 @@ struct soc_intel_fsp_baytrail_config { uint8_t DIMMtFAW; #define DIMM_TFAW_DEFAULT UPD_DEFAULT + /* LPE Audio Clock configuration. */ + int lpe_codec_clk_freq; /* 19 or 25 are valid. */ + int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + /* ***** ACPI configuration ***** */ /* Options for these are in src/arch/x86/include/arch/acpi.h */ uint8_t fadt_pm_profile; diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c new file mode 100644 index 0000000..4fbdce1 --- /dev/null +++ b/src/soc/intel/fsp_baytrail/lpe.c @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/lpc.h> +#include <soc/nvs.h> +#include <soc/pattrs.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/ramstage.h> +#include "chip.h" + + +/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. */ +#define FIRMWARE_PHYS_BASE (512 << 20) +#define FIRMWARE_PHYS_LENGTH (1 << 20) +#define FIRMWARE_PCI_REG_BASE 0xa8 +#define FIRMWARE_PCI_REG_LENGTH 0xac +#define FIRMWARE_REG_BASE_C0 0x144000 +#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) + +static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +{ + struct resource *res; + + res = find_resource(dev, index); + if (res) + *field = res->base; +} + +static void lpe_enable_acpi_mode(device_t dev) +{ + static const struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, + LPE_PCICFGCTR1_PCI_CFG_DIS | + LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END + }; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0, BAR1, and firmware base to ACPI NVS */ + assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); + assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); + assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpe_en = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} + +static void setup_codec_clock(device_t dev) +{ + uint32_t reg; + u32 *clk_reg; + struct soc_intel_fsp_baytrail_config *config; + const char *freq_str; + + config = dev->chip_info; + switch (config->lpe_codec_clk_freq) { + case 19: + freq_str = "19.2"; + reg = CLK_FREQ_19P2MHZ; + break; + case 25: + freq_str = "25"; + reg = CLK_FREQ_25MHZ; + break; + default: + printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + return; + } + + /* Default to always running. */ + reg |= CLK_CTL_ON; + + if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { + printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); + return; + } + + printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); + + clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg += config->lpe_codec_clk_num; + + write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); +} + +static void lpe_stash_firmware_info(device_t dev) +{ + struct resource *res; + struct resource *mmio; + const struct pattrs *pattrs = pattrs_get(); + + res = find_resource(dev, FIRMWARE_PCI_REG_BASE); + if (res == NULL) { + printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); + return; + } + + /* Continue using old way of informing firmware address / size. */ + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); + + /* C0 and later steppings use an offset in the MMIO space. */ + if (pattrs->stepping >= STEP_C0) { + mmio = find_resource(dev, PCI_BASE_ADDRESS_0); + write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), + res->base); + write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), + res->size); + } +} + +static void lpe_init(device_t dev) +{ + struct soc_intel_fsp_baytrail_config *config = dev->chip_info; + + lpe_stash_firmware_info(dev); + + setup_codec_clock(dev); + + if (config->LpeAcpiModeEnable == LPE_ACPI_MODE_ENABLED) + lpe_enable_acpi_mode(dev); +} + +static void lpe_read_resources(device_t dev) +{ + pci_dev_read_resources(dev); + + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, + FIRMWARE_PHYS_BASE >> 10, + FIRMWARE_PHYS_LENGTH >> 10); +} + +static const struct device_operations device_ops = { + .read_resources = lpe_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpe_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPE_DEVID, +};

1 0

Patch merged into coreboot/master: crossgcc/buildgcc: Add missing quotation mark
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit f14f640168ee0269b3c443cd2bba2fc8ee66e419 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Mar 11 20:22:23 2016 +0100 crossgcc/buildgcc: Add missing quotation mark Change-Id: I5c20fd7057751a912aa2b2118dc5610c1ef647dc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/14039 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See https://review.coreboot.org/14039 for details. -gerrit

1 0

New patch to review for coreboot: intel/fsp_baytrail: Don't clear gnvs in acpi_init_gnvs()
by Ben Gardner 11 Mar '16

11 Mar '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14040 -gerrit commit 9b251ffa2da05a62cd5da3c73ab5b033789e58a9 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Fri Mar 11 14:50:35 2016 -0600 intel/fsp_baytrail: Don't clear gnvs in acpi_init_gnvs() That wipes out all previously stored settings and breaks running devices in ACPI mode. This more closely matches what is done in intel/baytrail. Change-Id: Ie993c9f9e1eceb73d016d2df72770a27abb26ec1 Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/acpi.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index e55709c..0156816 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -85,9 +85,6 @@ static acpi_cstate_t cstate_map[] = { void acpi_init_gnvs(global_nvs_t *gnvs) { - /* Clear gnvs area so uninitialized portions are defined */ - memset(gnvs, 0, sizeof(*gnvs)); - /* CPU core count */ gnvs->pcnt = dev_count_cpu();

1 0

New patch to review for coreboot: crossgcc/buildgcc: Add missing quotation mark
by Jonathan Neuschäfer 11 Mar '16

11 Mar '16

Jonathan Neuschäfer just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14039 -gerrit commit 8ca31303b2da934c667793302d22d2cbcf697db7 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Fri Mar 11 20:22:23 2016 +0100 crossgcc/buildgcc: Add missing quotation mark Change-Id: I5c20fd7057751a912aa2b2118dc5610c1ef647dc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- util/crossgcc/buildgcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 67ff1b6..f88c09c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -344,7 +344,7 @@ myhelp() printf " [-S|--scripting] build scripting support for GDB\n\n" printf "Platforms for GCC & GDB:\n" printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" - printf " powerpc64le-linux-gnu nds32le-elf\n\n + printf " powerpc64le-linux-gnu nds32le-elf\n\n" } printversion() {

1 0

Patch merged into coreboot/master: northbridge/intel: move mrccache.c of sandybridge + haswell to common
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 92fc072c2faf3d1be82f50ee3feda42461e9ac16 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 14:36:46 2016 +0100 northbridge/intel: move mrccache.c of sandybridge + haswell to common The sourcecode is 99% the same. Only two lines differ, but not in functionality. Also rename mrccache.c -> mrc_cache.c Tested-on: boot + suspend/resume on x220 Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/14007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14007 for details. -gerrit

1 0

Patch merged into coreboot/master: northbridge/intel: move mrc_cache definition into a common header
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 81c5c761b305dd62019759e5e39248b02c0af820 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 03:13:45 2016 +0100 northbridge/intel: move mrc_cache definition into a common header The mrc_cache definition and the struct mrc_container are the same over all intel platforms. Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/13998 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13998 for details. -gerrit

1 0

Patch merged into coreboot/master: spi/SST: fix write support for SST25VF064C
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit 013accca7fb955dd04ee8a51d98e3d94a4941346 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 05:11:44 2016 +0100 spi/SST: fix write support for SST25VF064C The SST25VF064C doesn't support the auto incrementing write which all other supported SST chips support. Allow the chips to select their write method. Change-Id: Ic088d35461a625469ee6973d1267d7dd11963496 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/14000 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14000 for details. -gerrit

1 0

Patch merged into coreboot/master: nortbridge/sandybridge/mrccache: parse the return code of flash->write
by gerrit＠coreboot.org 11 Mar '16

11 Mar '16

the following patch was just integrated into master: commit f0ab23cb031b4430fa5690ced901bfd741db5832 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Wed Mar 9 04:02:42 2016 +0100 nortbridge/sandybridge/mrccache: parse the return code of flash->write Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/13999 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13999 for details. -gerrit

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2016