coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

1 participants
1119 discussions

New patch to review for coreboot: drivers/ati: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14054 -gerrit commit baf03a989b9b3aaa5d8cb84fd98983e4f704a3b7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:33:35 2016 -0800 drivers/ati: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iba43630208be02603f4e0de5f62047bb3d23863a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/ati/Kconfig | 1 - src/drivers/ati/Makefile.inc | 1 - 2 files changed, 2 deletions(-) diff --git a/src/drivers/ati/Kconfig b/src/drivers/ati/Kconfig deleted file mode 100644 index f1ea32c..0000000 --- a/src/drivers/ati/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/ati/ragexl/Kconfig diff --git a/src/drivers/ati/Makefile.inc b/src/drivers/ati/Makefile.inc deleted file mode 100644 index 15b5dfc..0000000 --- a/src/drivers/ati/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += ragexl

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New patch to review for coreboot: drivers/aspeed: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14053 -gerrit commit bfc0f1e5c2f76f556754cf922faec94d244b61d6 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:32:34 2016 -0800 drivers/aspeed: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I8cf021ea5baff05eb5f84cc014612084afe3f858 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/aspeed/Kconfig | 2 -- src/drivers/aspeed/Makefile.inc | 1 - 2 files changed, 3 deletions(-) diff --git a/src/drivers/aspeed/Kconfig b/src/drivers/aspeed/Kconfig deleted file mode 100644 index 3b0238b..0000000 --- a/src/drivers/aspeed/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -source src/drivers/aspeed/common/Kconfig -source src/drivers/aspeed/ast2050/Kconfig diff --git a/src/drivers/aspeed/Makefile.inc b/src/drivers/aspeed/Makefile.inc deleted file mode 100644 index 2553464..0000000 --- a/src/drivers/aspeed/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += common ast2050

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New patch to review for coreboot: drivers/ricoh: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14052 -gerrit commit 27933af99396d4367d17c9757d4e7110136279c9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:31:23 2016 -0800 drivers/ricoh: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I3cf32ec58ba40db11fae3dda6dcb2375002e7cb4 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/ricoh/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/drivers/ricoh/Kconfig b/src/drivers/ricoh/Kconfig deleted file mode 100644 index 6b05142..0000000 --- a/src/drivers/ricoh/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/ricoh/rce822/Kconfig

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New patch to review for coreboot: drivers/sil: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14051 -gerrit commit a07233687627265328f400de74f7626c6be54411 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:30:35 2016 -0800 drivers/sil: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Ifc32b251677f8b75ffca224c0c900e9c34c756b9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/sil/Kconfig | 1 - src/drivers/sil/Makefile.inc | 1 - 2 files changed, 2 deletions(-) diff --git a/src/drivers/sil/Kconfig b/src/drivers/sil/Kconfig deleted file mode 100644 index 69f53d9..0000000 --- a/src/drivers/sil/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "src/drivers/sil/3114/Kconfig" diff --git a/src/drivers/sil/Makefile.inc b/src/drivers/sil/Makefile.inc deleted file mode 100644 index 6826fc2..0000000 --- a/src/drivers/sil/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += 3114

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New patch to review for coreboot: drivers/ti: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14050 -gerrit commit 1e528b880f2ec181d504d3e0835b16fa1d1a464e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:29:45 2016 -0800 drivers/ti: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Iac737e15db512eac96cd16fe14983b66a03876bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/ti/Kconfig | 17 ----------------- src/drivers/ti/Makefile.inc | 18 ------------------ 2 files changed, 35 deletions(-) diff --git a/src/drivers/ti/Kconfig b/src/drivers/ti/Kconfig deleted file mode 100644 index 7c5ace9..0000000 --- a/src/drivers/ti/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The Chromium OS Authors. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -source src/drivers/ti/tps65090/Kconfig -source src/drivers/ti/tps65913/Kconfig diff --git a/src/drivers/ti/Makefile.inc b/src/drivers/ti/Makefile.inc deleted file mode 100644 index 8c6e62c..0000000 --- a/src/drivers/ti/Makefile.inc +++ /dev/null @@ -1,18 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2012 The Chromium OS Authors. -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-$(CONFIG_DRIVER_TI_TPS65090) += tps65090/ -subdirs-$(CONFIG_DRIVERS_TI_TPS65913) += tps65913/

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New patch to review for coreboot: drivers/xgi: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14049 -gerrit commit d5b6ddd5abda029062af9b1e4533acc1b714c720 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:28:55 2016 -0800 drivers/xgi: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I2cd6c1f1712e77ff98a9557519fb8efeeb400a69 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/xgi/Kconfig | 2 -- src/drivers/xgi/Makefile.inc | 1 - 2 files changed, 3 deletions(-) diff --git a/src/drivers/xgi/Kconfig b/src/drivers/xgi/Kconfig deleted file mode 100644 index dea25ea..0000000 --- a/src/drivers/xgi/Kconfig +++ /dev/null @@ -1,2 +0,0 @@ -source src/drivers/xgi/common/Kconfig -source src/drivers/xgi/z9s/Kconfig diff --git a/src/drivers/xgi/Makefile.inc b/src/drivers/xgi/Makefile.inc deleted file mode 100644 index ce83d7a..0000000 --- a/src/drivers/xgi/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-y += common z9s \ No newline at end of file

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New patch to review for coreboot: drivers/xpowers: Switch to src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14048 -gerrit commit cc0e4f72901a5a032ee1d211f71fdd4a021e2d3a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:17:55 2016 -0800 drivers/xpowers: Switch to src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: Idae5ee5f1f48d904b704abe618165c0bec839979 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/drivers/xpowers/Kconfig | 1 - src/drivers/xpowers/Makefile.inc | 1 - src/drivers/xpowers/axp209/Makefile.inc | 10 +++++++--- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/drivers/xpowers/Kconfig b/src/drivers/xpowers/Kconfig deleted file mode 100644 index 3ac2748..0000000 --- a/src/drivers/xpowers/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/xpowers/axp209/Kconfig diff --git a/src/drivers/xpowers/Makefile.inc b/src/drivers/xpowers/Makefile.inc deleted file mode 100644 index ef6dffc..0000000 --- a/src/drivers/xpowers/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209 diff --git a/src/drivers/xpowers/axp209/Makefile.inc b/src/drivers/xpowers/axp209/Makefile.inc index 5ac691e..e08a8e2 100644 --- a/src/drivers/xpowers/axp209/Makefile.inc +++ b/src/drivers/xpowers/axp209/Makefile.inc @@ -1,3 +1,7 @@ -bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c -romstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c -ramstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c +ifeq ($(CONFIG_DRIVER_XPOWERS_AXP209),y) + +bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c +romstage-y += axp209.c +ramstage-y += axp209.c + +endif

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New patch to review for coreboot: kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme
by Stefan Reinauer 12 Mar '16

12 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14047 -gerrit commit 5ed87017c8934e528d168b78615cb5afab160f31 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Mar 11 20:22:28 2016 -0800 kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make them pluggable. Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 4 +++- src/Kconfig | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 7ed229e..ffe587f 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -69,7 +69,9 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs build_complete subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) -subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode +subdirs-y += src/superio +subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) +subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom subdirs-y += util/futility util/marvell subdirs-y += $(wildcard src/arch/*) diff --git a/src/Kconfig b/src/Kconfig index 3def65b..0fa1397 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -432,6 +432,7 @@ source "src/superio/*/Kconfig" comment "Embedded Controllers" source "src/ec/acpi/Kconfig" source "src/ec/*/*/Kconfig" +# FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" @@ -445,6 +446,7 @@ source "src/device/Kconfig" menu "Generic Drivers" source "src/drivers/*/Kconfig" +source "src/drivers/*/*/Kconfig" endmenu config RTC

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Patch set updated for coreboot: util/ifdtool: add option to change chip density
by Jan Tatje 12 Mar '16

12 Mar '16

Jan Tatje just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14032 -gerrit commit 699321ac6a5de885ad7170429035d313488e4d53 Author: Jan Tatje <jan(a)jnt.io> Date: Fri Mar 11 00:52:07 2016 +0100 util/ifdtool: add option to change chip density Adds -D / --density option to change the chip density. This is only implemented for IFD version 1 as I do not have an IFD version 2 to test this. Density of both chips is changed by default, but a chip can be selected using -C / --chip. Change-Id: Iba7affbf6cbefa3147b7b0e019298d905e694716 Signed-off-by: Jan Tatje <jan(a)jnt.io> --- util/ifdtool/ifdtool.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 112 insertions(+), 3 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 8a12725..a9eb4cb 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -28,6 +28,7 @@ #endif static int ifd_version; +static int selected_chip = 0; static const struct region_name region_names[MAX_REGIONS] = { { "Flash Descriptor", "fd" }, @@ -748,6 +749,59 @@ static void set_em100_mode(char *filename, char *image, int size) set_spi_frequency(filename, image, size, freq); } +static void set_chipdensity(char *filename, char *image, int size, + unsigned int density) +{ + fdbar_t *fdb = find_fd(image, size); + fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)); + + printf("Setting chip density to "); + decode_component_density(density); + printf("\n"); + + switch (ifd_version) { + case IFD_VERSION_1: + /* fail if selected density is not supported by this version */ + if ( (density == COMPONENT_DENSITY_32MB) || + (density == COMPONENT_DENSITY_64MB) || + (density == COMPONENT_DENSITY_UNUSED) ) { + printf("error: Selected density not supported in IFD version 1.\n"); + exit(EXIT_FAILURE); + } + break; + case IFD_VERSION_2: + /* I do not have a version 2 IFD nor do i have the docs. */ + printf("error: Changing the chip density for IFD version 2 has not been" + " implemented yet.\n"); + exit(EXIT_FAILURE); + default: + printf("error: Unknown IFD version\n"); + exit(EXIT_FAILURE); + break; + } + + /* clear chip density for corresponding chip */ + switch (selected_chip) { + case 1: + fcba->flcomp &= ~(0x7); + break; + case 2: + fcba->flcomp &= ~(0x7 << 3); + break; + default: /*both chips*/ + fcba->flcomp &= ~(0x3F); + break; + } + + /* set the new density */ + if (selected_chip == 1 || selected_chip == 0) + fcba->flcomp |= (density); /* first chip */ + if (selected_chip == 2 || selected_chip == 0) + fcba->flcomp |= (density << 3); /* second chip */ + + write_image(filename, image, size); +} + static void lock_descriptor(char *filename, char *image, int size) { int wr_shift, rd_shift; @@ -1075,6 +1129,10 @@ static void print_usage(const char *name) " -i | --inject <region>:<module> inject file <module> into region <region>\n" " -n | --newlayout <filename> update regions using a flashrom layout file\n" " -s | --spifreq <17|20|30|33|48|50> set the SPI frequency\n" + " -D | --density <512|1|2|4|8|16> set chip density (512 in KByte, others in MByte)\n" + " -C | --chip <0|1|2> select spi chip on which to operate\n" + " can only be used once per run:\n" + " 0 - both chips, 1 - first chip, 2 - second chip\n" " -e | --em100 set SPI frequency to 20MHz and disable\n" " Dual Output Fast Read Support\n" " -l | --lock Lock firmware descriptor and ME region\n" @@ -1090,9 +1148,10 @@ int main(int argc, char *argv[]) int opt, option_index = 0; int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0; int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0; - int mode_layout = 0, mode_newlayout = 0; + int mode_layout = 0, mode_newlayout = 0, mode_density = 0; char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL; int region_type = -1, inputfreq = 0; + unsigned int new_density = 0; enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ; static struct option long_options[] = { @@ -1102,6 +1161,8 @@ int main(int argc, char *argv[]) {"inject", 1, NULL, 'i'}, {"newlayout", 1, NULL, 'n'}, {"spifreq", 1, NULL, 's'}, + {"density", 1, NULL, 'D'}, + {"chip", 1, NULL, 'C'}, {"em100", 0, NULL, 'e'}, {"lock", 0, NULL, 'l'}, {"unlock", 0, NULL, 'u'}, @@ -1110,7 +1171,7 @@ int main(int argc, char *argv[]) {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "df:xi:n:s:eluvh?", + while ((opt = getopt_long(argc, argv, "df:D:C:xi:n:s:eluvh?", long_options, &option_index)) != EOF) { switch (opt) { case 'd': @@ -1169,6 +1230,51 @@ int main(int argc, char *argv[]) exit(EXIT_FAILURE); } break; + case 'D': + mode_density = 1; + new_density = strtoul(optarg, NULL, 0); + switch (new_density) { + case 512: + new_density = COMPONENT_DENSITY_512KB; + break; + case 1: + new_density = COMPONENT_DENSITY_1MB; + break; + case 2: + new_density = COMPONENT_DENSITY_2MB; + break; + case 4: + new_density = COMPONENT_DENSITY_4MB; + break; + case 8: + new_density = COMPONENT_DENSITY_8MB; + break; + case 16: + new_density = COMPONENT_DENSITY_16MB; + break; + case 32: + new_density = COMPONENT_DENSITY_32MB; + break; + case 64: + new_density = COMPONENT_DENSITY_64MB; + break; + case 0: + new_density = COMPONENT_DENSITY_UNUSED; + break; + default: + printf("error: Unknown density\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; + case 'C': + selected_chip = strtol(optarg, NULL, 0); + if (selected_chip > 2) { + fprintf(stderr, "error: Invalid chip selection\n"); + print_usage(argv[0]); + exit(EXIT_FAILURE); + } + break; case 's': // Parse the requested SPI frequency inputfreq = strtol(optarg, NULL, 0); @@ -1239,7 +1345,7 @@ int main(int argc, char *argv[]) if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_newlayout + mode_spifreq + mode_em100 + mode_locked + - mode_unlocked) == 0) { + mode_unlocked + mode_density) == 0) { fprintf(stderr, "You need to specify a mode.\n\n"); print_usage(argv[0]); exit(EXIT_FAILURE); @@ -1300,6 +1406,9 @@ int main(int argc, char *argv[]) if (mode_spifreq) set_spi_frequency(filename, image, size, spifreq); + if (mode_density) + set_chipdensity(filename, image, size, new_density); + if (mode_em100) set_em100_mode(filename, image, size);

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Patch set updated for coreboot: nb/amd/mct_ddr3: Consolidate duplicated code
by Timothy Pearson 11 Mar '16

11 Mar '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13994 -gerrit commit 07ad9e9d90aebe348acc54ebb575f1e71d055c17 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Mar 8 18:25:15 2016 -0600 nb/amd/mct_ddr3: Consolidate duplicated code read_dqs_read_data_timing_registers() and read_read_dqs_timing_control_registers() served essentially the same function but had slightly different semantics, causing confusion and needlessly complex Family15h code. Consolidate both into read_dqs_read_data_timing_registers() and adjust surrounding code to match new semantics. Change-Id: I3be808db5d15ceec4c36d17582756b01425df09a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 97 ++++-------------------- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 100 ++++++++++++++++++------- 2 files changed, 87 insertions(+), 110 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index fc08154..182fab0 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -17,8 +17,11 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); +static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); + +static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, + uint8_t dct, uint8_t dimm, uint32_t index_reg); static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -383,76 +386,6 @@ static void write_dqs_write_data_timing_registers(uint16_t* delay, uint32_t dev, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x3 | (dimm << 8), dword); } -static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0x3e; - else - mask = 0x3f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - delay[3] = (dword >> 24) & mask; - delay[2] = (dword >> 16) & mask; - delay[1] = (dword >> 8) & mask; - delay[0] = dword & mask; - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - delay[7] = (dword >> 24) & mask; - delay[6] = (dword >> 16) & mask; - delay[5] = (dword >> 8) & mask; - delay[4] = dword & mask; - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - delay[8] = dword & mask; -} - -static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) -{ - uint32_t dword; - uint32_t mask; - - if (is_fam15h()) - mask = 0x3e; - else - mask = 0x3f; - - /* Lanes 0 - 3 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[3] & mask) << 24; - dword |= (delay[2] & mask) << 16; - dword |= (delay[1] & mask) << 8; - dword |= delay[0] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); - - /* Lanes 4 - 7 */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); - dword &= ~(mask << 24); - dword &= ~(mask << 16); - dword &= ~(mask << 8); - dword &= ~mask; - dword |= (delay[7] & mask) << 24; - dword |= (delay[6] & mask) << 16; - dword |= (delay[5] & mask) << 8; - dword |= delay[4] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); - - /* Lane 8 (ECC) */ - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); - dword &= ~mask; - dword |= delay[8] & mask; - Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); -} - /* DQS Position Training * Algorithm detailed in the Fam10h BKDG Rev. 3.62 section 2.8.9.9.3 */ @@ -982,7 +915,7 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, continue; read_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - read_read_dqs_timing_control_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); + read_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); for (lane = 0; lane < MAX_BYTE_LANES; lane++) if ((current_phy_phase_delay[lane] + current_read_dqs_delay[lane]) > max_delay) max_delay = (current_phy_phase_delay[lane] + current_read_dqs_delay[lane]); @@ -1409,10 +1342,10 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.4 (2 C) * For each Read DQS Delay value from 0 to 1 UI */ - for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x40; current_read_dqs_delay[lane] += 2) { + for (current_read_dqs_delay[lane] = 0; current_read_dqs_delay[lane] < 0x20; current_read_dqs_delay[lane]++) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 161 current_read_dqs_delay[lane] ", current_read_dqs_delay[lane], 6); - if ((current_read_dqs_delay[lane] >> 1) >= (32 - 16)) { + if (current_read_dqs_delay[lane] >= (32 - 16)) { check_antiphase = 1; } else { check_antiphase = 0; @@ -1433,7 +1366,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x264); if ((dword & 0x1ffffff) != 0) { print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 162 early abort: F2x264 ", dword, 6); - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ continue; } } @@ -1444,16 +1377,16 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, dword = Get_NB32_DCT(dev, dct, 0x268) & 0x3ffff; print_debug_dqs("\t\t\t\t\tTrainDQSRdWrPos: 163 read results: F2x268 ", dword, 6); if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 0; /* Fail */ else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][(current_read_dqs_delay[lane] >> 1) + 16] = 1; /* Pass */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][current_read_dqs_delay[lane] + 16] = 1; /* Pass */ if (check_antiphase == 1) { /* Check antiphase results */ dword = Get_NB32_DCT(dev, dct, 0x26c) & 0x3ffff; if (dword & (0x3 << (lane * 2))) - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - (current_read_dqs_delay[lane] >> 1))] = 0; /* Fail */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 0; /* Fail */ else - dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - (current_read_dqs_delay[lane] >> 1))] = 1; /* Pass */ + dqs_results_array[Receiver & 0x1][lane - lane_start][current_write_data_delay[lane] - initial_write_dqs_delay[lane]][16 - (32 - current_read_dqs_delay[lane])] = 1; /* Pass */ } } } @@ -1511,8 +1444,8 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay)); /* Program the Read DQS Timing Control register with the center of the passing window */ - current_read_dqs_delay[lane] = region_center << 1; - passing_read_dqs_delay_found = 1; + current_read_dqs_delay[lane] = region_center; + passing_dqs_delay_found[lane] = 1; /* Commit the current Read DQS Timing Control settings to the hardware registers */ write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index f0e670b..da71816 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -475,40 +475,84 @@ static void write_dram_phase_recovery_control_registers(uint16_t* current_total_ } } -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) { - uint8_t lane; + uint8_t shift; uint32_t dword; + uint32_t mask; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { - uint32_t rdt_reg; + if (is_fam15h()) { + mask = 0x3e; + shift = 1; + } + else { + mask = 0x3f; + shift = 0; + } - /* Calculate DRAM Read DQS Timing register location */ - if ((lane == 0) || (lane == 1) || (lane == 2) || (lane == 3)) - rdt_reg = 0x5; - if ((lane == 4) || (lane == 5) || (lane == 6) || (lane == 7)) - rdt_reg = 0x6; - if (lane == 8) - rdt_reg = 0x7; - rdt_reg |= (dimm << 8); + /* Lanes 0 - 3 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); + delay[3] = ((dword >> 24) & mask) >> shift; + delay[2] = ((dword >> 16) & mask) >> shift; + delay[1] = ((dword >> 8) & mask) >> shift; + delay[0] = (dword & mask) >> shift; + + /* Lanes 4 - 7 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); + delay[7] = ((dword >> 24) & mask) >> shift; + delay[6] = ((dword >> 16) & mask) >> shift; + delay[5] = ((dword >> 8) & mask) >> shift; + delay[4] = (dword & mask) >> shift; + + /* Lane 8 (ECC) */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); + delay[8] = (dword & mask) >> shift; +} - dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, rdt_reg); - if ((lane == 7) || (lane == 3)) { - current_total_delay[lane] = (dword >> 24) & 0x3f; - } - if ((lane == 6) || (lane == 2)) { - current_total_delay[lane] = (dword >> 16) & 0x3f; - } - if ((lane == 5) || (lane == 1)) { - current_total_delay[lane] = (dword >> 8) & 0x3f; - } - if ((lane == 8) || (lane == 4) || (lane == 0)) { - current_total_delay[lane] = dword & 0x3f; - } +static void write_dqs_read_data_timing_registers(uint16_t* delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +{ + uint8_t shift; + uint32_t dword; + uint32_t mask; - if (is_fam15h()) - current_total_delay[lane] >>= 1; + if (is_fam15h()) { + mask = 0x3e; + shift = 1; + } + else { + mask = 0x3f; + shift = 0; } + + /* Lanes 0 - 3 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8)); + dword &= ~(mask << 24); + dword &= ~(mask << 16); + dword &= ~(mask << 8); + dword &= ~mask; + dword |= ((delay[3] << shift) & mask) << 24; + dword |= ((delay[2] << shift) & mask) << 16; + dword |= ((delay[1] << shift) & mask) << 8; + dword |= (delay[0] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x5 | (dimm << 8), dword); + + /* Lanes 4 - 7 */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8)); + dword &= ~(mask << 24); + dword &= ~(mask << 16); + dword &= ~(mask << 8); + dword &= ~mask; + dword |= ((delay[7] << shift) & mask) << 24; + dword |= ((delay[6] << shift) & mask) << 16; + dword |= ((delay[5] << shift) & mask) << 8; + dword |= (delay[4] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x6 | (dimm << 8), dword); + + /* Lane 8 (ECC) */ + dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8)); + dword &= ~mask; + dword |= (delay[8] << shift) & mask; + Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x7 | (dimm << 8), dword); } static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDCTstat, uint32_t testaddr, uint8_t channel) @@ -1596,7 +1640,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - read_read_dqs_timing_control_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); + read_dqs_read_data_timing_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); for (lane = 0; lane < 8; lane++) { current_total_delay[lane] += current_rdqs_total_delay[lane];

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coreboot-gerrit March 2016