coreboot-gerrit October 2016

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Patch set updated for coreboot: riscv: Add a bandaid for the new toolchain
by Ronald G. Minnich 31 Oct '16

31 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17183 -gerrit commit 7296dc65ea0e2dbc2ce53d7f5b6061940559c8b3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Oct 28 15:08:59 2016 -0700 riscv: Add a bandaid for the new toolchain After I did a new toolchain build, I found the the mhartid register value is wrong for Spike. The docs seem to agree with Spike, not the code the toolchain produces? Until such time as the bitstreams and toolchain can find a way to agree, just hardcode it. We've been playing this game for two years now so this is hardly a new approach. This is intentionally ugly because we really need the toolchains and emulators and bitstreams to sync up, and that's not happening yet. Lowrisc allegedly implements the v1.9 spec but it's PTEs are clearly 1.7. Once it all settles down we can just use constants supplied by the toolchain. I hope the syncup will have happened by the workshop in November. This gets spike running again. Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/bootblock.S | 6 +++++- src/arch/riscv/trap_handler.c | 2 +- src/arch/riscv/trap_util.S | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 63df92b..c54c0e2 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -32,7 +32,11 @@ _start: # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - csrr a0, mhartid + // Once again, the docs and toolchain disagree. + // Rather than get fancy I'll just lock this down + // until it all stabilizes. + //csrr a0, mhartid + csrr a0, 0xf14 call hls_init # poison the stack diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..8c69366 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -29,7 +29,7 @@ void handle_supervisor_call(trapframe *tf) { switch(call) { case SBI_ECALL_HART_ID: printk(BIOS_DEBUG, "Getting hart id...\n"); - returnValue = read_csr(mhartid); + returnValue = read_csr(0xf14);//mhartid); break; case SBI_ECALL_NUM_HARTS: /* TODO: parse the hardware-supplied config string and diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 5ee0fdd..3357959 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -119,7 +119,9 @@ trap_entry: # SMP isn't supported yet, to avoid overwriting the same stack with different # harts that handle traps at the same time. - csrr sp, mhartid + # someday this gets fixed. + //csrr sp, mhartid + csrr sp, 0xf14 .Lsmp_hang: bnez sp, .Lsmp_hang

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Patch merged into coreboot/master: superiotool: Add undocumented registers of ITE IT8783E/F
by gerrit＠coreboot.org 31 Oct '16

31 Oct '16

the following patch was just integrated into master: commit 25445dca1700bea7c83e6d12c7936253ef9af8ca Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Sep 29 12:22:30 2016 +0200 superiotool: Add undocumented registers of ITE IT8783E/F Dumping and behavioral analysis have shown that there are more registers in the environment control of the IT8783E/F than documented in my data- sheet. This adds every register that wasn't 0x00/0xff by default. The default values are guesswork: those that looked like sensor readings became NANA, others are taken from dumps. Change-Id: I7e39700c9b98ed5be9f085bc8ffd848006310254 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17005 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17005 for details. -gerrit

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Patch merged into coreboot/master: superiotool: Add register definitions for ITE IT8783E/F
by gerrit＠coreboot.org 31 Oct '16

31 Oct '16

the following patch was just integrated into master: commit e35a3741790dc0bc40b26996033d00786f8e11d6 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Sep 29 12:22:30 2016 +0200 superiotool: Add register definitions for ITE IT8783E/F Values are taken from an unpublished datasheet. With the exception of the default value for register 0x55 in the environment controller space: Looks like this was just documented wrong. The dumped value of 0x50 also makes more sense. Change-Id: I2bd23d30b7158b2e05fcee7c6280df82570d1401 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17004 for details. -gerrit

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Patch merged into coreboot/master: superiotool: Add an alternative dump format
by gerrit＠coreboot.org 31 Oct '16

31 Oct '16

the following patch was just integrated into master: commit 3812a72907172f9e43b4f791f87cbd4e1a8c2f44 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Oct 12 12:12:51 2016 +0200 superiotool: Add an alternative dump format Add new dump format to superiotool that prints each register on a separate line. This should be more suitable for diff'ing dumps of multiple superiotool runs. Change-Id: I226ee82b903bf77e760d3396d02fa50688adb9f2 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17003 for details. -gerrit

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Patch merged into coreboot/master: ec/acpi: Add missing include
by gerrit＠coreboot.org 31 Oct '16

31 Oct '16

the following patch was just integrated into master: commit 8a9b7b59e3ddae3991530d50374b0fc0dd1d896a Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Oct 25 16:03:22 2016 +0200 ec/acpi: Add missing include Change-Id: I61c2191f28b6c2c9a6bc587dc3b6c2ae28205192 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/17124 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17124 for details. -gerrit

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Patch set updated for coreboot: mainboard/google/reef: update DMIC related pins configuration
by Sathyanarayana Nujella 31 Oct '16

31 Oct '16

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17199 -gerrit commit bab4bb28d52eaf2b6772a715d304d90daf6c7ccf Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Mon Oct 31 10:48:43 2016 -0700 mainboard/google/reef: update DMIC related pins configuration CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record on other potential DMIC's. DMIC blobs configure the clocks. For stereo & quad channel record, both CLK_A1 and CLK_B1 are enabled. For mono channel record, only CLK_A1 is enabled. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index c9fa3d3..ae84e9c 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -219,10 +219,10 @@ static const struct pad_config gpio_table[] = { /* DMIC or I2S4 */ PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ - PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */ PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ - PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */ /* I2S2 -- Headset amp */ PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */

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Patch merged into coreboot/master: lib/prog_loaders: use common ramstage_cache_invalid()
by gerrit＠coreboot.org 31 Oct '16

31 Oct '16

the following patch was just integrated into master: commit 8cd723bc0cb64f28b1009fd2fa55f6680a402b61 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 17:32:24 2016 -0500 lib/prog_loaders: use common ramstage_cache_invalid() All current implementations of ramstage_cache_invalid() were just resetting the system based on the RESET_ON_INVALID_RAMSTAGE_CACHE Kconfig option. Move that behavior to a single implementation within prog_loaders.c which removes duplication. Change-Id: I67aae73f9e1305732f90d947fe57c5aaf66ada9e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17184 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17184 for details. -gerrit

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Patch merged into coreboot/master: lib/program.ld: add .sdata sections
by gerrit＠coreboot.org 31 Oct '16

31 Oct '16

the following patch was just integrated into master: commit 9a2790e328c4cabefa201995aa4812be414d93c3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Oct 28 12:24:48 2016 -0500 lib/program.ld: add .sdata sections Ron reported some toolchain emitting .sdata sections. Let's ensure we catch objects in those sections instead of getting dropped on the floor for architectures which emit those sections. Change-Id: I0680228f8424f99611914ef5fc31adf5d3891eee Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17180 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17180 for details. -gerrit

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Patch set updated for coreboot: mainboard/google/reef: update DMIC related pins configuration
by Sathyanarayana Nujella 31 Oct '16

31 Oct '16

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17199 -gerrit commit 470ee10cc6caeecd4dc801e8728dcea00f18eecd Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Mon Oct 31 10:48:43 2016 -0700 mainboard/google/reef: update DMIC related pins configuration CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record on other potential DMIC's. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index c9fa3d3..ae84e9c 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -219,10 +219,10 @@ static const struct pad_config gpio_table[] = { /* DMIC or I2S4 */ PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ - PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */ PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ - PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */ /* I2S2 -- Headset amp */ PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */

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New patch to review for coreboot: mainboard/google/reef: update DMIC related pins configuration
by Sathyanarayana Nujella 31 Oct '16

31 Oct '16

Sathyanarayana Nujella (sathyanarayana.nujella(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17199 -gerrit commit c8ebd2ce59705d61ca8719fcde4cd49e9245609f Author: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Date: Mon Oct 31 10:48:43 2016 -0700 mainboard/google/reef: update DMIC related pins configuration CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> --- src/mainboard/google/reef/variants/baseboard/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index c9fa3d3..ae84e9c 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -219,10 +219,10 @@ static const struct pad_config gpio_table[] = { /* DMIC or I2S4 */ PAD_CFG_NF(GPIO_79, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_A1 */ - PAD_CFG_GPI(GPIO_80, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */ PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ - PAD_CFG_GPI(GPIO_83, UP_20K, DEEP), /* unused */ + PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */ /* I2S2 -- Headset amp */ PAD_CFG_NF(GPIO_84, NATIVE, DEEP, NF1), /* AVS_I2S2_MCLK */

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coreboot-gerrit October 2016