Patch set updated for coreboot: riscv: Add a bandaid for the new toolchain

[Ronald G. Minnich]

Ronald G. Minnich ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17183

-gerrit

commit 7296dc65ea0e2dbc2ce53d7f5b6061940559c8b3
Author: Ronald G. Minnich <[e-mail]>
Date:   Fri Oct 28 15:08:59 2016 -0700

    riscv: Add a bandaid for the new toolchain
    
    After I did a new toolchain build, I found the
    the mhartid register value is wrong for Spike.
    The docs seem to agree with Spike, not the
    code the toolchain produces?
    
    Until such time as the bitstreams and toolchain can find
    a way to agree, just hardcode it. We've been playing this game
    for two years now so this is hardly a new approach.
    
    This is intentionally ugly because we really need the
    toolchains and emulators and bitstreams to sync up,
    and that's not happening yet. Lowrisc
    allegedly implements the v1.9 spec but it's PTEs are clearly
    1.7. Once it all settles down we can just use constants
    supplied by the toolchain.
    
    I hope the syncup will have happened by the workshop in November.
    
    This gets spike running again.
    
    Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326
    Signed-off-by: Ronald G. Minnich <[e-mail]>
---
 src/arch/riscv/bootblock.S    | 6 +++++-
 src/arch/riscv/trap_handler.c | 2 +-
 src/arch/riscv/trap_util.S    | 4 +++-
 3 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 63df92b..c54c0e2 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -32,7 +32,11 @@ _start:
 
 	# make room for HLS and initialize it
 	addi sp, sp, -64 // MENTRY_FRAME_SIZE
-	csrr a0, mhartid
+	// Once again, the docs and toolchain disagree.
+	// Rather than get fancy I'll just lock this down
+	// until it all stabilizes.
+	//csrr a0, mhartid
+	csrr a0, 0xf14
 	call hls_init
 
 	# poison the stack
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ad49928..8c69366 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -29,7 +29,7 @@ void handle_supervisor_call(trapframe *tf) {
 	switch(call) {
 		case SBI_ECALL_HART_ID:
 			printk(BIOS_DEBUG, "Getting hart id...\n");
-			returnValue = read_csr(mhartid);
+			returnValue = read_csr(0xf14);//mhartid);
 			break;
 		case SBI_ECALL_NUM_HARTS:
 			/* TODO: parse the hardware-supplied config string and
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 5ee0fdd..3357959 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -119,7 +119,9 @@ trap_entry:
 
   # SMP isn't supported yet, to avoid overwriting the same stack with different
   # harts that handle traps at the same time.
-  csrr sp, mhartid
+  # someday this gets fixed.
+  //csrr sp, mhartid
+  csrr sp, 0xf14
 .Lsmp_hang:
   bnez sp, .Lsmp_hang