coreboot-gerrit January 2016

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Patch set updated for coreboot: util/crossgcc: Add ppc64el support
by Timothy Pearson 03 Jan '16

03 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12818 -gerrit commit f6e973c3139f63987ad5754c9caea2c3e2599dce Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Dec 30 18:59:00 2015 -0600 util/crossgcc: Add ppc64el support Change-Id: I619f7c3cef7f0aaa6fccb3d52f2ac1f6ace6d0d6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- Makefile.inc | 14 ++++++++++---- util/crossgcc/Makefile | 5 ++++- util/crossgcc/buildgcc | 21 +++++++++++---------- 3 files changed, 25 insertions(+), 15 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 06dea87..000ad63 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -488,7 +488,7 @@ help_toolchain help:: @echo ' clang - Build coreboot clang compiler' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' - @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", or "riscv"' + @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' @echo @@ -499,9 +499,9 @@ crossgcc: clean-for-update $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ - crossgcc-mips crossgcc-riscv crossgcc-clean iasl clang tools \ - crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 \ - crosstools-mips crosstools-riscv + crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ + clang tools crosstools-i386 crosstools-x64 crosstools-arm \ + crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 crossgcc-i386: clean-for-update $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 @@ -521,6 +521,9 @@ crossgcc-mips: clean-for-update crossgcc-riscv: clean-for-update $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 +crossgcc-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 + crosstools: clean-for-update $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 @@ -548,6 +551,9 @@ crosstools-mips: clean-for-update crosstools-riscv: clean-for-update $(MAKE) -C util/crossgcc build-riscv +crosstools-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 + crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 152115c..79e0c3c 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -61,6 +61,9 @@ build-mips: build-riscv: @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf +build-power8: + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -77,5 +80,5 @@ distclean: clean .PHONY: build_gcc build_iasl build_gdb build_clang \ all all_with_gdb all_without_gdb build_tools \ - build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv \ + build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-power8 \ clean distclean clean_tempfiles diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fad40bf..31db9cb 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -587,16 +587,17 @@ fi printversion case "$TARGETARCH" in - x86_64-elf) ;; - x86_64*) TARGETARCH=x86_64-elf;; - i386-elf) ;; - i386-mingw32) ;; - mipsel-elf) ;; - riscv-elf) ;; - i386*) TARGETARCH=i386-elf;; - arm*) TARGETARCH=armv7-a-eabi;; - aarch64*) TARGETARCH=aarch64-elf;; - *) printf "${red}WARNING: Unsupported architecture $TARGETARCH.${NC}\n\n"; ;; + x86_64-elf) ;; + x86_64*) TARGETARCH=x86_64-elf;; + i386-elf) ;; + i386-mingw32) ;; + mipsel-elf) ;; + riscv-elf) ;; + powerpc64le-linux-gnu) ;; + i386*) TARGETARCH=i386-elf;; + arm*) TARGETARCH=armv7-a-eabi;; + aarch64*) TARGETARCH=aarch64-elf;; + *) printf "${red}WARNING: Unsupported architecture $TARGETARCH.${NC}\n\n"; ;; esac # Figure out which packages to build

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Patch merged into coreboot/master: sb/intel/bd82x6x: Add missing PCIIDs for variants .
by gerrit＠coreboot.org 03 Jan '16

03 Jan '16

the following patch was just integrated into master: commit 42d55e0caf9999be461ef5c5029d11fb8f4c5593 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 2 01:47:26 2016 +0100 sb/intel/bd82x6x: Add missing PCIIDs for variants . Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: https://review.coreboot.org/12820 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/12820 for details. -gerrit

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Patch set updated for coreboot: sb/intel/bd82x6x: Add missing PCIIDs for variants .
by Vladimir Serbinenko 03 Jan '16

03 Jan '16

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12820 -gerrit commit 5b31d4ca1cf4bbde9477f0628beca3c6107109c0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 2 01:47:26 2016 +0100 sb/intel/bd82x6x: Add missing PCIIDs for variants . Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/lpc.c | 18 ++++++++++++------ util/autoport/bd82x6x.go | 11 ++--------- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 17f824c..1106912 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -859,12 +859,18 @@ static struct device_operations device_ops = { * Intel C200 Series Chipset */ -static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a, - 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, - 0x1c4f, 0x1c50, 0x1c52, 0x1c54, - 0x1e55, 0x1c56, 0x1e57, 0x1c5c, - 0x1e5d, 0x1e5e, 0x1e5f, 0x1e49, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c40, 0x1c41, 0x1c42, 0x1c43, 0x1c44, 0x1c45, 0x1c46, 0x1c47, 0x1c48, + 0x1c49, 0x1c4a, 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, 0x1c4f, 0x1c50, 0x1c51, + 0x1c52, 0x1c53, 0x1c54, 0x1c55, 0x1c56, 0x1c57, 0x1c58, 0x1c59, 0x1c5a, + 0x1c5b, 0x1c5c, 0x1c5d, 0x1c5e, 0x1c5f, + + 0x1e41, 0x1e42, 0x1e43, 0x1e44, 0x1e45, 0x1e46, 0x1e47, 0x1e48, 0x1e49, + 0x1e4a, 0x1e4b, 0x1e4c, 0x1e4d, 0x1e4e, 0x1e4f, 0x1e50, 0x1e51, 0x1e52, + 0x1e53, 0x1e54, 0x1e55, 0x1e56, 0x1e57, 0x1e58, 0x1e59, 0x1e5a, 0x1e5b, + 0x1e5c, 0x1e5d, 0x1e5e, 0x1e5f, + + 0 }; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 8756d07..a1513e8 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -396,19 +396,12 @@ void acpi_create_gnvs(global_nvs_t *gnvs) func init() { /* BD82X6X LPC */ - for _, id := range []uint16{ - 0x1c46, 0x1c47, 0x1c49, 0x1c4a, - 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e, - 0x1c4f, 0x1c50, 0x1c52, 0x1c54, - 0x1c56, 0x1c5c, - } { + for id := 0x1c40; id <= 0x1c5f; id++ { RegisterPCI(0x8086, id, bd82x6x{variant: "BD82X6X"}) } /* C216 LPC */ - for _, id := range []uint16{ - 0x1e55, 0x1e57, 0x1e5d, 0x1e5e, 0x1e5f, 0x1e49, - } { + for id := 0x1e41; id <= 0x1e5f; id++ { RegisterPCI(0x8086, id, bd82x6x{variant: "C216"}) }

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Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMCONFIG resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit 81433cab0478963f355dbf6e9b6b108c7388d6be Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMCONFIG resource The code committed in GIT hash * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support did not correctly locate the CPU MMCONFIG resource, leading to failures with operating systems and firmware (e.g. SeaBIOS) when the PCI extended configuration space option was activated. Due to the southbridge routing not being set up, MMCONFIG accesses were targetting DRAM and therefore the PCI devices were not being configured. The failure normally manifests as a system hang immediately after PCI configuration starts. Search for the CPU MMCONFIG resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..818b0e6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,13 +35,13 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) + for (domain = all_devices; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, 0xc0010058); if (res) return res; }

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Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMCONFIG resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit 19f97ae44a002b19a9fceab1159f4b8e7cad0bef Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMCONFIG resource The code committed in GIT hash * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support did not correctly locate the CPU MMIO resource, leading to failures with operating systems and firmware (e.g. SeaBIOS) when the PCI extended configuration space option was activated. Due to the southbridge routing not being set up, MMCONFIG accesses were targetting DRAM and therefore the PCI devices were not being configured. The failure normally manifests as a system hang immediately after PCI configuration starts. Search for the CPU MMCONFIG resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..818b0e6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,13 +35,13 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) + for (domain = all_devices; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, 0xc0010058); if (res) return res; }

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Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMIO resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit c372c765ea2452fa5993efd453978a5a573393c8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMIO resource The code committed in GIT hash 1eaaa0 [southbridge/amd/sr5650: Add MCFG ACPI table support] did not correctly locate the CPU MMIO resource, leading to failures with operating systems and firmware when the PCI extended configuration space option was activated. Search for the CPU MMIO resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..818b0e6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,13 +35,13 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) + for (domain = all_devices; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, 0xc0010058); if (res) return res; }

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Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMIO resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit 32684e32f8f61cd06d3a51a56ef076fe5ba9d7ae Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMIO resource The code committed in GIT hash 1eaaa0 [southbridge/amd/sr5650: Add MCFG ACPI table support] did not correctly locate the CPU MMIO resource, leading to failures with operating systems and firmware when the PCI extended configuration space option was activated. Search for the CPU MMIO resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..5fd5e2f 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,13 +35,15 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; + struct device *sibling; + struct bus *link; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) + for (domain = all_devices; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); + res = probe_resource(domain->bus->dev, 0xc0010058); if (res) return res; }

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Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMIO resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit d4d107dacbe50e1c97f1ee614837a3b9875c0747 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMIO resource The code committed in GIT hash 1eaaa0 did not correctly locate the CPU MMIO resource, leading to failures with operating systems and firmware when the PCI extended configuration space option was activated. Search for the CPU MMIO resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..c4336a6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,15 +35,21 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; + struct device *sibling; + struct bus *link; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) - continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); - if (res) - return res; + for (link = all_devices->link_list; link; link = link->next) { + for (sibling = link->children; sibling; sibling = sibling->sibling) { + for (domain = sibling; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) + continue; + res = probe_resource(domain->bus->dev, 0xc0010058); + if (res) + return res; + } + } } return NULL;

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Patch set updated for coreboot: sb/amd/sr5650: Correctly locate CPU MMIO resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit 2806b466c2f83f0d38482be9e71751b4b01e04f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMIO resource The code committed in GIT hash 1eaaa0 did not correctly locate the CPU MMIO resource, leading to failures with operating systems and firmware when the PCI extended configuration space option was activated. Search for the CPU MMIO resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..c4336a6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,15 +35,21 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; + struct device *sibling; + struct bus *link; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) - continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); - if (res) - return res; + for (link = all_devices->link_list; link; link = link->next) { + for (sibling = link->children; sibling; sibling = sibling->sibling) { + for (domain = sibling; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) + continue; + res = probe_resource(domain->bus->dev, 0xc0010058); + if (res) + return res; + } + } } return NULL;

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New patch to review for coreboot: sb/amd/sr5650: Correctly locate CPU MMIO resource
by Timothy Pearson 02 Jan '16

02 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12821 -gerrit commit 24ebeac5f5ffd4b3d292690243511b0886b1c903 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 1 23:30:42 2016 -0600 sb/amd/sr5650: Correctly locate CPU MMIO resource The code committed in GIT hash 1eaaa0 did not correctly locate the CPU MMIO resource, leading to failures with operating systems and firmware when the PCI extended configuration space option was activated. Search for the CPU MMIO resource on all domains below the root device. Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/sr5650.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index d4355d6..c4336a6 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -35,15 +35,21 @@ extern void set_pcie_dereset(void); extern void set_pcie_reset(void); struct resource * sr5650_retrieve_cpu_mmio_resource() { - device_t cpu; + device_t domain; + struct device *sibling; + struct bus *link; struct resource *res; - for (cpu = all_devices; cpu; cpu = cpu->next) { - if (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER) - continue; - res = probe_resource(cpu->bus->dev, 0xc0010058); - if (res) - return res; + for (link = all_devices->link_list; link; link = link->next) { + for (sibling = link->children; sibling; sibling = sibling->sibling) { + for (domain = sibling; domain; domain = domain->next) { + if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN) + continue; + res = probe_resource(domain->bus->dev, 0xc0010058); + if (res) + return res; + } + } } return NULL;

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coreboot-gerrit January 2016