Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12463
-gerrit
commit da39eb8ff24225aaf155c7d4320925f2cf5bd7fc
Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Date: Wed Nov 18 15:21:34 2015 -0800
Drop abuild.disabled files for Braswell / Skylake boards
Make sure the latest & greatest Intel targets actually
build in our build system.
Change-Id: I479ad473c260fc914d224cb58f4be1837aff2502
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/mainboard/google/chell/abuild.disabled | 2 --
src/mainboard/google/cyan/abuild.disabled | 2 --
src/mainboard/google/glados/abuild.disabled | 2 --
src/mainboard/google/lars/abuild.disabled | 2 --
src/mainboard/intel/kunimitsu/abuild.disabled | 2 --
src/mainboard/intel/sklrvp/abuild.disabled | 2 --
src/mainboard/intel/strago/abuild.disabled | 2 --
7 files changed, 14 deletions(-)
diff --git a/src/mainboard/google/chell/abuild.disabled b/src/mainboard/google/chell/abuild.disabled
deleted file mode 100644
index 7d1725a..0000000
--- a/src/mainboard/google/chell/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Skylake FSP binary and header files
-along with the Skylake microcode files from Intel.
diff --git a/src/mainboard/google/cyan/abuild.disabled b/src/mainboard/google/cyan/abuild.disabled
deleted file mode 100644
index 025ebea..0000000
--- a/src/mainboard/google/cyan/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Braswell FSP binary and header
-files along with the Braswell microcode files from Intel.
diff --git a/src/mainboard/google/glados/abuild.disabled b/src/mainboard/google/glados/abuild.disabled
deleted file mode 100644
index 7d1725a..0000000
--- a/src/mainboard/google/glados/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Skylake FSP binary and header files
-along with the Skylake microcode files from Intel.
diff --git a/src/mainboard/google/lars/abuild.disabled b/src/mainboard/google/lars/abuild.disabled
deleted file mode 100644
index 7d1725a..0000000
--- a/src/mainboard/google/lars/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Skylake FSP binary and header files
-along with the Skylake microcode files from Intel.
diff --git a/src/mainboard/intel/kunimitsu/abuild.disabled b/src/mainboard/intel/kunimitsu/abuild.disabled
deleted file mode 100644
index 7d1725a..0000000
--- a/src/mainboard/intel/kunimitsu/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Skylake FSP binary and header files
-along with the Skylake microcode files from Intel.
diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled
deleted file mode 100644
index 7d1725a..0000000
--- a/src/mainboard/intel/sklrvp/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Skylake FSP binary and header files
-along with the Skylake microcode files from Intel.
diff --git a/src/mainboard/intel/strago/abuild.disabled b/src/mainboard/intel/strago/abuild.disabled
deleted file mode 100644
index 025ebea..0000000
--- a/src/mainboard/intel/strago/abuild.disabled
+++ /dev/null
@@ -1,2 +0,0 @@
-Successful builds for this board require the Braswell FSP binary and header
-files along with the Braswell microcode files from Intel.
Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12834
-gerrit
commit 90b954b04092b4f0ffdc32b0def79df9fd428746
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Jan 5 11:00:49 2016 -0600
cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
The AMD Family 10h/15h processors use a TSC that increments at
the P0 core frequency. Allow coreboot to query the TSC frequency.
Change-Id: I73ead4fd4af18991452d59985b667a54689778cd
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
---
src/cpu/amd/family_10h-family_15h/Makefile.inc | 2 ++
src/cpu/amd/family_10h-family_15h/tsc_freq.c | 37 ++++++++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index 6cd2513..f10f732 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -3,6 +3,8 @@ ramstage-y += model_10xxx_init.c
ramstage-y += processor_name.c
romstage-y += update_microcode.c
+romstage-y += tsc_freq.c
+ramstage-y += tsc_freq.c
romstage-y += ram_calc.c
ramstage-y += ram_calc.c
ramstage-y += monotonic_timer.c
diff --git a/src/cpu/amd/family_10h-family_15h/tsc_freq.c b/src/cpu/amd/family_10h-family_15h/tsc_freq.c
new file mode 100644
index 0000000..afd7dab
--- /dev/null
+++ b/src/cpu/amd/family_10h-family_15h/tsc_freq.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Raptor Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+ msr_t msr;
+ uint8_t cpufid;
+ uint8_t cpudid;
+
+ /* On Family 10h/15h CPUs the TSC increments
+ * at the P0 clock rate. Read the P0 clock
+ * frequency from the P0 MSR and convert
+ * to MHz. See also the Family 15h BKDG
+ * Rev. 3.14 page 569.
+ */
+ msr = rdmsr(0xc0010064);
+ cpufid = (msr.lo & 0x3f);
+ cpudid = (msr.lo & 0x1c0) >> 6;
+
+ return (100 * (cpufid + 0x10)) / (0x01 << cpudid);
+}