coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

1 participants
859 discussions

Patch set updated for coreboot: linking: lay the groundwork for a unified linking approach
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507 -gerrit commit 1b3c261f4610fa2fac10c427566512af4ddd90d8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 22:49:36 2015 -0500 linking: lay the groundwork for a unified linking approach Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/memlayout.h | 25 +++++++ src/arch/x86/ramstage.ld | 2 +- src/include/memlayout.h | 126 ++++++++++++++++++++++++++++++++-- src/lib/Makefile.inc | 3 +- src/lib/program.ld | 67 ++++++++++++++++++ src/lib/ramstage.ld | 115 ------------------------------- 7 files changed, 218 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8311b11..23a24f2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-srcs += $(src)/arch/x86/ramstage.ld +ramstage-y += ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h new file mode 100644 index 0000000..54b8b4a --- /dev/null +++ b/src/arch/x86/include/arch/memlayout.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* Currently empty to satisfy common arch requirements. */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 5fcbbb6..c9b2f17 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -19,7 +19,7 @@ SECTIONS { . = CONFIG_RAMBASE; - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..3b3ff6d 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -22,10 +22,41 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H +#include <rules.h> #include <arch/memlayout.h> +/* Macros that the architecture can override. */ +#ifndef ARCH_POINTER_ALIGN_SIZE +#define ARCH_POINTER_ALIGN_SIZE 8 +#endif + +#ifndef ARCH_CACHELINE_ALIGN_SIZE +#define ARCH_CACHELINE_ALIGN_SIZE 64 +#endif + +#ifndef ARCH_FIRST_TEXT +#define ARCH_FIRST_TEXT +#endif + +/* Default to data as well as bss. */ +#ifndef ARCH_STAGE_HAS_DATA_SECTION +#define ARCH_STAGE_HAS_DATA_SECTION 1 +#endif + +#ifndef ARCH_STAGE_HAS_BSS_SECTION +#define ARCH_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Default is that currently ramstage and smm only has a heap. */ +#ifndef ARCH_STAGE_HAS_HEAP_SECTION +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#endif + #define STR(x) #x +#define ALIGN_COUNTER(align) \ + . = ALIGN(align); + #define SET_COUNTER(name, addr) \ _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ . = addr; @@ -34,6 +65,9 @@ SET_COUNTER(name, addr) \ _##name = .; +#define SYMBOL_CURRENT_LOC(name) \ + _##name = .; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ @@ -58,7 +92,7 @@ /* TODO: This only works if you never access CBFS in romstage before RAM is up! * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__) +#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) @@ -93,16 +127,100 @@ . += sz; #endif -#ifdef __RAMSTAGE__ +#if ENV_RAMSTAGE #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ - _ = ASSERT(_eramstage - _ramstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ . += sz; #endif +#if ENV_RAMSTAGE || ENV_ROMSTAGE +#define CBMEM_INIT_HOOKS \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ + KEEP(*(.rodata.cbmem_init_hooks)); \ + SYMBOL_CURRENT_LOC(ecbmem_init_hooks) +#else +#define CBMEM_INIT_HOOKS +#endif + +#if ENV_RAMSTAGE +#define DRIVERS_RODATA \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(pci_drivers) \ + KEEP(*(.rodata.pci_driver)); \ + SYMBOL_CURRENT_LOC(epci_drivers) \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cpu_drivers) \ + KEEP(*(.rodata.cpu_driver)); \ + SYMBOL_CURRENT_LOC(ecpu_drivers) +#else +#define DRIVERS_RODATA +#endif + +#define BEGIN_SECTION(name, align) \ + .##name : { \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(name) + +#define END_SECTION(name, align) \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(e##name) \ + } + +#if ARCH_STAGE_HAS_DATA_SECTION +#ifdef __PRE_RAM__ +/* Provide these symbols in PRE_RAM environments if not already provided. */ +#define DATA_EXTRA \ + PROVIDE(_preram_cbmem_console = .); \ + PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); +#elif ENV_RAMSTAGE +#define DATA_EXTRA \ + SYMBOL_CURRENT_LOC(bs_init_begin) \ + KEEP(*(.bs_init)); \ + LONG(0); \ + LONG(0); \ + SYMBOL_CURRENT_LOC(ebs_init_begin) +#else +#define DATA_EXTRA +#endif + +#define DATA_SECTION \ + BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + *(.data); \ + *(.data.*); \ + DATA_EXTRA \ + END_SECTION(data, ARCH_POINTER_ALIGN_SIZE) +#else +#define DATA_SECTION +#endif + +#if ARCH_STAGE_HAS_BSS_SECTION +#define BSS_SECTION \ + BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \ + *(.bss) \ + *(.bss.*) \ + *(.sbss) \ + *(.sbss.*) \ + END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) +#else +#define BSS_SECTION +#endif + +#if ARCH_STAGE_HAS_HEAP_SECTION +#define HEAP_SECTION \ + BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ + . += CONFIG_HEAP_SIZE ; \ + END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) +#else +#define HEAP_SECTION +#endif + +#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + #endif /* __MEMLAYOUT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8597667..cd2b70a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += bootblock.ld romstage-y += romstage.ld endif -ramstage-y += ramstage.ld + +ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/lib/program.ld b/src/lib/program.ld new file mode 100644 index 0000000..4900d3e --- /dev/null +++ b/src/lib/program.ld @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +BEGIN_SECTION(text, 1) + SYMBOL_CURRENT_LOC(program) + ARCH_FIRST_TEXT + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + POINTER_ALIGN + CBMEM_INIT_HOOKS + DRIVERS_RODATA + *(.rodata); + *(.rodata.*); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(etext) +END_SECTION(text, 1) : to_load + +#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +BEGIN_SECTION(ctors, 0x100) + SYMBOL_CURRENT_LOC(__CTOR_LIST__) + KEEP(*(.ctors)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(__CTOR_END__) +END_SECTION(ctors, 1) +#endif + +/* Include data, bss, and heap in that order. Not defined for all stages. */ +DATA_SECTION +BSS_SECTION +HEAP_SECTION +SYMBOL_CURRENT_LOC(eprogram) + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.comment.*) + *(.note) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld deleted file mode 100644 index b224827..0000000 --- a/src/lib/ramstage.ld +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -/* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ -.text : { - _program = .; - _ramstage = .; - _text = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; -} : to_load - -#if IS_ENABLED(CONFIG_COVERAGE) -.ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; -} -#endif - -/* TODO: align data sections to cache lines? (is that really useful?) */ -.rodata : { - _rodata = .; - . = ALIGN(8); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(8); - - _erodata = .; -} - -.data : { - /* Move to different cache line to avoid false sharing with .rodata. */ - . = ALIGN(64); /* May not be actual line size, not that important. */ - _data = .; - *(.data) - *(.data.*) - _edata = .; -} - -.bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; -} - -.heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - _eramstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ - -/DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) -}

1 0

Patch set updated for coreboot: x86: link romstage like the other architectures
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510 -gerrit commit 8ec989dc6b9bfb4b4335865c98fe6195009f9359 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:06:05 2015 -0500 x86: link romstage like the other architectures All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 23a24f2..8868a3f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */ +#include <rules.h> + PHDRS { to_load PT_LOAD; } +#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..9c44b13 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif +romstage-y += program.ld ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y)

1 0

Patch set updated for coreboot: linking: move romstage and bootblock to use program.ld
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509 -gerrit commit 9cf9c327e633f29b8526d1c1b8b1dbef779ca6d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:09:49 2015 -0500 linking: move romstage and bootblock to use program.ld Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 12 +++++----- src/lib/Makefile.inc | 4 ++-- src/lib/bootblock.ld | 51 --------------------------------------- src/lib/romstage.ld | 64 ------------------------------------------------- 4 files changed, 8 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 3b3ff6d..1a38256 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -103,24 +103,24 @@ #endif /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */ -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ - _ = ASSERT(_ebootblock - _bootblock <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ - INCLUDE "lib/bootblock.bootblock.ld" + INCLUDE "lib/program.bootblock.ld" #else #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ . += sz; #endif -#ifdef __ROMSTAGE__ +#if ENV_ROMSTAGE #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ - _ = ASSERT(_eromstage - _romstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/romstage.romstage.ld" + INCLUDE "lib/program.romstage.ld" #else #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index cd2b70a..4aa6bf8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -194,8 +194,8 @@ secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock and romstage use custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well -bootblock-y += bootblock.ld -romstage-y += romstage.ld +bootblock-y += program.ld +romstage-y += program.ld endif ramstage-y += program.ld diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld deleted file mode 100644 index 42e6d64..0000000 --- a/src/lib/bootblock.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.bootblock . : { - _program = .; - _bootblock = .; - *(.text._start); - *(.text.stage_entry); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; - _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; - _ebootblock = .; - _eprogram = .; -} : to_load = 0xff - -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - *(.MIPS.*) -} diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld deleted file mode 100644 index ba154ef..0000000 --- a/src/lib/romstage.ld +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _romstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - . = ALIGN(8); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - PROVIDE(_preram_cbmem_console = .); - PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _eromstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

1 0

Patch set updated for coreboot: x86: link ramstage like the other architectures
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508 -gerrit commit 693dc60b11bb82a616ee2e8191716e40947001d3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 10:19:05 2015 -0500 x86: link ramstage like the other architectures All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 24 +++--------------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld new file mode 100644 index 0000000..dd6cb27 --- /dev/null +++ b/src/arch/x86/include/arch/header.ld @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(_start) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index c9b2f17..0d329db 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -1,25 +1,7 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -ENTRY(_start) - -PHDRS -{ - to_load PT_LOAD; -} +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = CONFIG_RAMBASE; - - INCLUDE "lib/program.ramstage.ld" - - _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) }

1 0

New patch to review for coreboot: rules.h: add fall through where no ENV_<STAGE> is set
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513 -gerrit commit e8f331dfb57c362ed6230e3dafa0bdb176c75d83 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 16:28:15 2015 -0500 rules.h: add fall through where no ENV_<STAGE> is set There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/rules.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/include/rules.h b/src/include/rules.h index 523031a..2e7f88f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,13 +63,23 @@ #define ENV_SECMON 0 #define ENV_VERSTAGE 1 -#else +#elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 + +#else +/* Default case of nothing set for random blob generation using + * create_class_compiler that isn't bound to a stage. */ +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #endif /* For romstage and ramstage always build with simple device model, ie.

1 0

Patch set updated for coreboot: x86: link romstage like the other architectures
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510 -gerrit commit df4ddbd502b33e39ec82fa4f63be110bbdf3d33f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:06:05 2015 -0500 x86: link romstage like the other architectures All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 23a24f2..8868a3f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */ +#include <rules.h> + PHDRS { to_load PT_LOAD; } +#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..9c44b13 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif +romstage-y += program.ld ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y)

1 0

Patch set updated for coreboot: linking: move romstage and bootblock to use program.ld
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509 -gerrit commit cb4e405c79aad27a1a36d54eb92dcc75cbeb6eed Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:09:49 2015 -0500 linking: move romstage and bootblock to use program.ld Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 12 +++++----- src/lib/Makefile.inc | 4 ++-- src/lib/bootblock.ld | 51 --------------------------------------- src/lib/romstage.ld | 64 ------------------------------------------------- 4 files changed, 8 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 3b3ff6d..1a38256 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -103,24 +103,24 @@ #endif /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */ -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ - _ = ASSERT(_ebootblock - _bootblock <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ - INCLUDE "lib/bootblock.bootblock.ld" + INCLUDE "lib/program.bootblock.ld" #else #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ . += sz; #endif -#ifdef __ROMSTAGE__ +#if ENV_ROMSTAGE #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ - _ = ASSERT(_eromstage - _romstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/romstage.romstage.ld" + INCLUDE "lib/program.romstage.ld" #else #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index cd2b70a..4aa6bf8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -194,8 +194,8 @@ secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock and romstage use custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well -bootblock-y += bootblock.ld -romstage-y += romstage.ld +bootblock-y += program.ld +romstage-y += program.ld endif ramstage-y += program.ld diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld deleted file mode 100644 index 42e6d64..0000000 --- a/src/lib/bootblock.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.bootblock . : { - _program = .; - _bootblock = .; - *(.text._start); - *(.text.stage_entry); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; - _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; - _ebootblock = .; - _eprogram = .; -} : to_load = 0xff - -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - *(.MIPS.*) -} diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld deleted file mode 100644 index ba154ef..0000000 --- a/src/lib/romstage.ld +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _romstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - . = ALIGN(8); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - PROVIDE(_preram_cbmem_console = .); - PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _eromstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

1 0

Patch set updated for coreboot: linking: lay the groundwork for a unified linking approach
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507 -gerrit commit b5678b17b447ba7154060328e0f07002446db30f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 22:49:36 2015 -0500 linking: lay the groundwork for a unified linking approach Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/memlayout.h | 25 +++++++ src/arch/x86/ramstage.ld | 2 +- src/include/memlayout.h | 126 ++++++++++++++++++++++++++++++++-- src/lib/Makefile.inc | 3 +- src/lib/program.ld | 67 ++++++++++++++++++ src/lib/ramstage.ld | 115 ------------------------------- 7 files changed, 218 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8311b11..23a24f2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-srcs += $(src)/arch/x86/ramstage.ld +ramstage-y += ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h new file mode 100644 index 0000000..54b8b4a --- /dev/null +++ b/src/arch/x86/include/arch/memlayout.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* Currently empty to satisfy common arch requirements. */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 5fcbbb6..c9b2f17 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -19,7 +19,7 @@ SECTIONS { . = CONFIG_RAMBASE; - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..3b3ff6d 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -22,10 +22,41 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H +#include <rules.h> #include <arch/memlayout.h> +/* Macros that the architecture can override. */ +#ifndef ARCH_POINTER_ALIGN_SIZE +#define ARCH_POINTER_ALIGN_SIZE 8 +#endif + +#ifndef ARCH_CACHELINE_ALIGN_SIZE +#define ARCH_CACHELINE_ALIGN_SIZE 64 +#endif + +#ifndef ARCH_FIRST_TEXT +#define ARCH_FIRST_TEXT +#endif + +/* Default to data as well as bss. */ +#ifndef ARCH_STAGE_HAS_DATA_SECTION +#define ARCH_STAGE_HAS_DATA_SECTION 1 +#endif + +#ifndef ARCH_STAGE_HAS_BSS_SECTION +#define ARCH_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Default is that currently ramstage and smm only has a heap. */ +#ifndef ARCH_STAGE_HAS_HEAP_SECTION +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#endif + #define STR(x) #x +#define ALIGN_COUNTER(align) \ + . = ALIGN(align); + #define SET_COUNTER(name, addr) \ _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ . = addr; @@ -34,6 +65,9 @@ SET_COUNTER(name, addr) \ _##name = .; +#define SYMBOL_CURRENT_LOC(name) \ + _##name = .; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ @@ -58,7 +92,7 @@ /* TODO: This only works if you never access CBFS in romstage before RAM is up! * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__) +#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) @@ -93,16 +127,100 @@ . += sz; #endif -#ifdef __RAMSTAGE__ +#if ENV_RAMSTAGE #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ - _ = ASSERT(_eramstage - _ramstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ . += sz; #endif +#if ENV_RAMSTAGE || ENV_ROMSTAGE +#define CBMEM_INIT_HOOKS \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ + KEEP(*(.rodata.cbmem_init_hooks)); \ + SYMBOL_CURRENT_LOC(ecbmem_init_hooks) +#else +#define CBMEM_INIT_HOOKS +#endif + +#if ENV_RAMSTAGE +#define DRIVERS_RODATA \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(pci_drivers) \ + KEEP(*(.rodata.pci_driver)); \ + SYMBOL_CURRENT_LOC(epci_drivers) \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cpu_drivers) \ + KEEP(*(.rodata.cpu_driver)); \ + SYMBOL_CURRENT_LOC(ecpu_drivers) +#else +#define DRIVERS_RODATA +#endif + +#define BEGIN_SECTION(name, align) \ + .##name : { \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(name) + +#define END_SECTION(name, align) \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(e##name) \ + } + +#if ARCH_STAGE_HAS_DATA_SECTION +#ifdef __PRE_RAM__ +/* Provide these symbols in PRE_RAM environments if not already provided. */ +#define DATA_EXTRA \ + PROVIDE(_preram_cbmem_console = .); \ + PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); +#elif ENV_RAMSTAGE +#define DATA_EXTRA \ + SYMBOL_CURRENT_LOC(bs_init_begin) \ + KEEP(*(.bs_init)); \ + LONG(0); \ + LONG(0); \ + SYMBOL_CURRENT_LOC(ebs_init_begin) +#else +#define DATA_EXTRA +#endif + +#define DATA_SECTION \ + BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + *(.data); \ + *(.data.*); \ + DATA_EXTRA \ + END_SECTION(data, ARCH_POINTER_ALIGN_SIZE) +#else +#define DATA_SECTION +#endif + +#if ARCH_STAGE_HAS_BSS_SECTION +#define BSS_SECTION \ + BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \ + *(.bss) \ + *(.bss.*) \ + *(.sbss) \ + *(.sbss.*) \ + END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) +#else +#define BSS_SECTION +#endif + +#if ARCH_STAGE_HAS_HEAP_SECTION +#define HEAP_SECTION \ + BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ + . += CONFIG_HEAP_SIZE ; \ + END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) +#else +#define HEAP_SECTION +#endif + +#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + #endif /* __MEMLAYOUT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8597667..cd2b70a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += bootblock.ld romstage-y += romstage.ld endif -ramstage-y += ramstage.ld + +ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/lib/program.ld b/src/lib/program.ld new file mode 100644 index 0000000..4900d3e --- /dev/null +++ b/src/lib/program.ld @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +BEGIN_SECTION(text, 1) + SYMBOL_CURRENT_LOC(program) + ARCH_FIRST_TEXT + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + POINTER_ALIGN + CBMEM_INIT_HOOKS + DRIVERS_RODATA + *(.rodata); + *(.rodata.*); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(etext) +END_SECTION(text, 1) : to_load + +#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +BEGIN_SECTION(ctors, 0x100) + SYMBOL_CURRENT_LOC(__CTOR_LIST__) + KEEP(*(.ctors)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(__CTOR_END__) +END_SECTION(ctors, 1) +#endif + +/* Include data, bss, and heap in that order. Not defined for all stages. */ +DATA_SECTION +BSS_SECTION +HEAP_SECTION +SYMBOL_CURRENT_LOC(eprogram) + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.comment.*) + *(.note) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld deleted file mode 100644 index b224827..0000000 --- a/src/lib/ramstage.ld +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -/* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ -.text : { - _program = .; - _ramstage = .; - _text = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; -} : to_load - -#if IS_ENABLED(CONFIG_COVERAGE) -.ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; -} -#endif - -/* TODO: align data sections to cache lines? (is that really useful?) */ -.rodata : { - _rodata = .; - . = ALIGN(8); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(8); - - _erodata = .; -} - -.data : { - /* Move to different cache line to avoid false sharing with .rodata. */ - . = ALIGN(64); /* May not be actual line size, not that important. */ - _data = .; - *(.data) - *(.data.*) - _edata = .; -} - -.bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; -} - -.heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - _eramstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ - -/DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) -}

1 0

Patch set updated for coreboot: symbols: add '_' to pci_drivers and cpu_drivers symbols
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11506 -gerrit commit c25ca7be840d35ad5f7669e37abb064ac4871363 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 17:23:08 2015 -0500 symbols: add '_' to pci_drivers and cpu_drivers symbols In order to prepare for more unification of the linker scripts prefix pci_drivers, epci_drivers, cpu_drivers, and ecpu_drivers with an underscore. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built different boards includes ones w/ and w/o relocatable ramstage. Change-Id: I8918b38db3b754332e8d8506b424f3c6b3e06af8 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/arm64/cpu_ramstage.c | 2 +- src/arch/x86/cpu.c | 2 +- src/device/pci_device.c | 2 +- src/include/cpu/cpu.h | 4 ++-- src/include/device/pci.h | 4 ++-- src/lib/ramstage.ld | 8 ++++---- src/lib/rmodule.ld | 8 ++++---- 7 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c index 7b4b26a..a49bf48 100644 --- a/src/arch/arm64/cpu_ramstage.c +++ b/src/arch/arm64/cpu_ramstage.c @@ -42,7 +42,7 @@ static struct cpu_driver *locate_cpu_driver(uint32_t midr) { struct cpu_driver *cur; - for (cur = cpu_drivers; cur != ecpu_drivers; cur++) { + for (cur = _cpu_drivers; cur != _ecpu_drivers; cur++) { const struct cpu_device_id *id_table = cur->id_table; for (; id_table->midr != CPU_ID_END; id_table++) { diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 3eb7b94..ceed077 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -192,7 +192,7 @@ static void identify_cpu(struct device *cpu) struct cpu_driver *find_cpu_driver(struct device *cpu) { struct cpu_driver *driver; - for (driver = cpu_drivers; driver < ecpu_drivers; driver++) { + for (driver = _cpu_drivers; driver < _ecpu_drivers; driver++) { struct cpu_device_id *id; for (id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) { diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 6332209..f2e4d5d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -850,7 +850,7 @@ static void set_pci_ops(struct device *dev) * Look through the list of setup drivers and find one for * this PCI device. */ - for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) { + for (driver = &_pci_drivers[0]; driver != &_epci_drivers[0]; driver++) { if ((driver->vendor == dev->vendor) && device_id_match(driver, dev->device)) { dev->ops = (struct device_operations *)driver->ops; diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h index 47521d4..28431c0 100644 --- a/src/include/cpu/cpu.h +++ b/src/include/cpu/cpu.h @@ -18,9 +18,9 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1); #define __cpu_driver __attribute__ ((used,__section__(".rodata.cpu_driver"))) #ifndef __SIMPLE_DEVICE__ /** start of compile time generated pci driver array */ -extern struct cpu_driver cpu_drivers[]; +extern struct cpu_driver _cpu_drivers[]; /** end of compile time generated pci driver array */ -extern struct cpu_driver ecpu_drivers[]; +extern struct cpu_driver _ecpu_drivers[]; #endif #endif /* !__PRE_RAM__ && !__SMM__ */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 2a76ba9..fe31b54 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -55,9 +55,9 @@ struct pci_driver { #define __pci_driver __attribute__ ((used,__section__(".rodata.pci_driver"))) /** start of compile time generated pci driver array */ -extern struct pci_driver pci_drivers[]; +extern struct pci_driver _pci_drivers[]; /** end of compile time generated pci driver array */ -extern struct pci_driver epci_drivers[]; +extern struct pci_driver _epci_drivers[]; extern struct device_operations default_pci_ops_dev; diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 432df40..b224827 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -53,12 +53,12 @@ /* If any changes are made to the driver start/symbols or the * section names the equivalent changes need to made to * rmodule.ld. */ - pci_drivers = . ; + _pci_drivers = . ; KEEP(*(.rodata.pci_driver)); - epci_drivers = . ; - cpu_drivers = . ; + _epci_drivers = . ; + _cpu_drivers = . ; KEEP(*(.rodata.cpu_driver)); - ecpu_drivers = . ; + _ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); LONG(0); diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index e6b4da7..f5d5f06 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -42,13 +42,13 @@ SECTIONS * ramstage with the rmodule linker. Any changes made in * ramstage.ld should be made here as well. */ . = ALIGN(8); - pci_drivers = . ; + _pci_drivers = . ; KEEP(*(.rodata.pci_driver)); - epci_drivers = . ; + _epci_drivers = . ; . = ALIGN(8); - cpu_drivers = . ; + _cpu_drivers = . ; KEEP(*(.rodata.cpu_driver)); - ecpu_drivers = . ; + _ecpu_drivers = . ; . = ALIGN(8); _bs_init_begin = .; KEEP(*(.bs_init));

1 0

Patch set updated for coreboot: x86: link romstage like the other architectures
by Aaron Durbin 04 Sep '15

04 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510 -gerrit commit 5088b0ad4ec6373b5d16b75c95a53ced3f2fecd6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:06:05 2015 -0500 x86: link romstage like the other architectures All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 23a24f2..8868a3f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */ +#include <rules.h> + PHDRS { to_load PT_LOAD; } +#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..9c44b13 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif +romstage-y += program.ld ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y)

1 0

← Newer
1
...
73
74
75
76
77
78
79
...
86
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2015