coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: buildgcc: Show the progress when downloading
by Zheng Bao 06 Sep '15

06 Sep '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520 -gerrit commit eba84def407643d05044bedaf1f45032f17d2efc Author: zbao <fishbaozi(a)gmail.com> Date: Sun Sep 6 05:00:04 2015 -0400 buildgcc: Show the progress when downloading Leave the final "100%" unerased. Checking return code of wget is removed. Change-Id: I4559e88d541738a594dce92e23589992f234cb9b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0ed9a39..ed233d8 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -188,6 +188,14 @@ compute_sum() { printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" } +download_showing_percentage() { + url=$1 + printf " .. 0%%" + wget --no-check-certificate $url 2>&1 | while read line; do + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + done +} + download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" @@ -201,14 +209,13 @@ download() { printf "(downloading from $archive)" rm -f tarballs/$FILE cd tarballs - wget --no-check-certificate -q $archive - wgetret=$? + download_showing_percentage $archive cd .. compute_sum $FILE fi if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n" + printf "\n${RED}Failed to download $FILE.${NC}\n" exit 1 fi printf "\n"

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Patch set updated for coreboot: buildgcc: Show the progress when downloading
by Zheng Bao 06 Sep '15

06 Sep '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520 -gerrit commit f89f6137312ce006b50364c75e69e66d5b0e15d9 Author: zbao <fishbaozi(a)gmail.com> Date: Sun Sep 6 04:44:38 2015 -0400 buildgcc: Show the progress when downloading Change-Id: I4559e88d541738a594dce92e23589992f234cb9b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0ed9a39..a2c4b81 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -188,6 +188,14 @@ compute_sum() { printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" } +download_one() { + url=$1 + printf " .. 0%%" + wget --no-check-certificate $url 2>&1 | while read line; do + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + done +} + download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" @@ -201,14 +209,13 @@ download() { printf "(downloading from $archive)" rm -f tarballs/$FILE cd tarballs - wget --no-check-certificate -q $archive - wgetret=$? + download_one $archive cd .. compute_sum $FILE fi if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n" + printf "\n${RED}Failed to download $FILE.${NC}\n" exit 1 fi printf "\n"

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New patch to review for coreboot: buildgcc: Show the progress when downloading *still working*.
by Zheng Bao 06 Sep '15

06 Sep '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11520 -gerrit commit 1f6246dd823c1d3cb39603a177d1aa5ee2c345c6 Author: zbao <fishbaozi(a)gmail.com> Date: Sun Sep 6 02:10:42 2015 -0400 buildgcc: Show the progress when downloading *still working*. For some systems, the commands are buffered by default. On these systems, the progress can not been seen, except the final "ok". Change-Id: I4559e88d541738a594dce92e23589992f234cb9b Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/crossgcc/buildgcc | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0ed9a39..a8612ca 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -188,6 +188,13 @@ compute_sum() { printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" } +download_one() { + url=$1 + printf " .. " + wget --no-check-certificate $url 2>&1 | grep --line-buffered -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + printf "\b\b\b\b${green} ok${NC}" +} + download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" @@ -201,14 +208,13 @@ download() { printf "(downloading from $archive)" rm -f tarballs/$FILE cd tarballs - wget --no-check-certificate -q $archive - wgetret=$? + download_one $archive cd .. compute_sum $FILE fi if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE. Wget returns $wgetret. See 'man wget'.${NC}\n" + printf "\n${RED}Failed to download $FILE.${NC}\n" exit 1 fi printf "\n"

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New patch to review for coreboot: smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG
by Patrick Georgi 05 Sep '15

05 Sep '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11519 -gerrit commit 21716a5d3464e183c6fa08a215591a2aff5bc617 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 5 20:21:24 2015 +0200 smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG This mitigates the Memory Sinkhole issue (described on https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and crashing the system explicitly if LAPIC overlaps ASEG. This needs to happen without a data access (only code fetches) because data accesses could be tampered with. Don't try to recover because, if somebody tried to do shenanigans like these, we have to expect more. Sandybridge is safe because it does the same test in hardware, and crashes. Newer chipsets presumably do the same. This needs to be extended to deal with overlapping TSEG as well. Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/x86/smm/smmhandler.S | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 7b70ce9..f2094ef 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -25,6 +25,10 @@ * to 64k if we can though. */ +#include <kconfig.h> +#include <config.h> +#define LAPIC_BASE_MSR 0x1b + /* * +--------------------------------+ 0xaffff * | Save State Map Node 0 | @@ -74,8 +78,39 @@ * * All the bad magic is not all that bad after all. */ +#define SMM_START 0xa0000 +#define SMM_END 0xb0000 +#if SMM_END <= SMM_START +#error invalid SMM configuration +#endif .global smm_handler_start smm_handler_start: +#if IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_GM45) || \ + IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_I945) + mov $LAPIC_BASE_MSR, %ecx + rdmsr + and $(~0xfff), %eax + sub $(SMM_START), %eax + cmp $(SMM_END - SMM_START), %eax + ja untampered_lapic +1: + // "Crash" + mov $(CONFIG_TTYS0_BASE), %dx + mov $'C', %al + out %al, (%dx) + mov $'r', %al + out %al, (%dx) + mov $'a', %al + out %al, (%dx) + mov $'s', %al + out %al, (%dx) + mov $'h', %al + out %al, (%dx) + // now crash for real + ud2 +untampered_lapic: +#endif movw $(smm_gdtptr16 - smm_handler_start + SMM_HANDLER_OFFSET), %bx data32 lgdt %cs:(%bx)

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New patch to review for coreboot: rmodtool: honor ELF entry point
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11518 -gerrit commit e8e0e7d0433385f43118c3d277083a5618dfc928 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 13:17:25 2015 -0500 rmodtool: honor ELF entry point Instead of using a pre-determined symbol, _start, use the entry point within the ELF header. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: I53e9c6eaa1ce761ab8519677fe2f4d0d2b82bb40 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- util/cbfstool/rmodule.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 3b127b2..c35eff7 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -416,8 +416,8 @@ static int populate_program_info(struct rmod_context *ctx) if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) return -1; - if (populate_sym(ctx, "_start", &ctx->entry, nsyms, strtab)) - return -1; + /* Honor the entry point within the ELF header. */ + ctx->entry = ehdr->e_entry; /* Link address is the virtual address of the program segment. */ ctx->link_addr = ctx->phdr->p_vaddr;

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New patch to review for coreboot: rmodule: use program.ld for linking
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11517 -gerrit commit d98f88c1e63d6892a2cf04197fc73732e0b12161 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 12:59:26 2015 -0500 rmodule: use program.ld for linking Bring rmodule linking into the common linking method. For starters, assume '_start' is the entry point for rmodules instead of __rmodule_entry. That's the majority of this patch's work diff. Second, add support for ENV_RMODULE so that one can distinguish the environment when generating linker scripts. Lastly, directly use program.ld for the rmodule.ld linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage, sipi_vector, and smm rmodules. Change-Id: Iaa499eb229d8171272add9ee6d27cff75e7534ac Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- Makefile.inc | 3 + src/arch/arm64/include/arch/header.ld | 10 +++- src/arch/arm64/stage_entry.S | 4 +- src/arch/x86/c_start.S | 2 - src/arch/x86/include/arch/header.ld | 2 +- src/cpu/x86/Makefile.inc | 4 +- src/cpu/x86/sipi_vector.S | 10 ++-- src/cpu/x86/smm/smm_stub.S | 6 +- src/include/memlayout.h | 22 ++++++-- src/include/rmodule.h | 4 +- src/include/rules.h | 16 ++++++ src/lib/rmodule.ld | 101 ++-------------------------------- util/cbfstool/rmodule.c | 6 +- 13 files changed, 66 insertions(+), 124 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 1cac01b..b5d8309 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -72,6 +72,9 @@ classes-y := ramstage romstage bootblock smm smmstub cpu_microcode libverstage v # Add dynamic classes for rmodules $(foreach supported_arch,$(ARCH_SUPPORTED), \ $(eval $(call define_class,rmodules_$(supported_arch),$(supported_arch)))) +# Provide a macro to determine environment for free standing rmodules. +$(foreach supported_arch,$(ARCH_SUPPORTED), \ + $(eval rmodules_$(supported_arch)-generic-ccopts += -D__RMODULE__)) ####################################################################### # Helper functions for math and various file placement matters. diff --git a/src/arch/arm64/include/arch/header.ld b/src/arch/arm64/include/arch/header.ld index fa8fdfa..b3112e3 100644 --- a/src/arch/arm64/include/arch/header.ld +++ b/src/arch/arm64/include/arch/header.ld @@ -17,6 +17,8 @@ * Foundation, Inc. */ +#include <rules.h> + /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") OUTPUT_ARCH(aarch64) @@ -26,7 +28,13 @@ PHDRS to_load PT_LOAD; } -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBTLOCK TARGET(binary) #endif + +/* secmon uses rmodules */ +#if ENV_RMODULE +ENTRY(_start) +#else ENTRY(stage_entry) +#endif diff --git a/src/arch/arm64/stage_entry.S b/src/arch/arm64/stage_entry.S index 4e15dbb..dbc6cad 100644 --- a/src/arch/arm64/stage_entry.S +++ b/src/arch/arm64/stage_entry.S @@ -136,12 +136,12 @@ ENDPROC(arm64_c_environment) 2002: .endm -ENTRY(__rmodule_entry) +ENTRY(_start) split_bsp_path /* Save the arguments to secmon in x25 */ mov x25, x0 b arm64_c_environment -ENDPROC(__rmodule_entry) +ENDPROC(_start) /* * Setup SCTLR so that: diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 582966b..ad4589a 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -23,8 +23,6 @@ thread_stacks: .code32 #endif .globl _start - .globl __rmodule_entry -__rmodule_entry: _start: cli lgdt %cs:gdtaddr diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index 55547ad..0262c92 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -24,7 +24,7 @@ PHDRS to_load PT_LOAD; } -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_RMODULE ENTRY(_start) #elif ENV_ROMSTAGE ENTRY(protected_start) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9ec0768..e9394b2 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -20,9 +20,9 @@ $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32)) else -$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64)) +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64)) endif $(SIPI_BIN): $(SIPI_RMOD) diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index c7b1097..0887b0a 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -56,10 +56,8 @@ ap_count: .text .code16 -.global ap_start -.global __rmodule_entry -__rmodule_entry: -ap_start: +.global _start +_start: cli xorl %eax, %eax movl %eax, %cr3 /* Invalidate TLB*/ @@ -74,9 +72,9 @@ ap_start: /* The gdtaddr needs to be releative to the data segment in order * to properly dereference it. The .text section comes first in an - * rmodule so ap_start can be used as a proxy for the load address. */ + * rmodule so _start can be used as a proxy for the load address. */ movl $(gdtaddr), %ebx - sub $(ap_start), %ebx + sub $(_start), %ebx data32 lgdt (%ebx) diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 5fbec28..ead597c 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -59,10 +59,8 @@ fallback_stack_top: .text .code16 -.global smm_handler_start -.global __rmodule_entry -__rmodule_entry: -smm_handler_start: +.global _start +_start: movl $(smm_relocate_gdt), %ebx data32 lgdt (%ebx) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 02f67db..ef47f6b 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -47,9 +47,9 @@ #define ARCH_STAGE_HAS_BSS_SECTION 1 #endif -/* Default is that currently ramstage and smm only has a heap. */ +/* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) #endif #define STR(x) #x @@ -166,7 +166,7 @@ REGION(watchdog_tombstone, addr, size, 4) \ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); -#if ENV_RAMSTAGE || ENV_ROMSTAGE +#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ @@ -176,7 +176,7 @@ #define CBMEM_INIT_HOOKS #endif -#if ENV_RAMSTAGE +#if ENV_RAMSTAGE || ENV_RMODULE #define DRIVERS_RODATA \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(pci_drivers) \ @@ -206,7 +206,7 @@ #define DATA_EXTRA \ PROVIDE(_preram_cbmem_console = .); \ PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE +#elif ENV_RAMSTAGE || ENV_RMODULE #define DATA_EXTRA \ SYMBOL_CURRENT_LOC(bs_init_begin) \ KEEP(*(.bs_init)); \ @@ -217,8 +217,18 @@ #define DATA_EXTRA #endif +#if ENV_RMODULE +#define RMODULE_PARAMS \ + SYMBOL_CURRENT_LOC(rmodule_params) \ + KEEP(*(.module_parameters)); \ + SYMBOL_CURRENT_LOC(ermodule_params) +#else +#define RMODULE_PARAMS +#endif + #define DATA_SECTION \ BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + RMODULE_PARAMS \ *(.data); \ *(.data.*); \ DATA_EXTRA \ @@ -242,7 +252,7 @@ #if ARCH_STAGE_HAS_HEAP_SECTION #define HEAP_SECTION \ BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ - . += CONFIG_HEAP_SIZE ; \ + . += (ENV_RMODULE ? __heap_size : CONFIG_HEAP_SIZE); \ END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) #else #define HEAP_SECTION diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 719c6a6..03cdf76 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -73,9 +73,9 @@ struct rmodule { }; #if IS_ENABLED(CONFIG_RELOCATABLE_MODULES) -/* Rmodules have an entry point of named __rmodule_entry. */ +/* Rmodules have an entry point of named _start. */ #define RMODULE_ENTRY(entry_) \ - void __rmodule_entry(void *) __attribute__((alias (STRINGIFY(entry_)))) + void _start(void *) __attribute__((alias (STRINGIFY(entry_)))) #else #define RMODULE_ENTRY(entry_) #endif diff --git a/src/include/rules.h b/src/include/rules.h index 2e7f88f..c9d3f59 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -30,6 +30,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__ROMSTAGE__) #define ENV_BOOTBLOCK 0 @@ -38,6 +39,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__SMM__) #define ENV_BOOTBLOCK 0 @@ -46,6 +48,7 @@ #define ENV_SMM 1 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__SECMON__) #define ENV_BOOTBLOCK 0 @@ -54,6 +57,7 @@ #define ENV_SMM 0 #define ENV_SECMON 1 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #elif defined(__VERSTAGE__) #define ENV_BOOTBLOCK 0 @@ -62,6 +66,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 1 +#define ENV_RMODULE 0 #elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 @@ -70,6 +75,16 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 + +#elif defined(__RMODULE__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 1 #else /* Default case of nothing set for random blob generation using @@ -80,6 +95,7 @@ #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 #endif /* For romstage and ramstage always build with simple device model, ie. diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f5d5f06..340fe7a 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -12,103 +12,14 @@ * won't be a consistent mapping between the flat blob and the loaded program. */ -BASE_ADDRESS = 0x00000; - -ENTRY(__rmodule_entry); +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = BASE_ADDRESS; - - .payload : { - /* C code of the module. */ - _program = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - /* C read-only data. */ - . = ALIGN(16); - -#if IS_ENABLED(CONFIG_COVERAGE) - __CTOR_LIST__ = .; - *(.ctors); - LONG(0); - LONG(0); - __CTOR_END__ = .; -#endif - - /* The driver sections are to allow linking coreboot's - * ramstage with the rmodule linker. Any changes made in - * ramstage.ld should be made here as well. */ - . = ALIGN(8); - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - . = ALIGN(8); - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - . = ALIGN(8); - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - . = ALIGN(8); - - *(.rodata); - *(.rodata.*); - . = ALIGN(8); - - /* The parameters section can be used to pass parameters - * to a module, however there has to be an prior agreement - * on how to interpret the parameters. */ - _module_params_begin = .; - KEEP(*(.module_parameters)); - _module_params_end = .; - . = ALIGN(8); - - /* Data section. */ - . = ALIGN(64); /* Mirror cache line alignment from ramstage. */ - _sdata = .; - *(.data); - *(.data.*); - . = ALIGN(8); - _edata = .; - - . = ALIGN(8); - } - - .bss (NOLOAD) : { - /* C uninitialized data of the module. */ - _bss = .; - *(.bss); - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(COMMON); - . = ALIGN(8); - _ebss = .; - - /* - * Place the heap after BSS. The heap size is passed in by - * by way of ld --defsym=__heap_size=<> - */ - _heap = .; - . = . + __heap_size; - _eheap = .; - _eprogram = .; - } + SET_COUNTER(rmodule, 0x00000000) - /DISCARD/ : { - /* Drop unnecessary sections. */ - *(.eh_frame); - *(.note); - *(.note.*); - } + /* program.ld is directly included because there's no one particular + * class that rmodule is used on. */ + #include <lib/program.ld> } diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index f93f4f6..3b127b2 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -402,11 +402,11 @@ static int populate_program_info(struct rmod_context *ctx) break; } - if (populate_sym(ctx, "_module_params_begin", &ctx->parameters_begin, + if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin, nsyms, strtab)) return -1; - if (populate_sym(ctx, "_module_params_end", &ctx->parameters_end, + if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end, nsyms, strtab)) return -1; @@ -416,7 +416,7 @@ static int populate_program_info(struct rmod_context *ctx) if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) return -1; - if (populate_sym(ctx, "__rmodule_entry", &ctx->entry, nsyms, strtab)) + if (populate_sym(ctx, "_start", &ctx->entry, nsyms, strtab)) return -1; /* Link address is the virtual address of the program segment. */

1 0

Patch set updated for coreboot: stash
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11515 -gerrit commit b3468f79d27ff9eee5723f28200b87a757918f57 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 10:27:12 2015 -0500 stash Change-Id: I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe --- src/vendorcode/google/chromeos/memlayout.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h index 29434bd..e86246f 100644 --- a/src/vendorcode/google/chromeos/memlayout.h +++ b/src/vendorcode/google/chromeos/memlayout.h @@ -31,13 +31,13 @@ #ifdef __VERSTAGE__ #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ - _ = ASSERT(_everstage - _verstage <= sz, \ + SET_COUNTER(verstage, addr) \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Verstage exceeded its allotted size! (sz))); \ INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld" #else #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ + SET_COUNTER(verstage, addr) \ . += sz; #endif

1 0

Patch set updated for coreboot: verstage: use common program.ld for linking
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516 -gerrit commit 4dc3c98750f690e86bc5ec3e9adc4c92cadd2de5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 11:08:02 2015 -0500 verstage: use common program.ld for linking There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 27 ++++++++++ src/lib/Makefile.inc | 1 + src/soc/broadcom/cygnus/include/soc/memlayout.ld | 1 - src/soc/imgtec/pistachio/include/soc/memlayout.ld | 1 - src/soc/marvell/bg4cd/include/soc/memlayout.ld | 1 - src/soc/nvidia/tegra124/include/soc/memlayout.ld | 1 - .../tegra132/include/soc/memlayout_vboot2.ld | 1 - .../tegra210/include/soc/memlayout_vboot2.ld | 1 - src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 - .../samsung/exynos5250/include/soc/memlayout.ld | 1 - src/vendorcode/google/chromeos/memlayout.h | 54 -------------------- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 2 - src/vendorcode/google/chromeos/vboot2/verstage.ld | 58 ---------------------- 14 files changed, 28 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1a38256..02f67db 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -139,6 +139,33 @@ . += sz; #endif +/* Careful: required work buffer size depends on RW properties such as key size + * and algorithm -- what works for you might stop working after an update. Do + * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ +#define VBOOT2_WORK(addr, size) \ + REGION(vboot2_work, addr, size, 16) \ + _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); + +#if ENV_VERSTAGE + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + _ = ASSERT(_eprogram - _program <= sz, \ + STR(Verstage exceeded its allotted size! (sz))); \ + INCLUDE "lib/program.verstage.ld" + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) +#else + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + . += sz; + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) +#endif + +#define WATCHDOG_TOMBSTONE(addr, size) \ + REGION(watchdog_tombstone, addr, size, 4) \ + _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); + #if ENV_RAMSTAGE || ENV_ROMSTAGE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 464d631..d8cd1d8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -199,6 +199,7 @@ endif romstage-y += program.ld ramstage-y += program.ld +verstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 5e149b4..237ffc6 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 366b20a..59e3017 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld index 15c09d9..45835e2 100644 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 2312cc9..561833d 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 0f98fd2..a8164a9 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index c140e01..dee6798 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index cf417ba..ad0977a 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -19,7 +19,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 0b75932..b96923e 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 3b5b034..4469078 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h deleted file mode 100644 index e86246f..0000000 --- a/src/vendorcode/google/chromeos/memlayout.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file contains macro definitions for memlayout.ld linker scripts. */ - -#ifndef __CHROMEOS_MEMLAYOUT_H -#define __CHROMEOS_MEMLAYOUT_H - -/* Careful: required work buffer size depends on RW properties such as key size - * and algorithm -- what works for you might stop working after an update. Do - * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ -#define VBOOT2_WORK(addr, size) \ - REGION(vboot2_work, addr, size, 16) \ - _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); - -#ifdef __VERSTAGE__ - #define VERSTAGE(addr, sz) \ - SET_COUNTER(verstage, addr) \ - _ = ASSERT(_eprogram - _program <= sz, \ - STR(Verstage exceeded its allotted size! (sz))); \ - INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld" -#else - #define VERSTAGE(addr, sz) \ - SET_COUNTER(verstage, addr) \ - . += sz; -#endif - -#ifdef __VERSTAGE__ - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) -#else - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) -#endif - -#define WATCHDOG_TOMBSTONE(addr, size) \ - REGION(watchdog_tombstone, addr, size, 4) \ - _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); - -#endif /* __CHROMEOS_MEMLAYOUT_H */ diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index b805993..21613ba 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c ramstage-y += common.c -verstage-y += verstage.ld - ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) else diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld deleted file mode 100644 index fcb8af8..0000000 --- a/src/vendorcode/google/chromeos/vboot2/verstage.ld +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _verstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _everstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

1 0

Patch set updated for coreboot: linking: lay the groundwork for a unified linking approach
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507 -gerrit commit e304dbdd9d13b6f1f919af8ebba25d84fcc6303e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 22:49:36 2015 -0500 linking: lay the groundwork for a unified linking approach Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/memlayout.h | 25 +++++++ src/arch/x86/ramstage.ld | 2 +- src/include/memlayout.h | 126 ++++++++++++++++++++++++++++++++-- src/lib/Makefile.inc | 3 +- src/lib/program.ld | 66 ++++++++++++++++++ src/lib/ramstage.ld | 115 ------------------------------- 7 files changed, 217 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8311b11..23a24f2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-srcs += $(src)/arch/x86/ramstage.ld +ramstage-y += ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h new file mode 100644 index 0000000..54b8b4a --- /dev/null +++ b/src/arch/x86/include/arch/memlayout.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* Currently empty to satisfy common arch requirements. */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 5fcbbb6..c9b2f17 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -19,7 +19,7 @@ SECTIONS { . = CONFIG_RAMBASE; - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..3b3ff6d 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -22,10 +22,41 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H +#include <rules.h> #include <arch/memlayout.h> +/* Macros that the architecture can override. */ +#ifndef ARCH_POINTER_ALIGN_SIZE +#define ARCH_POINTER_ALIGN_SIZE 8 +#endif + +#ifndef ARCH_CACHELINE_ALIGN_SIZE +#define ARCH_CACHELINE_ALIGN_SIZE 64 +#endif + +#ifndef ARCH_FIRST_TEXT +#define ARCH_FIRST_TEXT +#endif + +/* Default to data as well as bss. */ +#ifndef ARCH_STAGE_HAS_DATA_SECTION +#define ARCH_STAGE_HAS_DATA_SECTION 1 +#endif + +#ifndef ARCH_STAGE_HAS_BSS_SECTION +#define ARCH_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Default is that currently ramstage and smm only has a heap. */ +#ifndef ARCH_STAGE_HAS_HEAP_SECTION +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#endif + #define STR(x) #x +#define ALIGN_COUNTER(align) \ + . = ALIGN(align); + #define SET_COUNTER(name, addr) \ _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ . = addr; @@ -34,6 +65,9 @@ SET_COUNTER(name, addr) \ _##name = .; +#define SYMBOL_CURRENT_LOC(name) \ + _##name = .; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ @@ -58,7 +92,7 @@ /* TODO: This only works if you never access CBFS in romstage before RAM is up! * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__) +#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) @@ -93,16 +127,100 @@ . += sz; #endif -#ifdef __RAMSTAGE__ +#if ENV_RAMSTAGE #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ - _ = ASSERT(_eramstage - _ramstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ . += sz; #endif +#if ENV_RAMSTAGE || ENV_ROMSTAGE +#define CBMEM_INIT_HOOKS \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ + KEEP(*(.rodata.cbmem_init_hooks)); \ + SYMBOL_CURRENT_LOC(ecbmem_init_hooks) +#else +#define CBMEM_INIT_HOOKS +#endif + +#if ENV_RAMSTAGE +#define DRIVERS_RODATA \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(pci_drivers) \ + KEEP(*(.rodata.pci_driver)); \ + SYMBOL_CURRENT_LOC(epci_drivers) \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cpu_drivers) \ + KEEP(*(.rodata.cpu_driver)); \ + SYMBOL_CURRENT_LOC(ecpu_drivers) +#else +#define DRIVERS_RODATA +#endif + +#define BEGIN_SECTION(name, align) \ + .##name : { \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(name) + +#define END_SECTION(name, align) \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(e##name) \ + } + +#if ARCH_STAGE_HAS_DATA_SECTION +#ifdef __PRE_RAM__ +/* Provide these symbols in PRE_RAM environments if not already provided. */ +#define DATA_EXTRA \ + PROVIDE(_preram_cbmem_console = .); \ + PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); +#elif ENV_RAMSTAGE +#define DATA_EXTRA \ + SYMBOL_CURRENT_LOC(bs_init_begin) \ + KEEP(*(.bs_init)); \ + LONG(0); \ + LONG(0); \ + SYMBOL_CURRENT_LOC(ebs_init_begin) +#else +#define DATA_EXTRA +#endif + +#define DATA_SECTION \ + BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + *(.data); \ + *(.data.*); \ + DATA_EXTRA \ + END_SECTION(data, ARCH_POINTER_ALIGN_SIZE) +#else +#define DATA_SECTION +#endif + +#if ARCH_STAGE_HAS_BSS_SECTION +#define BSS_SECTION \ + BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \ + *(.bss) \ + *(.bss.*) \ + *(.sbss) \ + *(.sbss.*) \ + END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) +#else +#define BSS_SECTION +#endif + +#if ARCH_STAGE_HAS_HEAP_SECTION +#define HEAP_SECTION \ + BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ + . += CONFIG_HEAP_SIZE ; \ + END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) +#else +#define HEAP_SECTION +#endif + +#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + #endif /* __MEMLAYOUT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8597667..cd2b70a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += bootblock.ld romstage-y += romstage.ld endif -ramstage-y += ramstage.ld + +ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/lib/program.ld b/src/lib/program.ld new file mode 100644 index 0000000..f4850d3 --- /dev/null +++ b/src/lib/program.ld @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +BEGIN_SECTION(text, 1) + SYMBOL_CURRENT_LOC(program) + ARCH_FIRST_TEXT + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + POINTER_ALIGN + CBMEM_INIT_HOOKS + DRIVERS_RODATA + *(.rodata); + *(.rodata.*); + POINTER_ALIGN +END_SECTION(text, 1) : to_load + +#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +BEGIN_SECTION(ctors, 0x100) + SYMBOL_CURRENT_LOC(__CTOR_LIST__) + KEEP(*(.ctors)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(__CTOR_END__) +END_SECTION(ctors, 1) +#endif + +/* Include data, bss, and heap in that order. Not defined for all stages. */ +DATA_SECTION +BSS_SECTION +HEAP_SECTION +SYMBOL_CURRENT_LOC(eprogram) + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.comment.*) + *(.note) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld deleted file mode 100644 index b224827..0000000 --- a/src/lib/ramstage.ld +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -/* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ -.text : { - _program = .; - _ramstage = .; - _text = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; -} : to_load - -#if IS_ENABLED(CONFIG_COVERAGE) -.ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; -} -#endif - -/* TODO: align data sections to cache lines? (is that really useful?) */ -.rodata : { - _rodata = .; - . = ALIGN(8); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(8); - - _erodata = .; -} - -.data : { - /* Move to different cache line to avoid false sharing with .rodata. */ - . = ALIGN(64); /* May not be actual line size, not that important. */ - _data = .; - *(.data) - *(.data.*) - _edata = .; -} - -.bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; -} - -.heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - _eramstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ - -/DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) -}

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Patch set updated for coreboot: x86: link romstage like the other architectures
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510 -gerrit commit 9889ad18a5bd1e62529b04b52fbe1006d5722416 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:06:05 2015 -0500 x86: link romstage like the other architectures All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 23a24f2..8868a3f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */ +#include <rules.h> + PHDRS { to_load PT_LOAD; } +#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..9c44b13 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif +romstage-y += program.ld ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y)

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coreboot-gerrit September 2015