coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: linking: move romstage and bootblock to use program.ld
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509 -gerrit commit 67f9dfe44f7b57365c53aec337f42c5a6d411848 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:09:49 2015 -0500 linking: move romstage and bootblock to use program.ld Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 12 +++++----- src/lib/Makefile.inc | 4 ++-- src/lib/bootblock.ld | 51 --------------------------------------- src/lib/romstage.ld | 64 ------------------------------------------------- 4 files changed, 8 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 3b3ff6d..1a38256 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -103,24 +103,24 @@ #endif /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */ -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ - _ = ASSERT(_ebootblock - _bootblock <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ - INCLUDE "lib/bootblock.bootblock.ld" + INCLUDE "lib/program.bootblock.ld" #else #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ . += sz; #endif -#ifdef __ROMSTAGE__ +#if ENV_ROMSTAGE #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ - _ = ASSERT(_eromstage - _romstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/romstage.romstage.ld" + INCLUDE "lib/program.romstage.ld" #else #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index cd2b70a..4aa6bf8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -194,8 +194,8 @@ secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock and romstage use custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well -bootblock-y += bootblock.ld -romstage-y += romstage.ld +bootblock-y += program.ld +romstage-y += program.ld endif ramstage-y += program.ld diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld deleted file mode 100644 index 42e6d64..0000000 --- a/src/lib/bootblock.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.bootblock . : { - _program = .; - _bootblock = .; - *(.text._start); - *(.text.stage_entry); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; - _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; - _ebootblock = .; - _eprogram = .; -} : to_load = 0xff - -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - *(.MIPS.*) -} diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld deleted file mode 100644 index ba154ef..0000000 --- a/src/lib/romstage.ld +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _romstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - . = ALIGN(8); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - PROVIDE(_preram_cbmem_console = .); - PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _eromstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

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Patch set updated for coreboot: x86: link ramstage like the other architectures
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508 -gerrit commit e87704b1108d0154fe76e5f6b45615ed83594af1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 10:19:05 2015 -0500 x86: link ramstage like the other architectures All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 24 +++--------------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld new file mode 100644 index 0000000..dd6cb27 --- /dev/null +++ b/src/arch/x86/include/arch/header.ld @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(_start) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index c9b2f17..0d329db 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -1,25 +1,7 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -ENTRY(_start) - -PHDRS -{ - to_load PT_LOAD; -} +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = CONFIG_RAMBASE; - - INCLUDE "lib/program.ramstage.ld" - - _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) }

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New patch to review for coreboot: verstage: use common program.ld for linking
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11516 -gerrit commit a7a39e52530ea4f465a0bdd76fff655f54e56774 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 11:08:02 2015 -0500 verstage: use common program.ld for linking There's no reason to have a separate verstage.ld now that there is a unified stage linking strategy. Moreover verstage support is throughout the code base as it is so bring in those link script macros into the common memlayout.h as that removes one more specific thing a board/chipset needs to do in order to turn on verstage. BUG=chrome-os-partner:44827 BRANCH=None TEST=None Change-Id: I1195e06e06c1f81a758f68a026167689c19589dd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 27 ++++++++++ src/lib/Makefile.inc | 1 + src/soc/broadcom/cygnus/include/soc/memlayout.ld | 1 - src/soc/imgtec/pistachio/include/soc/memlayout.ld | 1 - src/soc/marvell/bg4cd/include/soc/memlayout.ld | 1 - src/soc/nvidia/tegra124/include/soc/memlayout.ld | 1 - .../tegra132/include/soc/memlayout_vboot2.ld | 1 - .../tegra210/include/soc/memlayout_vboot2.ld | 1 - src/soc/qualcomm/ipq806x/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 - .../samsung/exynos5250/include/soc/memlayout.ld | 1 - src/vendorcode/google/chromeos/memlayout.h | 54 -------------------- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 2 - src/vendorcode/google/chromeos/vboot2/verstage.ld | 58 ---------------------- 14 files changed, 28 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1a38256..02f67db 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -139,6 +139,33 @@ . += sz; #endif +/* Careful: required work buffer size depends on RW properties such as key size + * and algorithm -- what works for you might stop working after an update. Do + * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ +#define VBOOT2_WORK(addr, size) \ + REGION(vboot2_work, addr, size, 16) \ + _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); + +#if ENV_VERSTAGE + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + _ = ASSERT(_eprogram - _program <= sz, \ + STR(Verstage exceeded its allotted size! (sz))); \ + INCLUDE "lib/program.verstage.ld" + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) +#else + #define VERSTAGE(addr, sz) \ + SET_COUNTER(verstage, addr) \ + . += sz; + + #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) +#endif + +#define WATCHDOG_TOMBSTONE(addr, size) \ + REGION(watchdog_tombstone, addr, size, 4) \ + _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); + #if ENV_RAMSTAGE || ENV_ROMSTAGE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 464d631..d8cd1d8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -199,6 +199,7 @@ endif romstage-y += program.ld ramstage-y += program.ld +verstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld index 5e149b4..237ffc6 100644 --- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld +++ b/src/soc/broadcom/cygnus/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 366b20a..59e3017 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld index 15c09d9..45835e2 100644 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 2312cc9..561833d 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld index 0f98fd2..a8164a9 100644 --- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld index c140e01..dee6798 100644 --- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld +++ b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld index cf417ba..ad0977a 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq806x/include/soc/memlayout.ld @@ -19,7 +19,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 0b75932..b96923e 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/soc/samsung/exynos5250/include/soc/memlayout.ld b/src/soc/samsung/exynos5250/include/soc/memlayout.ld index 3b5b034..4469078 100644 --- a/src/soc/samsung/exynos5250/include/soc/memlayout.ld +++ b/src/soc/samsung/exynos5250/include/soc/memlayout.ld @@ -18,7 +18,6 @@ */ #include <memlayout.h> -#include <vendorcode/google/chromeos/memlayout.h> #include <arch/header.ld> diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h deleted file mode 100644 index e86246f..0000000 --- a/src/vendorcode/google/chromeos/memlayout.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file contains macro definitions for memlayout.ld linker scripts. */ - -#ifndef __CHROMEOS_MEMLAYOUT_H -#define __CHROMEOS_MEMLAYOUT_H - -/* Careful: required work buffer size depends on RW properties such as key size - * and algorithm -- what works for you might stop working after an update. Do - * NOT lower the asserted minimum without consulting vboot devs (rspangler)! */ -#define VBOOT2_WORK(addr, size) \ - REGION(vboot2_work, addr, size, 16) \ - _ = ASSERT(size >= 12K, "vboot2 work buffer must be at least 12K!"); - -#ifdef __VERSTAGE__ - #define VERSTAGE(addr, sz) \ - SET_COUNTER(verstage, addr) \ - _ = ASSERT(_eprogram - _program <= sz, \ - STR(Verstage exceeded its allotted size! (sz))); \ - INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld" -#else - #define VERSTAGE(addr, sz) \ - SET_COUNTER(verstage, addr) \ - . += sz; -#endif - -#ifdef __VERSTAGE__ - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) -#else - #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) ROMSTAGE(addr, size) -#endif - -#define WATCHDOG_TOMBSTONE(addr, size) \ - REGION(watchdog_tombstone, addr, size, 4) \ - _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); - -#endif /* __CHROMEOS_MEMLAYOUT_H */ diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index b805993..21613ba 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -42,8 +42,6 @@ romstage-y += vboot_handoff.c common.c ramstage-y += common.c -verstage-y += verstage.ld - ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) VB_FIRMWARE_ARCH := $(ARCHDIR-$(ARCH-verstage-y)) else diff --git a/src/vendorcode/google/chromeos/vboot2/verstage.ld b/src/vendorcode/google/chromeos/vboot2/verstage.ld deleted file mode 100644 index fcb8af8..0000000 --- a/src/vendorcode/google/chromeos/vboot2/verstage.ld +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _verstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _everstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

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New patch to review for coreboot: stash
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11515 -gerrit commit 3db4663b1607b434292e752eba33230a7d8487b4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 10:27:12 2015 -0500 stash Change-Id: I17e5e8e4d8a541bb665b8b6d08ae43ed24e9d4fe --- src/vendorcode/google/chromeos/memlayout.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/memlayout.h b/src/vendorcode/google/chromeos/memlayout.h index 29434bd..e86246f 100644 --- a/src/vendorcode/google/chromeos/memlayout.h +++ b/src/vendorcode/google/chromeos/memlayout.h @@ -31,13 +31,13 @@ #ifdef __VERSTAGE__ #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ - _ = ASSERT(_everstage - _verstage <= sz, \ + SET_COUNTER(verstage, addr) \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Verstage exceeded its allotted size! (sz))); \ INCLUDE "vendorcode/google/chromeos/vboot2/verstage.verstage.ld" #else #define VERSTAGE(addr, sz) \ - SET_COUNTER(VERSTAGE, addr) \ + SET_COUNTER(verstage, addr) \ . += sz; #endif

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Patch set updated for coreboot: rules.h: add fall through where no ENV_<STAGE> is set
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513 -gerrit commit 86d35596353ff2330aa36e3dbac653273a51186e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 16:28:15 2015 -0500 rules.h: add fall through where no ENV_<STAGE> is set There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/rules.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/include/rules.h b/src/include/rules.h index 523031a..2e7f88f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,13 +63,23 @@ #define ENV_SECMON 0 #define ENV_VERSTAGE 1 -#else +#elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 + +#else +/* Default case of nothing set for random blob generation using + * create_class_compiler that isn't bound to a stage. */ +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #endif /* For romstage and ramstage always build with simple device model, ie.

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Patch set updated for coreboot: x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11503 -gerrit commit f4592227f29a2ef48f049c40725650ce90b4a2c3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 11:01:17 2015 -0500 x86: don't create MAINBOARDDIR/romstage.inc for !ROMCC boards Previously, the x86 romstage build process was unconditionally creating a romstage.inc and adding it to crt0s. This step is inherently not necessary in the !ROMCC case becaue the romstage.inc was created by the compiler outputting assembler. That means MAINBOARDDIR/romstage.c is truly a C environment that requires some sort of assembler stub to call into (cache_as_ram.inc from the chipset dirs). Therefore, remove this processing. The result is that MAINBOARDDIR/romstage.c can use the normal build steps in creating an object and linking. The layout of romstage.elf will change but that's only from a symbol perspective. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built multitude of boards. Compared readelf -e output. Change-Id: I9b8079caaaa55e3ae20d3db4c9b8be04cdc41ab7 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index cf69868..8d07603 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -125,13 +125,19 @@ endif crt0s += $(cpu_incs-y) -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc +ifneq ($(CONFIG_ROMCC),y) + +romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -ifeq ($(CONFIG_ROMCC),y) +else # CONFIG_ROMCC == y + +# This order matters. The mainboards requiring ROMCC need their mainboard +# code to follow the prior crt0s files for program flow control. The +# romstage.inc from the MAINBOARDDIR is implicitly main() for romstage +# because of the instruction sequen fall-through. +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc crt0s += $(src)/arch/x86/crt0_romcc_epilogue.inc -endif -ifeq ($(CONFIG_ROMCC),y) ifeq ($(CONFIG_MMX),y) ifeq ($(CONFIG_SSE),y) ROMCCFLAGS := -mcpu=p4 -O2 # MMX, SSE @@ -156,17 +162,7 @@ $(objcbfs)/romstage%.elf: $(objcbfs)/romstage%.debug $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" $(ROMCC) -c -S $(ROMCCFLAGS) -D__ROMSTAGE__ -D__PRE_RAM__ -I. $(CPPFLAGS_romstage) $< -o $@ -else -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h - @printf " CC romstage.inc\n" - $(CC_romstage) $(CPPFLAGS_romstage) $(CFLAGS_romstage) -MMD -D__ROMSTAGE__ -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $< -o $@ - -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - @printf " POST romstage.inc\n" - sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ - -e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp - mv $@.tmp $@ endif romstage-srcs += $(objgenerated)/crt0.S

1 0

Patch set updated for coreboot: linking: lay the groundwork for a unified linking approach
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11507 -gerrit commit ff0bc7882fb8b354e72e194a63eb2a8d634b6926 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 22:49:36 2015 -0500 linking: lay the groundwork for a unified linking approach Though coreboot started as x86 only, the current approach to x86 linking is out of the norm with respect to other architectures. To start alleviating that the way ramstage is linked is partially unified. A new file, program.ld, was added to provide a common way to link stages by deferring to per-stage architectural overrides. The previous ramstage.ld is no longer required. Note that this change doesn't handle RELOCATABLE_RAMSTAGE because that is handled by rmodule.ld. Future convergence can be achieved, but for the time being that's being left out. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Change-Id: I5d689bfa7e0e9aff3a148178515ef241b5f70661 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/memlayout.h | 25 +++++++ src/arch/x86/ramstage.ld | 2 +- src/include/memlayout.h | 126 ++++++++++++++++++++++++++++++++-- src/lib/Makefile.inc | 3 +- src/lib/program.ld | 67 ++++++++++++++++++ src/lib/ramstage.ld | 115 ------------------------------- 7 files changed, 218 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8311b11..23a24f2 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -289,7 +289,7 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-srcs += $(src)/arch/x86/ramstage.ld +ramstage-y += ramstage.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h new file mode 100644 index 0000000..54b8b4a --- /dev/null +++ b/src/arch/x86/include/arch/memlayout.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __ARCH_MEMLAYOUT_H +#define __ARCH_MEMLAYOUT_H + +/* Currently empty to satisfy common arch requirements. */ + +#endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 5fcbbb6..c9b2f17 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -19,7 +19,7 @@ SECTIONS { . = CONFIG_RAMBASE; - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); } diff --git a/src/include/memlayout.h b/src/include/memlayout.h index a529628..3b3ff6d 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -22,10 +22,41 @@ #ifndef __MEMLAYOUT_H #define __MEMLAYOUT_H +#include <rules.h> #include <arch/memlayout.h> +/* Macros that the architecture can override. */ +#ifndef ARCH_POINTER_ALIGN_SIZE +#define ARCH_POINTER_ALIGN_SIZE 8 +#endif + +#ifndef ARCH_CACHELINE_ALIGN_SIZE +#define ARCH_CACHELINE_ALIGN_SIZE 64 +#endif + +#ifndef ARCH_FIRST_TEXT +#define ARCH_FIRST_TEXT +#endif + +/* Default to data as well as bss. */ +#ifndef ARCH_STAGE_HAS_DATA_SECTION +#define ARCH_STAGE_HAS_DATA_SECTION 1 +#endif + +#ifndef ARCH_STAGE_HAS_BSS_SECTION +#define ARCH_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Default is that currently ramstage and smm only has a heap. */ +#ifndef ARCH_STAGE_HAS_HEAP_SECTION +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) +#endif + #define STR(x) #x +#define ALIGN_COUNTER(align) \ + . = ALIGN(align); + #define SET_COUNTER(name, addr) \ _ = ASSERT(. <= addr, STR(name overlaps the previous region!)); \ . = addr; @@ -34,6 +65,9 @@ SET_COUNTER(name, addr) \ _##name = .; +#define SYMBOL_CURRENT_LOC(name) \ + _##name = .; + #define REGION(name, addr, size, expected_align) \ SYMBOL(name, addr) \ _ = ASSERT(. == ALIGN(expected_align), \ @@ -58,7 +92,7 @@ /* TODO: This only works if you never access CBFS in romstage before RAM is up! * If you need to change that assumption, you have some work ahead of you... */ -#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__) +#if defined(__PRE_RAM__) && !ENV_ROMSTAGE #define PRERAM_CBFS_CACHE(addr, size) CBFS_CACHE(addr, size) #define POSTRAM_CBFS_CACHE(addr, size) \ REGION(unused_cbfs_cache, addr, size, 4) @@ -93,16 +127,100 @@ . += sz; #endif -#ifdef __RAMSTAGE__ +#if ENV_RAMSTAGE #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ - _ = ASSERT(_eramstage - _ramstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/ramstage.ramstage.ld" + INCLUDE "lib/program.ramstage.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ . += sz; #endif +#if ENV_RAMSTAGE || ENV_ROMSTAGE +#define CBMEM_INIT_HOOKS \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ + KEEP(*(.rodata.cbmem_init_hooks)); \ + SYMBOL_CURRENT_LOC(ecbmem_init_hooks) +#else +#define CBMEM_INIT_HOOKS +#endif + +#if ENV_RAMSTAGE +#define DRIVERS_RODATA \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(pci_drivers) \ + KEEP(*(.rodata.pci_driver)); \ + SYMBOL_CURRENT_LOC(epci_drivers) \ + POINTER_ALIGN \ + SYMBOL_CURRENT_LOC(cpu_drivers) \ + KEEP(*(.rodata.cpu_driver)); \ + SYMBOL_CURRENT_LOC(ecpu_drivers) +#else +#define DRIVERS_RODATA +#endif + +#define BEGIN_SECTION(name, align) \ + .##name : { \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(name) + +#define END_SECTION(name, align) \ + ALIGN_COUNTER(align) \ + SYMBOL_CURRENT_LOC(e##name) \ + } + +#if ARCH_STAGE_HAS_DATA_SECTION +#ifdef __PRE_RAM__ +/* Provide these symbols in PRE_RAM environments if not already provided. */ +#define DATA_EXTRA \ + PROVIDE(_preram_cbmem_console = .); \ + PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); +#elif ENV_RAMSTAGE +#define DATA_EXTRA \ + SYMBOL_CURRENT_LOC(bs_init_begin) \ + KEEP(*(.bs_init)); \ + LONG(0); \ + LONG(0); \ + SYMBOL_CURRENT_LOC(ebs_init_begin) +#else +#define DATA_EXTRA +#endif + +#define DATA_SECTION \ + BEGIN_SECTION(data, ARCH_CACHELINE_ALIGN_SIZE) \ + *(.data); \ + *(.data.*); \ + DATA_EXTRA \ + END_SECTION(data, ARCH_POINTER_ALIGN_SIZE) +#else +#define DATA_SECTION +#endif + +#if ARCH_STAGE_HAS_BSS_SECTION +#define BSS_SECTION \ + BEGIN_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) \ + *(.bss) \ + *(.bss.*) \ + *(.sbss) \ + *(.sbss.*) \ + END_SECTION(bss, ARCH_POINTER_ALIGN_SIZE) +#else +#define BSS_SECTION +#endif + +#if ARCH_STAGE_HAS_HEAP_SECTION +#define HEAP_SECTION \ + BEGIN_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) \ + . += CONFIG_HEAP_SIZE ; \ + END_SECTION(heap, ARCH_POINTER_ALIGN_SIZE) +#else +#define HEAP_SECTION +#endif + +#define POINTER_ALIGN ALIGN_COUNTER(ARCH_POINTER_ALIGN_SIZE) + #endif /* __MEMLAYOUT_H */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8597667..cd2b70a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -197,7 +197,8 @@ ifneq ($(CONFIG_ARCH_X86),y) bootblock-y += bootblock.ld romstage-y += romstage.ld endif -ramstage-y += ramstage.ld + +ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c diff --git a/src/lib/program.ld b/src/lib/program.ld new file mode 100644 index 0000000..4900d3e --- /dev/null +++ b/src/lib/program.ld @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +BEGIN_SECTION(text, 1) + SYMBOL_CURRENT_LOC(program) + ARCH_FIRST_TEXT + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + POINTER_ALIGN + CBMEM_INIT_HOOKS + DRIVERS_RODATA + *(.rodata); + *(.rodata.*); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(etext) +END_SECTION(text, 1) : to_load + +#if ENV_RAMSTAGE && IS_ENABLED(CONFIG_COVERAGE) +BEGIN_SECTION(ctors, 0x100) + SYMBOL_CURRENT_LOC(__CTOR_LIST__) + KEEP(*(.ctors)); + LONG(0); + LONG(0); + SYMBOL_CURRENT_LOC(__CTOR_END__) +END_SECTION(ctors, 1) +#endif + +/* Include data, bss, and heap in that order. Not defined for all stages. */ +DATA_SECTION +BSS_SECTION +HEAP_SECTION +SYMBOL_CURRENT_LOC(eprogram) + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.comment.*) + *(.note) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld deleted file mode 100644 index b224827..0000000 --- a/src/lib/ramstage.ld +++ /dev/null @@ -1,115 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -/* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ -.text : { - _program = .; - _ramstage = .; - _text = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); - . = ALIGN(16); - _etext = .; -} : to_load - -#if IS_ENABLED(CONFIG_COVERAGE) -.ctors : { - . = ALIGN(0x100); - __CTOR_LIST__ = .; - KEEP(*(.ctors)); - LONG(0); - LONG(0); - __CTOR_END__ = .; -} -#endif - -/* TODO: align data sections to cache lines? (is that really useful?) */ -.rodata : { - _rodata = .; - . = ALIGN(8); - - /* If any changes are made to the driver start/symbols or the - * section names the equivalent changes need to made to - * rmodule.ld. */ - _pci_drivers = . ; - KEEP(*(.rodata.pci_driver)); - _epci_drivers = . ; - _cpu_drivers = . ; - KEEP(*(.rodata.cpu_driver)); - _ecpu_drivers = . ; - _bs_init_begin = .; - KEEP(*(.bs_init)); - LONG(0); - LONG(0); - _bs_init_end = .; - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(8); - - _erodata = .; -} - -.data : { - /* Move to different cache line to avoid false sharing with .rodata. */ - . = ALIGN(64); /* May not be actual line size, not that important. */ - _data = .; - *(.data) - *(.data.*) - _edata = .; -} - -.bss . : { - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; -} - -.heap . : { - _heap = .; - /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ - . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); - _eheap = .; - _eramstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ - -/DISCARD/ : { - *(.comment) - *(.note) - *(.note.*) -}

1 0

Patch set updated for coreboot: x86: remove unused sections from romstage.ld
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505 -gerrit commit e31e50d19293590b6f82f9bbb24af6c1ef373c90 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 14:39:39 2015 -0500 x86: remove unused sections from romstage.ld Now that the only source of ELF sections for romstage are from directly included .inc files or ROMCC generated inc files the subsection globs can be removed. i.e. Remove .rom.data.* and .rom.text.* listings. Lastly, put the .rom.data section directly after the .rom.text. They are by definition read-only and they are generated from the same place. BUG=chrome-os-partner:44827 BRANCH=None TEST=Spot checked !ROMCC and ROMCC boards. Confirmed only .rom.text .rom.data sections exist. Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/romstage.ld | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index 951ca65..cc0142e 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -26,17 +26,15 @@ SECTIONS .rom . : { _rom = .; *(.rom.text); - *(.rom.text.*); + *(.rom.data); *(.text); *(.text.*); - *(.rom.data); . = ALIGN(4); _cbmem_init_hooks = .; KEEP(*(.rodata.cbmem_init_hooks)); _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); - *(.rom.data.*); . = ALIGN(16); _erom = .; }

1 0

Patch set updated for coreboot: x86: add rosmtage.S to bind program flow and ordering
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504 -gerrit commit e0ea8950fcea9297e3a57e9bfb2c488d768a879c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 11:29:28 2015 -0500 x86: add rosmtage.S to bind program flow and ordering The build system was previously determining the flow of the romstage code by the order of files added to the crt0s make variable. Those files were then concatenated together, and the resulting file was added to the build dependencies for romstage proper. Now romstage.S is added that can be built using the default object file rules. The generated romstage.inc is pulled in by way of an #include in the newly added romstage.S. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. compared readelf -e output. Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 26 +++++++++++++------------- src/arch/x86/romstage.S | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8d07603..8311b11 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -crt0s = $(src)/arch/x86/prologue.inc romstage-srcs += $(src)/arch/x86/romstage.ld -crt0s += $(src)/cpu/x86/32bit/entry32.inc romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld -crt0s += $(src)/cpu/x86/fpu_enable.inc -ifeq ($(CONFIG_SSE),y) -crt0s += $(src)/cpu/x86/sse_enable.inc -endif +# Chipset specific assembly stubs in the romstage program flow. Certain +# boards have more than one assembly stub so collect those and put them +# into a single generated file. +crt0s = $(cpu_incs-y) + +$(objgenerated)/romstage.inc: $$(crt0s) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ -crt0s += $(cpu_incs-y) +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated romstage.inc is a proper +# dependency. +romstage-y += romstage.S +$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc ifneq ($(CONFIG_ROMCC),y) @@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/ endif -romstage-srcs += $(objgenerated)/crt0.S - romstage-libs ?= ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) @@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ -$(objgenerated)/crt0.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ - # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S new file mode 100644 index 0000000..b19b954 --- /dev/null +++ b/src/arch/x86/romstage.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The romstage.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/romstage.inc>

1 0

Patch set updated for coreboot: x86: bootblock: remove linking and program flow from build system
by Aaron Durbin 05 Sep '15

05 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11495 -gerrit commit 9f5ea87a535b6962a74f776d25fc89b8445c8bf5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 00:41:29 2015 -0500 x86: bootblock: remove linking and program flow from build system The build system was previously determining the flow and linking scripts bootblock code by the order of files added to the bootblock_inc bootblock-y variables.Those files were then concatenated together and built by a myriad of make rules. Now bootblock.S and bootblock.ld is added so that bootblock can be built and linked using the default build rules. CHIPSET_BOOTBLOCK_INCLUDE is introduced in order to allow the chipset code to place include files in the path of the bootblock program -- a replacement for the chipset_bootblock_inc make variable. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. Change-Id: Ida4571cbe6eed65e77ade98b8d9ad056353c53f9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 54 +++++++------------------- src/arch/x86/bootblock.S | 51 ++++++++++++++++++++++++ src/arch/x86/bootblock.ld | 29 ++++++++++++++ src/arch/x86/id.inc | 2 + src/cpu/dmp/vortex86ex/Kconfig | 4 ++ src/cpu/dmp/vortex86ex/Makefile.inc | 2 - src/cpu/dmp/vortex86ex/biosdata.inc | 2 +- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 + src/northbridge/via/vx800/Kconfig | 8 ++++ src/northbridge/via/vx800/Makefile.inc | 1 - src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/Makefile.inc | 1 - src/soc/intel/baytrail/Kconfig | 4 ++ src/soc/intel/baytrail/Makefile.inc | 1 - src/soc/intel/baytrail/bootblock/Makefile.inc | 1 - src/soc/intel/braswell/Kconfig | 4 ++ src/soc/intel/braswell/Makefile.inc | 1 - src/soc/intel/braswell/bootblock/Makefile.inc | 1 - src/soc/intel/broadwell/Kconfig | 4 ++ src/soc/intel/broadwell/Makefile.inc | 1 - src/soc/intel/broadwell/bootblock/Makefile.inc | 1 - src/soc/intel/skylake/Kconfig | 4 ++ src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/Makefile.inc | 1 - src/southbridge/nvidia/ck804/Kconfig | 5 +++ src/southbridge/nvidia/ck804/Makefile.inc | 1 - src/southbridge/nvidia/mcp55/Kconfig | 4 ++ src/southbridge/nvidia/mcp55/Makefile.inc | 1 - src/southbridge/sis/sis966/Kconfig | 12 +++++- src/southbridge/sis/sis966/Makefile.inc | 1 - src/southbridge/via/k8t890/Kconfig | 4 ++ src/southbridge/via/k8t890/Makefile.inc | 1 - 32 files changed, 155 insertions(+), 58 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index a9d708d..cf69868 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -67,65 +67,41 @@ CBFS_BASE_ADDRESS=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_CBFS_ ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) -bootblock-srcs += $(src)/arch/x86/failover.ld -bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld -bootblock-srcs += $(src)/cpu/x86/16bit/reset16.ld -bootblock-srcs += $(src)/arch/x86/id.ld -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock-srcs += $(src)/cpu/intel/fit/fit.ld -endif - -# TODO: Why can't this use the real bootblock-y += xxx.S mechanism instead? -bootblock_inc = $(src)/arch/x86/prologue.inc -bootblock_inc += $(src)/cpu/x86/16bit/entry16.inc -bootblock_inc += $(src)/cpu/x86/16bit/reset16.inc -bootblock_inc += $(src)/cpu/x86/32bit/entry32.inc -bootblock_inc += $(src)/arch/x86/id.inc -ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -bootblock_inc += $(src)/cpu/intel/fit/fit.inc -endif -bootblock_inc += $(chipset_bootblock_inc) +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated bootblock.inc is a proper +# dependency. Make the same true for the linker sript. +bootblock-y += bootblock.S +$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc -ifeq ($(CONFIG_SSE),y) -bootblock_inc += $(src)/cpu/x86/sse_enable.inc -endif -bootblock_inc += $(objgenerated)/bootblock.inc -bootblock_inc += $(src)/arch/x86/walkcbfs.S +bootblock-y += bootblock.ld +$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOTBLOCK__ endif -$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) +# This is a hack in case there are no per chipset linker files. +$(objgenerated)/empty: + touch $@ + +$(objgenerated)/bootblock.ld: $$(filter %.ld,$$(bootblock-objs)) $(objgenerated)/empty @printf " GEN $(subst $(obj)/,,$(@))\n" cat $^ >> $@.tmp mv $@.tmp $@ -$(objgenerated)/bootblock_inc.S: $$(bootblock_inc) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(bootblock_inc),#include "$(crt0)"\n)' > $@ - -$(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CFLAGS_bootblock) -c -o $@ $< > $(basename $(a)).disasm - -$(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $< -o $@ - $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(obj)/arch/x86/bootblock.bootblock.o $(obj)/arch/x86/bootblock.bootblock.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) - $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_i386 --oformat elf32-i386 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld else - $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld + $(LD_bootblock) -m elf_x86_64 --oformat elf64-x86-64 -static -o $@ -L$(obj) $< -T $(obj)/arch/x86/bootblock.bootblock.ld endif diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S new file mode 100644 index 0000000..7276c7a --- /dev/null +++ b/src/arch/x86/bootblock.S @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <arch/x86/id.inc> + +#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#include <cpu/intel/fit/fit.inc> +#endif + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generated by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions at the beginning of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> + +#include <arch/x86/walkcbfs.S> diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld new file mode 100644 index 0000000..6835430 --- /dev/null +++ b/src/arch/x86/bootblock.ld @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/x86/failover.ld> +#include <cpu/x86/16bit/entry16.ld> +#include <cpu/x86/16bit/reset16.ld> +#include <arch/x86/id.ld> +#if IS_ENABLED(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE) +#include <cpu/intel/fit/fit.ld> +#endif + +/* Include generated .ld files. */ +#include <generated/bootblock.ld> diff --git a/src/arch/x86/id.inc b/src/arch/x86/id.inc index f8aba0b..a3df25e 100644 --- a/src/arch/x86/id.inc +++ b/src/arch/x86/id.inc @@ -1,3 +1,5 @@ +#include <build.h> + .section ".id", "a", @progbits .globl __id_start diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 2c893ac..3bd6c2c 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -77,4 +77,8 @@ config PLL_500_375_33 endchoice +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "cpu/dmp/vortex86ex/chipset_bootblock.inc" + endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 7924ca4..15ea4ea 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -23,8 +23,6 @@ subdirs-y += ../../x86/lapic subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata.inc -chipset_bootblock_inc += $(src)/cpu/dmp/vortex86ex/biosdata_ex.inc bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc index 5e6a70f..4f408b4 100644 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ b/src/cpu/dmp/vortex86ex/biosdata.inc @@ -37,7 +37,7 @@ .section ".dmp_kbd_fw_part1", "a", @progbits - #include "src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc" + #include "dmp_kbd_fw_part1.inc" .previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc new file mode 100644 index 0000000..bdcda1d --- /dev/null +++ b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc @@ -0,0 +1,2 @@ +#include "biosdata.inc" +#include "biosdata_ex.inc" diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..d7d5349 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -3,3 +3,11 @@ config NORTHBRIDGE_VIA_VX800 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT + +if NORTHBRIDGE_VIA_VX800 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx800/romstrap.inc" + +endif diff --git a/src/northbridge/via/vx800/Makefile.inc b/src/northbridge/via/vx800/Makefile.inc index 90ab0af..d3c4c7b 100644 --- a/src/northbridge/via/vx800/Makefile.inc +++ b/src/northbridge/via/vx800/Makefile.inc @@ -25,7 +25,6 @@ ramstage-y += vga.c ramstage-y += lpc.c ramstage-y += ide.c -chipset_bootblock_inc += $(src)/northbridge/via/vx800/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 617074f..335c265 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -42,4 +42,8 @@ config VGA_BIOS_ID string default "1106,7122" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "northbridge/via/vx900/romstrap.inc" + endif diff --git a/src/northbridge/via/vx900/Makefile.inc b/src/northbridge/via/vx900/Makefile.inc index 6178c11..e761f90 100644 --- a/src/northbridge/via/vx900/Makefile.inc +++ b/src/northbridge/via/vx900/Makefile.inc @@ -46,7 +46,6 @@ ramstage-y += lpc.c ramstage-y += ./../../../drivers/pc80/vga/vga_io.c -chipset_bootblock_inc += $(src)/northbridge/via/vx900/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..921f568 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -171,4 +171,8 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/baytrail/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 7417526..e8c5022 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc deleted file mode 100644 index 3a40251..0000000 --- a/src/soc/intel/baytrail/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4c9c8aa..ab99a08 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -198,4 +198,8 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/braswell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 9bf6cb2..755c15a 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc deleted file mode 100644 index 17d1ee8..0000000 --- a/src/soc/intel/braswell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 30c0093..c2db2a1 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -272,4 +272,8 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/broadwell/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 4b14ff8..ca295fc 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc deleted file mode 100644 index 2ca5a45..0000000 --- a/src/soc/intel/broadwell/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index d53e67e..843cb8a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -200,4 +200,8 @@ config UART_DEBUG select DRIVERS_UART_8250MEM select DRIVERS_UART_8250MEM_32 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index defb945..2e119a1 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -1,6 +1,5 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) -subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode diff --git a/src/soc/intel/skylake/bootblock/Makefile.inc b/src/soc/intel/skylake/bootblock/Makefile.inc deleted file mode 100644 index a31f588..0000000 --- a/src/soc/intel/skylake/bootblock/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -chipset_bootblock_inc += $(src)/soc/intel/skylake/bootblock/timestamp.inc diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 4126355..42dce07 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -41,4 +41,9 @@ config CK804_NUM config HPET_MIN_TICKS hex default 0xfa + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/ck804/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc index de1162a..69dd4b2 100644 --- a/src/southbridge/nvidia/ck804/Makefile.inc +++ b/src/southbridge/nvidia/ck804/Makefile.inc @@ -21,7 +21,6 @@ romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_smbus.c -chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index 89aa452..666d3f8 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -42,4 +42,8 @@ config MCP55_PCI_E_X_3 int default 4 +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/nvidia/mcp55/romstrap.inc" + endif diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index fb9c3fb..74ef14c 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -24,7 +24,6 @@ ifeq ($(CONFIG_MCP55_USE_AZA),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif -chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig index 390589c..20f3bff 100644 --- a/src/southbridge/sis/sis966/Kconfig +++ b/src/southbridge/sis/sis966/Kconfig @@ -4,10 +4,18 @@ config SOUTHBRIDGE_SIS_SIS966 select HAVE_USBDEBUG select HAVE_HARD_RESET +if SOUTHBRIDGE_SIS_SIS966 + config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966 + default "southbridge/sis/sis966/bootblock.c" config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_SIS_SIS966 + default 0xfef00000 + +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/sis/sis966/romstrap.inc" + +endif diff --git a/src/southbridge/sis/sis966/Makefile.inc b/src/southbridge/sis/sis966/Makefile.inc index 71fff02..e703e1f 100644 --- a/src/southbridge/sis/sis966/Makefile.inc +++ b/src/southbridge/sis/sis966/Makefile.inc @@ -15,7 +15,6 @@ ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -chipset_bootblock_inc += $(src)/southbridge/sis/sis966/romstrap.inc bootblock-y += romstrap.ld endif diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..76be0c1 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -51,4 +51,8 @@ config VIDEO_MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "southbridge/via/k8t890/romstrap.inc" + endif # SOUTHBRIDGE_K8T890 diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 18cb5aa..2789499 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -10,7 +10,6 @@ ramstage-y += traf_ctrl.c ramstage-y += error.c ramstage-y += chrome.c -chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc bootblock-y += romstrap.ld endif

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coreboot-gerrit September 2015