coreboot-gerrit September 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: x86: remove unused sections from romstage.ld
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11505 -gerrit commit c4552e5be1e76e36abf5e26d5464b668a795cc29 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 14:39:39 2015 -0500 x86: remove unused sections from romstage.ld Now that the only source of ELF sections for romstage are from directly included .inc files or ROMCC generated inc files the subsection globs can be removed. i.e. Remove .rom.data.* and .rom.text.* listings. Lastly, put the .rom.data section directly after the .rom.text. They are by definition read-only and they are generated from the same place. BUG=chrome-os-partner:44827 BRANCH=None TEST=Spot checked !ROMCC and ROMCC boards. Confirmed only .rom.text .rom.data sections exist. Change-Id: Id17cf95c943103de006c5f3f21a625838ab49929 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/romstage.ld | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index 951ca65..cc0142e 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -26,17 +26,15 @@ SECTIONS .rom . : { _rom = .; *(.rom.text); - *(.rom.text.*); + *(.rom.data); *(.text); *(.text.*); - *(.rom.data); . = ALIGN(4); _cbmem_init_hooks = .; KEEP(*(.rodata.cbmem_init_hooks)); _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); - *(.rom.data.*); . = ALIGN(16); _erom = .; }

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Patch set updated for coreboot: x86: add rosmtage.S to bind program flow and ordering
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11504 -gerrit commit 0a91aeec5940b719a559ef17b347c86144185573 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Sep 3 11:29:28 2015 -0500 x86: add rosmtage.S to bind program flow and ordering The build system was previously determining the flow of the romstage code by the order of files added to the crt0s make variable. Those files were then concatenated together, and the resulting file was added to the build dependencies for romstage proper. Now romstage.S is added that can be built using the default object file rules. The generated romstage.inc is pulled in by way of an #include in the newly added romstage.S. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built vortex, rambi, and some asus boards. compared readelf -e output. Change-Id: Ib1168f9541eaf96651c52d03dc0f60e2489a77bd Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/Makefile.inc | 26 +++++++++++++------------- src/arch/x86/romstage.S | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+), 13 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 00d8d27..fe974ef 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,17 +113,23 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -crt0s = $(src)/arch/x86/prologue.inc romstage-srcs += $(src)/arch/x86/romstage.ld -crt0s += $(src)/cpu/x86/32bit/entry32.inc romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld -crt0s += $(src)/cpu/x86/fpu_enable.inc -ifeq ($(CONFIG_SSE),y) -crt0s += $(src)/cpu/x86/sse_enable.inc -endif +# Chipset specific assembly stubs in the romstage program flow. Certain +# boards have more than one assembly stub so collect those and put them +# into a single generated file. +crt0s = $(cpu_incs-y) + +$(objgenerated)/romstage.inc: $$(crt0s) + @printf " GEN $(subst $(obj)/,,$(@))\n" + printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ -crt0s += $(cpu_incs-y) +# Add the assembly file that pulls in the rest of the dependencies in +# the right order. Make sure the auto generated romstage.inc is a proper +# dependency. +romstage-y += romstage.S +$(obj)/arch/x86/romstage.romstage.o: $(objgenerated)/romstage.inc ifneq ($(CONFIG_ROMCC),y) @@ -165,8 +171,6 @@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/ endif -romstage-srcs += $(objgenerated)/crt0.S - romstage-libs ?= ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) @@ -209,10 +213,6 @@ $(objcbfs)/base_xip.txt: $(obj)/coreboot.pre1 $(objcbfs)/romstage_null.bin || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } mv $@.tmp $@ -$(objgenerated)/crt0.S: $$(crt0s) - @printf " GEN $(subst $(obj)/,,$(@))\n" - printf '$(foreach crt0,$(crt0s),#include "$(crt0)"\n)' > $@ - # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 diff --git a/src/arch/x86/romstage.S b/src/arch/x86/romstage.S new file mode 100644 index 0000000..b19b954 --- /dev/null +++ b/src/arch/x86/romstage.S @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* This file assembles the start of the romstage program by the order of the + * includes. Thus, it's extremely important that one pays very careful + * attention to the order of the includes. */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/32bit/entry32.inc> +#include <cpu/x86/fpu_enable.inc> +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * The romstage.inc is generated based on the requirements of the mainboard. + * For example, for ROMCC boards the MAINBOARDDIR/romstage.c would be + * processed by ROMCC and added. In non-ROMCC boards the chipsets' + * cache-as-ram setup files would be here. + */ +#include <generated/romstage.inc>

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Patch set updated for coreboot: x86: link romstage like the other architectures
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11510 -gerrit commit 5a5e43a3b269a54732b51e30720e043d0cae949c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:06:05 2015 -0500 x86: link romstage like the other architectures All the other architectures are using the memlayout for linking romstage. Use that same method on x86 as well for consistency. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 7 +++-- src/arch/x86/include/arch/header.ld | 6 +++++ src/arch/x86/include/arch/memlayout.h | 13 ++++++++- src/arch/x86/romstage.ld | 50 +++++++++-------------------------- src/cpu/x86/32bit/entry32.ld | 1 - src/lib/Makefile.inc | 4 +-- 6 files changed, 35 insertions(+), 46 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9d3f07f..0b8058f 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,8 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-srcs += $(src)/arch/x86/romstage.ld -romstage-srcs += $(src)/cpu/x86/32bit/entry32.ld +romstage-y += romstage.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -193,11 +192,11 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $$(filter %.ld,$$(romstage-objs)) +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp - cat $^ >> $@.tmp + cat $< >> $@.tmp mv $@.tmp $@ $(objgenerated)/romstage.ld: $(objgenerated)/romstage_null.ld $(objcbfs)/base_xip.txt diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld index dd6cb27..55547ad 100644 --- a/src/arch/x86/include/arch/header.ld +++ b/src/arch/x86/include/arch/header.ld @@ -17,9 +17,15 @@ * Foundation, Inc. */ +#include <rules.h> + PHDRS { to_load PT_LOAD; } +#if ENV_RAMSTAGE ENTRY(_start) +#elif ENV_ROMSTAGE +ENTRY(protected_start) +#endif diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index 54b8b4a..abaa8c7 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -20,6 +20,17 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* Currently empty to satisfy common arch requirements. */ +#include <rules.h> + +#if ENV_ROMSTAGE +/* Ensure the binding for .rom sections comes prior to all other text. */ +#define ARCH_FIRST_TEXT \ + *(.rom.text); \ + *(.rom.data); + +/* No .data or .bss in romstage. Cache as ram is handled separately. */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142e..9c44b13 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { - _car_data_start = .; + SYMBOL_CURRENT_LOC(car_data_start) #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); - _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage diff --git a/src/cpu/x86/32bit/entry32.ld b/src/cpu/x86/32bit/entry32.ld deleted file mode 100644 index 471b5f7..0000000 --- a/src/cpu/x86/32bit/entry32.ld +++ /dev/null @@ -1 +0,0 @@ -ENTRY(protected_start) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 4aa6bf8..464d631 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -192,12 +192,12 @@ smm-y += halt.c secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) -# X86 bootblock and romstage use custom ldscripts that are all glued together, +# X86 bootblock uses custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well bootblock-y += program.ld -romstage-y += program.ld endif +romstage-y += program.ld ramstage-y += program.ld ifeq ($(CONFIG_RELOCATABLE_MODULES),y)

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Patch set updated for coreboot: linking: move romstage and bootblock to use program.ld
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11509 -gerrit commit 70f201fa83e6ca04ae550dea52ef2dc884a67fbc Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 12:09:49 2015 -0500 linking: move romstage and bootblock to use program.ld Instead of having separate <stage>.ld files in src/lib one file can be used: program.ld. There's now only one touch point for stage layout. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I4c3e3671d696caa2c7601065a85fab803e86f971 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/memlayout.h | 12 +++++----- src/lib/Makefile.inc | 4 ++-- src/lib/bootblock.ld | 51 --------------------------------------- src/lib/romstage.ld | 64 ------------------------------------------------- 4 files changed, 8 insertions(+), 123 deletions(-) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 3b3ff6d..1a38256 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -103,24 +103,24 @@ #endif /* Careful: 'INCLUDE <filename>' must always be at the end of the output line */ -#ifdef __BOOTBLOCK__ +#if ENV_BOOTBLOCK #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ - _ = ASSERT(_ebootblock - _bootblock <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ - INCLUDE "lib/bootblock.bootblock.ld" + INCLUDE "lib/program.bootblock.ld" #else #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ . += sz; #endif -#ifdef __ROMSTAGE__ +#if ENV_ROMSTAGE #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ - _ = ASSERT(_eromstage - _romstage <= sz, \ + _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/romstage.romstage.ld" + INCLUDE "lib/program.romstage.ld" #else #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index cd2b70a..4aa6bf8 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -194,8 +194,8 @@ secmon-y += halt.c ifneq ($(CONFIG_ARCH_X86),y) # X86 bootblock and romstage use custom ldscripts that are all glued together, # so we need to exclude it here or it would pick these up as well -bootblock-y += bootblock.ld -romstage-y += romstage.ld +bootblock-y += program.ld +romstage-y += program.ld endif ramstage-y += program.ld diff --git a/src/lib/bootblock.ld b/src/lib/bootblock.ld deleted file mode 100644 index 42e6d64..0000000 --- a/src/lib/bootblock.ld +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.bootblock . : { - _program = .; - _bootblock = .; - *(.text._start); - *(.text.stage_entry); - KEEP(*(.id)); - *(.text); - *(.text.*); - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - *(.bss); - *(.bss.*); - *(.sbss); - *(.sbss.*); - _preram_cbmem_console = DEFINED(_preram_cbmem_console) ? _preram_cbmem_console : 0; - _epreram_cbmem_console = DEFINED(_epreram_cbmem_console) ? _epreram_cbmem_console : 0; - _ebootblock = .; - _eprogram = .; -} : to_load = 0xff - -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.ARM.*) - *(.MIPS.*) -} diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld deleted file mode 100644 index ba154ef..0000000 --- a/src/lib/romstage.ld +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -/* This file is included inside a SECTIONS block */ - -.text . : { - _program = .; - _romstage = .; - *(.text._start); - *(.text.stage_entry); - *(.text); - *(.text.*); -} : to_load - -.data . : { - . = ALIGN(8); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - *(.data); - *(.data.*); - PROVIDE(_preram_cbmem_console = .); - PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); - . = ALIGN(8); -} - -.bss . : { - . = ALIGN(8); - _bss = .; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - _ebss = .; - _eromstage = .; - _eprogram = .; -} - -/* Discard the sections we don't need/want */ -/DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); -}

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Patch set updated for coreboot: x86: link ramstage like the other architectures
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11508 -gerrit commit 0aeeab0a18974a10ef2bb8fe6a950fc6a9fc4dac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 10:19:05 2015 -0500 x86: link ramstage like the other architectures All the other architectures are using the memlayout for linking ramstage. The last piece to align x86 is to use arch/header.ld and the macros within memlayout.h to automaticaly generate the necessary linker script. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: I012c9b88c178b43bf6a6dde0bab821e066728139 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/include/arch/header.ld | 25 +++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 24 +++--------------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/include/arch/header.ld b/src/arch/x86/include/arch/header.ld new file mode 100644 index 0000000..dd6cb27 --- /dev/null +++ b/src/arch/x86/include/arch/header.ld @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +PHDRS +{ + to_load PT_LOAD; +} + +ENTRY(_start) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index c9b2f17..0d329db 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -1,25 +1,7 @@ -/* - * Memory map: - * - * CONFIG_RAMBASE : text segment - * : rodata segment - * : data segment - * : bss segment - * : stack - * : heap - */ -ENTRY(_start) - -PHDRS -{ - to_load PT_LOAD; -} +#include <memlayout.h> +#include <arch/header.ld> SECTIONS { - . = CONFIG_RAMBASE; - - INCLUDE "lib/program.ramstage.ld" - - _ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) }

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New patch to review for coreboot: x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11524 -gerrit commit 4e9869685f2cb10e9fa6d4740f0bdb49d55ebcea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:45:18 2015 -0500 x86: link ramstage the same way regardless of RELOCATABLE_RAMSTAGE Previously there were 2 paths in linking ramstage. One was used for RELOCATABLE_RAMSTAGE while the other was fixed location. Now that rmodtool can handle multiple secitons for a single proram segment there's no need for linking ramstage using lib/rmodule.ld. That also means true rmodules don't have symbols required for ramstage purposes so fix memlayout.h. Lastly add default rules for creating rmod files from the known file names and locations. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi. Inspected ramstage.debug as well as rmodules created during the build. Change-Id: I98d249036c27cb4847512ab8bca5ea7b02ce04bd Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 +--------- src/include/memlayout.h | 6 +++--- src/lib/Makefile.inc | 9 ++++++--- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index fc1a7c8..e6b7484 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -276,17 +276,11 @@ ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) -else -$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64)) -endif - # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod cp $< $@ -else +endif ramstage-y += memlayout.ld @@ -294,8 +288,6 @@ $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout. @printf " CC $(subst $(obj)/,,$(@))\n" $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld -endif - $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) diff --git a/src/include/memlayout.h b/src/include/memlayout.h index ef47f6b..82fa73e 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -166,7 +166,7 @@ REGION(watchdog_tombstone, addr, size, 4) \ _ = ASSERT(size == 4, "watchdog tombstones should be exactly 4 byte!"); -#if ENV_RAMSTAGE || ENV_ROMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE || ENV_ROMSTAGE #define CBMEM_INIT_HOOKS \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(cbmem_init_hooks) \ @@ -176,7 +176,7 @@ #define CBMEM_INIT_HOOKS #endif -#if ENV_RAMSTAGE || ENV_RMODULE +#if ENV_RAMSTAGE #define DRIVERS_RODATA \ POINTER_ALIGN \ SYMBOL_CURRENT_LOC(pci_drivers) \ @@ -206,7 +206,7 @@ #define DATA_EXTRA \ PROVIDE(_preram_cbmem_console = .); \ PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); -#elif ENV_RAMSTAGE || ENV_RMODULE +#elif ENV_RAMSTAGE #define DATA_EXTRA \ SYMBOL_CURRENT_LOC(bs_init_begin) \ KEEP(*(.bs_init)); \ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index a89f7d4..f4d8c2c 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -218,9 +218,12 @@ define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map - -$(strip $(1)).rmod: $(strip $(1)) - $$(RMODTOOL) -i $$^ -o $$@ endef endif + +$(objcbfs)/%.debug.rmod: $(objcbfs)/%.debug | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@ + +$(obj)/%.elf.rmod: $(obj)/%.elf | $(RMODTOOL) + $(RMODTOOL) -i $< -o $@

1 0

New patch to review for coreboot: rmodtool: make rmodule parameter section optional
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11523 -gerrit commit 6a7b810eb774ecc72ad7ff341106f443f88707e8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:39:10 2015 -0500 rmodtool: make rmodule parameter section optional There are currently 2 uses for rmodule programs: stand alone programs that are separate from the coreboot stages and a relocatable ramstage. For the ramstage usage there's no reason to require a rmodule parameter section. Therefore make this optional. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built ramstage w/ normal linking (w/o a rmodule parameter section). No error. Change-Id: I5f8a415e86510be9409a28068e3d3a4d0ba8733e Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- util/cbfstool/rmodule.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index c35eff7..1f41d17 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -344,7 +344,7 @@ static int collect_relocations(struct rmod_context *ctx) static int populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr, - int nsyms, const char *strtab) + int nsyms, const char *strtab, int optional) { int i; Elf64_Sym *syms; @@ -360,6 +360,13 @@ populate_sym(struct rmod_context *ctx, const char *sym_name, Elf64_Addr *addr, *addr = syms[i].st_value; return 0; } + + if (optional) { + DEBUG("optional symbol '%s' not found.\n", sym_name); + *addr = 0; + return 0; + } + ERROR("symbol '%s' not found.\n", sym_name); return -1; } @@ -403,17 +410,17 @@ static int populate_program_info(struct rmod_context *ctx) } if (populate_sym(ctx, "_rmodule_params", &ctx->parameters_begin, - nsyms, strtab)) + nsyms, strtab, 1)) return -1; if (populate_sym(ctx, "_ermodule_params", &ctx->parameters_end, - nsyms, strtab)) + nsyms, strtab, 1)) return -1; - if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab)) + if (populate_sym(ctx, "_bss", &ctx->bss_begin, nsyms, strtab, 0)) return -1; - if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab)) + if (populate_sym(ctx, "_ebss", &ctx->bss_end, nsyms, strtab, 0)) return -1; /* Honor the entry point within the ELF header. */

1 0

New patch to review for coreboot: linking: add and use LDFLAGS_common
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11522 -gerrit commit 718bf308e2181e74917391650c94b097831aec60 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Sep 6 10:15:17 2015 -0500 linking: add and use LDFLAGS_common Add an LDFLAGS_common variable and use that for each stage during linking within all the architectures. All the architectures support gc-sections, and as such they should be linking in the same way. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and analyzed the relocatable ramstage. Change-Id: I41fbded54055455889b297b9e8738db4dda0aad0 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/arm/Makefile.inc | 8 ++++---- src/arch/arm64/Makefile.inc | 8 ++++---- src/arch/mips/Makefile.inc | 6 +++--- src/arch/riscv/Makefile.inc | 6 +++--- src/arch/x86/Makefile.inc | 6 +++--- src/cpu/x86/smm/Makefile.inc | 2 +- src/lib/Makefile.inc | 4 ++-- toolchain.inc | 6 ++++++ 8 files changed, 26 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 7a4409e..82ce8b3 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -63,7 +63,7 @@ bootblock-y += clock.c $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -75,7 +75,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group verstage-y += boot.c verstage-y += div0.c @@ -110,7 +110,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -139,6 +139,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index a625c7a..5294b69 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -73,7 +73,7 @@ bootblock-y += memmove.S $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -85,7 +85,7 @@ ifeq ($(CONFIG_ARCH_VERSTAGE_ARM64),y) $(objcbfs)/verstage.debug: $(objgenerated)/libverstage.a $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) $(objgenerated)/libverstage.a --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.verstage.ld verstage-y += boot.c verstage-y += div0.c @@ -125,7 +125,7 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm64.o $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) -nostdlib --gc-sections -static -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -172,7 +172,7 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) -nostdlib --gc-sections -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld + $(LD_ramstage) $(LDFLAGS_ramstage) $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc index e3aff0c..fab8a05 100644 --- a/src/arch/mips/Makefile.inc +++ b/src/arch/mips/Makefile.inc @@ -50,7 +50,7 @@ bootblock-S-ccopts += -undef $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group endif # CONFIG_ARCH_BOOTBLOCK_MIPS @@ -70,7 +70,7 @@ romstage-y += ../../lib/memset.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group endif # CONFIG_ARCH_ROMSTAGE_MIPS @@ -94,6 +94,6 @@ ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group endif # CONFIG_ARCH_RAMSTAGE_MIPS diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 0f3eb0f..5233faa 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -40,7 +40,7 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \ + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) @@ -67,7 +67,7 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) @@ -105,7 +105,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bbbe273..fc1a7c8 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -180,7 +180,7 @@ endif $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage_null.ld --oformat $(romstage-oformat) LANG=C LC_ALL= $(OBJCOPY_romstage) --only-section .illegal_globals $(@) $(objcbfs)/romstage_null.offenders 2>&1 | \ grep -v "Empty loadable segment detected" && \ $(NM_romstage) $(objcbfs)/romstage_null.offenders | grep -q ""; if [ $$? -eq 0 ]; then \ @@ -190,7 +190,7 @@ $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null. $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) $(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" @@ -292,7 +292,7 @@ ramstage-y += memlayout.ld $(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) $(LDFLAGS_ramstage) -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld endif diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 239689e..7b4ad59 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -84,7 +84,7 @@ $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod else # CONFIG_SMM_TSEG $(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) -nostdlib -nostartfiles --gc-sections -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index d8cd1d8..a89f7d4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -205,7 +205,7 @@ ifeq ($(CONFIG_RELOCATABLE_MODULES),y) ramstage-y += rmodule.c romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += rmodule.c -RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic +RMODULE_LDFLAGS := -z defs -Bsymbolic # rmodule_link_rules is a function that should be called with: # (1) the object name to link @@ -216,7 +216,7 @@ RMODULE_LDFLAGS := -nostartfiles --gc-sections --emit-relocs -z defs -Bsymbolic # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(obj)/lib/rmodule.rmodules_$(4).ld | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(obj)/lib/rmodule.rmodules_$(4).ld --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map $(strip $(1)).rmod: $(strip $(1)) diff --git a/toolchain.inc b/toolchain.inc index 195ed77..d143dd7 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -69,6 +69,11 @@ CFLAGS_riscv += CFLAGS_x86_32 += CFLAGS_x86_64 += -mcmodel=large -mno-red-zone +# Set the LDFLAGS for each arch. +LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +$(foreach arch,$(ARCH_SUPPORTED), \ + $(eval LDFLAGS_$(arch):=$(LDFLAGS_common))) + # Some boards only provide 2K stacks, so storing lots of data there leads to # problems. Since C rules don't allow us to statically determine the maximum # stack use, we use 1.5K as heuristic, assuming that we typically have lots @@ -122,6 +127,7 @@ CFLAGS_$(1) = $$(CFLAGS_common) $$(CFLAGS_$(2)) CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) COMPILER_RT_$(1) := $$(COMPILER_RT_$(2)) COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2)) +LDFLAGS_$(1) = $$(LDFLAGS_$(2)) endef # define_class: Allows defining any program as dynamic class and compiler tool

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New patch to review for coreboot: x86: link romstage and ramstage with 1 file
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11521 -gerrit commit bdaffefe0ddf3a7bae7cb7fd4ebadac03c53a8f3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Sep 5 13:31:14 2015 -0500 x86: link romstage and ramstage with 1 file To reduce file clutter merge romstage.ld and ramstage.ld into a single memlayout.ld. The naming is consistent with other architectures and chipsets for their linker script names. The cache-as-ram linking rules are put into a separate file such that other rules can be applied for future verstage support. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built rambi and dmp/vortex86ex. Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2 Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/arch/x86/Makefile.inc | 10 ++++---- src/arch/x86/car.ld | 50 +++++++++++++++++++++++++++++++++++++++ src/arch/x86/memlayout.ld | 42 +++++++++++++++++++++++++++++++++ src/arch/x86/ramstage.ld | 7 ------ src/arch/x86/romstage.ld | 59 ----------------------------------------------- 5 files changed, 97 insertions(+), 71 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 4c88a27..bbbe273 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -113,7 +113,7 @@ endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) -romstage-y += romstage.ld +romstage-y += memlayout.ld # Chipset specific assembly stubs in the romstage program flow. Certain # boards have more than one assembly stub so collect those and put them @@ -192,7 +192,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) $(objgenerated)/romstage.ld $$(roms @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_romstage) --gc-sections -nostdlib -nostartfiles -static -o $@ -L$(obj) $(COMPILER_RT_FLAGS_romstage) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) $(romstage-libs) --no-whole-archive $(COMPILER_RT_romstage) --end-group -T $(objgenerated)/romstage.ld --oformat $(romstage-oformat) -$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/romstage.romstage.ld +$(objgenerated)/romstage_null.ld: $(obj)/arch/x86/memlayout.romstage.ld @printf " GEN $(subst $(obj)/,,$(@))\n" rm -f $@ printf "ROMSTAGE_BASE = 0x0;\n" > $@.tmp @@ -288,11 +288,11 @@ $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod else -ramstage-y += ramstage.ld +ramstage-y += memlayout.ld -$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/ramstage.ramstage.ld +$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(obj)/arch/x86/memlayout.ramstage.ld @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/ramstage.ramstage.ld + $(LD_ramstage) $(CPPFLAGS) --gc-sections -o $@ -L$(obj) $< -T $(obj)/arch/x86/memlayout.ramstage.ld endif diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld new file mode 100644 index 0000000..1724a73 --- /dev/null +++ b/src/arch/x86/car.ld @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + + . = CONFIG_DCACHE_RAM_BASE; + .car.data . (NOLOAD) : { + SYMBOL_CURRENT_LOC(car_data_start) +#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) + TIMESTAMP(., 0x100) +#endif + *(.car.global_data); + POINTER_ALIGN + SYMBOL_CURRENT_LOC(car_data_end) + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) + } + + /* Global variables are not allowed in romstage + * This section is checked during stage creation to ensure + * that there are no global variables present + */ + + . = 0xffffff00; + .illegal_globals . : { + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + } + + _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld new file mode 100644 index 0000000..43c5229 --- /dev/null +++ b/src/arch/x86/memlayout.ld @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + /* + * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively + * like other architectures/chipsets it's not possible because of + * the linking games played during romstage creation by trying + * to find the final landing place in CBFS for XIP. Therefore, + * conditionalize with macros. + */ +#if ENV_RAMSTAGE + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + +#elif ENV_ROMSTAGE + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) + + /* Pull in the cache-as-ram rules. */ + #include "car.ld" +#endif +} diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld deleted file mode 100644 index 0d329db..0000000 --- a/src/arch/x86/ramstage.ld +++ /dev/null @@ -1,7 +0,0 @@ -#include <memlayout.h> -#include <arch/header.ld> - -SECTIONS -{ - RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) -} diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld deleted file mode 100644 index 9c44b13..0000000 --- a/src/arch/x86/romstage.ld +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Advanced Micro Devices, Inc. - * Copyright (C) 2008-2010 coresystems GmbH - * Copyright 2015 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <memlayout.h> -#include <arch/header.ld> - -SECTIONS -{ - /* The 1M size is not allocated. It's just for basic size checking. */ - ROMSTAGE(ROMSTAGE_BASE, 1M) - - . = CONFIG_DCACHE_RAM_BASE; - .car.data . (NOLOAD) : { - SYMBOL_CURRENT_LOC(car_data_start) -#if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - TIMESTAMP(., 0x100) -#endif - *(.car.global_data); - POINTER_ALIGN - SYMBOL_CURRENT_LOC(car_data_end) - - PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) - } - - /* Global variables are not allowed in romstage - * This section is checked during stage creation to ensure - * that there are no global variables present - */ - - . = 0xffffff00; - .illegal_globals . : { - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - } - - _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full"); -}

1 0

Patch set updated for coreboot: rules.h: add fall through where no ENV_<STAGE> is set
by Aaron Durbin 06 Sep '15

06 Sep '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11513 -gerrit commit 91a1abe3ad8df72dfa5b68a276053784a718d19f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Sep 4 16:28:15 2015 -0500 rules.h: add fall through where no ENV_<STAGE> is set There are cases where rules.h can be pulled in, but the usage is not associated with a particular stage. For example, the cpu/ti/am335x build creates an opmap header. That is a case where there is no stage associated with the process. Therefore, provide a case of no ENV_>STAGE> being set. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built a myriad of boards. Analyzed readelf output. Change-Id: Ia9688886d445c961f4a448fc7bfcb28f691609db Signed-off-by: Aaron Durbin <adubin(a)chromium.org> --- src/include/rules.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/include/rules.h b/src/include/rules.h index 523031a..2e7f88f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -63,13 +63,23 @@ #define ENV_SECMON 0 #define ENV_VERSTAGE 1 -#else +#elif defined(__RAMSTAGE__) #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 #define ENV_RAMSTAGE 1 #define ENV_SMM 0 #define ENV_SECMON 0 #define ENV_VERSTAGE 0 + +#else +/* Default case of nothing set for random blob generation using + * create_class_compiler that isn't bound to a stage. */ +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_SECMON 0 +#define ENV_VERSTAGE 0 #endif /* For romstage and ramstage always build with simple device model, ie.

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coreboot-gerrit September 2015