coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: cbfstool: more descriptive variable name
by gerrit＠coreboot.org 26 Aug '15

26 Aug '15

the following patch was just integrated into master: commit 4eb8abeb8570f2dca688f4e2a22697c756404ab2 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Aug 25 12:24:49 2015 +0200 cbfstool: more descriptive variable name "target", for what? It's the offset where the file header of the currently added file will be located, name it as such. Change-Id: I382f08f81991faf660e217566849773d9a7ec227 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11319 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11319 for details. -gerrit

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Patch set updated for coreboot: cbfstool: move cbfs_file header creation further up the call chain
by Patrick Georgi 26 Aug '15

26 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11326 -gerrit commit 2c9c010f374e90e8f5f2834b5c58cced4f1aba49 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Aug 25 13:48:10 2015 +0200 cbfstool: move cbfs_file header creation further up the call chain The header is now created before the "converters" are run. Adding new capabilities (and fields to the header) will happen there, so we're close. Change-Id: I0556df724bd93816b435efff7d931293dbed918f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/cbfstool/cbfs_image.c | 8 ++------ util/cbfstool/cbfs_image.h | 2 +- util/cbfstool/cbfstool.c | 16 +++++++++++++--- 3 files changed, 16 insertions(+), 10 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 84f4be6..8297cf1 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -533,12 +533,13 @@ static int cbfs_add_entry_at(struct cbfs_image *image, int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, const char *name, uint32_t type, uint32_t content_offset, - uint32_t header_size) + void *header, uint32_t header_size) { assert(image); assert(buffer); assert(buffer->data); assert(name); + type = type; assert(!IS_TOP_ALIGNED_ADDRESS(content_offset)); uint32_t entry_type; @@ -607,16 +608,11 @@ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, DEBUG("section 0x%x+0x%x for content_offset 0x%x.\n", addr, addr_next - addr, content_offset); - struct cbfs_file *header = - cbfs_create_file_header(type, buffer->size, name); - if (cbfs_add_entry_at(image, entry, buffer->data, content_offset, header, header_size) == 0) { - free(header); return 0; } - free(header); break; } diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 432ea72..c1df911 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -94,7 +94,7 @@ int cbfs_export_entry(struct cbfs_image *image, const char *entry_name, * Returns 0 on success, otherwise non-zero. */ int cbfs_add_entry(struct cbfs_image *image, struct buffer *buffer, const char *name, uint32_t type, uint32_t content_offset, - uint32_t header_size); + void *header, uint32_t header_size); /* Removes an entry from CBFS image. Returns 0 on success, otherwise non-zero. */ int cbfs_remove_entry(struct cbfs_image *image, const char *name); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 8672362..abb812a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -123,6 +123,7 @@ static int cbfs_add_integer_component(const char *name, uint32_t offset, uint32_t headeroffset) { struct cbfs_image image; + struct cbfs_file *header = NULL; struct buffer buffer; int i, ret = 1; @@ -151,8 +152,11 @@ static int cbfs_add_integer_component(const char *name, offset = convert_to_from_top_aligned(param.image_region, -offset); + header = cbfs_create_file_header(CBFS_COMPONENT_RAW, + buffer.size, name); + uint32_t header_size = cbfs_calculate_file_header_size(name); if (cbfs_add_entry(&image, &buffer, name, CBFS_COMPONENT_RAW, - offset, 0) != 0) { + offset, header, header_size) != 0) { ERROR("Failed to add %llu into ROM image as '%s'.\n", (long long unsigned)u64val, name); goto done; @@ -161,6 +165,7 @@ static int cbfs_add_integer_component(const char *name, ret = 0; done: + free(header); buffer_delete(&buffer); return ret; } @@ -202,9 +207,11 @@ static int cbfs_add_component(const char *filename, return 1; } + struct cbfs_file *header = + cbfs_create_file_header(type, buffer.size, name); uint32_t header_size = cbfs_calculate_file_header_size(name); - if (convert && convert(&buffer, &offset, NULL) != 0) { + if (convert && convert(&buffer, &offset, header) != 0) { ERROR("Failed to parse file '%s'.\n", filename); buffer_delete(&buffer); return 1; @@ -214,13 +221,16 @@ static int cbfs_add_component(const char *filename, offset = convert_to_from_top_aligned(param.image_region, -offset); - if (cbfs_add_entry(&image, &buffer, name, type, offset, header_size) + if (cbfs_add_entry(&image, &buffer, name, type, offset, + header, header_size) != 0) { ERROR("Failed to add '%s' into ROM image.\n", filename); + free(header); buffer_delete(&buffer); return 1; } + free(header); buffer_delete(&buffer); return 0; }

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Patch merged into coreboot/master: crossgcc: rename source file names from gcc-5.2.0/* to binutils-2.25/* in binutils riscv patches
by gerrit＠coreboot.org 26 Aug '15

26 Aug '15

the following patch was just integrated into master: commit 64fc433a567011238a4c1ee886445173a5d8ae56 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Tue Aug 25 13:09:51 2015 -0500 crossgcc: rename source file names from gcc-5.2.0/* to binutils-2.25/* in binutils riscv patches Followup-To: I6f37748b4cf0852d292f8f5156fc27ab8fd481b6 Change-Id: Ib6599b2380b5f2efd92ae78b72b45f3d65681379 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Reviewed-on: http://review.coreboot.org/11329 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Idwer Vollering <vidwer(a)gmail.com> See http://review.coreboot.org/11329 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Move a bunch of code into a function
by gerrit＠coreboot.org 26 Aug '15

26 Aug '15

the following patch was just integrated into master: commit 06e85acb4047142cd00442ce8251d30f3754bef1 Author: zbao <fishbaozi(a)gmail.com> Date: Mon Aug 24 22:08:36 2015 -0400 buildgcc: Move a bunch of code into a function Refactor the code to be better understandable. Change-Id: Ia815a27f7cc83c226a32e87485d712a5fbf4168e Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/11318 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11318 for details. -gerrit

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New patch to review for coreboot: northbridge/intel/gm45/Kconfig: Define IOMMU symbol
by Martin Roth 25 Aug '15

25 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11345 -gerrit commit 9a72eb31b986cfedfa14678414d9439eb4b0a987 Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 25 17:04:59 2015 -0600 northbridge/intel/gm45/Kconfig: Define IOMMU symbol IOMMU needs to be created here, not selected. Selecting it causes errors because it's not created in any locations where the dependencies are met. Change-Id: Ibc5939cd1e297d497bf71b1787d852f7cc09a551 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/northbridge/intel/gm45/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 2374a1f..5c65b57 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_DEBUG_RAM_SETUP select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select IOMMU select VGA select INTEL_EDID select INTEL_GMA_ACPI @@ -40,4 +39,7 @@ config VGA_BIOS_ID string default "8086,2a42" +config IOMMU + def_bool y + endif

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New patch to review for coreboot: hp/dl165_g6_fam10/Kconfig: remove unused QRANK_DIMM_SUPPORT
by Martin Roth 25 Aug '15

25 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11344 -gerrit commit 7086d13d7a761014a2c43507d98afb1294dddea6 Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 25 17:00:04 2015 -0600 hp/dl165_g6_fam10/Kconfig: remove unused QRANK_DIMM_SUPPORT AMD family 10 boards don't use QRANK_DIMM_SUPPORT. Change-Id: Id7e1fba86e2ea1d4d5f5c2e123bd36ad802fd15e Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index ca36aaf..703200d 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select QRANK_DIMM_SUPPORT select MMCONF_SUPPORT_DEFAULT config MAINBOARD_DIR

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New patch to review for coreboot: google/storm/Kconfig: remove select CONSOLE_CBMEM_DUMP_TO_UART
by Martin Roth 25 Aug '15

25 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11343 -gerrit commit 8c9e7b0eb2bd747c366900cdfc8eee1204dbd7ab Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 25 15:27:54 2015 -0600 google/storm/Kconfig: remove select CONSOLE_CBMEM_DUMP_TO_UART This seems like more of a debug option, than something that should be forced to be enabled by the platform. Since it's causing a Kconfig warning, I'm just removing it. The alternative to removing it would be to add dependencies on CONSOLE_CBMEM && !CONSOLE_SERIAL Change-Id: Ifc4e4cbeea08a503c38827dd75e0e2e78e8a5eda Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/storm/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index a86752f..2d97634 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS select SPI_FLASH_SPANSION select SPI_FLASH_STMICRO select DRIVERS_UART - select CONSOLE_CBMEM_DUMP_TO_UART config CHROMEOS select VBOOT_DISABLE_DEV_ON_RECOVERY

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New patch to review for coreboot: intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMER
by Martin Roth 25 Aug '15

25 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11342 -gerrit commit 55e05bf414af031ac5021a95b74e9236e5c58f92 Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 25 14:47:39 2015 -0600 intel/model_2065x/Kconfig: Don't use LAPIC_MONOTONIC_TIMER The LAPIC_MONOTONIC_TIMER symbol doesn't do anything in the code unless UDELAY_LAPIC is selected. Since this chip uses UDELAY_TSC, LAPIC_MONOTONIC_TIMER generates a Kconfig warning and should be removed. Change-Id: I5caa60ca7ab9a24d25c184c85184f9492b453706 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/intel/model_2065x/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 4a85f09..f6d812f 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -19,7 +19,6 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_CPU_INIT #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE - select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string

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New patch to review for coreboot: Allow Tegra210 to use ARCH_ARM64_CPU_CORTEX_A57
by Martin Roth 25 Aug '15

25 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11341 -gerrit commit d6c2a8544e4c8a402a1ab3d423a6398e32f0061a Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 25 14:44:36 2015 -0600 Allow Tegra210 to use ARCH_ARM64_CPU_CORTEX_A57 The Tegra210 uses ARCH_ARM64_CPU_CORTEX_A57, even though it doesn't use ARCH_ARM64. Add the SOC to the depends list to make this valid. Change-Id: I969ed4cd5e3b7dad05b61faa8c619d37a531f842 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/arch/arm64/cpu/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/arm64/cpu/Kconfig b/src/arch/arm64/cpu/Kconfig index 8e12aa7..4dd7e61 100644 --- a/src/arch/arm64/cpu/Kconfig +++ b/src/arch/arm64/cpu/Kconfig @@ -20,9 +20,10 @@ config ARCH_ARM64_CPU_CORTEX_A57 bool default n - depends on ARCH_ARM64 + depends on ARCH_ARM64 || SOC_NVIDIA_TEGRA210 config ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT bool default n - depends on ARCH_ARM64 && ARCH_ARM64_CPU_CORTEX_A57 + depends on ARCH_ARM64 && ARCH_ARM64_CPU_CORTEX_A57 || SOC_NVIDIA_TEGRA210 && ARCH_ARM64_CPU_CORTEX_A57 +

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New patch to review for coreboot: Don't select serirq_continuous_mode when it doesn't exist
by Martin Roth 25 Aug '15

25 Aug '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11340 -gerrit commit 8d39d163616f923b4700f1f136dc55f16a4d2c2b Author: Martin Roth <martinroth(a)google.com> Date: Tue Aug 25 14:41:33 2015 -0600 Don't select serirq_continuous_mode when it doesn't exist Bay Trail and Braswell don't use SERIRQ_CONTINUOUS_MODE, which Google's Chrome EC selects. By adding a flag saying that the Kconfig symbol isn't used on these platforms, this can be avoided. Change-Id: I1107e1e58dbc4fb7fd068e4a253c25fb2b145b5f Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/ec/google/chromeec/Kconfig | 2 +- src/soc/intel/baytrail/Kconfig | 6 ++++++ src/soc/intel/braswell/Kconfig | 6 ++++++ 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 25cc0e4..9c778e2 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -37,7 +37,7 @@ config EC_GOOGLE_CHROMEEC_I2C_PROTO3 config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y - select SERIRQ_CONTINUOUS_MODE + select SERIRQ_CONTINUOUS_MODE if !NO_LPC_SERIRQ_CONTINUOUS_MODE help Google Chrome EC via LPC bus. diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5754c15..28676db 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -171,4 +171,10 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB +config NO_LPC_SERIRQ_CONTINUOUS_MODE + def_bool y + help + Baytrail doesn't use SERIRQ_CONTINUOUS_MODE. This flag tells + Google's Chrome EC not to try to set it. + endif diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 4f7ed6a..edbbf85 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -211,4 +211,10 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" +config NO_LPC_SERIRQ_CONTINUOUS_MODE + def_bool y + help + Braswell doesn't use SERIRQ_CONTINUOUS_MODE. This flag tells + Google's Chrome EC not to try to set it. + endif

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coreboot-gerrit August 2015