July 2015 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: smm: 64bit fixes
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11089 -gerrit commit 66ab6a5ca348a3f0ce501bbc2bc8e69d84d28459 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:28:44 2015 -0700 smm: 64bit fixes Change-Id: I35dab4e66514948aafa912d993fb8d42c5a520a0 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/x86/smm/Makefile.inc | 8 ++++++++ src/cpu/x86/smm/smihandler.c | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 239689e..2e61018 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -61,14 +61,22 @@ $(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs) $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ # Link the SMM stub module with a 0-byte heap. +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_32)) +else +$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_64)) +endif $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ $(obj)/cpu/x86/smm/smmstub.ramstage.manual: $(obj)/cpu/x86/smm/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) +else + cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) +endif # C-based SMM handler. diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 9c282c3..295e5a8 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -109,7 +109,7 @@ static void smi_restore_pci_address(void) outl(pci_orig, 0xcf8); } -static inline void *smm_save_state(u32 base, int arch_offset, int node) +static inline void *smm_save_state(uintptr_t base, int arch_offset, int node) { base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); return (void *)base;

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Patch merged into coreboot/master: what-jenkins-does: make CPU count configurable
by gerrit＠coreboot.org July 31, 2015

July 31, 2015

the following patch was just integrated into master: commit c6a4aae8a310d36272c9547ff002bd1aeabf5a42 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:54:44 2015 +0200 what-jenkins-does: make CPU count configurable Change-Id: I55eb833dba3b13c46138f7d1facc31d999e52db4 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11097 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11097 for details. -gerrit

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Patch merged into coreboot/master: what-jenkins-does: make its payload selection overridable
by gerrit＠coreboot.org July 31, 2015

July 31, 2015

the following patch was just integrated into master: commit e1514070c9cccb4c69fcf622f7159c114d08d7f3 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:54:12 2015 +0200 what-jenkins-does: make its payload selection overridable Change-Id: Ifbdc6bf73595a0d04a8ae09c80394787b6f76d13 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11096 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11096 for details. -gerrit

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Patch merged into coreboot/master: what-jenkins-does: Adapt to recent libpayload kconfig changes
by gerrit＠coreboot.org July 31, 2015

July 31, 2015

the following patch was just integrated into master: commit b551d8b0c338d207b60d90adec023bc787f7f285 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:39:06 2015 +0200 what-jenkins-does: Adapt to recent libpayload kconfig changes Since we don't actually use this target at this time, it was bitrotting. Fix it up, so we can start to use it. Change-Id: I27d2ed4fb2640680acf739a87d61cb0d1463d705 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11095 for details. -gerrit

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Patch set updated for coreboot: cpu/amd: Fix cbtypes.h to match UINTN convention
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10601 -gerrit commit 1128045fae15904abdcca5a72e081cbb22232074 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jul 29 23:54:38 2015 -0700 cpu/amd: Fix cbtypes.h to match UINTN convention There are some inconsistencies in AMDs APIs between the coreboot code and the vendorcode code. Unify the API. UINTN maps to uintptr_t in UEFI land. Do the same here. Also switch the other UEFI types to map to fixed size types. Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/include/cpu/amd/common/cbtypes.h | 22 +++++++++++++--------- src/mainboard/amd/dinar/rd890_cfg.c | 2 +- src/mainboard/amd/dinar/sb700_cfg.c | 2 +- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 2 +- src/mainboard/supermicro/h8scm/rd890_cfg.c | 2 +- src/mainboard/tyan/s8226/rd890_cfg.c | 2 +- src/northbridge/amd/cimx/rd890/amd.h | 2 +- src/vendorcode/amd/agesa/common/Porting.h | 24 ++++++++++++++---------- src/vendorcode/amd/cimx/sb700/SBTYPE.h | 2 +- src/vendorcode/amd/cimx/sb800/AMDSBLIB.h | 4 +++- src/vendorcode/amd/cimx/sb900/AmdSbLib.h | 4 ++-- src/vendorcode/amd/cimx/sb900/SbDef.h | 2 +- src/vendorcode/amd/cimx/sb900/SbMain.c | 2 +- src/vendorcode/amd/cimx/sb900/SbSubFun.h | 5 +++-- 14 files changed, 44 insertions(+), 33 deletions(-) diff --git a/src/include/cpu/amd/common/cbtypes.h b/src/include/cpu/amd/common/cbtypes.h index 346f1a3..54da783 100644 --- a/src/include/cpu/amd/common/cbtypes.h +++ b/src/include/cpu/amd/common/cbtypes.h @@ -20,16 +20,20 @@ #ifndef _CBTYPES_H_ #define _CBTYPES_H_ -typedef signed long long __int64; +/* Map coreboot stdint types to AGESA types. */ + +#include <stdint.h> + +typedef int64_t __int64; typedef void VOID; -typedef unsigned int UINTN; -typedef signed char CHAR8; -typedef unsigned char UINT8; -typedef unsigned short UINT16; -typedef unsigned int UINT32; -typedef signed int INT32; -typedef unsigned long long UINT64; -typedef unsigned char BOOLEAN; +typedef uintptr_t UINTN; +typedef char CHAR8; +typedef uint8_t UINT8; +typedef uint16_t UINT16; +typedef uint32_t UINT32; +typedef int32_t INT32; +typedef uint64_t UINT64; +typedef uint8_t BOOLEAN; #define DMSG_SB_TRACE 0x02 #define TRACE(Arguments) diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index c90f9f0..13f18ec 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/amd/dinar/sb700_cfg.c b/src/mainboard/amd/dinar/sb700_cfg.c index 53e93ce..2ce47ce 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.c +++ b/src/mainboard/amd/dinar/sb700_cfg.c @@ -135,7 +135,7 @@ void sb700_cimx_config(AMDSBCFG *sb_config) #ifndef __PRE_RAM__ /* ramstage cimx config here */ if (!sb_config->StdHeader.pCallBack) { - sb_config->StdHeader.pCallBack = sb700_callout_entry; + sb_config->StdHeader.pCallBack = (CIM_HOOK_ENTRY)&sb700_callout_entry; } //sb_config-> diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.c +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 1e78f93..f42a279 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. diff --git a/src/northbridge/amd/cimx/rd890/amd.h b/src/northbridge/amd/cimx/rd890/amd.h index 5e69ac4..ade5a31 100644 --- a/src/northbridge/amd/cimx/rd890/amd.h +++ b/src/northbridge/amd/cimx/rd890/amd.h @@ -41,7 +41,7 @@ #define OUT #define IMAGE_SIGNATURE 'DMA$' -typedef UINTN AGESA_STATUS; +typedef UINT32 AGESA_STATUS; #define AGESA_SUCCESS ((AGESA_STATUS) 0x0) diff --git a/src/vendorcode/amd/agesa/common/Porting.h b/src/vendorcode/amd/agesa/common/Porting.h index fc65cfc..44257e3 100644 --- a/src/vendorcode/amd/agesa/common/Porting.h +++ b/src/vendorcode/amd/agesa/common/Porting.h @@ -216,6 +216,7 @@ #elif defined __GNUC__ + #include <stdint.h> #define IN #define OUT #define STATIC static @@ -228,17 +229,20 @@ #define CALLCONV #define _16BYTE_ALIGN __attribute__ ((aligned (16))) + + // Create the universal 32, 16, and 8-bit data types typedef unsigned char BOOLEAN; - typedef signed char INT8; - typedef signed short INT16; - typedef signed long INT32; - typedef char CHAR8; - typedef unsigned char UINT8; - typedef unsigned short UINT16; - typedef unsigned long UINT32; - typedef unsigned long UINTN; - typedef unsigned long long UINT64; - typedef long long INT64; + typedef uintptr_t UINTN; + typedef int64_t INT64; + typedef uint64_t UINT64; + typedef int32_t INT32; + typedef uint32_t UINT32; + typedef int16_t INT16; + typedef uint16_t UINT16; + typedef int8_t INT8; + typedef uint8_t UINT8; + typedef char CHAR8; + typedef unsigned short CHAR16; typedef void VOID; //typedef unsigned long size_t; diff --git a/src/vendorcode/amd/cimx/sb700/SBTYPE.h b/src/vendorcode/amd/cimx/sb700/SBTYPE.h index faeae5d..3dc571f 100644 --- a/src/vendorcode/amd/cimx/sb700/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb700/SBTYPE.h @@ -32,7 +32,7 @@ #pragma pack(push,1) -typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig); +typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig); typedef void (*SMM_SERVICE_ROUTINE) (void); typedef struct _STDCFG{ diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h index 9e50bf9..a50cda4 100644 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h +++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.h @@ -46,6 +46,8 @@ #ifndef __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ #define __VENDORCODE_AMD_CIMX_SB800_AMDSBLIB_H__ +#include <cpu/amd/common/cbtypes.h> + //AMDSBLIB Routines /** @@ -105,7 +107,7 @@ AGESA_STATUS AmdSbDispatcher (IN void *pConfig); * @param[in] Length - Data length * */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /* SB800 CIMx and AGESA V5 can share lib functions */ diff --git a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h index cf9589b..47a7048 100644 --- a/src/vendorcode/amd/cimx/sb900/AmdSbLib.h +++ b/src/vendorcode/amd/cimx/sb900/AmdSbLib.h @@ -69,10 +69,10 @@ unsigned char getEfuseByte (IN unsigned char Index); AGESA_STATUS AmdSbDispatcher (IN void *pConfig); /**< AmdSbCopyMem - Reserved */ -void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN unsigned int Length); +void AmdSbCopyMem (IN void* pDest, IN void* pSource, IN UINTN Length); /**< GetRomSigPtr - Reserved */ -void* GetRomSigPtr (IN unsigned int* RomSigPtr); +void* GetRomSigPtr (IN UINTN * RomSigPtr); /**< RWXhciIndReg - Reserved */ void RWXhciIndReg (IN unsigned int Index, IN unsigned int AndMask, IN unsigned int OrMask); diff --git a/src/vendorcode/amd/cimx/sb900/SbDef.h b/src/vendorcode/amd/cimx/sb900/SbDef.h index 91fec4a..b600627 100644 --- a/src/vendorcode/amd/cimx/sb900/SbDef.h +++ b/src/vendorcode/amd/cimx/sb900/SbDef.h @@ -71,7 +71,7 @@ void MemoryCopy ( IN unsigned char *Dest, IN unsigned char *Source, - IN unsigned int Size + IN unsigned long Size ); //AMD Library Routines (PCILIB.C) diff --git a/src/vendorcode/amd/cimx/sb900/SbMain.c b/src/vendorcode/amd/cimx/sb900/SbMain.c index 958e44b..7c9dbbd 100644 --- a/src/vendorcode/amd/cimx/sb900/SbMain.c +++ b/src/vendorcode/amd/cimx/sb900/SbMain.c @@ -278,7 +278,7 @@ sbSmmAcpiOn ( UINTN CallBackToOEM ( IN UINT32 Func, - IN UINT32 Data, + IN UINTN Data, IN AMDSBCFG* pConfig ) { diff --git a/src/vendorcode/amd/cimx/sb900/SbSubFun.h b/src/vendorcode/amd/cimx/sb900/SbSubFun.h index 447f5c9..68574a7 100644 --- a/src/vendorcode/amd/cimx/sb900/SbSubFun.h +++ b/src/vendorcode/amd/cimx/sb900/SbSubFun.h @@ -40,6 +40,7 @@ ; ;*********************************************************************************/ +#include <cpu/amd/common/cbtypes.h> // Southbridge SBMAIN Routines /** @@ -127,7 +128,7 @@ void sbSmmAcpiOn (IN AMDSBCFG* pConfig); * @param[in] Data Callback specific data. * @param[in] pConfig Southbridge configuration structure pointer. */ -unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig); +UINTN CallBackToOEM (IN unsigned int Func, IN UINTN Data, IN AMDSBCFG* pConfig); // Southbridge SBPOR Routines @@ -605,4 +606,4 @@ void TurnOffCG2 (OUT void); */ void BackUpCG2 (OUT void); -void XhciA12Fix (OUT void); \ No newline at end of file +void XhciA12Fix (OUT void);

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Patch set updated for coreboot: RD890: 64bit fixes
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11086 -gerrit commit aff4e56230566c3b988c281d241c7042e865cea3 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:25:33 2015 -0700 RD890: 64bit fixes Change-Id: I326c070398c72a877054969d3a03e6e427edc304 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/northbridge/amd/cimx/rd890/late.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index bc51543..3bdce27 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -86,7 +86,8 @@ static void rd890_enable(device_t dev) /* CIMX configuration defualt initialize */ rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, + (uintptr_t)dev, (VOID*)NbConfigPtr); } /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree * After this call EP are fully operational on particular NB @@ -122,7 +123,7 @@ static void ioapic_init(struct device *dev) void *ioapic_base; pci_write_config32(dev, 0xF8, 0x1); - ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + ioapic_base = (void *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); clear_ioapic(ioapic_base); setup_ioapic(ioapic_base, 1); }

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Patch set updated for coreboot: SB700: 64bit fixes
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11085 -gerrit commit 56a43a5cc58aa6d66d491867f0d058610103a19d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:24:46 2015 -0700 SB700: 64bit fixes Change-Id: Ib4b643441a5b887abf73cc55930ea9b01037f6ea Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/amd/cimx/sb700/late.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index cd36fac..998710d 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -234,7 +234,7 @@ static void sb700_enable(device_t dev) case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ { - u32 ioapic_base; + uintptr_t ioapic_base; printk(BIOS_DEBUG, "sm_init().\n"); ioapic_base = IO_APIC_ADDR; clear_ioapic((void *)ioapic_base);

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Patch set updated for coreboot: SB900 64bit fixes
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11084 -gerrit commit 62063b22527676a26be10d0f341413009a96f070 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:24:23 2015 -0700 SB900 64bit fixes Change-Id: I5ea0f9338ccdd658b5fbec72aa35b4f80d63d4f9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/amd/cimx/sb900/cfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index ed35a5d..3640966 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -213,7 +213,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config) sb_config->GppHardwareDowngrade = INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option sb_config->GppToggleReset = INCHIP_GPP_TOGGLE_RESET; // External Option sb_config->sdbEnable = 0; // CIMx Internal Used - sb_config->TempMMIO = (typeof(sb_config->TempMMIO))NULL; // CIMx Internal Used + sb_config->TempMMIO = (UINTN)NULL; // CIMx Internal Used // sb_config->GecPhyStatus = INCHIP_GEC_PHY_STATUS; // Field Retired sb_config->SBGecPwr = INCHIP_GEC_POWER_POLICY; // Internal Option sb_config->SBGecDebugBus = INCHIP_GEC_DEBUGBUS; // Internal Option

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Patch set updated for coreboot: More Hudson 64bit fixes
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11083 -gerrit commit 414ba276ff0e25e9c8ded9ea8d5c3e8c8c8561c6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:23:50 2015 -0700 More Hudson 64bit fixes Change-Id: I2a6cd7ad27cb6d16dfe3267ea6fb844a5e2e20c6 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/southbridge/amd/agesa/hudson/hudson.c | 8 ++++---- src/southbridge/amd/agesa/hudson/sata.c | 2 +- src/southbridge/amd/agesa/hudson/smi.h | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index cafd6c6..dd52b3a 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,22 +40,22 @@ void pm_write8(u8 reg, u8 value) { - write8((void *)(PM_MMIO_BASE + reg), value); + write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); } u8 pm_read8(u8 reg) { - return read8((void *)(PM_MMIO_BASE + reg)); + return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); } void pm_write16(u8 reg, u16 value) { - write16((void *)(PM_MMIO_BASE + reg), value); + write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); } u16 pm_read16(u16 reg) { - return read16((void *)(PM_MMIO_BASE + reg)); + return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); } #define PM_REG_USB_ENABLE 0xef diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index 00c2a07..c5dc196 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -41,7 +41,7 @@ static void sata_init(struct device *dev) #define CFG_CAP_SPM (1<<12) volatile u32 *ahci_ptr = - (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); + (u32*)(uintptr_t)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00); u32 temp; /* unlock the write-protect */ diff --git a/src/southbridge/amd/agesa/hudson/smi.h b/src/southbridge/amd/agesa/hudson/smi.h index 520c65f..652c886 100644 --- a/src/southbridge/amd/agesa/hudson/smi.h +++ b/src/southbridge/amd/agesa/hudson/smi.h @@ -36,22 +36,22 @@ enum smi_lvl { static inline uint32_t smi_read32(uint8_t offset) { - return read32((void *)(SMI_BASE + offset)); + return read32((void *)((uintptr_t)SMI_BASE + offset)); } static inline void smi_write32(uint8_t offset, uint32_t value) { - write32((void *)(SMI_BASE + offset), value); + write32((void *)((uintptr_t)SMI_BASE + offset), value); } static inline uint16_t smi_read16(uint8_t offset) { - return read16((void *)(SMI_BASE + offset)); + return read16((void *)((uintptr_t)SMI_BASE + offset)); } static inline void smi_write16(uint8_t offset, uint16_t value) { - write16((void *)(SMI_BASE + offset), value); + write16((void *)((uintptr_t)SMI_BASE + offset), value); } void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);

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Patch set updated for coreboot: mainboard 64bit fixes
by Stefan Reinauer July 31, 2015

July 31, 2015

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11082 -gerrit commit a6464d82811b3e42d0de38e7a2242e485452181d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:17:10 2015 -0700 mainboard 64bit fixes Change-Id: I2b4338927d56a2075c0a95f2ab981f1beaf69cc7 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/mainboard/amd/dinar/fadt.c | 20 ++++++++++++++------ src/mainboard/amd/dinar/mptable.c | 4 ++-- src/mainboard/amd/dinar/rd890_cfg.c | 2 +- src/mainboard/amd/torpedo/fadt.c | 20 ++++++++++++++------ src/mainboard/gizmosphere/gizmo/mainboard.c | 7 +++---- src/mainboard/supermicro/h8qgi/fadt.c | 20 ++++++++++++++------ src/mainboard/supermicro/h8qgi/mptable.c | 4 ++-- src/mainboard/supermicro/h8qgi/rd890_cfg.c | 2 +- src/mainboard/supermicro/h8scm/fadt.c | 20 ++++++++++++++------ src/mainboard/supermicro/h8scm/mptable.c | 4 ++-- src/mainboard/supermicro/h8scm/rd890_cfg.c | 2 +- src/mainboard/tyan/s8226/fadt.c | 20 ++++++++++++++------ src/mainboard/tyan/s8226/mptable.c | 4 ++-- src/mainboard/tyan/s8226/rd890_cfg.c | 2 +- 14 files changed, 85 insertions(+), 46 deletions(-) diff --git a/src/mainboard/amd/dinar/fadt.c b/src/mainboard/amd/dinar/fadt.c index 5137964..7553852 100644 --- a/src/mainboard/amd/dinar/fadt.c +++ b/src/mainboard/amd/dinar/fadt.c @@ -48,8 +48,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; @@ -102,10 +110,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 172c497..aeefe54 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set sb700 IOAPIC ID */ - dword = (u8 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); + dword = (u8 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0); smp_write_ioapic(mc, apicid_sb700, 0x20, dword); /* @@ -80,7 +80,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); - dword = (u8 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + dword = (u8 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); smp_write_ioapic(mc, apicid_rd890, 0x20, dword); } diff --git a/src/mainboard/amd/dinar/rd890_cfg.c b/src/mainboard/amd/dinar/rd890_cfg.c index 13f18ec..9689b9d 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.c +++ b/src/mainboard/amd/dinar/rd890_cfg.c @@ -109,7 +109,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * @param[in] *config Northbridge configuration structure pointer. * */ -static u32 rd890_callout_entry(u32 func, u32 data, void *config) +static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) { u32 ret = 0; #ifndef __PRE_RAM__ diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 1bab638..2cdbc42 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -60,8 +60,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; @@ -138,10 +146,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 82de752..6c12a8a 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -75,17 +75,16 @@ static void mainboard_enable(device_t dev) RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); } -void mainboard_final( void *chip_info ); -void mainboard_final( void *chip_info ) +static void mainboard_final(void *chip_info) { device_t ahci_dev; - u32 ABAR; + uintptr_t ABAR; u8 *memptr; ahci_dev = dev_find_slot(0, PCI_DEVFN(0x11, 0)); ABAR = pci_read_config32(ahci_dev, 0x24); ABAR &= 0xFFFFFC00; - memptr = (u8 *) (ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */ + memptr = (u8 *)(ABAR + 0x100 + 0x80 + 0x2C); /* we're on the 2nd port */ *memptr = 0x21; /* force to GEN2 and start re-negotiate */ mdelay (1); *memptr = 0x20; diff --git a/src/mainboard/supermicro/h8qgi/fadt.c b/src/mainboard/supermicro/h8qgi/fadt.c index 54de8ca..cce8948 100644 --- a/src/mainboard/supermicro/h8qgi/fadt.c +++ b/src/mainboard/supermicro/h8qgi/fadt.c @@ -49,8 +49,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; @@ -103,10 +111,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 9880812..d0e0a6e 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ - dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); + dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0); smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); #ifdef UNUSED_CODE @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); - dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); } diff --git a/src/mainboard/supermicro/h8qgi/rd890_cfg.c b/src/mainboard/supermicro/h8qgi/rd890_cfg.c index f42a279..a337714 100644 --- a/src/mainboard/supermicro/h8qgi/rd890_cfg.c +++ b/src/mainboard/supermicro/h8qgi/rd890_cfg.c @@ -109,7 +109,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * @param[in] *config Northbridge configuration structure pointer. * */ -static u32 rd890_callout_entry(u32 func, u32 data, void *config) +static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) { u32 ret = 0; #ifndef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c index d91ae6f..b3d4762 100644 --- a/src/mainboard/supermicro/h8scm/fadt.c +++ b/src/mainboard/supermicro/h8scm/fadt.c @@ -49,8 +49,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; @@ -103,10 +111,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index d5ee68d..d5cdf24 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ - dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); + dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0); smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); #ifdef UNUSED_CODE @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); - dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); } diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c index f42a279..a337714 100644 --- a/src/mainboard/supermicro/h8scm/rd890_cfg.c +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -109,7 +109,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * @param[in] *config Northbridge configuration structure pointer. * */ -static u32 rd890_callout_entry(u32 func, u32 data, void *config) +static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) { u32 ret = 0; #ifndef __PRE_RAM__ diff --git a/src/mainboard/tyan/s8226/fadt.c b/src/mainboard/tyan/s8226/fadt.c index d91ae6f..b3d4762 100644 --- a/src/mainboard/tyan/s8226/fadt.c +++ b/src/mainboard/tyan/s8226/fadt.c @@ -49,8 +49,16 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) memcpy(header->asl_compiler_id, ASLC, 4); header->asl_compiler_revision = 0; - fadt->firmware_ctrl = (u32) facs; - fadt->dsdt = (u32) dsdt; + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ fadt->preferred_pm_profile = 0x03; fadt->sci_int = 9; @@ -103,10 +111,10 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (u32) facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (u32) dsdt; - fadt->x_dsdt_h = 0; + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; fadt->x_pm1a_evt_blk.space_id = 1; fadt->x_pm1a_evt_blk.bit_width = 32; diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 9880812..d0e0a6e 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -59,7 +59,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ - dword = (u32 *)(pci_read_config32(dev, 0x74) & 0xfffffff0); + dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0x74) & 0xfffffff0); smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); #ifdef UNUSED_CODE @@ -96,7 +96,7 @@ static void *smp_write_config_table(void *v) dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (dev) { pci_write_config32(dev, 0xF8, 0x1); - dword = (u32 *)(pci_read_config32(dev, 0xFC) & 0xfffffff0); + dword = (u32 *)(uintptr_t)(pci_read_config32(dev, 0xFC) & 0xfffffff0); smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); } diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index f42a279..a337714 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -109,7 +109,7 @@ static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) * @param[in] *config Northbridge configuration structure pointer. * */ -static u32 rd890_callout_entry(u32 func, u32 data, void *config) +static u32 rd890_callout_entry(u32 func, uintptr_t data, void *config) { u32 ret = 0; #ifndef __PRE_RAM__

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