coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 955881d libpayload: usb: Support MTK xHCI host controller
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10389 -gerrit commit 955881dbb2d9f52c3f1bad27fb87712534138337 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Thu May 7 15:36:04 2015 +0800 libpayload: usb: Support MTK xHCI host controller 1. There is a mis-understanding to calculate the value of TD Size in Normal TRB. For MTK's xHCI controller it defines a number of packets that remain to be transferred for a TD after processing all Max packets in all previous TRBs,that means don't include the current TRB's. 2. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK architecture defines some extra SW scheduling parameters for HW. According to these parameters provided by SW, the xHC can easily decide whether a synchronous endpoint should be scheduled in a specific uFrame. The extra SW scheduling parameters are put into reserved DWs in Slot and Endpoint Context. But in core-boot synchronous transfer can be ignored, so only tow fields are set to a default value 1 to support bulk and interrupt transfers, and others are set to zero. 3. For control transfer, it is better to read back doorbell register or add a memory barrier after ringing the doorbell to flush posted write. Otherwise the first command will be aborted on MTK's xHCI controller. 4. Before send commands to a port, the Port Power in PORTSC register should be set to 1 on MTK's xHCI. so a hook function of enbale_port in generic_hub_ops_t struct is provided. Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41 Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265362 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> --- payloads/libpayload/Config.in | 6 ++++++ payloads/libpayload/drivers/usb/xhci.c | 17 ++++++++++++++++- payloads/libpayload/drivers/usb/xhci_commands.c | 2 ++ payloads/libpayload/drivers/usb/xhci_devconf.c | 10 ++++++++++ payloads/libpayload/drivers/usb/xhci_private.h | 9 +++++++++ payloads/libpayload/drivers/usb/xhci_rh.c | 20 +++++++++++++++++++- 6 files changed, 62 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 4d48761..92c89ab 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -495,6 +495,12 @@ config USB_XHCI Select this option if you want to use USB 3.0 NOTE: This option is not (fully) implemented yet +config USB_XHCI_MTK_QUIRK + bool "Support for USB xHCI controllers on MTK SoC" + depends on USB_XHCI + help + Select this option if you want to use USB 3.0 on MTK platform. + config USB_DWC2 bool "Support for USB DesignWare HCD controllers" depends on USB && !USB_HID diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 26dcdbe..77645bf 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -370,6 +370,8 @@ xhci_reinit (hci_t *controller) xhci->ev_ring_table[0].seg_base_hi = 0; xhci->ev_ring_table[0].seg_size = EVENT_RING_SIZE; + /* pass event ring table to hardware */ + wmb(); /* Initialize primary interrupter */ xhci->hcrreg->intrrs[0].erstsz = 1; xhci_update_event_dq(xhci); @@ -510,6 +512,7 @@ xhci_enqueue_trb(transfer_ring_t *const tr) xhci_spew("Handling LINK pointer\n"); const int tc = TRB_GET(TC, tr->cur); TRB_SET(CH, tr->cur, chain); + wmb(); TRB_SET(C, tr->cur, tr->pcs); tr->cur = phys_to_virt(tr->cur->ptr_low); if (tc) @@ -535,7 +538,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, cur_length = length; packets = 0; length = 0; - } else { + } else if (!IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) { packets -= (residue + cur_length) / mps; residue = (residue + cur_length) % mps; length -= cur_length; @@ -548,6 +551,18 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets)); TRB_SET(CH, trb, 1); + if (length && IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) { + /* + * For MTK's xHCI controller, TDS defines a number of + * packets that remain to be transferred for a TD after + * processing all Max packets in all previousTRBs, that + * means don't include the current TRB's. + */ + packets -= (residue + cur_length) / mps; + residue = (residue + cur_length) % mps; + length -= cur_length; + } + /* Check for first, data stage TRB */ if (!trb_count && ep == 1) { TRB_SET(DIR, trb, dir); diff --git a/payloads/libpayload/drivers/usb/xhci_commands.c b/payloads/libpayload/drivers/usb/xhci_commands.c index 009a69c..845a34d 100644 --- a/payloads/libpayload/drivers/usb/xhci_commands.c +++ b/payloads/libpayload/drivers/usb/xhci_commands.c @@ -47,6 +47,8 @@ xhci_post_command(xhci_t *const xhci) TRB_SET(C, xhci->cr.cur, xhci->cr.pcs); ++xhci->cr.cur; + /* pass command trb to hardware */ + wmb(); /* Ring the doorbell */ xhci->dbreg[0] = 0; diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 012f610..5b5bb5e 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -313,6 +313,16 @@ xhci_finish_ep_config(const endpoint_t *const ep, inputctx_t *const ic) EC_SET(AVRTRB, epctx, avrtrb); EC_SET(MXESIT, epctx, EC_GET(MPS, epctx) * EC_GET(MBS, epctx)); + if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + /* The MTK xHCI defines some extra SW parameters which are + * put into reserved DWs in Slot and Endpoint Contexts for + * synchronous endpoints. But for non-isochronous transfers, + * it is enough to set the following two fields to 1, and others + * are set to 0. + */ + EC_SET(BPKTS, epctx, 1); + EC_SET(BBM, epctx, 1); + } return 0; } diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 3861858..f01a37f 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -33,6 +33,8 @@ //#define USB_DEBUG #include <usb/usb.h> +#include <arch/barrier.h> +#include <kconfig.h> //#define XHCI_DUMPS #define xhci_debug(fmt, args...) usb_debug("%s: " fmt, __func__, ## args) @@ -242,6 +244,13 @@ typedef volatile struct slotctx { #define EC_MXESIT_FIELD f5 /* MXESIT - Max ESIT Payload */ #define EC_MXESIT_START 16 #define EC_MXESIT_LEN 16 +#define EC_BPKTS_FIELD rsvd[0] /* BPKTS - packets tx in scheduled uframe */ +#define EC_BPKTS_START 0 +#define EC_BPKTS_LEN 6 +#define EC_BBM_FIELD rsvd[0] /* BBM - burst mode for scheduling */ +#define EC_BBM_START 11 +#define EC_BBM_LEN 1 + #define EC_MASK(tok) MASK(EC_##tok##_START, EC_##tok##_LEN) #define EC_GET(tok, ec) (((ec)->EC_##tok##_FIELD & EC_MASK(tok)) \ >> EC_##tok##_START) diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index fa118fe..a6b94c2 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -119,6 +119,24 @@ xhci_rh_reset_port(usbdev_t *const dev, const int port) return 0; } +static int +xhci_rh_enable_port(usbdev_t *const dev, int port) +{ + if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + xhci_t *const xhci = XHCI_INST(dev->controller); + volatile u32 *const portsc = + &xhci->opreg->prs[port - 1].portsc; + + /* + * Before send commands to a port, the Port Power in + * PORTSC register should be enabled on MTK's xHCI. + */ + *portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PP; + } + return 0; +} + + static const generic_hub_ops_t xhci_rh_ops = { .hub_status_changed = xhci_rh_hub_status_changed, .port_status_changed = xhci_rh_port_status_changed, @@ -126,7 +144,7 @@ static const generic_hub_ops_t xhci_rh_ops = { .port_in_reset = xhci_rh_port_in_reset, .port_enabled = xhci_rh_port_enabled, .port_speed = xhci_rh_port_speed, - .enable_port = NULL, + .enable_port = xhci_rh_enable_port, .disable_port = NULL, .start_port_reset = NULL, .reset_port = xhci_rh_reset_port,

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Patch set updated for coreboot: 3cd04d3 libpayload: usb: Max packet size of SuperSpeed control EPs should be 512.
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10388 -gerrit commit 3cd04d340af7fe0a28a4e67e4cf7a3407c7eddcd Author: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Date: Thu May 7 15:28:19 2015 +0800 libpayload: usb: Max packet size of SuperSpeed control EPs should be 512. BRANCH=none BUG=none TEST=none Change-Id: I563ef65db900d7675aeb5b9123dfb5a8980bf964 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9764115d7bcce1d6423464bd81b58211ac728409 Original-Change-Id: Ibac8d3b9e28b4a563079f288901abcfbff6913ee Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269863 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> --- payloads/libpayload/drivers/usb/usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index 54b113c..b97ba6f 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -252,7 +252,7 @@ usb_decode_mps0(usb_speed speed, u8 bMaxPacketSize0) usb_debug("Invalid MPS0: 0x%02x\n", bMaxPacketSize0); bMaxPacketSize0 = 9; } - return 2 << bMaxPacketSize0; + return 1 << bMaxPacketSize0; default: /* GCC is stupid and cannot deal with enums correctly */ return 8; }

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Patch set updated for coreboot: e1f3f6b Make common macros double-evaluation-safe
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10393 -gerrit commit e1f3f6bd0928710320b51cafbb1f0386a72f2530 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 22 18:09:48 2015 -0700 Make common macros double-evaluation-safe Our MIN(), MAX() and ALIGN*() macros are currently vulnerable to double-evaluation (e.g. x = ALIGN_UP(y, big_func_with_side_effects(y)); doesn't do what you'd think it should). GCC (and mostly GCC-compatible compilers like clang) long had the statement expression and typeof() extensions to deal with problems like this. We should use them. BRANCH=None BUG=None TEST=None Change-Id: I4cc368a2f9966139c988257afc013151cd90c7ab Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 985abba1a9b8fa659a9f40e224f81266d7e542bb Original-Change-Id: I2519d552b67096c9277c5206964f83dda97c8d01 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273009 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/include/libpayload.h | 12 ++++++++++-- payloads/libpayload/include/stdlib.h | 6 +++++- src/include/stdlib.h | 18 +++++++++++++++--- 3 files changed, 30 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index c3ca123..4670051 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -62,8 +62,16 @@ #include <lar.h> #endif -#define MIN(a,b) ((a) < (b) ? (a) : (b)) -#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ({ \ + typeof(a) _a = a; \ + typeof(b) _b = b; \ + _a < _b ? _a : _b; \ +}) +#define MAX(a, b) ({ \ + typeof(a) _a = a; \ + typeof(b) _b = b; \ + _a > _b ? _a : _b; \ +}) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) static inline u32 div_round_up(u32 n, u32 d) { return n + d - 1 / d; } diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index 08c7d06..71610c1 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -35,8 +35,12 @@ #include <stddef.h> #include <string.h> +#define __ALIGN_MASK(x, mask) ({ \ + typeof(mask) _mask = mask; \ + ((x) + _mask) & ~_mask; \ +}) + #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x,a) ALIGN((x),(a)) #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) #define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 35e8b32..37ed6ef 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -5,14 +5,26 @@ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#define __ALIGN_MASK(x, mask) ({ \ + typeof(mask) _mask = mask; \ + ((x) + _mask) & ~_mask; \ +}) + #define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) #define ALIGN_UP(x,a) ALIGN((x),(a)) #define ALIGN_DOWN(x,a) ((x) & ~((typeof(x))(a)-1UL)) #define IS_ALIGNED(x,a) (((x) & ((typeof(x))(a)-1UL)) == 0) -#define MIN(a,b) ((a) < (b) ? (a) : (b)) -#define MAX(a,b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ({ \ + typeof(a) _a = a; \ + typeof(b) _b = b; \ + _a < _b ? _a : _b; \ +}) +#define MAX(a, b) ({ \ + typeof(a) _a = a; \ + typeof(b) _b = b; \ + _a > _b ? _a : _b; \ +}) #define ABS(a) (((a) < 0) ? (-(a)) : (a)) #define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)

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Patch set updated for coreboot: ded6d53 Make common macros double-evaluation-safe
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10395 -gerrit commit ded6d536daedce73b9cc858bed92439248d957ef Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jun 1 10:27:02 2015 +0200 Make common macros double-evaluation-safe In the style of I4cc368a2f996, adapt more macros. Change-Id: I948ac39a307a2f0703b3a5c611c6eccd1559ca1f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/include/stdlib.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index 37ed6ef..4acf1ed 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -25,9 +25,19 @@ typeof(b) _b = b; \ _a > _b ? _a : _b; \ }) -#define ABS(a) (((a) < 0) ? (-(a)) : (a)) -#define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) -#define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) +#define ABS(a) ({ \ + typeof(a) _a = a; \ + _a < 0 ? -_a : _a; \ +}) +#define CEIL_DIV(a, b) ({ \ + typeof(a) _a = a; \ + typeof(b) _b = b; \ + (((_a) + (_b) - 1) / (_b)); \ +}) +#define IS_POWER_OF_2(x) ({ \ + typeof(x) _x = x; \ + (((_x) & ((_x) - 1)) == 0); \ +}) #define min(a,b) MIN((a),(b)) #define max(a,b) MAX((a),(b))

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Patch set updated for coreboot: 15fd6d1 lib: Unify log2() and related functions
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10394 -gerrit commit 15fd6d10f2038aa0161ce699c40b9f3642398529 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 22 16:26:40 2015 -0700 lib: Unify log2() and related functions This patch adds a few bit counting functions that are commonly needed for certain register calculations. We previously had a log2() implementation already, but it was awkwardly split between some C code that's only available in ramstage and an optimized x86-specific implementation in pre-RAM that prevented other archs from pulling it into earlier stages. Using __builtin_clz() as the baseline allows GCC to inline optimized assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and to perform constant-folding if possible. What was previously named log2f on pre-RAM x86 is now ffs, since that's the standard name for that operation and I honestly don't have the slightest idea how it could've ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm with Float result, whereas the Find First Set operation has no direct correlation to logarithms that I know of). Make ffs result 0-based instead of the POSIX standard's 1-based since that is consistent with clz, log2 and the former log2f, and generally closer to what you want for most applications (a value that can directly be used as a shift to reach the found bit). Call it __ffs() instead of ffs() to avoid problems when importing code, since that's what Linux uses for the 0-based operation. CQ-DEPEND=CL:273023 BRANCH=None BUG=None TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new log2() and __ffs() results on Falco for a bunch of test values. Change-Id: I599209b342059e17b3130621edb6b6bbeae26876 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273008 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/include/libpayload.h | 7 +++ payloads/libpayload/include/strings.h | 35 -------------- payloads/libpayload/libc/Makefile.inc | 4 +- payloads/libpayload/libc/libgcc.c | 68 +++++++++++++++++++++++++++ payloads/libpayload/libc/strings.c | 42 ----------------- src/arch/arm/include/utils.h | 55 ---------------------- src/arch/x86/include/arch/io.h | 4 +- src/include/lib.h | 18 ++++--- src/lib/Makefile.inc | 6 +-- src/lib/clog2.c | 37 --------------- src/lib/libgcc.c | 56 ++++++++++++++++++++++ src/northbridge/amd/amdk8/coherent_ht.c | 1 + src/northbridge/amd/amdk8/raminit.c | 5 +- src/northbridge/amd/amdk8/raminit_f.c | 1 + src/northbridge/amd/amdk8/raminit_test.c | 1 + src/northbridge/intel/e7501/raminit.c | 1 + src/northbridge/intel/i3100/raminit_ep80579.c | 1 + src/northbridge/intel/i855/raminit.c | 1 + src/northbridge/intel/i945/raminit.c | 1 + src/soc/rockchip/rk3288/clock.c | 17 +------ src/southbridge/via/k8t890/traf_ctrl.c | 3 +- 21 files changed, 162 insertions(+), 202 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 781a41d..c3ca123 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -311,6 +311,13 @@ u8 bin2hex(u8 b); u8 hex2bin(u8 h); void hexdump(const void *memory, size_t length); void fatal(const char *msg) __attribute__ ((noreturn)); + +/* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ +static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +/* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ +static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +/* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ +static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h deleted file mode 100644 index 5beddc6..0000000 --- a/payloads/libpayload/include/strings.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2011 secunet Security Networks AG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _STRINGS_H -#define _STRINGS_H - -int ffs(int i); - -#endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index b4f75a6..272cda9 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -29,10 +29,10 @@ ## libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c -libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c +libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c libgcc.c libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c -libc-$(CONFIG_LP_LIBC) += args.c strings.c +libc-$(CONFIG_LP_LIBC) += args.c libc-$(CONFIG_LP_LIBC) += strlcpy.c libc-$(CONFIG_LP_LIBC) += qsort.c libc-$(CONFIG_LP_LIBC) += hexdump.c diff --git a/payloads/libpayload/libc/libgcc.c b/payloads/libpayload/libc/libgcc.c new file mode 100644 index 0000000..86698d8 --- /dev/null +++ b/payloads/libpayload/libc/libgcc.c @@ -0,0 +1,68 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +/* + * Provide platform-independent backend implementation for __builtin_clz() in + * <libpayload.h> in case GCC does not have an assembly version for this arch. + */ + +int __clzsi2(u32 a); +int __clzsi2(u32 a) +{ + static const u8 four_bit_table[] = { + [0x0] = 4, [0x1] = 3, [0x2] = 2, [0x3] = 2, + [0x4] = 1, [0x5] = 1, [0x6] = 1, [0x7] = 1, + [0x8] = 0, [0x9] = 0, [0xa] = 0, [0xb] = 0, + [0xc] = 0, [0xd] = 0, [0xe] = 0, [0xf] = 0, + }; + int r = 0; + + if (!(a & (0xffff << 16))) { + r += 16; + a <<= 16; + } + + if (!(a & (0xff << 24))) { + r += 8; + a <<= 8; + } + + if (!(a & (0xf << 28))) { + r += 4; + a <<= 4; + } + + return r + four_bit_table[a >> 28]; +} diff --git a/payloads/libpayload/libc/strings.c b/payloads/libpayload/libc/strings.c deleted file mode 100644 index 465ae4f..0000000 --- a/payloads/libpayload/libc/strings.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2011 secunet Security Networks AG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <strings.h> - -int ffs(int i) -{ - int count = 1; - if (i == 0) return 0; - - while ((i & 1) != 1) { - i>>=1; - count++; - } - return count; -} diff --git a/src/arch/arm/include/utils.h b/src/arch/arm/include/utils.h deleted file mode 100644 index 2482c6b..0000000 --- a/src/arch/arm/include/utils.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh(a)ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ -#ifndef _UTILS_H_ -#define _UTILS_H_ - -static inline s32 log_2_n_round_up(u32 n) -{ - s32 log2n = -1; - u32 temp = n; - - while (temp) { - log2n++; - temp >>= 1; - } - - if (n & (n - 1)) - return log2n + 1; /* not power of 2 - round up */ - else - return log2n; /* power of 2 */ -} - -static inline s32 log_2_n_round_down(u32 n) -{ - s32 log2n = -1; - u32 temp = n; - - while (temp) { - log2n++; - temp >>= 1; - } - - return log2n; -} - -#endif diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index ce94773..a83d1e0 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -175,7 +175,7 @@ static inline __attribute__((always_inline)) void write32(volatile void *addr, u /* Conflicts with definition in lib.h */ #if defined(__ROMCC__) || defined(__SMM__) -static inline int log2(int value) +static inline int log2(u32 value) { unsigned int r = 0; __asm__ volatile ( @@ -190,7 +190,7 @@ static inline int log2(int value) #endif #if defined(__PRE_RAM__) || defined(__SMM__) -static inline int log2f(int value) +static inline int __ffs(u32 value) { unsigned int r = 0; __asm__ volatile ( diff --git a/src/include/lib.h b/src/include/lib.h index 7ad33dd..b81b1b1 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,12 +24,6 @@ #include <stdint.h> #include <types.h> -#if !defined(__ROMCC__) /* Conflicts with inline function in arch/io.h */ -/* Defined in src/lib/clog2.c */ -unsigned long log2(unsigned long x); -#endif -unsigned long log2_ceil(unsigned long x); - /* Defined in src/lib/lzma.c */ unsigned long ulzma(unsigned char *src, unsigned char *dst); @@ -49,4 +43,16 @@ int checkstack(void *top_of_stack, int core); void hexdump(const void *memory, size_t length); void hexdump32(char LEVEL, const void *d, size_t len); +#if !defined(__ROMCC__) +/* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ +static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +/* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ +static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +/* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ +static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +#endif + +/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ +static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } + #endif /* __LIB_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 5ec9de7..4f7fe9b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -22,7 +22,7 @@ bootblock-y += prog_ops.c bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c - +bootblock-y += libgcc.c bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -40,6 +40,7 @@ verstage-y += cbfs.c verstage-y += cbfs_core.c verstage-y += halt.c verstage-y += fmap.c +verstage-y += libgcc.c verstage-y += memcmp.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-y += region.c @@ -69,6 +70,7 @@ romstage-$(CONFIG_I2C_TPM) += delay.c romstage-y += cbfs.c cbfs_core.c romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +romstage-y += libgcc.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c @@ -104,8 +106,6 @@ ramstage-y += cbfs.c cbfs_core.c ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c -ramstage-y += clog2.c -romstage-y += clog2.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/clog2.c b/src/lib/clog2.c deleted file mode 100644 index 5e0d591..0000000 --- a/src/lib/clog2.c +++ /dev/null @@ -1,37 +0,0 @@ -#include <console/console.h> -#include <lib.h> - -/* Assume 8 bits per byte */ -#define CHAR_BIT 8 - -unsigned long log2(unsigned long x) -{ - /* assume 8 bits per byte. */ - unsigned long pow = sizeof(x) * CHAR_BIT - 1ULL; - unsigned long i = 1ULL << pow; - - if (!x) { - printk(BIOS_WARNING, "%s called with invalid parameter of 0\n", - __func__); - return -1; - } - - for (; i > x; i >>= 1, pow--); - - return pow; -} - -unsigned long log2_ceil(unsigned long x) -{ - unsigned long pow; - - if (!x) - return -1; - - pow = log2(x); - - if (x > (1ULL << pow)) - pow++; - - return pow; -} diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c new file mode 100644 index 0000000..6ce7ae5 --- /dev/null +++ b/src/lib/libgcc.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <types.h> + +/* + * Provide platform-independent backend implementation for __builtin_clz() in + * <lib.h> in case GCC does not have an assembly version for this arch. + */ + +#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ +int __clzsi2(u32 a); +int __clzsi2(u32 a) +{ + static const u8 four_bit_table[] = { + [0x0] = 4, [0x1] = 3, [0x2] = 2, [0x3] = 2, + [0x4] = 1, [0x5] = 1, [0x6] = 1, [0x7] = 1, + [0x8] = 0, [0x9] = 0, [0xa] = 0, [0xb] = 0, + [0xc] = 0, [0xd] = 0, [0xe] = 0, [0xf] = 0, + }; + int r = 0; + + if (!(a & (0xffff << 16))) { + r += 16; + a <<= 16; + } + + if (!(a & (0xff << 24))) { + r += 8; + a <<= 8; + } + + if (!(a & (0xf << 28))) { + r += 4; + a <<= 4; + } + + return r + four_bit_table[a >> 28]; +} +#endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index a8d8700..6554e07 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -66,6 +66,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/hypertransport_def.h> +#include <lib.h> #include <stdlib.h> #include <arch/io.h> #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 4213cfb..c58abb1 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -7,6 +7,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <lib.h> #include <stdlib.h> #include <arch/acpi.h> #include <reset.h> @@ -1655,7 +1656,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* if the next lower frequency gives a CL at least one whole cycle * shorter, select that (see end of BKDG 4.1.1.1) */ if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && - log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + __ffs(cl_at_freq[freq]) - __ffs(cl_at_freq[freq+1]) >= 2) freq++; if (freq == sizeof(cl_at_freq)) @@ -1690,7 +1691,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; + value |= latencies[__ffs(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 1469684..1c1a6ea 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -25,6 +25,7 @@ #include <cpu/x86/tsc.h> #include <cpu/amd/mtrr.h> +#include <lib.h> #include <stdlib.h> #include <arch/acpi.h> #include "raminit.h" diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index be46f27..87e281d 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -1,5 +1,6 @@ #include <unistd.h> #include <limits.h> +#include <lib.h> #include <stdint.h> #include <string.h> #include <setjmp.h> diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index f4fc9a8..93a3a5b 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -12,6 +12,7 @@ /* converted to C 6/2004 yhlu */ #include <assert.h> +#include <lib.h> #include <spd.h> #include <sdram_mode.h> #include <stdlib.h> diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 85660e9..ee8c4fd 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/intel/speedstep.h> +#include <lib.h> #include "raminit_ep80579.h" #include "ep80579.h" diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 81dcbb5..a43f5be 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -19,6 +19,7 @@ */ #include <assert.h> +#include <lib.h> #include <spd.h> #include <sdram_mode.h> #include <stdlib.h> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a3be680..7bd6240 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 2c56376..a2e8d88 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -21,6 +21,7 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <lib.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/grf.h> @@ -236,22 +237,6 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) return 0; } -/* - TODO: - it should be replaced by lib.h function - 'unsigned long log2(unsigned long x)' -*/ -static unsigned int log2(unsigned int value) -{ - unsigned int div = 0; - - while (value != 1) { - div++; - value = ALIGN_UP(value, 2) / 2; - } - return div; -} - void rkclk_init(void) { u32 aclk_div; diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index b4620da..24c1e65 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -24,10 +24,9 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <cpu/amd/powernow.h> +#include <lib.h> #include "k8t890.h" -extern unsigned long log2(unsigned long x); - static void mmconfig_set_resources(device_t dev) { struct resource *resource;

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Patch merged into coreboot/master: 68bdd00 libpayload: Add div_round_up() function
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 68bdd00799c7b2b25f265fa9e31beb709c877eb6 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 22 18:18:46 2015 -0700 libpayload: Add div_round_up() function The lack of a div_round_up() function in libpayload keeps being a problem for payloads and has already caused us to sprinkle numerous less-readable ALIGN_UP(n, d) / d throughout depthcharge. Let's add this so we can avoid adding any more and then maybe cocchinelle them all over later. BRANCH=None BUG=None TEST=None Change-Id: I241a52770a0edcf7003b48a81875b3fa0cb7ed53 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a3f9514f9cfd325cc3c4b542020574b605fac935 Original-Change-Id: Ia55bd4bc52ab8a249b4854e40727cf6917af7b30 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273050 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/10392 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10392 for details. -gerrit

1 0

Patch merged into coreboot/master: 0bd22ce ipq806x: clear the RPM initialization Acknowledge bit
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 0bd22ce82c6e4beaacfe591a6ae8ce2874d042b7 Author: Sourabh Banerjee <sbanerje(a)codeaurora.org> Date: Fri Apr 24 22:54:18 2015 +0530 ipq806x: clear the RPM initialization Acknowledge bit The RPM initialization Acknowledge is cleared by writing 1 into bit-10 of the RPM_INT_ACK register. The existing code got it wrong and is writing zero to that bit. BRANCH=storm BUG=chrome-os-partner:39231 TEST=with this patch and an RPM firmware update, an SP4 device survived more than 1000 reboots in a row. Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7 Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524 Original-Signed-off-by: Viswanath Kraleti <vkraleti(a)codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/266969 Original-Reviewed-by: Manoj Juneja <mjuneja(a)qti.qualcomm.com> Reviewed-on: http://review.coreboot.org/10310 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10310 for details. -gerrit

1 0

Patch merged into coreboot/master: 641529b TPM: Add Infineon SLB9670 SPI TPM support
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 641529b0678d7399c9072f23891151ecfb13ae27 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Fri May 29 10:54:27 2015 -0700 TPM: Add Infineon SLB9670 SPI TPM support This patch provides support for TPM Infineon SLB9670 by adding its device ID to the list. BRANCH=None BUG=chrome-os-partner:40640 TEST=Built and test SLB9670 on SKL U Reference board Fab 2 Change-Id: I2d26fc6c7d074881f2e6189e1325808544b7d26d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3c92884be75b631c302801e162292c245ed7bf5d Original-Change-Id: I4607fc96f70175b2461b40ba61e7a821e187de40 Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/274053 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/10387 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10387 for details. -gerrit

1 0

Patch merged into coreboot/master: 2e01e8d arm64: correct cacheable/non-cacheable tag string in print_tag
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 2e01e8df4d61301da421a542b0005a1c15068eaa Author: Jimmy Huang <jimmy.huang(a)mediatek.com> Date: Wed May 20 15:57:06 2015 +0800 arm64: correct cacheable/non-cacheable tag string in print_tag BRANCH=none BUG=none TEST=Booted on Oak and confirmed the output cacheable/non-cacheable string is correct. Change-Id: I062c1cc384b8cb9d07038399b1bc7ef47d992103 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 45552f95b55cd9fc81817e4ff02c78e885377065 Original-Change-Id: Ie52066dbefd2f54d0746792b89f0b57767811adb Original-Signed-off-by: Jimmy Huang <jimmy.huang(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273994 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: http://review.coreboot.org/10390 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10390 for details. -gerrit

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Patch merged into coreboot/master: 3553119 arm64: Guard prints in mmu.c
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 35531197d4ef0c5ef59c9720d12a68235da86558 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed May 20 17:10:55 2015 -0700 arm64: Guard prints in mmu.c We have observed issues with enabling CONFIG_SMP and adding prints before MMU is enabled on Tegra-based SoCs. This seems to be related to the hardware assisted locks and the restrictions laid down by ARMv8 spec. BUG=None BRANCH=None TEST=Boots to kernel prompt on smaug. Change-Id: I29a52f5a972baf396c01faba3ae3e5ecd27563e9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f52ee4b5b2e9b7f54eee0d105cb7e17f9a7e1613 Original-Change-Id: I432895560f468903c7beef00e78b6d38275a619c Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/272449 Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10311 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10311 for details. -gerrit

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coreboot-gerrit June 2015