Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10391
-gerrit
commit cab0abeb95059968127eb1b7e0969a6261228d9e
Author: Furquan Shaikh <furquan(a)google.com>
Date: Thu May 28 11:32:46 2015 -0700
vboot: Increase max parsed fw components to 6
With addition of bl31 and trusty, we need to increase the number of
parsed fw components in vboot to 6.
CQ-DEPEND=CL:273866
BUG=chrome-os-partner:40713
BRANCH=None
TEST=Compiles successfully and vboot finds trusty and bl31.
Change-Id: I3597e98370bbaef4d2e563c868eed59b2e18adca
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 0ff87fdbc7779e6ee410905d1618281411b38a93
Original-Change-Id: Ia403f895b50cc5349bb700d01f62e13c679f68f4
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/273865
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org>
---
src/vendorcode/google/chromeos/vboot_handoff.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/vendorcode/google/chromeos/vboot_handoff.h b/src/vendorcode/google/chromeos/vboot_handoff.h
index 8ae6e02..997ea30 100644
--- a/src/vendorcode/google/chromeos/vboot_handoff.h
+++ b/src/vendorcode/google/chromeos/vboot_handoff.h
@@ -32,7 +32,7 @@
* number of parsed firmware components (address and size) included in the
* handoff structure.
*/
-#define MAX_PARSED_FW_COMPONENTS 5
+#define MAX_PARSED_FW_COMPONENTS 6
struct firmware_component {
uint32_t address;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10389
-gerrit
commit a54b1ad031646c4bf59fcd9688da0378ed0b516d
Author: Yidi Lin <yidi.lin(a)mediatek.com>
Date: Thu May 7 15:36:04 2015 +0800
libpayload: usb: Support MTK xHCI host controller
1. There is a mis-understanding to calculate the value of TD Size
in Normal TRB. For MTK's xHCI controller it defines a number of
packets that remain to be transferred for a TD after processing
all Max packets in all previous TRBs,that means don't include the
current TRB's.
2. To minimize the scheduling effort for synchronous endpoints in xHC,
the MTK architecture defines some extra SW scheduling parameters for
HW. According to these parameters provided by SW, the xHC can easily
decide whether a synchronous endpoint should be scheduled in a specific
uFrame. The extra SW scheduling parameters are put into reserved DWs
in Slot and Endpoint Context. But in core-boot synchronous transfer can
be ignored, so only tow fields are set to a default value 1 to support
bulk and interrupt transfers, and others are set to zero.
3. For control transfer, it is better to read back doorbell register or add
a memory barrier after ringing the doorbell to flush posted write.
Otherwise the first command will be aborted on MTK's xHCI controller.
4. Before send commands to a port, the Port Power in PORTSC register should
be set to 1 on MTK's xHCI. so a hook function of enbale_port in
generic_hub_ops_t struct is provided.
Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41
Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/265362
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com>
---
payloads/libpayload/Config.in | 6 ++++++
payloads/libpayload/drivers/usb/xhci.c | 17 ++++++++++++++++-
payloads/libpayload/drivers/usb/xhci_commands.c | 2 ++
payloads/libpayload/drivers/usb/xhci_devconf.c | 10 ++++++++++
payloads/libpayload/drivers/usb/xhci_private.h | 9 +++++++++
payloads/libpayload/drivers/usb/xhci_rh.c | 20 +++++++++++++++++++-
6 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in
index 4d48761..92c89ab 100644
--- a/payloads/libpayload/Config.in
+++ b/payloads/libpayload/Config.in
@@ -495,6 +495,12 @@ config USB_XHCI
Select this option if you want to use USB 3.0
NOTE: This option is not (fully) implemented yet
+config USB_XHCI_MTK_QUIRK
+ bool "Support for USB xHCI controllers on MTK SoC"
+ depends on USB_XHCI
+ help
+ Select this option if you want to use USB 3.0 on MTK platform.
+
config USB_DWC2
bool "Support for USB DesignWare HCD controllers"
depends on USB && !USB_HID
diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c
index 26dcdbe..77645bf 100644
--- a/payloads/libpayload/drivers/usb/xhci.c
+++ b/payloads/libpayload/drivers/usb/xhci.c
@@ -370,6 +370,8 @@ xhci_reinit (hci_t *controller)
xhci->ev_ring_table[0].seg_base_hi = 0;
xhci->ev_ring_table[0].seg_size = EVENT_RING_SIZE;
+ /* pass event ring table to hardware */
+ wmb();
/* Initialize primary interrupter */
xhci->hcrreg->intrrs[0].erstsz = 1;
xhci_update_event_dq(xhci);
@@ -510,6 +512,7 @@ xhci_enqueue_trb(transfer_ring_t *const tr)
xhci_spew("Handling LINK pointer\n");
const int tc = TRB_GET(TC, tr->cur);
TRB_SET(CH, tr->cur, chain);
+ wmb();
TRB_SET(C, tr->cur, tr->pcs);
tr->cur = phys_to_virt(tr->cur->ptr_low);
if (tc)
@@ -535,7 +538,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
cur_length = length;
packets = 0;
length = 0;
- } else {
+ } else if (!IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) {
packets -= (residue + cur_length) / mps;
residue = (residue + cur_length) % mps;
length -= cur_length;
@@ -548,6 +551,18 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps,
TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets));
TRB_SET(CH, trb, 1);
+ if (length && IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) {
+ /*
+ * For MTK's xHCI controller, TDS defines a number of
+ * packets that remain to be transferred for a TD after
+ * processing all Max packets in all previousTRBs, that
+ * means don't include the current TRB's.
+ */
+ packets -= (residue + cur_length) / mps;
+ residue = (residue + cur_length) % mps;
+ length -= cur_length;
+ }
+
/* Check for first, data stage TRB */
if (!trb_count && ep == 1) {
TRB_SET(DIR, trb, dir);
diff --git a/payloads/libpayload/drivers/usb/xhci_commands.c b/payloads/libpayload/drivers/usb/xhci_commands.c
index 009a69c..845a34d 100644
--- a/payloads/libpayload/drivers/usb/xhci_commands.c
+++ b/payloads/libpayload/drivers/usb/xhci_commands.c
@@ -47,6 +47,8 @@ xhci_post_command(xhci_t *const xhci)
TRB_SET(C, xhci->cr.cur, xhci->cr.pcs);
++xhci->cr.cur;
+ /* pass command trb to hardware */
+ wmb();
/* Ring the doorbell */
xhci->dbreg[0] = 0;
diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c
index 012f610..5b5bb5e 100644
--- a/payloads/libpayload/drivers/usb/xhci_devconf.c
+++ b/payloads/libpayload/drivers/usb/xhci_devconf.c
@@ -313,6 +313,16 @@ xhci_finish_ep_config(const endpoint_t *const ep, inputctx_t *const ic)
EC_SET(AVRTRB, epctx, avrtrb);
EC_SET(MXESIT, epctx, EC_GET(MPS, epctx) * EC_GET(MBS, epctx));
+ if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) {
+ /* The MTK xHCI defines some extra SW parameters which are
+ * put into reserved DWs in Slot and Endpoint Contexts for
+ * synchronous endpoints. But for non-isochronous transfers,
+ * it is enough to set the following two fields to 1, and others
+ * are set to 0.
+ */
+ EC_SET(BPKTS, epctx, 1);
+ EC_SET(BBM, epctx, 1);
+ }
return 0;
}
diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h
index 3861858..f01a37f 100644
--- a/payloads/libpayload/drivers/usb/xhci_private.h
+++ b/payloads/libpayload/drivers/usb/xhci_private.h
@@ -33,6 +33,8 @@
//#define USB_DEBUG
#include <usb/usb.h>
+#include <arch/barrier.h>
+#include <kconfig.h>
//#define XHCI_DUMPS
#define xhci_debug(fmt, args...) usb_debug("%s: " fmt, __func__, ## args)
@@ -242,6 +244,13 @@ typedef volatile struct slotctx {
#define EC_MXESIT_FIELD f5 /* MXESIT - Max ESIT Payload */
#define EC_MXESIT_START 16
#define EC_MXESIT_LEN 16
+#define EC_BPKTS_FIELD rsvd[0] /* BPKTS - packets tx in scheduled uframe */
+#define EC_BPKTS_START 0
+#define EC_BPKTS_LEN 6
+#define EC_BBM_FIELD rsvd[0] /* BBM - burst mode for scheduling */
+#define EC_BBM_START 11
+#define EC_BBM_LEN 1
+
#define EC_MASK(tok) MASK(EC_##tok##_START, EC_##tok##_LEN)
#define EC_GET(tok, ec) (((ec)->EC_##tok##_FIELD & EC_MASK(tok)) \
>> EC_##tok##_START)
diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c
index fa118fe..a6b94c2 100644
--- a/payloads/libpayload/drivers/usb/xhci_rh.c
+++ b/payloads/libpayload/drivers/usb/xhci_rh.c
@@ -119,6 +119,24 @@ xhci_rh_reset_port(usbdev_t *const dev, const int port)
return 0;
}
+static int
+xhci_rh_enable_port(usbdev_t *const dev, int port)
+{
+ if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) {
+ xhci_t *const xhci = XHCI_INST(dev->controller);
+ volatile u32 *const portsc =
+ &xhci->opreg->prs[port - 1].portsc;
+
+ /*
+ * Before send commands to a port, the Port Power in
+ * PORTSC register should be enabled on MTK's xHCI.
+ */
+ *portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PP;
+ }
+ return 0;
+}
+
+
static const generic_hub_ops_t xhci_rh_ops = {
.hub_status_changed = xhci_rh_hub_status_changed,
.port_status_changed = xhci_rh_port_status_changed,
@@ -126,7 +144,7 @@ static const generic_hub_ops_t xhci_rh_ops = {
.port_in_reset = xhci_rh_port_in_reset,
.port_enabled = xhci_rh_port_enabled,
.port_speed = xhci_rh_port_speed,
- .enable_port = NULL,
+ .enable_port = xhci_rh_enable_port,
.disable_port = NULL,
.start_port_reset = NULL,
.reset_port = xhci_rh_reset_port,
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10388
-gerrit
commit e04fbeb28f4eb88fb3f9717abce1d1d0545e484c
Author: Chunfeng Yun <chunfeng.yun(a)mediatek.com>
Date: Thu May 7 15:28:19 2015 +0800
libpayload: usb: Max packet size of SuperSpeed control EPs should be 512.
BRANCH=none
BUG=none
TEST=none
Change-Id: I563ef65db900d7675aeb5b9123dfb5a8980bf964
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 9764115d7bcce1d6423464bd81b58211ac728409
Original-Change-Id: Ibac8d3b9e28b4a563079f288901abcfbff6913ee
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/269863
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com>
---
payloads/libpayload/drivers/usb/usb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c
index 54b113c..b97ba6f 100644
--- a/payloads/libpayload/drivers/usb/usb.c
+++ b/payloads/libpayload/drivers/usb/usb.c
@@ -252,7 +252,7 @@ usb_decode_mps0(usb_speed speed, u8 bMaxPacketSize0)
usb_debug("Invalid MPS0: 0x%02x\n", bMaxPacketSize0);
bMaxPacketSize0 = 9;
}
- return 2 << bMaxPacketSize0;
+ return 1 << bMaxPacketSize0;
default: /* GCC is stupid and cannot deal with enums correctly */
return 8;
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10387
-gerrit
commit 9929f2dcb54b54d456ed4afcb1b6f2265bfd0c75
Author: Wenkai Du <wenkai.du(a)intel.com>
Date: Fri May 29 10:54:27 2015 -0700
TPM: Add Infineon SLB9670 SPI TPM support
This patch provides support for TPM Infineon SLB9670 by adding its
device ID to the list.
BRANCH=None
BUG=chrome-os-partner:40640
TEST=Built and test SLB9670 on SKL U Reference board Fab 2
Change-Id: I2d26fc6c7d074881f2e6189e1325808544b7d26d
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 3c92884be75b631c302801e162292c245ed7bf5d
Original-Change-Id: I4607fc96f70175b2461b40ba61e7a821e187de40
Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/274053
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/drivers/pc80/tpm/tpm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/drivers/pc80/tpm/tpm.c b/src/drivers/pc80/tpm/tpm.c
index 0ee3a90..ba2561d 100644
--- a/src/drivers/pc80/tpm/tpm.c
+++ b/src/drivers/pc80/tpm/tpm.c
@@ -128,6 +128,7 @@ static const struct device_name atmel_devices[] = {
static const struct device_name infineon_devices[] = {
{0x000b, "SLB9635 TT 1.2"},
{0x001a, "SLB9660 TT 1.2"},
+ {0x001b, "SLB9670 TT 1.2"},
{0xffff}
};
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10311
-gerrit
commit feff556ac0cd07a8c3ebe8ad99521f238c663bda
Author: Furquan Shaikh <furquan(a)google.com>
Date: Wed May 20 17:10:55 2015 -0700
arm64: Guard prints in mmu.c
We have observed issues with enabling CONFIG_SMP and adding prints
before MMU is enabled on Tegra-based SoCs. This seems to be related
to the hardware assisted locks and the restrictions laid down by ARMv8
spec.
BUG=None
BRANCH=None
TEST=Boots to kernel prompt on smaug.
Change-Id: I29a52f5a972baf396c01faba3ae3e5ecd27563e9
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: f52ee4b5b2e9b7f54eee0d105cb7e17f9a7e1613
Original-Change-Id: I432895560f468903c7beef00e78b6d38275a619c
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/272449
Original-Trybot-Ready: Furquan Shaikh <furquan(a)chromium.org>
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
src/arch/arm64/armv8/mmu.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm64/armv8/mmu.c b/src/arch/arm64/armv8/mmu.c
index 0bd678a..e16ee71 100644
--- a/src/arch/arm64/armv8/mmu.c
+++ b/src/arch/arm64/armv8/mmu.c
@@ -220,9 +220,12 @@ void mmu_config_range(void *start, size_t size, uint64_t tag)
uint64_t base_addr = (uintptr_t)start;
uint64_t temp_size = size;
- printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
- start, start + size);
- print_tag(BIOS_INFO, tag);
+ if (!IS_ENABLED(CONFIG_SMP)) {
+ printk(BIOS_INFO, "Mapping address range [%p:%p) as ",
+ start, start + size);
+ print_tag(BIOS_INFO, tag);
+ }
+
sanity_check(base_addr, temp_size);
while (temp_size)
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10310
-gerrit
commit 91f088552d3dcf8d22c1b38f0585944e0c18450f
Author: Sourabh Banerjee <sbanerje(a)codeaurora.org>
Date: Fri Apr 24 22:54:18 2015 +0530
ipq806x: clear the RPM initialization Acknowledge bit
The RPM initialization Acknowledge is cleared by writing 1
into bit-10 of the RPM_INT_ACK register.
The existing code got it wrong and is writing zero to that bit.
BRANCH=storm
BUG=chrome-os-partner:39231
TEST=with this patch and an RPM firmware update, an SP4 device
survived more than 1000 reboots in a row.
Change-Id: Ibba296ed0571ad9403a0c51c7f82f07f185b4e83
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 13b4a0f093ba652ad6bccdfc4b3686c0741c6fe7
Original-Change-Id: I39e6ea50e0f66b4af68bdb868dd4437c34bb4524
Original-Signed-off-by: Viswanath Kraleti <vkraleti(a)codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/266969
Original-Reviewed-by: Manoj Juneja <mjuneja(a)qti.qualcomm.com>
---
src/soc/qualcomm/ipq806x/blobs_init.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c
index dc52200..ae7e4d4 100644
--- a/src/soc/qualcomm/ipq806x/blobs_init.c
+++ b/src/soc/qualcomm/ipq806x/blobs_init.c
@@ -131,7 +131,11 @@ void start_rpm(void)
printk(BIOS_INFO, "Starting RPM\n");
/* Clear 'ready' indication. */
- write32(RPM_INT_ACK, read32(RPM_INT_ACK) & ~ready_mask);
+ /*
+ * RPM_INT_ACK is clear-on-write type register,
+ * read-modify-write is not recommended.
+ */
+ write32(RPM_INT_ACK, ready_mask);
/* Set RPM entry address */
write32(RPM_SIGNAL_ENTRY, load_addr);