coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

Patch merged into coreboot/master: 1cac2c9 Hide PLATFORM_USES_FSP1_1.
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 1cac2c9713a864fe90f40040cd1ede130983544c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 30 22:30:13 2015 +0200 Hide PLATFORM_USES_FSP1_1. This should be an internal selectable variable rather than user-visible config. Moreover the description is misleading. This is a typical case of an option "Should it work?" where there is only one right answer yet we still ask it. Change-Id: Idc0ce2e1b9f89eddd034966cc877483d994ce0eb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10378 for details. -gerrit

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Patch merged into coreboot/master: 633352c Kconfig: Remove RELOCATABLE_MODULES.
by gerrit＠coreboot.org 02 Jun '15

02 Jun '15

the following patch was just integrated into master: commit 633352c74ac73567f07eb406e6a95d08b4771555 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 30 22:21:37 2015 +0200 Kconfig: Remove RELOCATABLE_MODULES. RELOCATABLE_MODULES controls inclusion of rmodule support but including it without having anything that uses it is a pure waste of space. So instead make RELOCATABLE_MODULES be selected exactly when there is something using it. Change-Id: I377a955f0cd95b0f811b986df287864c3dc9f89a Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10377 for details. -gerrit

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Patch set updated for coreboot: 7f939e9 cpu/amd/car: Increase Family 10h CAR size limit to 128k
by Timothy Pearson 02 Jun '15

02 Jun '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10402 -gerrit commit 7f939e96ff0d26dee9d2040ee8a77d2a0ba6cc82 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 13:53:25 2015 -0500 cpu/amd/car: Increase Family 10h CAR size limit to 128k This resolves issues with 4-node (32-core) systems not having sufficient CAR memory available to boot. Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/cache_as_ram.inc | 25 +++++++++++++++++++++++-- src/cpu/amd/car/disable_cache_as_ram.c | 7 +++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..e563d67 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -3,6 +3,7 @@ * * Copyright (C) 2005-2007 Advanced Micro Devices, Inc. * Copyright (C) 2008 Carl-Daniel Hailfinger + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -249,8 +250,14 @@ clear_fixed_var_mtrr_out: */ .endm -#if CacheSize > 0x10000 -#error Invalid CAR size, must be at most 64k. +#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) + #if CacheSize > 0x80000 + #error Invalid CAR size, must be at most 128k (processor limit is 512k). + #endif +#else + #if CacheSize > 0x10000 + #error Invalid CAR size, must be at most 64k. + #endif #endif #if CacheSize < 0x1000 #error Invalid CAR size, must be at least 4k. This is a processor limitation. @@ -266,6 +273,20 @@ clear_fixed_var_mtrr_out: wrmsr #endif +#if CacheSize > 0x10000 + /* Enable caching for 64K-96K using fixed MTRR. */ + movl $MTRRfix4K_D0000_MSR, %ecx + simplemask CacheSize, 0x10000 + wrmsr +#endif + +#if CacheSize > 0x18000 + /* Enable caching for 96K-128K using fixed MTRR. */ + movl $MTRRfix4K_D8000_MSR, %ecx + simplemask CacheSize, 0x18000 + wrmsr +#endif + /* Enable caching for 0-32K using fixed MTRR. */ movl $MTRRfix4K_C8000_MSR, %ecx simplemask CacheSize, 0 diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 4a86280..d3a3812 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -4,6 +4,7 @@ * original idea yhlu 6.2005 (assembler code) * * Copyright (C) 2010 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,6 +37,12 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) #if CONFIG_DCACHE_RAM_SIZE > 0x8000 wrmsr(MTRRfix4K_C0000_MSR, msr); #endif +#if CONFIG_DCACHE_RAM_SIZE > 0x10000 + wrmsr(MTRRfix4K_D0000_MSR, msr); +#endif +#if CONFIG_DCACHE_RAM_SIZE > 0x18000 + wrmsr(MTRRfix4K_D8000_MSR, msr); +#endif /* disable fixed mtrr from now on, it will be enabled by ramstage again*/ msr = rdmsr(SYSCFG_MSR);

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New patch to review for coreboot: 27646a2 cpu/amd/car: Increase Family 10h CAR size limit to 128k
by Timothy Pearson 02 Jun '15

02 Jun '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10402 -gerrit commit 27646a2a828a020d5615964b1b250d23b030a36d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 13:53:25 2015 -0500 cpu/amd/car: Increase Family 10h CAR size limit to 128k This resolves issues with 4-node (32-core) systems not having sufficient CAR memory available to boot. Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/cache_as_ram.inc | 24 ++++++++++++++++++++++-- src/cpu/amd/car/disable_cache_as_ram.c | 6 ++++++ 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..89c79e2 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -249,8 +249,14 @@ clear_fixed_var_mtrr_out: */ .endm -#if CacheSize > 0x10000 -#error Invalid CAR size, must be at most 64k. +#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX) + #if CacheSize > 0x80000 + #error Invalid CAR size, must be at most 128k (processor limit is 512k). + #endif +#else + #if CacheSize > 0x10000 + #error Invalid CAR size, must be at most 64k. + #endif #endif #if CacheSize < 0x1000 #error Invalid CAR size, must be at least 4k. This is a processor limitation. @@ -266,6 +272,20 @@ clear_fixed_var_mtrr_out: wrmsr #endif +#if CacheSize > 0x10000 + /* Enable caching for 64K-96K using fixed MTRR. */ + movl $MTRRfix4K_D0000_MSR, %ecx + simplemask CacheSize, 0x10000 + wrmsr +#endif + +#if CacheSize > 0x18000 + /* Enable caching for 96K-128K using fixed MTRR. */ + movl $MTRRfix4K_D8000_MSR, %ecx + simplemask CacheSize, 0x18000 + wrmsr +#endif + /* Enable caching for 0-32K using fixed MTRR. */ movl $MTRRfix4K_C8000_MSR, %ecx simplemask CacheSize, 0 diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index 4a86280..03b6434 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -36,6 +36,12 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) #if CONFIG_DCACHE_RAM_SIZE > 0x8000 wrmsr(MTRRfix4K_C0000_MSR, msr); #endif +#if CONFIG_DCACHE_RAM_SIZE > 0x10000 + wrmsr(MTRRfix4K_D0000_MSR, msr); +#endif +#if CONFIG_DCACHE_RAM_SIZE > 0x18000 + wrmsr(MTRRfix4K_D8000_MSR, msr); +#endif /* disable fixed mtrr from now on, it will be enabled by ramstage again*/ msr = rdmsr(SYSCFG_MSR);

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New patch to review for coreboot: bca178d cpu/amd: Detect any conflicts betwwen sysinfo and the stack region
by Timothy Pearson 02 Jun '15

02 Jun '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10401 -gerrit commit bca178dbb7f2e026363cf3a5931d01c918f7921a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Jun 2 13:47:36 2015 -0500 cpu/amd: Detect any conflicts betwwen sysinfo and the stack region When increasing the number of supported CPUs on AMD Family 10h/15h systems there is a relatively high chance of causing a collision between the CAR global variable region and the AP stack space. Detect collision at runtime and print a warning if collision is present. Change-Id: Ib5c32f868b1dfffb3b840bb1b1df5f55b5a25f8d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/Kconfig | 6 ++++++ src/cpu/amd/car/cache_as_ram.inc | 3 ++- src/cpu/amd/model_10xxx/Kconfig | 8 ++++++++ src/cpu/amd/model_10xxx/init_cpus.c | 7 +++++++ 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index c8dc136..ae2e88c 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -16,6 +16,12 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex +config DCACHE_BSP_STACK_SIZE + hex + +config DCACHE_AP_STACK_SIZE + hex + config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 769e5cf..1c22447 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -24,9 +24,10 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE /* For CAR with Fam10h. */ -#define CacheSizeAPStack 0x400 /* 1K */ +#define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE #define MSR_MCFG_BASE 0xC0010058 #define MSR_FAM10 0xC001102A diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig index cd69cae..4b5cded 100644 --- a/src/cpu/amd/model_10xxx/Kconfig +++ b/src/cpu/amd/model_10xxx/Kconfig @@ -30,6 +30,14 @@ config DCACHE_RAM_SIZE hex default 0x0c000 +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + +config DCACHE_AP_STACK_SIZE + hex + default 0x400 + config UDELAY_IO bool default n diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c index 62ba0b0..aa21f37 100644 --- a/src/cpu/amd/model_10xxx/init_cpus.c +++ b/src/cpu/amd/model_10xxx/init_cpus.c @@ -250,6 +250,13 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) u32 apicid; struct node_core_id id; + void * lower_stack_region_boundary = (void*)((CONFIG_DCACHE_RAM_BASE + (CONFIG_DCACHE_RAM_SIZE / 2)) + - (CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE)); + if (((void*)(sysinfo+1)) > lower_stack_region_boundary) + printk(BIOS_WARNING, + "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", + sysinfo, sysinfo + 1, lower_stack_region_boundary); + /* * already set early mtrr in cache_as_ram.inc */

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New patch to review for coreboot: 51f933f totally harmless commit to test build nodes
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10400 -gerrit commit 51f933fdc9c7e7c4aec02169ab8563477b9c0c3f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Jun 2 19:44:10 2015 +0200 totally harmless commit to test build nodes Change-Id: I4cb0439524ad53423a85916c43b25ba62e591175 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- toolchain.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/toolchain.inc b/toolchain.inc index e089f2e..2fba998 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -1,4 +1,5 @@ ## + ## This file is part of the coreboot project. ## ## Copyright (C) 2014 Google Inc

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Patch set updated for coreboot: 654f701 toolchain.inc: Add x86-64 support
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8690 -gerrit commit 654f70181727e1c22dfd3626c5f8f19b62e929fb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 04:19:58 2015 +0100 toolchain.inc: Add x86-64 support For now, share code with x86, and use the "large" code model. Also align the architecture specific CFLAGS in toolchain.inc for cosmetics. Change-Id: Ie84893d3460115802fbd70c28b10e709029c6b4e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- toolchain.inc | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/toolchain.inc b/toolchain.inc index e089f2e..84aa7fc 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -56,6 +56,7 @@ MAP-libverstage := verstage ARCHDIR-i386 := x86 ARCHDIR-x86_32 := x86 +ARCHDIR-x86_64 := x86 ARCHDIR-arm := arm ARCHDIR-arm64 := arm64 ARCHDIR-riscv := riscv @@ -63,7 +64,7 @@ ARCHDIR-mips := mips CFLAGS_arm := -ffunction-sections -fdata-sections -CFLAGS_arm64 := -ffunction-sections -fdata-sections +CFLAGS_arm64 := -ffunction-sections -fdata-sections CFLAGS_mips := -mips32r2 -G 0 -ffunction-sections -fdata-sections CFLAGS_mips += -mno-abicalls -fno-pic @@ -71,6 +72,8 @@ CFLAGS_mips += -mno-abicalls -fno-pic CFLAGS_x86_32 += -ffunction-sections -fdata-sections CFLAGS_riscv := -ffunction-sections -fdata-sections +CFLAGS_x86_64 := -mcmodel=large + toolchain_to_dir = \ $(foreach arch,$(ARCH_SUPPORTED),\ $(eval CPPFLAGS_$(arch) += \

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Patch set updated for coreboot: 61df27b x86: Make x86 architecture makefiles x64 aware
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8693 -gerrit commit 61df27bd52ef15f76db470d9abacacfa56a03159 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 19:23:50 2015 +0100 x86: Make x86 architecture makefiles x64 aware Almost all of the code between x86 and x64 can be shared, so select it for either architecture. Change-Id: I681149ed7698c08b702bb19f074f369699cef1bf Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Makefile.inc | 25 ++++++++++++++++--------- src/arch/x86/boot/Makefile.inc | 8 ++++---- src/arch/x86/lib/Makefile.inc | 14 ++++++++++---- src/cpu/x86/Makefile.inc | 10 +++++++++- 4 files changed, 39 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 49caef5..902728d 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -60,19 +60,18 @@ cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE)) mbi.bin-type := mbi -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) CBFSTOOL_PRE1_OPTS = -m x86 -s $(CONFIG_ROM_SIZE) \ -o $$(( $(CONFIG_ROM_SIZE) - $(CONFIG_CBFS_SIZE) )) # Make sure that segment for .car.data is ignored while adding romstage. CBFSTOOL_PRE_OPTS = -b $(shell cat $(objcbfs)/base_xip.txt) -S ".car.data" endif - ############################################################################### # bootblock ############################################################################### -ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) +ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32)$(CONFIG_ARCH_BOOTBLOCK_X86_64),y) bootblock-srcs += $(src)/arch/x86/init/failover.ld bootblock-srcs += $(src)/cpu/x86/16bit/entry16.ld @@ -114,7 +113,7 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) $(CFLAGS_x86_32) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm + $(CC_bootblock) $(CFLAGS_bootblock) $(DISASSEMBLY) -c -o $@ $< > $(basename $(a)).disasm $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf " CC $(subst $(obj)/,,$(@))\n" @@ -131,13 +130,13 @@ $(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootbloc $(LD_bootblock) -m elf_i386 -static -o $@ -L$(obj) $< -T $(objgenerated)/bootblock.ld -endif # CONFIG_ARCH_BOOTBLOCK_X86_32 +endif # CONFIG_ARCH_BOOTBLOCK_X86_32 / CONFIG_ARCH_BOOTBLOCK_X86_64 ############################################################################### # romstage ############################################################################### -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) crt0s = $(src)/arch/x86/init/prologue.inc romstage-srcs += $(src)/arch/x86/init/romstage.ld @@ -240,13 +239,13 @@ $(objgenerated)/crt0.S: $$(crt0s) # Compiling crt0 with -g seems to trigger https://sourceware.org/bugzilla/show_bug.cgi?id=6428 romstage-S-ccopts += -I. -g0 -endif # CONFIG_ARCH_ROMSTAGE_X86_32 +endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ############################################################################### # ramstage ############################################################################### -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) ifeq ($(CONFIG_GENERATE_MP_TABLE),y) @@ -292,7 +291,11 @@ ramstage-libs ?= ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_32)) +else +$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE),x86_64)) +endif # The rmodule_link defintion creates an elf file with .rmod extension. $(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod @@ -310,9 +313,13 @@ endif $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group +else + $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group +endif -endif # CONFIG_ARCH_RAMSTAGE_X86_32 +endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 ################################################################################ diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc index 7810ba8..10a1efd 100644 --- a/src/arch/x86/boot/Makefile.inc +++ b/src/arch/x86/boot/Makefile.inc @@ -1,12 +1,12 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-y += cbmem.c romstage-y += boot.c -endif # CONFIG_ARCH_ROMSTAGE_X86_32 +endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-y += boot.c ramstage-y += gdt.c @@ -19,4 +19,4 @@ ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S -endif # CONFIG_ARCH_RAMSTAGE_X86_32 +endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 0d88a6d..1b111d8 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -1,5 +1,5 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-y += cbfs_and_run.c romstage-y += memset.c @@ -7,9 +7,9 @@ romstage-y += memcpy.c romstage-y += memmove.c romstage-y += mmap_boot.c -endif # CONFIG_ARCH_ROMSTAGE_X86_32 +endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-y += c_start.S ramstage-y += cpu.c @@ -33,8 +33,14 @@ smm-y += memcpy.c smm-y += memmove.c smm-y += mmap_boot.c +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) rmodules_x86_32-y += memset.c rmodules_x86_32-y += memcpy.c rmodules_x86_32-y += memmove.c +else +rmodules_x86_64-y += memset.c +rmodules_x86_64-y += memcpy.c +rmodules_x86_64-y += memmove.c +endif -endif # CONFIG_ARCH_RAMSTAGE_X86_32 +endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 34d97ce..9ec0768 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) +ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32)$(CONFIG_ARCH_ROMSTAGE_X86_64),y) romstage-$(CONFIG_CACHE_AS_RAM) += car.c endif @@ -19,11 +19,19 @@ rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S $(SIPI_DOTO): $(dir $(SIPI_ELF))sipi_vector.rmodules_$(ARCH-ramstage-y).o $(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^ +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_32)) +else +$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_ELF:.elf=.o), 0,x86_64)) +endif $(SIPI_BIN): $(SIPI_RMOD) $(OBJCOPY_ramstage) -O binary $< $@ $(SIPI_BIN).ramstage.manual: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" +ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) +else + cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) +endif

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Patch set updated for coreboot: 6d96182 Add x64 support to src/arch/x86/Kconfig
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8692 -gerrit commit 6d961826c99663d3cae2d04bd9f1bbef94b6ed9a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 04:34:03 2015 +0100 Add x64 support to src/arch/x86/Kconfig Change-Id: I81f6d8a21ea0d8218f5a4aab2feb39be32f88e01 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/Kconfig | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 29f0514..1e35846 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -18,6 +18,8 @@ config ARCH_X86 default n select PCI +# stage selectors for x86 + config ARCH_BOOTBLOCK_X86_32 bool default n @@ -35,6 +37,25 @@ config ARCH_RAMSTAGE_X86_32 bool default n +# stage selectors for x64 + +config ARCH_BOOTBLOCK_X86_64 + bool + default n + select ARCH_X86 + +config ARCH_VERSTAGE_X86_64 + bool + default n + +config ARCH_ROMSTAGE_X86_64 + bool + default n + +config ARCH_RAMSTAGE_X86_64 + bool + default n + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description.

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Patch set updated for coreboot: 7f6f31f x86: Make stdint.h x64 proof
by Patrick Georgi 02 Jun '15

02 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8695 -gerrit commit 7f6f31f8424fdebae7b75f0059583c830be77853 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sun Mar 15 19:49:11 2015 +0100 x86: Make stdint.h x64 proof Change-Id: Ibcfdc08c9aac02fe263afd629fc262f71da80e9a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/arch/x86/include/stdint.h | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h index e8453ab..fdfa4d8 100644 --- a/src/arch/x86/include/stdint.h +++ b/src/arch/x86/include/stdint.h @@ -1,5 +1,5 @@ -#ifndef I386_STDINT_H -#define I386_STDINT_H +#ifndef X86_STDINT_H +#define X86_STDINT_H #if defined(__GNUC__) #define __HAVE_LONG_LONG__ 1 @@ -53,8 +53,8 @@ typedef signed long long int_fast64_t; #endif /* Types for `void *' pointers. */ -typedef int intptr_t; -typedef unsigned int uintptr_t; +typedef long intptr_t; +typedef unsigned long uintptr_t; /* Largest integral types */ #if __HAVE_LONG_LONG__ @@ -85,6 +85,18 @@ typedef uint8_t bool; #ifndef UINT64_MAX # define UINT64_MAX (18446744073709551615ULL) #endif + +#if __x86_64__ + +#ifndef UINT64_C +#define UINT64_C(c) c ## UL +#endif +#ifndef PRIu64 +#define PRIu64 "lu" +#endif + +#else + #ifndef UINT64_C #define UINT64_C(c) c ## ULL #endif @@ -92,7 +104,9 @@ typedef uint8_t bool; #define PRIu64 "llu" #endif +#endif + #undef __HAVE_LONG_LONG__ -#endif /* I386_STDINT_H */ +#endif /* X86_STDINT_H */

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coreboot-gerrit June 2015