coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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1226 discussions

New patch to review for coreboot: b158222 crossgcc: Build gmp compatibly
by Patrick Georgi 04 Jun '15

04 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10412 -gerrit commit b158222decea62afcaf6b58db1e153d4cddf0e0c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 00:09:12 2015 +0200 crossgcc: Build gmp compatibly Normally gmp only links in the assembler routines for the system it's built on. Worse, its configure script determines the CPU and select -mtune flags for the compiler. That's neat when you're building for the current machine, but a real problem when building portable binaries. Change-Id: I72d20627270baa082cd02ebb4c9a09cd23f30f8c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/crossgcc/buildgcc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 15bcd92..a1b596e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -22,8 +22,8 @@ cd `dirname $0` -CROSSGCC_DATE="March 8th, 2015" -CROSSGCC_VERSION="1.27" +CROSSGCC_DATE="June 3th, 2015" +CROSSGCC_VERSION="1.28" # default settings TARGETDIR=`pwd`/xgcc @@ -418,7 +418,7 @@ printf "Building GMP ${GMP_VERSION} ... " ( cd ${BUILDDIRPREFIX}-gmp rm -f .failed - CC="$CC" ../${GMP_DIR}/configure --disable-shared --prefix=$TARGETDIR $OPTIONS \ + CC="$CC" CFLAGS="-Os" ../${GMP_DIR}/configure --disable-shared --enable-fat --prefix=$TARGETDIR $OPTIONS \ || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed

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New patch to review for coreboot: 26f59d9 mainboard/lenovo/{t430s, t420s, t520, t530, x220}: Add TPM 1.2 mainboard support
by Philipp Deppenwiese 03 Jun '15

03 Jun '15

Philipp Deppenwiese (zaolin(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10411 -gerrit commit 26f59d968c5afdc0d242fbbc003b6e6e226a5465 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Jun 3 23:09:36 2015 +0200 mainboard/lenovo/{t430s,t420s,t520,t530,x220}: Add TPM 1.2 mainboard support Every Lenovo Thinkpad includes a Trusted Platform Module, so we can enable it for the sandy-/ivybridge platforms. Change-Id: Icda443ba88c2a49a0033014ce7710dd607fa15dc Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t420s/devicetree.cb | 4 ++++ src/mainboard/lenovo/t420s/dsdt.asl | 8 ++++++++ src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t430s/devicetree.cb | 4 ++++ src/mainboard/lenovo/t430s/dsdt.asl | 8 ++++++++ src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t520/devicetree.cb | 4 ++++ src/mainboard/lenovo/t520/dsdt.asl | 8 ++++++++ src/mainboard/lenovo/t530/Kconfig | 1 + src/mainboard/lenovo/t530/devicetree.cb | 4 ++++ src/mainboard/lenovo/t530/dsdt.asl | 8 ++++++++ src/mainboard/lenovo/x220/Kconfig | 1 + src/mainboard/lenovo/x220/devicetree.cb | 4 ++++ src/mainboard/lenovo/x220/dsdt.asl | 8 ++++++++ 15 files changed, 65 insertions(+) diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index be18eb0a..47e70d6 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SANDYBRIDGE_LVDS + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 0385e83..cd70228 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -112,6 +112,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index b40b6db..27dcf54 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -53,6 +53,14 @@ DefinitionBlock( } } + /* + * LPC Trusted Platform Module + */ + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index dbe08b5..0769466 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select IVYBRIDGE_LVDS select ENABLE_VMX + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 54e763e..f3e453e 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -116,6 +116,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index b40b6db..27dcf54 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -53,6 +53,14 @@ DefinitionBlock( } } + /* + * LPC Trusted Platform Module + */ + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 98355d4..56fa395 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SANDYBRIDGE_LVDS + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 4c396e2..ff9745e 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -93,6 +93,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 42165a1..c8591a4 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -52,6 +52,14 @@ DefinitionBlock( } } + /* + * LPC Trusted Platform Module + */ + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 2dcfa90..f144afb 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select IVYBRIDGE_LVDS select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index 09c8b43..e1b22fd 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -98,6 +98,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 42165a1..c8591a4 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -52,6 +52,14 @@ DefinitionBlock( } } + /* + * LPC Trusted Platform Module + */ + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> } diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 006388f..9fa95b9 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SANDYBRIDGE_LVDS select DRIVERS_RICOH_RCE822 + select MAINBOARD_HAS_LPC_TPM # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index e9a4178..9c3aac6 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -126,6 +126,10 @@ chip northbridge/intel/sandybridge register "dock_event_enable" = "0x01" end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/lenovo/h8 device pnp ff.2 on # dummy io 0x60 = 0x62 diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 42165a1..c8591a4 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -52,6 +52,14 @@ DefinitionBlock( } } + /* + * LPC Trusted Platform Module + */ + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/tpm/acpi/tpm.asl> + } + /* Chipset specific sleep states */ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> }

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New patch to review for coreboot: 85572ee update_image: add all CBFS_PREFIX files to cbfs
by Aaron Durbin 03 Jun '15

03 Jun '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10410 -gerrit commit 85572ee56d59a48949a578781da678c48c2086e5 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jun 3 11:54:59 2015 -0500 update_image: add all CBFS_PREFIX files to cbfs In order to accomodate objects not directly linked into ramstage anymore those files need to be added to the image when UPDATE_IMAGE is selected. Otherwise many required pieces are missing from booting correctly. Change-Id: Ic0b24387d24d0af3b75f5fd6fa1795fd381c4d58 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index d5ef301..f07e8cd 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -552,9 +552,18 @@ $(obj)/coreboot.pre1: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(FMAPTOOL) $( $(call add-cpu-microcode-to-cbfs,$@.tmp) mv $@.tmp $@ else +prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) +prebuild-files = \ + $(foreach file,$(filter $(CONFIG_CBFS_PREFIX)/%, $(cbfs-files)), \ + $(if $(call extract_nth,6,$(file)),$(CBFSTOOL) $@.tmp locate -f $(call extract_nth,1,$(file)) -n $(call extract_nth,2,$(file)) -a $(call extract_nth,6,$(file))|xargs -i \ + $(cbfs-add-cmd) -b {} &&,\ + $(cbfs-add-cmd) $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file))) &&)) + .PHONY: $(obj)/coreboot.pre1 -$(obj)/coreboot.pre1: $(CBFSTOOL) - mv $(obj)/coreboot.rom $@ +$(obj)/coreboot.pre1: $$(prebuilt-files) $(CBFSTOOL) + mv $(obj)/coreboot.rom $@.tmp + $(prebuild-files) true + mv $@.tmp $@ endif ifeq ($(CONFIG_PAYLOAD_LINUX),y)

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New patch to review for coreboot: 7702b79 Remove address from GPLv2 headers
by Patrick Georgi 03 Jun '15

03 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10409 -gerrit commit 7702b799664dcda9fe51093f221408b57a633449 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Thu Mar 26 15:17:45 2015 +0100 Remove address from GPLv2 headers Follow up for commit b890a12, some contributions brought back a number of FSF addresses, so get rid of them again. Change-Id: Idcd059f05523916f726b94931c2487ab028b7d72 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/cpu/intel/fsp_model_206ax/smmrelocate.c | 2 +- src/cpu/intel/model_2065x/smmrelocate.c | 2 +- src/cpu/intel/model_206ax/smmrelocate.c | 2 +- src/drivers/intel/gma/igd.asl | 3 +-- 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/smmrelocate.c b/src/cpu/intel/fsp_model_206ax/smmrelocate.c index c2f6712..6b954d0 100644 --- a/src/cpu/intel/fsp_model_206ax/smmrelocate.c +++ b/src/cpu/intel/fsp_model_206ax/smmrelocate.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <types.h> diff --git a/src/cpu/intel/model_2065x/smmrelocate.c b/src/cpu/intel/model_2065x/smmrelocate.c index 94811c3..e357aa5 100644 --- a/src/cpu/intel/model_2065x/smmrelocate.c +++ b/src/cpu/intel/model_2065x/smmrelocate.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #define __SIMPLE_DEVICE__ diff --git a/src/cpu/intel/model_206ax/smmrelocate.c b/src/cpu/intel/model_206ax/smmrelocate.c index 587fee9..461286f 100644 --- a/src/cpu/intel/model_206ax/smmrelocate.c +++ b/src/cpu/intel/model_206ax/smmrelocate.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc. */ #include <types.h> diff --git a/src/drivers/intel/gma/igd.asl b/src/drivers/intel/gma/igd.asl index 31e8fec..88cc2cd 100644 --- a/src/drivers/intel/gma/igd.asl +++ b/src/drivers/intel/gma/igd.asl @@ -15,8 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc. */ External(LCD0, DeviceObj)

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New patch to review for coreboot: dbbd9f7 veyron_mickey: Initial import
by Patrick Georgi 03 Jun '15

03 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10408 -gerrit commit dbbd9f7b793ce0ef0dbf3c200a99f7eb7d298e1b Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed May 13 13:58:24 2015 -0700 veyron_mickey: Initial import This simply copies veyron_brain to veyron_mickey and makes the minimal set of changes (s/brain/mickey) to make it compile. The follow-up patch will take into account board differences. BUG=none BRANCH=none TEST="emerge-veyron_mickey coreboot" doesn't fail Change-Id: I7d029b36d2fb865446490b896117ade632325a52 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 34f6b391290f99caf517d7e98c31c89dc57309be Original-Change-Id: I03a2b80eb441384f363910467180479521765431 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271360 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_mickey/Kconfig | 80 ++++++++++++++ src/mainboard/google/veyron_mickey/Kconfig.name | 2 + src/mainboard/google/veyron_mickey/Makefile.inc | 41 +++++++ src/mainboard/google/veyron_mickey/board.h | 30 +++++ src/mainboard/google/veyron_mickey/boardid.c | 49 +++++++++ src/mainboard/google/veyron_mickey/bootblock.c | 76 +++++++++++++ src/mainboard/google/veyron_mickey/chromeos.c | 103 ++++++++++++++++++ src/mainboard/google/veyron_mickey/devicetree.cb | 25 +++++ src/mainboard/google/veyron_mickey/mainboard.c | 117 ++++++++++++++++++++ src/mainboard/google/veyron_mickey/memlayout.ld | 1 + src/mainboard/google/veyron_mickey/reset.c | 30 +++++ src/mainboard/google/veyron_mickey/romstage.c | 121 +++++++++++++++++++++ src/mainboard/google/veyron_mickey/sdram_configs.c | 54 +++++++++ .../sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 +++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 +++++++++++++ .../veyron_mickey/sdram_inf/sdram-unused.inc | 3 + 24 files changed, 1510 insertions(+) diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig new file mode 100644 index 0000000..2337e5b --- /dev/null +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -0,0 +1,80 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +if BOARD_GOOGLE_VEYRON_MICKEY + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_4096 + select COMMON_CBFS_SPI_WRAPPER + select HAVE_HARD_RESET + select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS + select RAM_CODE_SUPPORT + select RETURN_FROM_VERSTAGE + select SOC_ROCKCHIP_RK3288 + select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND + select VIRTUAL_DEV_SWITCH + select CHROMEOS_VBNV_FLASH + +config MAINBOARD_DIR + string + default google/veyron_mickey + +config MAINBOARD_PART_NUMBER + string + default "Veyron_mickey" + +config MAINBOARD_VENDOR + string + default "Google" + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0xFF690000 + +# FIXME(dhendrix): This is a gross hack intended to get us past +# display init which currently hangs the machine. It will be removed +# once we've re-factored the display init code to properly handle +# various types of displays. +config SKIP_DISPLAY_INIT_HACK + int + default 1 + +config PMIC_BUS + int + default 0 + +endif # BOARD_GOOGLE_VEYRON_MICKEY diff --git a/src/mainboard/google/veyron_mickey/Kconfig.name b/src/mainboard/google/veyron_mickey/Kconfig.name new file mode 100644 index 0000000..622b10f --- /dev/null +++ b/src/mainboard/google/veyron_mickey/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_VEYRON_Mickey + bool "Veyron_Mickey" diff --git a/src/mainboard/google/veyron_mickey/Makefile.inc b/src/mainboard/google/veyron_mickey/Makefile.inc new file mode 100644 index 0000000..a027c6d --- /dev/null +++ b/src/mainboard/google/veyron_mickey/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## +bootblock-y += bootblock.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += romstage.c +romstage-y += sdram_configs.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_mickey/board.h b/src/mainboard/google/veyron_mickey/board.h new file mode 100644 index 0000000..98ffce0 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/board.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H + +#include <boardid.h> +#include <gpio.h> + +#define GPIO_RESET GPIO(0, B, 5) + +void setup_chromeos_gpios(void); + +#endif /* __MAINBOARD_GOOGLE_VEYRON_MICKEY_BOARD_H */ diff --git a/src/mainboard/google/veyron_mickey/boardid.c b/src/mainboard/google/veyron_mickey/boardid.c new file mode 100644 index 0000000..f7cddcc --- /dev/null +++ b/src/mainboard/google/veyron_mickey/boardid.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boardid.h> +#include <console/console.h> +#include <gpio.h> +#include <stdlib.h> + +uint8_t board_id(void) +{ + static int id = -1; + static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ + + if (id < 0) { + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "Board ID: %d.\n", id); + } + + return id; +} + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "RAM Config: %u.\n", code); + + return code; +} diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c new file mode 100644 index 0000000..a4a756d --- /dev/null +++ b/src/mainboard/google/veyron_mickey/bootblock.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <assert.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <delay.h> +#include <reset.h> +#include <soc/clock.h> +#include <soc/i2c.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +void bootblock_mainboard_early_init() +{ + if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); + write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); + } + +} + +void bootblock_mainboard_init(void) +{ + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + + gpio_output(GPIO(7, A, 0), 1); /* Power LED */ + + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ + i2c_init(CONFIG_PMIC_BUS, 400*KHz); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ + rkclk_configure_cpu(); + + /* i2c1 for tpm */ + write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); + i2c_init(1, 400*KHz); + + /* spi2 for firmware ROM */ + write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); + write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c new file mode 100644 index 0000000..20e679b --- /dev/null +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_POWER GPIO(0, A, 5) +#define GPIO_RECOVERY GPIO(0, B, 1) + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input(GPIO_POWER); + gpio_input_pullup(GPIO_RECOVERY); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_WP.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(GPIO_WP); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active low */ + gpios->gpios[count].port = GPIO_RECOVERY.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Power Button: GPIO active low */ + gpios->gpios[count].port = GPIO_POWER.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Reset: GPIO active high (output) */ + gpios->gpios[count].port = GPIO_RESET.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "reset", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return !gpio_get(GPIO_RECOVERY); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} + diff --git a/src/mainboard/google/veyron_mickey/devicetree.cb b/src/mainboard/google/veyron_mickey/devicetree.cb new file mode 100644 index 0000000..4c2ea8f --- /dev/null +++ b/src/mainboard/google/veyron_mickey/devicetree.cb @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + register "vop_id" = "1" + register "framebuffer_bits_per_pixel" = "16" +end diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c new file mode 100644 index 0000000..a5c40c23 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/i2c.h> +#include <edid.h> +#include <elog.h> +#include <gpio.h> +#include <soc/display.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <soc/clock.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <soc/i2c.h> +#include <symbols.h> +#include <vbe.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +static void configure_usb(void) +{ + gpio_output(GPIO(0, B, 4), 1); /* USB2_PWR_EN */ +} + +static void configure_emmc(void) +{ + write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA); + write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN); + write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD); + + gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */ +} + +static void configure_codec(void) +{ + write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */ + i2c_init(2, 400*KHz); /* CODEC I2C */ + + write32(&rk3288_grf->iomux_i2s, IOMUX_I2S); + write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK); + + rk808_configure_ldo(6, 1800); /* VCC18_CODEC */ + + /* AUDIO IO domain 1.8V voltage selection */ + write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6)); + rkclk_configure_i2s(12288000); +} + +static void configure_vop(void) +{ + write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC); + + /* lcdc(vop) iodomain select 1.8V */ + write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0)); + + rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */ + rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */ + rk808_configure_switch(1, 1); /* VCC33_LCD */ +} + +static void mainboard_init(device_t dev) +{ + gpio_output(GPIO_RESET, 0); + + configure_usb(); + configure_emmc(); + configure_codec(); + configure_vop(); + + elog_init(); + elog_add_watchdog_reset(); + elog_add_boot_reason(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; +} diff --git a/src/mainboard/google/veyron_mickey/memlayout.ld b/src/mainboard/google/veyron_mickey/memlayout.ld new file mode 100644 index 0000000..ead7f47 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/memlayout.ld @@ -0,0 +1 @@ +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/veyron_mickey/reset.c b/src/mainboard/google/veyron_mickey/reset.c new file mode 100644 index 0000000..bc26ece --- /dev/null +++ b/src/mainboard/google/veyron_mickey/reset.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <gpio.h> +#include <reset.h> + +#include "board.h" + +void hard_reset(void) +{ + gpio_output(GPIO_RESET, 1); + while (1); +} diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c new file mode 100644 index 0000000..9f7b1a5 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/cache.h> +#include <arch/exception.h> +#include <arch/stages.h> +#include <armv7.h> +#include <assert.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <delay.h> +#include <program_loading.h> +#include <soc/sdram.h> +#include <soc/clock.h> +#include <soc/pwm.h> +#include <soc/grf.h> +#include <soc/rk808.h> +#include <soc/tsadc.h> +#include <stdlib.h> +#include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +static void regulate_vdd_log(unsigned int mv) +{ + unsigned int duty_ns; + const u32 period_ns = 2000; /* pwm period: 2000ns */ + const u32 max_regulator_mv = 1350; /* 1.35V */ + const u32 min_regulator_mv = 870; /* 0.87V */ + + write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1); + + assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); + + duty_ns = (max_regulator_mv - mv) * period_ns / + (max_regulator_mv - min_regulator_mv); + + pwm_init(1, period_ns, duty_ns); +} + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + +void main(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t start_romstage_time; + uint64_t before_dram_time; + uint64_t after_dram_time; + uint64_t base_time = timestamp_get(); + start_romstage_time = timestamp_get(); +#endif + + console_init(); + configure_l2ctlr(); + tsadc_init(); + + /* vdd_log 1200mv is enough for ddr run 666Mhz */ + regulate_vdd_log(1200); +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); +#endif + sdram_init(get_sdram_config()); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); +#endif + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + sdram_size_mb(), DCACHE_WRITEBACK); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); + + cbmem_initialize_empty(); + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + + run_ramstage(); +} diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c new file mode 100644 index 0000000..63e7317 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <arch/io.h> +#include <boardid.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/sdram.h> +#include <string.h> +#include <types.h> + +static struct rk3288_sdram_params sdram_configs[] = { +#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */ +#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ +#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ +#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ +}; + +const struct rk3288_sdram_params *get_sdram_config() +{ + u32 ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) + || sdram_configs[ramcode].dramtype == UNUSED) + die("Invalid RAMCODE."); + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-hynix-2GB.inc new file mode 100644 index 0000000..659cfd4 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-hynix-4GB.inc new file mode 100644 index 0000000..9f2ca8a --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-hynix-4GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Hynix H5TC8G63xxx chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 13, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc new file mode 100644 index 0000000..f5793d1 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4B4G1646D-BYK0 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-4GB.inc new file mode 100644 index 0000000..a32f1a6 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-ddr3-samsung-4GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Samsung K4B8G1646Q chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 13, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-2GB.inc new file mode 100644 index 0000000..ef82b27 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two ELPIDA F8132A3MA-GD-F chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-4GB.inc new file mode 100644 index 0000000..e071646 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-elpida-4GB.inc @@ -0,0 +1,78 @@ +{ + /* two ELPIDA FA232A2MA-GC-F chips */ + { + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 6, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0 +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc new file mode 100644 index 0000000..00dc549 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Hynix H9CCNNN8GTMLAR chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-4GB.inc new file mode 100644 index 0000000..a48ac42 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-4GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc new file mode 100644 index 0000000..0f15ba5 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4E8E304ED-EGCE000 chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB.inc new file mode 100644 index 0000000..09d260b --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 6, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-unused.inc new file mode 100644 index 0000000..06498f7 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-unused.inc @@ -0,0 +1,3 @@ +{ + .dramtype= UNUSED +}, \ No newline at end of file

1 0

New patch to review for coreboot: e82bd47 veyron_romy: Initial import
by Patrick Georgi 03 Jun '15

03 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10407 -gerrit commit e82bd47e74be42decb7f2d23464bb466efd3aa66 Author: David Hendricks <dhendrix(a)chromium.org> Date: Wed May 13 14:29:23 2015 -0700 veyron_romy: Initial import This simply copies veyron_brain to veyron_romy and makes the minimal set of changes (s/brain/romy) to make it compile. The follow-up patch will take into account board differences. BUG=none BRANCH=none TEST="emerge-veyron_romy coreboot" doesn't fail Change-Id: Ice1bc012bddd6c51b43944747e0df3ffa34207fa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0ab849178b69cf2323f126e503bd61080048240a Original-Change-Id: I0516ce94fd3c6a38170fae221a070f503ccfaf0f Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271345 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_romy/Kconfig | 80 ++++++++++++++ src/mainboard/google/veyron_romy/Kconfig.name | 2 + src/mainboard/google/veyron_romy/Makefile.inc | 41 +++++++ src/mainboard/google/veyron_romy/board.h | 30 +++++ src/mainboard/google/veyron_romy/boardid.c | 49 +++++++++ src/mainboard/google/veyron_romy/bootblock.c | 76 +++++++++++++ src/mainboard/google/veyron_romy/chromeos.c | 103 ++++++++++++++++++ src/mainboard/google/veyron_romy/devicetree.cb | 25 +++++ src/mainboard/google/veyron_romy/mainboard.c | 117 ++++++++++++++++++++ src/mainboard/google/veyron_romy/memlayout.ld | 1 + src/mainboard/google/veyron_romy/reset.c | 30 +++++ src/mainboard/google/veyron_romy/romstage.c | 121 +++++++++++++++++++++ src/mainboard/google/veyron_romy/sdram_configs.c | 54 +++++++++ .../veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc | 78 +++++++++++++ .../veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-ddr3-samsung-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-ddr3-samsung-4GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-elpida-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-elpida-4GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-hynix-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-hynix-4GB.inc | 77 +++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-2GB.inc | 78 +++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB.inc | 77 +++++++++++++ .../google/veyron_romy/sdram_inf/sdram-unused.inc | 3 + 24 files changed, 1510 insertions(+) diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig new file mode 100644 index 0000000..f96a3e9 --- /dev/null +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -0,0 +1,80 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +if BOARD_GOOGLE_VEYRON_ROMY + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ID_AUTO + select BOARD_ROMSIZE_KB_4096 + select COMMON_CBFS_SPI_WRAPPER + select HAVE_HARD_RESET + select MAINBOARD_DO_NATIVE_VGA_INIT + select MAINBOARD_HAS_CHROMEOS + select RAM_CODE_SUPPORT + select RETURN_FROM_VERSTAGE + select SOC_ROCKCHIP_RK3288 + select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND + select VIRTUAL_DEV_SWITCH + select CHROMEOS_VBNV_FLASH + +config MAINBOARD_DIR + string + default google/veyron_romy + +config MAINBOARD_PART_NUMBER + string + default "Veyron_Romy" + +config MAINBOARD_VENDOR + string + default "Google" + +config BOOT_MEDIA_SPI_BUS + int + default 2 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x20 + +config CONSOLE_SERIAL_UART_ADDRESS + hex + depends on DRIVERS_UART + default 0xFF690000 + +# FIXME(dhendrix): This is a gross hack intended to get us past +# display init which currently hangs the machine. It will be removed +# once we've re-factored the display init code to properly handle +# various types of displays. +config SKIP_DISPLAY_INIT_HACK + int + default 1 + +config PMIC_BUS + int + default 0 + +endif # BOARD_GOOGLE_VEYRON_ROMY diff --git a/src/mainboard/google/veyron_romy/Kconfig.name b/src/mainboard/google/veyron_romy/Kconfig.name new file mode 100644 index 0000000..5c02b7e --- /dev/null +++ b/src/mainboard/google/veyron_romy/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_VEYRON_ROMY + bool "Veyron_Romy" diff --git a/src/mainboard/google/veyron_romy/Makefile.inc b/src/mainboard/google/veyron_romy/Makefile.inc new file mode 100644 index 0000000..a027c6d --- /dev/null +++ b/src/mainboard/google/veyron_romy/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## +bootblock-y += bootblock.c +bootblock-y += boardid.c +bootblock-y += chromeos.c +bootblock-y += reset.c + +verstage-y += boardid.c +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += boardid.c +romstage-y += romstage.c +romstage-y += sdram_configs.c +romstage-y += reset.c + +ramstage-y += boardid.c +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c + +bootblock-y += memlayout.ld +verstage-y += memlayout.ld +romstage-y += memlayout.ld +ramstage-y += memlayout.ld diff --git a/src/mainboard/google/veyron_romy/board.h b/src/mainboard/google/veyron_romy/board.h new file mode 100644 index 0000000..631e3a0 --- /dev/null +++ b/src/mainboard/google/veyron_romy/board.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H +#define __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H + +#include <boardid.h> +#include <gpio.h> + +#define GPIO_RESET GPIO(0, B, 5) + +void setup_chromeos_gpios(void); + +#endif /* __MAINBOARD_GOOGLE_VEYRON_ROMY_BOARD_H */ diff --git a/src/mainboard/google/veyron_romy/boardid.c b/src/mainboard/google/veyron_romy/boardid.c new file mode 100644 index 0000000..f7cddcc --- /dev/null +++ b/src/mainboard/google/veyron_romy/boardid.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boardid.h> +#include <console/console.h> +#include <gpio.h> +#include <stdlib.h> + +uint8_t board_id(void) +{ + static int id = -1; + static gpio_t pins[] = {[3] = GPIO(2, A, 7), [2] = GPIO(2, A, 2), + [1] = GPIO(2, A, 1), [0] = GPIO(2, A, 0)}; /* GPIO2_A0 is LSB */ + + if (id < 0) { + id = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "Board ID: %d.\n", id); + } + + return id; +} + +uint32_t ram_code(void) +{ + uint32_t code; + static gpio_t pins[] = {[3] = GPIO(8, A, 3), [2] = GPIO(8, A, 2), + [1] = GPIO(8, A, 1), [0] = GPIO(8, A, 0)}; /* GPIO8_A0 is LSB */ + + code = gpio_base2_value(pins, ARRAY_SIZE(pins)); + printk(BIOS_SPEW, "RAM Config: %u.\n", code); + + return code; +} diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c new file mode 100644 index 0000000..a4a756d --- /dev/null +++ b/src/mainboard/google/veyron_romy/bootblock.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <assert.h> +#include <bootblock_common.h> +#include <console/console.h> +#include <delay.h> +#include <reset.h> +#include <soc/clock.h> +#include <soc/i2c.h> +#include <soc/grf.h> +#include <soc/pmu.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +void bootblock_mainboard_early_init() +{ + if (IS_ENABLED(CONFIG_DRIVERS_UART)) { + assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE); + write32(&rk3288_grf->iomux_uart2, IOMUX_UART2); + } + +} + +void bootblock_mainboard_init(void) +{ + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + + gpio_output(GPIO(7, A, 0), 1); /* Power LED */ + + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ + setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); + setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); + assert(CONFIG_PMIC_BUS == 0); /* must correspond with IOMUX */ + i2c_init(CONFIG_PMIC_BUS, 400*KHz); + + /* Slowly raise to max CPU voltage to prevent overshoot */ + rk808_configure_buck(1, 1200); + udelay(175);/* Must wait for voltage to stabilize,2mV/us */ + rk808_configure_buck(1, 1400); + udelay(100);/* Must wait for voltage to stabilize,2mV/us */ + rkclk_configure_cpu(); + + /* i2c1 for tpm */ + write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1); + i2c_init(1, 400*KHz); + + /* spi2 for firmware ROM */ + write32(&rk3288_grf->iomux_spi2csclk, IOMUX_SPI2_CSCLK); + write32(&rk3288_grf->iomux_spi2txrx, IOMUX_SPI2_TXRX); + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + + setup_chromeos_gpios(); +} diff --git a/src/mainboard/google/veyron_romy/chromeos.c b/src/mainboard/google/veyron_romy/chromeos.c new file mode 100644 index 0000000..20e679b --- /dev/null +++ b/src/mainboard/google/veyron_romy/chromeos.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +#define GPIO_WP GPIO(7, A, 6) +#define GPIO_POWER GPIO(0, A, 5) +#define GPIO_RECOVERY GPIO(0, B, 1) + +void setup_chromeos_gpios(void) +{ + gpio_input(GPIO_WP); + gpio_input(GPIO_POWER); + gpio_input_pullup(GPIO_RECOVERY); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_WP.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(GPIO_WP); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active low */ + gpios->gpios[count].port = GPIO_RECOVERY.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get(GPIO_RECOVERY); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Power Button: GPIO active low */ + gpios->gpios[count].port = GPIO_POWER.raw; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Reset: GPIO active high (output) */ + gpios->gpios[count].port = GPIO_RESET.raw; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = -1; + strncpy((char *)gpios->gpios[count].name, "reset", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + return !gpio_get(GPIO_RECOVERY); +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP); +} + diff --git a/src/mainboard/google/veyron_romy/devicetree.cb b/src/mainboard/google/veyron_romy/devicetree.cb new file mode 100644 index 0000000..4c2ea8f --- /dev/null +++ b/src/mainboard/google/veyron_romy/devicetree.cb @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2014 Rockchip Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +# TODO fill with Versatile Express board data in QEMU. +chip soc/rockchip/rk3288 + device cpu_cluster 0 on end + register "vop_id" = "1" + register "framebuffer_bits_per_pixel" = "16" +end diff --git a/src/mainboard/google/veyron_romy/mainboard.c b/src/mainboard/google/veyron_romy/mainboard.c new file mode 100644 index 0000000..2f61d01 --- /dev/null +++ b/src/mainboard/google/veyron_romy/mainboard.c @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/cache.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/i2c.h> +#include <edid.h> +#include <elog.h> +#include <gpio.h> +#include <soc/display.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <soc/pmu.h> +#include <soc/clock.h> +#include <soc/rk808.h> +#include <soc/spi.h> +#include <soc/i2c.h> +#include <symbols.h> +#include <vbe.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +static void configure_usb(void) +{ + gpio_output(GPIO(0, B, 4), 1); /* USBOTG_PWREN_H */ +} + +static void configure_emmc(void) +{ + write32(&rk3288_grf->iomux_emmcdata, IOMUX_EMMCDATA); + write32(&rk3288_grf->iomux_emmcpwren, IOMUX_EMMCPWREN); + write32(&rk3288_grf->iomux_emmccmd, IOMUX_EMMCCMD); + + gpio_output(GPIO(2, B, 1), 1); /* EMMC_RST_L */ +} + +static void configure_codec(void) +{ + write32(&rk3288_grf->iomux_i2c2, IOMUX_I2C2); /* CODEC I2C */ + i2c_init(2, 400*KHz); /* CODEC I2C */ + + write32(&rk3288_grf->iomux_i2s, IOMUX_I2S); + write32(&rk3288_grf->iomux_i2sclk, IOMUX_I2SCLK); + + rk808_configure_ldo(6, 1800); /* VCC18_CODEC */ + + /* AUDIO IO domain 1.8V voltage selection */ + write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 6)); + rkclk_configure_i2s(12288000); +} + +static void configure_vop(void) +{ + write32(&rk3288_grf->iomux_lcdc, IOMUX_LCDC); + + /* lcdc(vop) iodomain select 1.8V */ + write32(&rk3288_grf->io_vsel, RK_SETBITS(1 << 0)); + + rk808_configure_switch(2, 1); /* VCC18_LCD (HDMI_AVDD_1V8) */ + rk808_configure_ldo(7, 1000); /* VDD10_LCD (HDMI_AVDD_1V0) */ + rk808_configure_switch(1, 1); /* VCC33_LCD */ +} + +static void mainboard_init(device_t dev) +{ + gpio_output(GPIO_RESET, 0); + + configure_usb(); + configure_emmc(); + configure_codec(); + configure_vop(); + + elog_init(); + elog_add_watchdog_reset(); + elog_add_boot_reason(); +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (uintptr_t)_dma_coherent; + dma->range_size = _dma_coherent_size; +} diff --git a/src/mainboard/google/veyron_romy/memlayout.ld b/src/mainboard/google/veyron_romy/memlayout.ld new file mode 100644 index 0000000..ead7f47 --- /dev/null +++ b/src/mainboard/google/veyron_romy/memlayout.ld @@ -0,0 +1 @@ +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/veyron_romy/reset.c b/src/mainboard/google/veyron_romy/reset.c new file mode 100644 index 0000000..bc26ece --- /dev/null +++ b/src/mainboard/google/veyron_romy/reset.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <gpio.h> +#include <reset.h> + +#include "board.h" + +void hard_reset(void) +{ + gpio_output(GPIO_RESET, 1); + while (1); +} diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c new file mode 100644 index 0000000..9f7b1a5 --- /dev/null +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/cache.h> +#include <arch/exception.h> +#include <arch/stages.h> +#include <armv7.h> +#include <assert.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <delay.h> +#include <program_loading.h> +#include <soc/sdram.h> +#include <soc/clock.h> +#include <soc/pwm.h> +#include <soc/grf.h> +#include <soc/rk808.h> +#include <soc/tsadc.h> +#include <stdlib.h> +#include <symbols.h> +#include <timestamp.h> +#include <types.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include "board.h" + +static void regulate_vdd_log(unsigned int mv) +{ + unsigned int duty_ns; + const u32 period_ns = 2000; /* pwm period: 2000ns */ + const u32 max_regulator_mv = 1350; /* 1.35V */ + const u32 min_regulator_mv = 870; /* 0.87V */ + + write32(&rk3288_grf->iomux_pwm1, IOMUX_PWM1); + + assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); + + duty_ns = (max_regulator_mv - mv) * period_ns / + (max_regulator_mv - min_regulator_mv); + + pwm_init(1, period_ns, duty_ns); +} + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} + +void main(void) +{ +#if CONFIG_COLLECT_TIMESTAMPS + uint64_t start_romstage_time; + uint64_t before_dram_time; + uint64_t after_dram_time; + uint64_t base_time = timestamp_get(); + start_romstage_time = timestamp_get(); +#endif + + console_init(); + configure_l2ctlr(); + tsadc_init(); + + /* vdd_log 1200mv is enough for ddr run 666Mhz */ + regulate_vdd_log(1200); +#if CONFIG_COLLECT_TIMESTAMPS + before_dram_time = timestamp_get(); +#endif + sdram_init(get_sdram_config()); +#if CONFIG_COLLECT_TIMESTAMPS + after_dram_time = timestamp_get(); +#endif + + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ + mmu_config_range((uintptr_t)_dram/MiB, + sdram_size_mb(), DCACHE_WRITEBACK); + mmu_config_range((uintptr_t)_dma_coherent/MiB, + _dma_coherent_size/MiB, DCACHE_OFF); + + cbmem_initialize_empty(); + +#if CONFIG_COLLECT_TIMESTAMPS + timestamp_init(base_time); + timestamp_add(TS_START_ROMSTAGE, start_romstage_time); + timestamp_add(TS_BEFORE_INITRAM, before_dram_time); + timestamp_add(TS_AFTER_INITRAM, after_dram_time); + timestamp_add_now(TS_END_ROMSTAGE); +#endif + + run_ramstage(); +} diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c new file mode 100644 index 0000000..63e7317 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_configs.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ +#include <arch/io.h> +#include <boardid.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/sdram.h> +#include <string.h> +#include <types.h> + +static struct rk3288_sdram_params sdram_configs[] = { +#include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ +#include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ +#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ +#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */ +#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */ +#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ +#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ +#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ +#include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ +}; + +const struct rk3288_sdram_params *get_sdram_config() +{ + u32 ramcode = ram_code(); + + if (ramcode >= ARRAY_SIZE(sdram_configs) + || sdram_configs[ramcode].dramtype == UNUSED) + die("Invalid RAMCODE."); + return &sdram_configs[ramcode]; +} diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc new file mode 100644 index 0000000..659cfd4 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Hynic H5TC4G63CFR(0101b) or H5TC4G63AFR(1101b) chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc new file mode 100644 index 0000000..9f2ca8a --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-hynix-4GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Hynix H5TC8G63xxx chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 13, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-2GB.inc new file mode 100644 index 0000000..f5793d1 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4B4G1646D-BYK0 chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 9, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-4GB.inc new file mode 100644 index 0000000..a32f1a6 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-ddr3-samsung-4GB.inc @@ -0,0 +1,78 @@ +{ + /* 4 Samsung K4B8G1646Q chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x29A, + .tinit = 0xC8, + .trsth = 0x1F4, + .togcnt100n = 0x42, + .trefi = 0x4E, + .tmrd = 0x4, + .trfc = 0xEA, + .trp = 0xA, + .trtw = 0x5, + .tal = 0x0, + .tcl = 0xA, + .tcwl = 0x7, + .tras = 0x19, + .trc = 0x24, + .trcd = 0xA, + .trrd = 0x7, + .trtp = 0x5, + .twr = 0xA, + .twtr = 0x5, + .texsr = 0x200, + .txp = 0x5, + .txpdll = 0x10, + .tzqcs = 0x40, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x7, + .tcksrx = 0x7, + .tcke = 0x4, + .tmod = 0xC, + .trstl = 0x43, + .tzqcl = 0x100, + .tmrr = 0x0, + .tckesr = 0x5, + .tdpd = 0x0 + }, + { + .dtpr0 = 0x48F9AAB4, + .dtpr1 = 0xEA0910, + .dtpr2 = 0x1002C200, + .mr[0] = 0xA60, + .mr[1] = 0x40, + .mr[2] = 0x10, + .mr[3] = 0x0 + }, + .noc_timing = 0x30B25564, + .noc_activate = 0x627, + .ddrconfig = 3, + .ddr_freq = 666*MHz, + .dramtype = DDR3, + .num_channels = 2, + .stride = 13, + .odt = 1 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-2GB.inc new file mode 100644 index 0000000..ef82b27 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two ELPIDA F8132A3MA-GD-F chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc new file mode 100644 index 0000000..e071646 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-elpida-4GB.inc @@ -0,0 +1,78 @@ +{ + /* two ELPIDA FA232A2MA-GC-F chips */ + { + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 6, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0 +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc new file mode 100644 index 0000000..00dc549 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Hynix H9CCNNN8GTMLAR chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-4GB.inc new file mode 100644 index 0000000..a48ac42 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-4GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB.inc new file mode 100644 index 0000000..0f15ba5 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB.inc @@ -0,0 +1,78 @@ +{ + /* two Samsung K4E8E304ED-EGCE000 chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 2, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB.inc new file mode 100644 index 0000000..09d260b --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + }, + { + .rank = 0x2, + .col = 0xB, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x1, + .row_3_4 = 0x0, + .cs0_row = 0xE, + .cs1_row = 0xE + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 6, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc new file mode 100644 index 0000000..06498f7 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-unused.inc @@ -0,0 +1,3 @@ +{ + .dramtype= UNUSED +}, \ No newline at end of file

1 0

Patch set updated for coreboot: 494665a lib: Unify log2() and related functions
by Patrick Georgi 03 Jun '15

03 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10394 -gerrit commit 494665a31627b3f6f64539cea559f6c8d27d5313 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 22 16:26:40 2015 -0700 lib: Unify log2() and related functions This patch adds a few bit counting functions that are commonly needed for certain register calculations. We previously had a log2() implementation already, but it was awkwardly split between some C code that's only available in ramstage and an optimized x86-specific implementation in pre-RAM that prevented other archs from pulling it into earlier stages. Using __builtin_clz() as the baseline allows GCC to inline optimized assembly for most archs (including CLZ on ARM/ARM64 and BSR on x86), and to perform constant-folding if possible. What was previously named log2f on pre-RAM x86 is now ffs, since that's the standard name for that operation and I honestly don't have the slightest idea how it could've ever ended up being called log2f (which in POSIX is 'binary(2) LOGarithm with Float result, whereas the Find First Set operation has no direct correlation to logarithms that I know of). Make ffs result 0-based instead of the POSIX standard's 1-based since that is consistent with clz, log2 and the former log2f, and generally closer to what you want for most applications (a value that can directly be used as a shift to reach the found bit). Call it __ffs() instead of ffs() to avoid problems when importing code, since that's what Linux uses for the 0-based operation. CQ-DEPEND=CL:273023 BRANCH=None BUG=None TEST=Built on Big, Falco, Jerry, Oak and Urara. Compared old and new log2() and __ffs() results on Falco for a bunch of test values. Change-Id: I599209b342059e17b3130621edb6b6bbeae26876 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3701a16ae944ecff9c54fa9a50d28015690fcb2f Original-Change-Id: I60f7cf893792508188fa04d088401a8bca4b4af6 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/273008 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> --- payloads/libpayload/include/libpayload.h | 7 +++ payloads/libpayload/include/strings.h | 35 -------------- payloads/libpayload/libc/Makefile.inc | 4 +- payloads/libpayload/libc/libgcc.c | 68 +++++++++++++++++++++++++++ payloads/libpayload/libc/strings.c | 42 ----------------- src/arch/arm/include/utils.h | 55 ---------------------- src/arch/x86/include/arch/io.h | 8 ++-- src/include/lib.h | 18 ++++--- src/lib/Makefile.inc | 6 +-- src/lib/clog2.c | 37 --------------- src/lib/libgcc.c | 56 ++++++++++++++++++++++ src/northbridge/amd/amdk8/coherent_ht.c | 1 + src/northbridge/amd/amdk8/raminit.c | 5 +- src/northbridge/amd/amdk8/raminit_f.c | 1 + src/northbridge/amd/amdk8/raminit_test.c | 1 + src/northbridge/intel/e7501/raminit.c | 1 + src/northbridge/intel/i3100/raminit_ep80579.c | 1 + src/northbridge/intel/i855/raminit.c | 1 + src/northbridge/intel/i945/raminit.c | 1 + src/soc/rockchip/rk3288/clock.c | 17 +------ src/southbridge/via/k8t890/traf_ctrl.c | 3 +- 21 files changed, 163 insertions(+), 205 deletions(-) diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 781a41d..c3ca123 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -311,6 +311,13 @@ u8 bin2hex(u8 b); u8 hex2bin(u8 h); void hexdump(const void *memory, size_t length); void fatal(const char *msg) __attribute__ ((noreturn)); + +/* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ +static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +/* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ +static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +/* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ +static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ diff --git a/payloads/libpayload/include/strings.h b/payloads/libpayload/include/strings.h deleted file mode 100644 index 5beddc6..0000000 --- a/payloads/libpayload/include/strings.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2011 secunet Security Networks AG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#ifndef _STRINGS_H -#define _STRINGS_H - -int ffs(int i); - -#endif diff --git a/payloads/libpayload/libc/Makefile.inc b/payloads/libpayload/libc/Makefile.inc index b4f75a6..272cda9 100644 --- a/payloads/libpayload/libc/Makefile.inc +++ b/payloads/libpayload/libc/Makefile.inc @@ -29,10 +29,10 @@ ## libc-$(CONFIG_LP_LIBC) += malloc.c printf.c console.c string.c -libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c +libc-$(CONFIG_LP_LIBC) += memory.c ctype.c ipchecksum.c lib.c libgcc.c libc-$(CONFIG_LP_LIBC) += rand.c time.c exec.c libc-$(CONFIG_LP_LIBC) += readline.c getopt_long.c sysinfo.c -libc-$(CONFIG_LP_LIBC) += args.c strings.c +libc-$(CONFIG_LP_LIBC) += args.c libc-$(CONFIG_LP_LIBC) += strlcpy.c libc-$(CONFIG_LP_LIBC) += qsort.c libc-$(CONFIG_LP_LIBC) += hexdump.c diff --git a/payloads/libpayload/libc/libgcc.c b/payloads/libpayload/libc/libgcc.c new file mode 100644 index 0000000..86698d8 --- /dev/null +++ b/payloads/libpayload/libc/libgcc.c @@ -0,0 +1,68 @@ +/* + * This file is part of the libpayload project. + * + * Copyright 2015 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * Alternatively, this software may be distributed under the terms of the + * GNU General Public License ("GPL") version 2 as published by the Free + * Software Foundation. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +/* + * Provide platform-independent backend implementation for __builtin_clz() in + * <libpayload.h> in case GCC does not have an assembly version for this arch. + */ + +int __clzsi2(u32 a); +int __clzsi2(u32 a) +{ + static const u8 four_bit_table[] = { + [0x0] = 4, [0x1] = 3, [0x2] = 2, [0x3] = 2, + [0x4] = 1, [0x5] = 1, [0x6] = 1, [0x7] = 1, + [0x8] = 0, [0x9] = 0, [0xa] = 0, [0xb] = 0, + [0xc] = 0, [0xd] = 0, [0xe] = 0, [0xf] = 0, + }; + int r = 0; + + if (!(a & (0xffff << 16))) { + r += 16; + a <<= 16; + } + + if (!(a & (0xff << 24))) { + r += 8; + a <<= 8; + } + + if (!(a & (0xf << 28))) { + r += 4; + a <<= 4; + } + + return r + four_bit_table[a >> 28]; +} diff --git a/payloads/libpayload/libc/strings.c b/payloads/libpayload/libc/strings.c deleted file mode 100644 index 465ae4f..0000000 --- a/payloads/libpayload/libc/strings.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the libpayload project. - * - * Copyright (C) 2011 secunet Security Networks AG - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include <strings.h> - -int ffs(int i) -{ - int count = 1; - if (i == 0) return 0; - - while ((i & 1) != 1) { - i>>=1; - count++; - } - return count; -} diff --git a/src/arch/arm/include/utils.h b/src/arch/arm/include/utils.h deleted file mode 100644 index 2482c6b..0000000 --- a/src/arch/arm/include/utils.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh(a)ti.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ -#ifndef _UTILS_H_ -#define _UTILS_H_ - -static inline s32 log_2_n_round_up(u32 n) -{ - s32 log2n = -1; - u32 temp = n; - - while (temp) { - log2n++; - temp >>= 1; - } - - if (n & (n - 1)) - return log2n + 1; /* not power of 2 - round up */ - else - return log2n; /* power of 2 */ -} - -static inline s32 log_2_n_round_down(u32 n) -{ - s32 log2n = -1; - u32 temp = n; - - while (temp) { - log2n++; - temp >>= 1; - } - - return log2n; -} - -#endif diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index ce94773..5c85019 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -174,8 +174,8 @@ static inline __attribute__((always_inline)) void write32(volatile void *addr, u } /* Conflicts with definition in lib.h */ -#if defined(__ROMCC__) || defined(__SMM__) -static inline int log2(int value) +#if defined(__ROMCC__) +static inline int log2(u32 value) { unsigned int r = 0; __asm__ volatile ( @@ -187,10 +187,8 @@ static inline int log2(int value) return r; } -#endif -#if defined(__PRE_RAM__) || defined(__SMM__) -static inline int log2f(int value) +static inline int __ffs(u32 value) { unsigned int r = 0; __asm__ volatile ( diff --git a/src/include/lib.h b/src/include/lib.h index 7ad33dd..b81b1b1 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -24,12 +24,6 @@ #include <stdint.h> #include <types.h> -#if !defined(__ROMCC__) /* Conflicts with inline function in arch/io.h */ -/* Defined in src/lib/clog2.c */ -unsigned long log2(unsigned long x); -#endif -unsigned long log2_ceil(unsigned long x); - /* Defined in src/lib/lzma.c */ unsigned long ulzma(unsigned char *src, unsigned char *dst); @@ -49,4 +43,16 @@ int checkstack(void *top_of_stack, int core); void hexdump(const void *memory, size_t length); void hexdump32(char LEVEL, const void *d, size_t len); +#if !defined(__ROMCC__) +/* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ +static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +/* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ +static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +/* Find First Set: __ffs(1) == 0, __ffs(0) == -1, __ffs(1<<31) == 31 */ +static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } +#endif + +/* Integer binary logarithm (rounding up): log2_ceil(0) == -1, log2(5) == 3 */ +static inline int log2_ceil(u32 x) { return (x == 0) ? -1 : log2(x * 2 - 1); } + #endif /* __LIB_H__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 557cd66..76c8fd3 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -25,7 +25,7 @@ bootblock-y += cbfs.c bootblock-y += cbfs_boot_props.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c - +bootblock-y += libgcc.c bootblock-$(CONFIG_GENERIC_UDELAY) += timer.c bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -45,6 +45,7 @@ verstage-y += cbfs.c verstage-y += halt.c verstage-y += fmap.c verstage-y += cbfs_boot_props.c +verstage-y += libgcc.c verstage-y += memcmp.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-y += region.c @@ -77,6 +78,7 @@ romstage-y += cbfs.c romstage-y += cbfs_boot_props.c romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c +romstage-y += libgcc.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c @@ -115,8 +117,6 @@ ramstage-y += cbfs_boot_props.c ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c -ramstage-y += clog2.c -romstage-y += clog2.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/clog2.c b/src/lib/clog2.c deleted file mode 100644 index 5e0d591..0000000 --- a/src/lib/clog2.c +++ /dev/null @@ -1,37 +0,0 @@ -#include <console/console.h> -#include <lib.h> - -/* Assume 8 bits per byte */ -#define CHAR_BIT 8 - -unsigned long log2(unsigned long x) -{ - /* assume 8 bits per byte. */ - unsigned long pow = sizeof(x) * CHAR_BIT - 1ULL; - unsigned long i = 1ULL << pow; - - if (!x) { - printk(BIOS_WARNING, "%s called with invalid parameter of 0\n", - __func__); - return -1; - } - - for (; i > x; i >>= 1, pow--); - - return pow; -} - -unsigned long log2_ceil(unsigned long x) -{ - unsigned long pow; - - if (!x) - return -1; - - pow = log2(x); - - if (x > (1ULL << pow)) - pow++; - - return pow; -} diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c new file mode 100644 index 0000000..14685be --- /dev/null +++ b/src/lib/libgcc.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <types.h> + +/* + * Provide platform-independent backend implementation for __builtin_clz() in + * <lib.h> in case GCC does not have an assembly version for this arch. + */ + +#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ +int __clzsi2(u32 a); +int __clzsi2(u32 a) +{ + static const u8 four_bit_table[] = { + [0x0] = 4, [0x1] = 3, [0x2] = 2, [0x3] = 2, + [0x4] = 1, [0x5] = 1, [0x6] = 1, [0x7] = 1, + [0x8] = 0, [0x9] = 0, [0xa] = 0, [0xb] = 0, + [0xc] = 0, [0xd] = 0, [0xe] = 0, [0xf] = 0, + }; + int r = 0; + + if (!(a & (0xffff << 16))) { + r += 16; + a <<= 16; + } + + if (!(a & (0xff << 24))) { + r += 8; + a <<= 8; + } + + if (!(a & (0xf << 28))) { + r += 4; + a <<= 4; + } + + return r + four_bit_table[a >> 28]; +} +#endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index a8d8700..6554e07 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -66,6 +66,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/hypertransport_def.h> +#include <lib.h> #include <stdlib.h> #include <arch/io.h> #include <pc80/mc146818rtc.h> diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 4213cfb..c58abb1 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -7,6 +7,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <lib.h> #include <stdlib.h> #include <arch/acpi.h> #include <reset.h> @@ -1655,7 +1656,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* if the next lower frequency gives a CL at least one whole cycle * shorter, select that (see end of BKDG 4.1.1.1) */ if (freq < sizeof(cl_at_freq)-1 && cl_at_freq[freq+1] && - log2f(cl_at_freq[freq]) - log2f(cl_at_freq[freq+1]) >= 2) + __ffs(cl_at_freq[freq]) - __ffs(cl_at_freq[freq+1]) >= 2) freq++; if (freq == sizeof(cl_at_freq)) @@ -1690,7 +1691,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * /* Update DRAM Timing Low with our selected cas latency */ value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT); - value |= latencies[log2f(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; + value |= latencies[__ffs(cl_at_freq[freq]) - 2] << DTL_TCL_SHIFT; pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value); result.dimm_mask = dimm_mask; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 1469684..1c1a6ea 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -25,6 +25,7 @@ #include <cpu/x86/tsc.h> #include <cpu/amd/mtrr.h> +#include <lib.h> #include <stdlib.h> #include <arch/acpi.h> #include "raminit.h" diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c index be46f27..87e281d 100644 --- a/src/northbridge/amd/amdk8/raminit_test.c +++ b/src/northbridge/amd/amdk8/raminit_test.c @@ -1,5 +1,6 @@ #include <unistd.h> #include <limits.h> +#include <lib.h> #include <stdint.h> #include <string.h> #include <setjmp.h> diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c index f4fc9a8..93a3a5b 100644 --- a/src/northbridge/intel/e7501/raminit.c +++ b/src/northbridge/intel/e7501/raminit.c @@ -12,6 +12,7 @@ /* converted to C 6/2004 yhlu */ #include <assert.h> +#include <lib.h> #include <spd.h> #include <sdram_mode.h> #include <stdlib.h> diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 85660e9..ee8c4fd 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/intel/speedstep.h> +#include <lib.h> #include "raminit_ep80579.h" #include "ep80579.h" diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c index 81dcbb5..a43f5be 100644 --- a/src/northbridge/intel/i855/raminit.c +++ b/src/northbridge/intel/i855/raminit.c @@ -19,6 +19,7 @@ */ #include <assert.h> +#include <lib.h> #include <spd.h> #include <sdram_mode.h> #include <stdlib.h> diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a3be680..7bd6240 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> #include <string.h> diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 2c56376..a2e8d88 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -21,6 +21,7 @@ #include <assert.h> #include <console/console.h> #include <delay.h> +#include <lib.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/grf.h> @@ -236,22 +237,6 @@ static int rkclk_set_pll(u32 *pll_con, const struct pll_div *div) return 0; } -/* - TODO: - it should be replaced by lib.h function - 'unsigned long log2(unsigned long x)' -*/ -static unsigned int log2(unsigned int value) -{ - unsigned int div = 0; - - while (value != 1) { - div++; - value = ALIGN_UP(value, 2) / 2; - } - return div; -} - void rkclk_init(void) { u32 aclk_div; diff --git a/src/southbridge/via/k8t890/traf_ctrl.c b/src/southbridge/via/k8t890/traf_ctrl.c index b4620da..24c1e65 100644 --- a/src/southbridge/via/k8t890/traf_ctrl.c +++ b/src/southbridge/via/k8t890/traf_ctrl.c @@ -24,10 +24,9 @@ #include <arch/acpi.h> #include <arch/acpigen.h> #include <cpu/amd/powernow.h> +#include <lib.h> #include "k8t890.h" -extern unsigned long log2(unsigned long x); - static void mmconfig_set_resources(device_t dev) { struct resource *resource;

1 0

Patch merged into coreboot/master: d42ee15 libpayload: usb: Support MTK xHCI host controller
by gerrit＠coreboot.org 03 Jun '15

03 Jun '15

the following patch was just integrated into master: commit d42ee150a0330f22986ad7237c9e70cebd9d995c Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Thu May 7 15:36:04 2015 +0800 libpayload: usb: Support MTK xHCI host controller 1. There is a mis-understanding to calculate the value of TD Size in Normal TRB. For MTK's xHCI controller it defines a number of packets that remain to be transferred for a TD after processing all Max packets in all previous TRBs, that means don't include the current TRB's. 2. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK architecture defines some extra SW scheduling parameters for HW. According to these parameters provided by SW, the xHC can easily decide whether a synchronous endpoint should be scheduled in a specific uFrame. The extra SW scheduling parameters are put into reserved DWs in Slot and Endpoint Context. But in coreboot synchronous transfer can be ignored, so only two fields are set to a default value 1 to support bulk and interrupt transfers, and others are set to zero. 3. For control transfer, it is better to read back doorbell register or add a memory barrier after ringing the doorbell to flush posted write. Otherwise the first command will be aborted on MTK's xHCI controller. 4. Before send commands to a port, the Port Power in PORTSC register should be set to 1 on MTK's xHCI so a hook function of enable_port in generic_hub_ops_t struct is provided. Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41 Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265362 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: http://review.coreboot.org/10389 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/10389 for details. -gerrit

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Patch merged into coreboot/master: 08e3013 libpayload: usb: Max packet size of SuperSpeed control EPs should be 512.
by gerrit＠coreboot.org 03 Jun '15

03 Jun '15

the following patch was just integrated into master: commit 08e30134900c1c8f169668e8b5b2b90254996c9a Author: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Date: Thu May 7 15:28:19 2015 +0800 libpayload: usb: Max packet size of SuperSpeed control EPs should be 512. BRANCH=none BUG=none TEST=none Change-Id: I563ef65db900d7675aeb5b9123dfb5a8980bf964 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 9764115d7bcce1d6423464bd81b58211ac728409 Original-Change-Id: Ibac8d3b9e28b4a563079f288901abcfbff6913ee Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269863 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Reviewed-on: http://review.coreboot.org/10388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10388 for details. -gerrit

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Patch set updated for coreboot: 85873b9 libpayload: usb: Support MTK xHCI host controller
by Patrick Georgi 03 Jun '15

03 Jun '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10389 -gerrit commit 85873b9702026e816b77f0077220bfc70382e1a3 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Thu May 7 15:36:04 2015 +0800 libpayload: usb: Support MTK xHCI host controller 1. There is a mis-understanding to calculate the value of TD Size in Normal TRB. For MTK's xHCI controller it defines a number of packets that remain to be transferred for a TD after processing all Max packets in all previous TRBs, that means don't include the current TRB's. 2. To minimize the scheduling effort for synchronous endpoints in xHC, the MTK architecture defines some extra SW scheduling parameters for HW. According to these parameters provided by SW, the xHC can easily decide whether a synchronous endpoint should be scheduled in a specific uFrame. The extra SW scheduling parameters are put into reserved DWs in Slot and Endpoint Context. But in coreboot synchronous transfer can be ignored, so only two fields are set to a default value 1 to support bulk and interrupt transfers, and others are set to zero. 3. For control transfer, it is better to read back doorbell register or add a memory barrier after ringing the doorbell to flush posted write. Otherwise the first command will be aborted on MTK's xHCI controller. 4. Before send commands to a port, the Port Power in PORTSC register should be set to 1 on MTK's xHCI so a hook function of enable_port in generic_hub_ops_t struct is provided. Change-Id: Ie8878b50c048907ebf939b3f6657535a54877fde Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 738609c11f16264c6e6429d478b2040cb391fe41 Original-Change-Id: Id9156892699e2e42a166c77fbf6690049abe953b Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265362 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> --- payloads/libpayload/Config.in | 6 ++++++ payloads/libpayload/drivers/usb/xhci.c | 17 ++++++++++++++++- payloads/libpayload/drivers/usb/xhci_commands.c | 2 ++ payloads/libpayload/drivers/usb/xhci_devconf.c | 10 ++++++++++ payloads/libpayload/drivers/usb/xhci_private.h | 9 +++++++++ payloads/libpayload/drivers/usb/xhci_rh.c | 20 +++++++++++++++++++- 6 files changed, 62 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 4d48761..92c89ab 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -495,6 +495,12 @@ config USB_XHCI Select this option if you want to use USB 3.0 NOTE: This option is not (fully) implemented yet +config USB_XHCI_MTK_QUIRK + bool "Support for USB xHCI controllers on MTK SoC" + depends on USB_XHCI + help + Select this option if you want to use USB 3.0 on MTK platform. + config USB_DWC2 bool "Support for USB DesignWare HCD controllers" depends on USB && !USB_HID diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 26dcdbe..89930e0 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -370,6 +370,8 @@ xhci_reinit (hci_t *controller) xhci->ev_ring_table[0].seg_base_hi = 0; xhci->ev_ring_table[0].seg_size = EVENT_RING_SIZE; + /* pass event ring table to hardware */ + wmb(); /* Initialize primary interrupter */ xhci->hcrreg->intrrs[0].erstsz = 1; xhci_update_event_dq(xhci); @@ -510,6 +512,7 @@ xhci_enqueue_trb(transfer_ring_t *const tr) xhci_spew("Handling LINK pointer\n"); const int tc = TRB_GET(TC, tr->cur); TRB_SET(CH, tr->cur, chain); + wmb(); TRB_SET(C, tr->cur, tr->pcs); tr->cur = phys_to_virt(tr->cur->ptr_low); if (tc) @@ -535,7 +538,7 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, cur_length = length; packets = 0; length = 0; - } else { + } else if (!IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) { packets -= (residue + cur_length) / mps; residue = (residue + cur_length) % mps; length -= cur_length; @@ -548,6 +551,18 @@ xhci_enqueue_td(transfer_ring_t *const tr, const int ep, const size_t mps, TRB_SET(TDS, trb, MIN(TRB_MAX_TD_SIZE, packets)); TRB_SET(CH, trb, 1); + if (length && IS_ENABLED(CONFIG_LP_XHCI_MTK_QUIRK)) { + /* + * For MTK's xHCI controller, TDS defines a number of + * packets that remain to be transferred for a TD after + * processing all Max packets in all previous TRBs, that + * means don't include the current TRB's. + */ + packets -= (residue + cur_length) / mps; + residue = (residue + cur_length) % mps; + length -= cur_length; + } + /* Check for first, data stage TRB */ if (!trb_count && ep == 1) { TRB_SET(DIR, trb, dir); diff --git a/payloads/libpayload/drivers/usb/xhci_commands.c b/payloads/libpayload/drivers/usb/xhci_commands.c index 009a69c..845a34d 100644 --- a/payloads/libpayload/drivers/usb/xhci_commands.c +++ b/payloads/libpayload/drivers/usb/xhci_commands.c @@ -47,6 +47,8 @@ xhci_post_command(xhci_t *const xhci) TRB_SET(C, xhci->cr.cur, xhci->cr.pcs); ++xhci->cr.cur; + /* pass command trb to hardware */ + wmb(); /* Ring the doorbell */ xhci->dbreg[0] = 0; diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 012f610..5b5bb5e 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -313,6 +313,16 @@ xhci_finish_ep_config(const endpoint_t *const ep, inputctx_t *const ic) EC_SET(AVRTRB, epctx, avrtrb); EC_SET(MXESIT, epctx, EC_GET(MPS, epctx) * EC_GET(MBS, epctx)); + if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + /* The MTK xHCI defines some extra SW parameters which are + * put into reserved DWs in Slot and Endpoint Contexts for + * synchronous endpoints. But for non-isochronous transfers, + * it is enough to set the following two fields to 1, and others + * are set to 0. + */ + EC_SET(BPKTS, epctx, 1); + EC_SET(BBM, epctx, 1); + } return 0; } diff --git a/payloads/libpayload/drivers/usb/xhci_private.h b/payloads/libpayload/drivers/usb/xhci_private.h index 3861858..f01a37f 100644 --- a/payloads/libpayload/drivers/usb/xhci_private.h +++ b/payloads/libpayload/drivers/usb/xhci_private.h @@ -33,6 +33,8 @@ //#define USB_DEBUG #include <usb/usb.h> +#include <arch/barrier.h> +#include <kconfig.h> //#define XHCI_DUMPS #define xhci_debug(fmt, args...) usb_debug("%s: " fmt, __func__, ## args) @@ -242,6 +244,13 @@ typedef volatile struct slotctx { #define EC_MXESIT_FIELD f5 /* MXESIT - Max ESIT Payload */ #define EC_MXESIT_START 16 #define EC_MXESIT_LEN 16 +#define EC_BPKTS_FIELD rsvd[0] /* BPKTS - packets tx in scheduled uframe */ +#define EC_BPKTS_START 0 +#define EC_BPKTS_LEN 6 +#define EC_BBM_FIELD rsvd[0] /* BBM - burst mode for scheduling */ +#define EC_BBM_START 11 +#define EC_BBM_LEN 1 + #define EC_MASK(tok) MASK(EC_##tok##_START, EC_##tok##_LEN) #define EC_GET(tok, ec) (((ec)->EC_##tok##_FIELD & EC_MASK(tok)) \ >> EC_##tok##_START) diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c index fa118fe..bcb01ac 100644 --- a/payloads/libpayload/drivers/usb/xhci_rh.c +++ b/payloads/libpayload/drivers/usb/xhci_rh.c @@ -119,6 +119,24 @@ xhci_rh_reset_port(usbdev_t *const dev, const int port) return 0; } +static int +xhci_rh_enable_port(usbdev_t *const dev, int port) +{ + if (IS_ENABLED(CONFIG_LP_USB_XHCI_MTK_QUIRK)) { + xhci_t *const xhci = XHCI_INST(dev->controller); + volatile u32 *const portsc = + &xhci->opreg->prs[port - 1].portsc; + + /* + * Before sending commands to a port, the Port Power in + * PORTSC register should be enabled on MTK's xHCI. + */ + *portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PP; + } + return 0; +} + + static const generic_hub_ops_t xhci_rh_ops = { .hub_status_changed = xhci_rh_hub_status_changed, .port_status_changed = xhci_rh_port_status_changed, @@ -126,7 +144,7 @@ static const generic_hub_ops_t xhci_rh_ops = { .port_in_reset = xhci_rh_port_in_reset, .port_enabled = xhci_rh_port_enabled, .port_speed = xhci_rh_port_speed, - .enable_port = NULL, + .enable_port = xhci_rh_enable_port, .disable_port = NULL, .start_port_reset = NULL, .reset_port = xhci_rh_reset_port,

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coreboot-gerrit June 2015