coreboot-gerrit June 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ac72f41 AMD fam10: Fix add_more_links
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8555 -gerrit commit ac72f416365cb0dde210c12b7863760e7a196f2f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 23:56:07 2015 +0200 AMD fam10: Fix add_more_links One PCI function may contain upto 4 links, further links must be added to PCI function 4 on the same device. There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: If7ebdd1ad52653d3757b5930bd0a83e2cf2fcac6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 41 +++++++++++++----------------- 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 4734522..424ecd7 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -176,18 +176,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #endif u32 max_devfn; - if (link->link_num > 3) { - u32 regpos; - u32 reg; - regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 - reg = pci_read_config32(dev, regpos); - if(reg & 1) return max; // already ganged no sblink1 - - dev = get_node_pci(nodeid, 4); - } - /* Check for connected link. */ - link->cap = 0x80 + ((link->link_num & 3) * 0x20); + link->cap = 0x80 + (link->link_num * 0x20); if (!is_non_coherent_link(dev, link)) return max; @@ -1178,14 +1168,16 @@ static void sysconf_init(device_t dev) // first node static void add_more_links(device_t dev, unsigned total_links) { struct bus *link, *last = NULL; - int link_num; + int link_num = -1; - for (link = dev->link_list; link; link = link->next) + for (link = dev->link_list; link; link = link->next) { + if (link_num < link->link_num) + link_num = link->link_num; last = link; + } if (last) { - int links = total_links - last->link_num; - link_num = last->link_num; + int links = total_links - (link_num + 1); if (links > 0) { link = malloc(links*sizeof(*link)); if (!link) @@ -1195,7 +1187,6 @@ static void add_more_links(device_t dev, unsigned total_links) } } else { - link_num = -1; link = malloc(total_links*sizeof(*link)); memset(link, 0, total_links*sizeof(*link)); dev->link_list = link; @@ -1337,15 +1328,19 @@ static void cpu_bus_scan(device_t dev) cdb_dev = pci_probe_dev(NULL, pbus, PCI_DEVFN(devn, fn)); } - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - } - if (cdb_dev) { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 8); } + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (cdb_dev) + add_more_links(cdb_dev, 4); + + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 4)); + if (cdb_dev) + add_more_links(cdb_dev, 4); + cores_found = 0; // one core cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); int enable_node = cdb_dev && cdb_dev->enabled;

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Patch set updated for coreboot: 06532cc devicetree: Add fields for HyperTransport scans
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8557 -gerrit commit 06532ccd1b6b1abfb8e5ba2022fd7835b707a637 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 11:38:49 2015 +0200 devicetree: Add fields for HyperTransport scans Change-Id: I3b00e5e4e45089fbd7d0d6243d5e441bd8929c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/device/device.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/device/device.h b/src/include/device/device.h index 9c53f95..396ecf8 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -86,6 +86,8 @@ struct bus { uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ + uint32_t hcdn_reg; /* For HyperTransport link */ + unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; };

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Patch set updated for coreboot: 8d9e4f7 AMD K8 fam10: Add ht_route_link()
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8556 -gerrit commit 8d9e4f70c9f31126f83458490a9d65089beecf98 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 12:05:33 2015 +0200 AMD K8 fam10: Add ht_route_link() Change-Id: I41aeb80121f120641b65759c8502150ce89caa30 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 50 +++++++++++++++++-------- src/northbridge/amd/amdk8/northbridge.c | 60 +++++++++++++++++++----------- 2 files changed, 73 insertions(+), 37 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 424ecd7..ff5dc31 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -158,6 +158,37 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link) return !!(link_type & NonCoherent); } +typedef enum { + HT_ROUTE_CLOSE, + HT_ROUTE_SCAN, + HT_ROUTE_FINAL, +} scan_state; + +static void ht_route_link(struct bus *link, scan_state mode) +{ + struct bus *parent = link->dev->bus; + u32 busses; + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xff000000; + busses |= parent->secondary & 0xff; + if (mode == HT_ROUTE_CLOSE) { + busses |= 0xfeff << 8; + } else if (mode == HT_ROUTE_SCAN) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= 0xfc << 16; + } else if (mode == HT_ROUTE_FINAL) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->subordinate & 0xff) << 16; + } + pci_write_config32(link->dev, link->cap + 0x14, busses); + +} + static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, u32 max) { @@ -170,7 +201,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - u32 busses; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 u32 busn = max&0xff; #endif @@ -219,23 +249,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool link->secondary = min_bus; link->subordinate = link->secondary; - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xffff00ff; - busses |= ((u32)(link->secondary) << 8); - pci_write_config32(dev, link->cap + 0x14, busses); - + ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, max_bus, sysconf.segbit, sysconf.nodes); + set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -255,6 +273,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* Now that nothing is overlapping it is safe to scan the children. */ pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); + ht_route_link(link, HT_ROUTE_FINAL); + /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 45cff9e..018b68a 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -96,6 +96,38 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link) return !!(link_type & NonCoherent); } +typedef enum { + HT_ROUTE_CLOSE, + HT_ROUTE_SCAN, + HT_ROUTE_FINAL, +} scan_state; + +static void ht_route_link(struct bus *link, scan_state mode) +{ + struct device *dev = link->dev; + struct bus *parent = dev->bus; + u32 busses; + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xff000000; + busses |= parent->secondary & 0xff; + if (mode == HT_ROUTE_CLOSE) { + busses |= 0xfeff << 8; + } else if (mode == HT_ROUTE_SCAN) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= 0xff << 16; + } else if (mode == HT_ROUTE_FINAL) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->subordinate & 0xff) << 16; + } + pci_write_config32(link->dev, link->cap + 0x14, busses); + +} + static u32 amdk8_nodeid(device_t dev) { return (dev->path.pci.devfn >> 3) - 0x18; @@ -106,10 +138,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ { int i; unsigned int next_unitid; - u32 busses, config_busses; + u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; u32 max_devfn; @@ -168,34 +199,20 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ #else min_bus = ++max; #endif - max_bus = 0xff; link->secondary = min_bus; link->subordinate = link->secondary; - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - config_busses = f1_read_config32(config_reg); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xff000000; - busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(link->secondary) << 8) | - (max_bus << 16)); - pci_write_config32(dev, link->cap + 0x14, busses); + ht_route_link(link, HT_ROUTE_SCAN); + config_busses = f1_read_config32(config_reg); config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | ((link->link_num & 3) << 8) | ((link->secondary) << 16) | - (max_bus << 24); + (0xff << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the @@ -218,9 +235,8 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - busses = (busses & 0xff00ffff) | - ((unsigned int) (link->subordinate) << 16); - pci_write_config32(dev, link->cap + 0x14, busses); + + ht_route_link(link, HT_ROUTE_FINAL); config_busses = (config_busses & 0x00ffffff) | (link->subordinate << 24);

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Patch set updated for coreboot: 0f342df AMD K8: Refactor calls for HT configuration
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8559 -gerrit commit 0f342dfba95b39f396b5679c8f9e8b19a4ceefbf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 11:19:01 2015 +0200 AMD K8: Refactor calls for HT configuration Change-Id: I24ca1dce025e00064f9209affa27586292c7650e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/northbridge.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 7826749..e087888 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -232,18 +232,15 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ (link->subordinate << 24); f1_write_config32(config_reg, config_busses); - { - // use config_reg and ht_unitid_base to update hcdn_reg - int index; - u32 temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } - sysconf.hcdn_reg[index] = temp; + // use config_reg and ht_unitid_base to update hcdn_reg + link->hcdn_reg = 0; + for (i = 0; i < 4; i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + int index = (config_reg-0xe0) >> 2; + sysconf.hcdn_reg[index] = link->hcdn_reg; - } return link->subordinate; }

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Patch set updated for coreboot: f50d9dc AMD fam10: Refactor calls for HT configuration
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8558 -gerrit commit f50d9dc4b909f0264e75caf72251a63503a01776 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 19 16:49:47 2015 +0200 AMD fam10: Refactor calls for HT configuration Change-Id: Ic8fbafdfadbc4ef0896d93e61c8a54ce69297e07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/ht_config.c | 71 +++++++++++++++++------------- src/northbridge/amd/amdfam10/ht_config.h | 15 +++---- src/northbridge/amd/amdfam10/northbridge.c | 33 +++++++------- 3 files changed, 60 insertions(+), 59 deletions(-) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 3110980..6eec534 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -47,54 +47,51 @@ struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } - -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes) +void set_config_map_reg(struct bus *link) { u32 tempreg; u32 i; + u32 ht_c_index = get_ht_c_index(link); + u32 linkn = link->link_num & 0x0f; + u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; + u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; + u32 nodeid = amdfam10_nodeid(link->dev); - busn_min>>=segbit; - busn_max>>=segbit; + tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; + tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } } -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes) +void clear_config_map_reg(struct bus *link) { u32 i; + u32 ht_c_index = get_ht_c_index(link); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } } -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) +static u32 ht_c_key(struct bus *link) { - u32 tempreg; - u32 ht_c_index = 0; + u32 nodeid = amdfam10_nodeid(link->dev); + u32 linkn = link->link_num & 0x0f; + u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; + return val; +} -#if 0 - tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); +static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) +{ + u32 ht_c_index = 0; - for (ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); - if (((reg & 0xffff) == 0x0000)) { /*found free*/ - break; - } - } -#endif - tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { + if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } } @@ -108,14 +105,26 @@ u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) return -1; } -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo) +u32 get_ht_c_index(struct bus *link) { - u32 val; - val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same + u32 val = ht_c_key(link); + return get_ht_c_index_by_key(val, &sysconf); +} + +void store_ht_c_conf_bus(struct bus *link) +{ + u32 val = ht_c_key(link); + u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); + + u32 segn = (link->subordinate >> 8) & 0x0f; + u32 busn_min = link->secondary & 0xff; + u32 busn_max = link->subordinate & 0xff; + + val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); + sysconf.ht_c_conf_bus[ht_c_index] = val; + sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; + sysconf.ht_c_num++; } u32 get_io_addr_index(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index 08c5263..fcec368 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -20,6 +20,7 @@ typedef struct amdfam10_sysconf_t sys_info_conf_t; /* FIXME */ +u32 amdfam10_nodeid(device_t dev); extern device_t __f1_dev[]; struct dram_base_mask_t { @@ -29,17 +30,11 @@ struct dram_base_mask_t { struct dram_base_mask_t get_dram_base_mask(u32 nodeid); -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes); -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes); +u32 get_ht_c_index(struct bus *link); +void store_ht_c_conf_bus(struct bus *link); -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo); - -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo); +void set_config_map_reg(struct bus *link); +void clear_config_map_reg(struct bus *link); void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index efd8a70..fb963f6 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -114,7 +114,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +u32 amdfam10_nodeid(device_t dev) { #if NODE_NUMS == 64 unsigned busn; @@ -197,7 +197,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; unsigned int next_unitid; - u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; @@ -209,9 +208,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link->link_num, &sysconf); - - if(ht_c_index>=4) return max; + if (get_ht_c_index(link) >= 4) + return max; /* Set up the primary, secondary and subordinate bus numbers. * We have no idea how many busses are behind this bridge yet, @@ -239,8 +237,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ - - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(link); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -265,20 +262,20 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); - sysconf.ht_c_num++; + if (0) { + /* Clear the extend reg. */ + clear_config_map_reg(link); + } - { - // use ht_unitid_base to update hcdn_reg - u32 temp = 0; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } + set_config_map_reg(link); - sysconf.hcdn_reg[ht_c_index] = temp; + /* Use ht_unitid_base to update hcdn_reg. */ + link->hcdn_reg = 0; + for (i = 0; i < 4;i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + store_ht_c_conf_bus(link); - } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); return link->subordinate; }

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Patch set updated for coreboot: 6ffd034 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8352 -gerrit commit 6ffd034dab722bf7c4b3cdf7e00684bdb3c5b7ac Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:24:59 2015 +0200 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0 Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 36 +++++++++++++----------------- src/northbridge/amd/amdk8/northbridge.c | 28 +++++++++-------------- 2 files changed, 26 insertions(+), 38 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index fd134a2..caf5410 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -218,29 +218,25 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if (is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. - else { + + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { + min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + // second chain will be on 0x40, third 0x80, forth 0xc0 + // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 + // >4 will use more segments, + // We can have 16 segmment and every segment have 256 bus, + // For that case need the kernel support mmio pci config. + /* One node can have 8 link and segn is the same. */ min_bus = (((max & 0xff) >> 3) + 1) << 3; + max = min_bus; } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif -#else - min_bus = ++max; -#endif link->secondary = min_bus; link->subordinate = link->secondary; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 018b68a..b27404e 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -179,26 +179,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if(is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + min_bus = (max & ~0x3f) + 0x40; + max = min_bus; } - #endif -#else - min_bus = ++max; -#endif link->secondary = min_bus; link->subordinate = link->secondary;

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Patch set updated for coreboot: ffe4262 AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8353 -gerrit commit ffe4262e35513dc208bd51fa1fd66d8b2ac7b4dd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 14:05:51 2015 +0200 AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0 Define the default value under northbridge. The list of boards this patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with follow-up patch. Based on code analysis, these boards already scan system bus as the first (active) HT chain, so it is placed as bus 0 even when this option was not explicitly selected. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/ibm/e325/Kconfig | 4 ---- src/mainboard/ibm/e326/Kconfig | 4 ---- src/mainboard/iwill/dk8s2/Kconfig | 4 ---- src/mainboard/iwill/dk8x/Kconfig | 4 ---- src/mainboard/newisys/khepri/Kconfig | 4 ---- src/mainboard/tyan/s2850/Kconfig | 4 ---- src/mainboard/tyan/s2875/Kconfig | 4 ---- src/mainboard/tyan/s2880/Kconfig | 4 ---- src/mainboard/tyan/s2882/Kconfig | 4 ---- src/mainboard/tyan/s4880/Kconfig | 4 ---- src/mainboard/tyan/s4882/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 4 ++++ 12 files changed, 4 insertions(+), 44 deletions(-) diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 10b6fde..0400677 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 005012a..bd2bb26 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6b54645 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index af35bb6..f2660c6 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 7f618af..f1c2687 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "Khepri" diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index e6e3df2..2866b0c 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -40,10 +40,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 30aa01e..85c3ab4 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -42,10 +42,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 5186337..62b4e70 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -22,10 +22,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2880" diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 646b5a8..bf980d7 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -23,10 +23,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2882" diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index d4feacb..6c85c6c 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4880" diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2bd3854..7723acf 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4882" diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index e5161ab..cc0cc66 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -64,6 +64,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config QRANK_DIMM_SUPPORT bool default n

1 0

Patch set updated for coreboot: 19dd50d AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8366 -gerrit commit 19dd50daa9b7e8ed7fb130ced5ba5f8c42106ce1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 15:48:38 2015 +0200 AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0 If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 4 ---- src/mainboard/amd/bimini_fam10/Kconfig | 4 ---- src/mainboard/amd/dbm690t/Kconfig | 4 ---- src/mainboard/amd/mahogany/Kconfig | 4 ---- src/mainboard/amd/mahogany_fam10/Kconfig | 4 ---- src/mainboard/amd/pistachio/Kconfig | 4 ---- src/mainboard/amd/serengeti_cheetah/Kconfig | 5 +---- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 5 +---- src/mainboard/amd/tilapia_fam10/Kconfig | 4 ---- src/mainboard/arima/hdama/Kconfig | 4 ---- src/mainboard/asrock/939a785gmh/Kconfig | 4 ---- src/mainboard/asus/a8n_e/Kconfig | 5 +---- src/mainboard/asus/a8v-e_deluxe/Kconfig | 4 ---- src/mainboard/asus/a8v-e_se/Kconfig | 4 ---- src/mainboard/asus/k8v-x/Kconfig | 4 ---- src/mainboard/asus/kfsn4-dre/Kconfig | 4 ---- src/mainboard/asus/m2n-e/Kconfig | 5 +---- src/mainboard/asus/m2v-mx_se/Kconfig | 4 ---- src/mainboard/asus/m2v/Kconfig | 4 ---- src/mainboard/asus/m4a78-em/Kconfig | 4 ---- src/mainboard/asus/m4a785-m/Kconfig | 4 ---- src/mainboard/asus/m4a785t-m/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Kconfig | 4 ---- src/mainboard/avalue/eax-785e/Kconfig | 4 ---- src/mainboard/broadcom/blast/Kconfig | 4 ---- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 5 +---- src/mainboard/gigabyte/m57sli/Kconfig | 5 +---- src/mainboard/gigabyte/ma785gm/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gmt/Kconfig | 4 ---- src/mainboard/gigabyte/ma78gm/Kconfig | 4 ---- src/mainboard/hp/dl145_g1/Kconfig | 5 +---- src/mainboard/hp/dl145_g3/Kconfig | 5 +---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---- src/mainboard/iei/kino-780am2-fam10/Kconfig | 4 ---- src/mainboard/iwill/dk8_htx/Kconfig | 5 +---- src/mainboard/jetway/pa78vm5/Kconfig | 4 ---- src/mainboard/kontron/kt690/Kconfig | 4 ---- src/mainboard/msi/ms7135/Kconfig | 5 +---- src/mainboard/msi/ms7260/Kconfig | 5 +---- src/mainboard/msi/ms9185/Kconfig | 5 +---- src/mainboard/msi/ms9282/Kconfig | 4 ---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/nvidia/l1_2pvv/Kconfig | 5 +---- src/mainboard/siemens/sitemp_g1p1/Kconfig | 4 ---- src/mainboard/sunw/ultra40/Kconfig | 5 +---- src/mainboard/supermicro/h8dme/Kconfig | 5 +---- src/mainboard/supermicro/h8dmr/Kconfig | 5 +---- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8qme_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim5690/Kconfig | 4 ---- src/mainboard/technexion/tim8690/Kconfig | 4 ---- src/mainboard/tyan/s2881/Kconfig | 5 +---- src/mainboard/tyan/s2885/Kconfig | 5 +---- src/mainboard/tyan/s2891/Kconfig | 5 +---- src/mainboard/tyan/s2892/Kconfig | 5 +---- src/mainboard/tyan/s2895/Kconfig | 5 +---- src/mainboard/tyan/s2912/Kconfig | 5 +---- src/mainboard/tyan/s2912_fam10/Kconfig | 5 +---- src/mainboard/winent/mb6047/Kconfig | 5 +---- src/northbridge/amd/amdfam10/Kconfig | 6 ++++++ src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/Kconfig | 6 ++++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- 64 files changed, 41 insertions(+), 246 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 388249f..b6213d5 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 369cb7e..261c60a 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 70d63ad..77bafc5 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 394ad77..8861b4a 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -47,10 +47,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index ec5ca0b..393882c 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 9a91eec..2296e82 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index e1363eb..2d2d4d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -55,10 +56,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 2a3e6a7..3e6e025 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -41,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 901d6b1..254cf66 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 49860b3..66177f5 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -38,10 +38,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index cfaa599..2148385 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -49,10 +49,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 5b7c1e6..1852ae4 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 8ebff31..a1c2fd9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E Deluxe" diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index d819b0d..dffe9eb 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E SE" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 1deb5b6..52bf661 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -32,10 +32,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "K8V-X" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 47fccda..2750c17 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -44,10 +44,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "KFSN4-DRE" diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index b7375f2..02e516e 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -57,10 +58,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "M2N-E" diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index ab155b9..efcfc81 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -67,10 +67,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 35ad38d..72527be 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -36,10 +36,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "M2V" diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index b00a0b6..0382daf 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -39,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index f93c484..a945d2a 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index d98ad95..a347f02 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -42,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 1430189..a5f19f5 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -50,10 +50,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 38a3aa3..9d7c2e0 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b821f7a..ddd2aca 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "Blast" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..e182c99 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_SIS_SIS966 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8716F select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -37,10 +38,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..cc8be43 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -41,10 +42,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 8f44e76..bf441e9 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 03b9237..827c8da 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 32421e8..3d85708 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 0c6d642..74ce0e7 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET select HAVE_OPTION_TABLE @@ -28,10 +29,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "ProLiant DL145 G1" diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 439188a..da20fb3 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index 8376d89..ca36aaf 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 @@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index deea898..4b3bce6 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index cdfd99a..929f47f 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -38,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index b13bead..30478d2 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 8d1f039..e679e66 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index f2cfd9a..50f989e 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..e3863a0 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -39,10 +40,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7260" diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 0b0ff1c..355fdcf 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -34,10 +35,6 @@ config APIC_ID_OFFSET hex default 0x8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-9185" diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..dd96992 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "MS-9282" diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index c1c095b..c64fdda 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -76,10 +76,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x00 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config VAR_MTRR_HOLE bool default n diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..e9664ac 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -43,10 +44,6 @@ config MCP55_NUM int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "l1_2pvv" diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index dff329f..d9ad74b 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 8f3ff2a..a29cf16 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 52d5581..35f9bf0 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -60,10 +61,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index f85460b..9efc5d2 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -59,10 +60,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 0f94620..0d20204 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 5b195bb..27a74bb 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -53,10 +54,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 3105493..0673390 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 98dce39..0220d77 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 4e0b25a..ad80e85 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 6c759e1..de641cd 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -24,10 +25,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2881" diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 86e43f8..b218ab7 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8151 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2885" diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index 3d1c1fb..238f5bc 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2891" diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index b9c4105..cbe076c 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 544b0c5..21db63c 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -47,10 +48,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..7ad1a1c 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -38,10 +39,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912" diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..b5e31fa 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -35,10 +36,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 86b0ae0..622441e 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -25,10 +26,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MB6047" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index b298ee1..fa8a26a 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -64,6 +64,12 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index c7888ff..e4d32f9 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -216,11 +216,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; /* One node can have 8 link and segn is the same. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 8); link->secondary = max; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index cc0cc66..b293ce3 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,8 +65,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY default n config SB_HT_CHAIN_ON_BUS0 - int - default 0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n config QRANK_DIMM_SUPPORT bool diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index bdfe355..3ac626d 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -179,11 +179,11 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 0x40); link->secondary = max;

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Patch set updated for coreboot: 6fe5314 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8560 -gerrit commit 6fe5314677012ed36c352e9480bac8ad152f4e62 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 14:31:01 2015 +0200 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree When we want to scan the HT chain to southbridge first, we relocate it as the first item of dev->link_list of node 0. Change-Id: Ic73ba43aadb3c5e0c8d4b82ed7d41094692ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 45 +++++++++++++++++++++++------ src/northbridge/amd/amdk8/northbridge.c | 46 +++++++++++++++++++++++------- 2 files changed, 72 insertions(+), 19 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 98f41f3..c7888ff 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -271,6 +271,36 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool return link->subordinate; } +/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + if (!CONFIG_SB_HT_CHAIN_ON_BUS0) + return; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; + } + prev = link; + link = link->next; + } +} + static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; @@ -283,15 +313,6 @@ static void amdfam10_scan_chains(device_t dev) /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -582,9 +603,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1200, }; +static void amdfam10_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdfam10_ops = { CHIP_NAME("AMD FAM10 Northbridge") .enable_dev = 0, + .init = amdfam10_nb_init, }; static void amdfam10_domain_read_resources(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 7184c38..bdfe355 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -240,6 +240,36 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ return link->subordinate; } +/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + if (!CONFIG_SB_HT_CHAIN_ON_BUS0) + return; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; + } + prev = link; + link = link->next; + } +} + static void amdk8_scan_chains(device_t dev) { unsigned nodeid; @@ -251,18 +281,8 @@ static void amdk8_scan_chains(device_t dev) if (nodeid == 0) sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -604,9 +624,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1100, }; +static void amdk8_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdk8_ops = { CHIP_NAME("AMD K8 Northbridge") .enable_dev = 0, + .init = amdk8_nb_init, }; static void amdk8_domain_read_resources(device_t dev)

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Patch set updated for coreboot: 2fd1f22 AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki 04 Jun '15

04 Jun '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8561 -gerrit commit 2fd1f22bcc62af9dc4eac5254c368a0e1edd71a1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 15:43:23 2015 +0200 AMD K8 fam10: Always have SB_HT_CHAIN_ON_BUS0 Change-Id: I65fad1cfba95f0ee1ed3f7f7a57d874144da1e40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/Kconfig | 3 --- src/northbridge/amd/amdfam10/northbridge.c | 5 +---- src/northbridge/amd/amdk8/Kconfig | 3 --- src/northbridge/amd/amdk8/northbridge.c | 5 +---- 4 files changed, 2 insertions(+), 14 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index fa8a26a..0987a1f 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -64,9 +64,6 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n -config SB_HT_CHAIN_ON_BUS0 - def_bool y - config HT_CHAIN_DISTRIBUTE def_bool n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index e4d32f9..df0d712 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -216,7 +216,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) + if (!is_sblink) max++; /* One node can have 8 link and segn is the same. */ @@ -280,9 +280,6 @@ static void relocate_sb_ht_chain(void) struct bus *link, *prev = NULL; u8 sblink; - if (!CONFIG_SB_HT_CHAIN_ON_BUS0) - return; - dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); sblink = (pci_read_config32(dev, 0x64)>>8) & 7; link = dev->link_list; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index b293ce3..21d3c29 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -64,9 +64,6 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n -config SB_HT_CHAIN_ON_BUS0 - def_bool y - config HT_CHAIN_DISTRIBUTE def_bool n diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 3ac626d..84c1144 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -179,7 +179,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ - if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) + if (!is_sblink) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ @@ -249,9 +249,6 @@ static void relocate_sb_ht_chain(void) struct bus *link, *prev = NULL; u8 sblink; - if (!CONFIG_SB_HT_CHAIN_ON_BUS0) - return; - dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); sblink = (pci_read_config32(dev, 0x64)>>8) & 3; link = dev->link_list;

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coreboot-gerrit June 2015