coreboot-gerrit June 2015

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Patch merged into coreboot/master: 34de29a build system: move more clang handling to xcompile
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 34de29aeb3a8d5013044fea9387609ea63d8ecf6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 13:45:40 2015 +0200 build system: move more clang handling to xcompile clang requires some additional options to disable warnings which can be handled by xcompile. Also drop the hard coded clang compilers in Makefile Change-Id: I0f12f755420f315127e6d9adc00b1246c6e7131b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/7612 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/7612 for details. -gerrit

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Patch merged into coreboot/master: 45dd591 arch/x86: No need to specify -Wa, --divide in a Makefile
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 45dd591ff6e55a71dbe539588de673a9d4a2bc35 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 13:14:54 2015 +0200 arch/x86: No need to specify -Wa,--divide in a Makefile We test for it in xcompile and add it to CFLAGS. Change-Id: I041a881b542bc55c1725af384f038da3356e3bb1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10426 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10426 for details. -gerrit

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Patch merged into coreboot/master: 527f392 build system: move compiler runtime determination to xcompile
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 527f3923b0dc4a33b3be368107768792e09dc31e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 13:31:38 2015 +0200 build system: move compiler runtime determination to xcompile Instead of fetching libgcc's location and required compiler flags on every individual build, do it once in xcompile. Change-Id: Ie5832fcb21710c4cf381ba475589d42ce0235f96 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/10425 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10425 for details. -gerrit

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Patch merged into coreboot/master: 8b5a051 xcompile: Detect clang compilers
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 8b5a051c3efa13da323413c8d913694d04f18c41 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 13:44:41 2015 +0200 xcompile: Detect clang compilers This uses the availability of CONFIG_* variables in .xcompile and tests for compilers in xcompile so that the build system doesn't need to probe them. Change-Id: I359ad6245d2527efa7e848a9b38f5f194744c827 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/10424 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10424 for details. -gerrit

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Patch merged into coreboot/master: 532df29 xcompile: Rename internal variable CFLAGS to CFLAGS_GCC
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 532df293da6f82cdbc10fd02b224ba8131d42533 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 13:20:24 2015 +0200 xcompile: Rename internal variable CFLAGS to CFLAGS_GCC This is in preparation of adding support for clang to xcompile. Change-Id: I518d077f134610082b0939b1525682f2289eec34 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10423 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10423 for details. -gerrit

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Patch merged into coreboot/master: 93af2f2 board_id: Remove extra quotes.
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 93af2f271d8448dd99c52b9eb0aeeb1ac9c2e87d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 30 23:13:48 2015 +0200 board_id: Remove extra quotes. Kconfig already quotes the string. Double quoting actually removes the quoting. Change-Id: I927d90dc2ce8af4e8d2d700d2bb3e04254459e1b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10382 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10382 for details. -gerrit

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Patch merged into coreboot/master: 7b9762f build system: Move .xcompile include further down
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 7b9762fe20c29b5bc7e2054913c0b323b759d123 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 13:18:11 2015 +0200 build system: Move .xcompile include further down It's not used until then, but by moving it below including .config, we can use CONFIG_* in the .xcompile file in the future. Change-Id: I672f444dd28b5fae1fc339a1e0e78a249c9b7875 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10422 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10422 for details. -gerrit

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Patch merged into coreboot/master: 31bf37e crossgcc: Improve compatibility of the toolchain across host systems
by gerrit＠coreboot.org 04 Jun '15

04 Jun '15

the following patch was just integrated into master: commit 31bf37eb32170bf69be845a1218438c12fe5bf75 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jun 4 00:09:12 2015 +0200 crossgcc: Improve compatibility of the toolchain across host systems crossgcc builds gmp, whose build system normally optimises for the hardware it's built on. That may give a minor performance boost but has the downside that the compiler becomes non-portable and may break on other systems due to illegal instructions. Setting CFLAGS to some reasonable value prevents gmp's configure script from choosing CPU specific -mtune flags (which may enable optimizations that only run on CPUs with the same feature set). Enabling "fat" builds make the build system add all optimized assembler routines and makes the selection of the right one a runtime decision instead of deciding at compile time. Change-Id: I72d20627270baa082cd02ebb4c9a09cd23f30f8c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/10412 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10412 for details. -gerrit

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Patch set updated for coreboot: 7df8640 acpi/sata: add generic sata ssdt port generator
by Alexander Couzens 04 Jun '15

04 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9708 -gerrit commit 7df86404aef6e041d6d1888c49c2146d048afea2 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:03:26 2015 +0200 acpi/sata: add generic sata ssdt port generator generate_sata_ssdt_ports() generates ports based on sata enable map Change-Id: Ie68e19c93f093d6c61634c4adfde484b88f28a77 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- Makefile.inc | 2 +- src/Kconfig | 2 ++ src/acpi/Kconfig | 6 +++++ src/acpi/Makefile.inc | 1 + src/acpi/sata.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ src/acpi/sata.h | 3 +++ 6 files changed, 74 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index d5ef301..f1475e6 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -52,7 +52,7 @@ PHONY+= clean-abuild coreboot lint lint-stable build-dirs ####################################################################### # root source directories of coreboot -subdirs-y := src/lib src/console src/device +subdirs-y := src/lib src/console src/device src/acpi subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) subdirs-y += $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) subdirs-y += src/superio $(wildcard src/drivers/*) src/cpu src/vendorcode diff --git a/src/Kconfig b/src/Kconfig index 5aa76fb..f685cc3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -330,6 +330,8 @@ config RAM_CODE_SUPPORT endmenu +source "src/acpi/Kconfig" + source "src/mainboard/Kconfig" source "src/arch/*/Kconfig" diff --git a/src/acpi/Kconfig b/src/acpi/Kconfig new file mode 100644 index 0000000..e025f99 --- /dev/null +++ b/src/acpi/Kconfig @@ -0,0 +1,6 @@ + +config ACPI_SATA_GENERATOR + bool + default n + help + Use acpi sata port generator. diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc new file mode 100644 index 0000000..53ac679 --- /dev/null +++ b/src/acpi/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_ACPI_SATA_GENERATOR) += sata.c diff --git a/src/acpi/sata.c b/src/acpi/sata.c new file mode 100644 index 0000000..b488574 --- /dev/null +++ b/src/acpi/sata.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Alexander Couzens <lynxis(a)fe80.eu> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include "sata.h" + +#include <arch/acpi.h> +#include <arch/acpigen.h> + +/* e.g. + * generate_sata_ssdt_ports("\_SB.PCI0.SATA", 0x3); + * generates: + * Scope (\_SB.PCI0.SATA) + * { + * Device (PRT0) + * { + * Name (_ADR, 0x0000FFFF) // _ADR: Address + * } + * + * Device (PRT1) + * { + * Name (_ADR, 0x0001FFFF) // _ADR: Address + * } + * } + */ +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map) +{ + int i; + int bit; + char port_name[4] = "PRT0"; + + acpigen_write_scope(scope); + + /* generate a device for every enabled port */ + for (i = 0; i < 8; i++) { + bit = 1 << i; + if (!(bit & enable_map)) + continue; + + port_name[3] = '0' + i; + acpigen_write_device(port_name); + + acpigen_write_name_dword("_ADR", 0xffff + i * 0x10000); + acpigen_pop_len(); /* close PRT%d */ + } + + acpigen_pop_len(); /* close scope */ +} diff --git a/src/acpi/sata.h b/src/acpi/sata.h new file mode 100644 index 0000000..b7f17b2 --- /dev/null +++ b/src/acpi/sata.h @@ -0,0 +1,3 @@ +#include <stdint.h> + +void generate_sata_ssdt_ports(const char *scope, uint8_t enable_map);

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Patch set updated for coreboot: f9c3df7 southbridge/bd82x6x: use new ssdt sata port generator
by Alexander Couzens 04 Jun '15

04 Jun '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709 -gerrit commit f9c3df7b6c7cb643e7f971ccdbf788a19e0ff014 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 ----------------------------- src/southbridge/intel/bd82x6x/sata.c | 8 +++++ 3 files changed, 9 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 6190879..3a68fec 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index fb685a3..00d3010 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -26,56 +26,4 @@ Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1cdc5e2..18e5a08 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -255,6 +261,8 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator + = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0,

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coreboot-gerrit June 2015