coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 58625ac bd82x6x, ibexpeak: Support fully locking ROM on S3 resume.
by Vladimir Serbinenko 13 May '15

13 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10191 -gerrit commit 58625ac1a44bf34b9fb878f7be24879e6dcf3b82 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue May 12 12:39:53 2015 +0200 bd82x6x, ibexpeak: Support fully locking ROM on S3 resume. Currently only RO-lock is supported. Make full lock available as an option. Change-Id: … [View More]Ib68a1e82733a51053a9adc80ac501b6205c6b8a7 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/Kconfig | 25 +++++++++++++++++++++++-- src/southbridge/intel/bd82x6x/finalize.c | 17 ++++++++++------- 2 files changed, 33 insertions(+), 9 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 8c51520..63118e1 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -151,9 +151,19 @@ config LOCK_MANAGEMENT_ENGINE If unsure, say N. -config LOCK_SPI_ON_RESUME +endif + +if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK + +choice + prompt "Flash ROM locking on S3 resume" + default LOCK_SPI_ON_RESUME_NONE + +config LOCK_SPI_ON_RESUME_NONE + bool "Don't lock ROM sections on S3 resume" + +config LOCK_SPI_ON_RESUME_RO bool "Lock all flash ROM sections on S3 resume" - default n help If the flash ROM shall be protected against write accesses from the operating system (OS), the locking procedure has to be repeated after @@ -161,4 +171,15 @@ config LOCK_SPI_ON_RESUME ROM from within your OS. Notice: Even with this option, the write lock has still to be enabled on the normal boot path (e.g. by the payload). +config LOCK_SPI_ON_RESUME_NO_ACCESS + bool "Lock and disable reads all flash ROM sections on S3 resume" + help + If the flash ROM shall be protected against write accesses from the + operating system (OS), the locking procedure has to be repeated after + each resume from S3. Select this if you never want to update the flash + ROM from within your OS. Notice: Even with this option, the write lock + has still to be enabled on the normal boot path (e.g. by the payload). + +endchoice + endif diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index ad2586c..df7b070 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -25,13 +25,16 @@ void intel_pch_finalize_smm(void) { -#if CONFIG_LOCK_SPI_ON_RESUME - /* Copy flash regions from FREG0-4 to PR0-4 - and enable write protection bit31 */ - int i; - for (i = 0; i < 20; i += 4) - RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | (1 << 31); -#endif + if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) { + /* Copy flash regions from FREG0-4 to PR0-4 + and enable write protection bit31 */ + int i; + u32 lockmask = (1 << 31); + if (CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) + lockmask |= (1 << 15); + for (i = 0; i < 20; i += 4) + RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; + } /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; [View Less]

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New patch to review for coreboot: 7a36b06 lenovo: Disable radio when suspending or turning off.
by Vladimir Serbinenko 13 May '15

13 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10190 -gerrit commit 7a36b06d61c8951cb1a9866c7b6ae2176ca25d3b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 13 18:22:49 2015 +0200 lenovo: Disable radio when suspending or turning off. Without this some radios may remain operational. The may consume power but the immediate demonstrable effect is wireless LED still being … [View More]on. Coreboot will reenable radios on resume or poweron. Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/acpi/ec.asl | 11 +++++++++++ src/mainboard/lenovo/t420s/acpi/platform.asl | 2 +- src/mainboard/lenovo/t430s/acpi/platform.asl | 2 +- src/mainboard/lenovo/t520/acpi/platform.asl | 2 +- src/mainboard/lenovo/t530/acpi/platform.asl | 2 +- src/mainboard/lenovo/t60/acpi/platform.asl | 1 + src/mainboard/lenovo/x200/acpi/platform.asl | 1 + src/mainboard/lenovo/x201/acpi/platform.asl | 1 + src/mainboard/lenovo/x220/acpi/platform.asl | 2 +- src/mainboard/lenovo/x230/acpi/platform.asl | 2 +- src/mainboard/lenovo/x60/acpi/platform.asl | 1 + 11 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 8db9221..b7f8741 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -43,6 +43,10 @@ Device(EC) EVNT, 8, /* write will trigger EC event */ Offset (0x3a), AMUT, 1, /* Audio Mute */ + , 3, + BTEB, 1, + WLEB, 1, + WWEB, 1, Offset (0x3B), , 1, KBLT, 1, /* Keyboard Light */ @@ -90,6 +94,13 @@ Device(EC) Store(Arg0, AMUT) } + Method (RADI, 1, NotSerialized) + { + Store(Arg0, WLEB) + Store(Arg0, WWEB) + Store(Arg0, BTEB) + } + Method (USBP, 1, NotSerialized) { Store(Arg0, USPW) diff --git a/src/mainboard/lenovo/t420s/acpi/platform.asl b/src/mainboard/lenovo/t420s/acpi/platform.asl index f937dc5..c59e26a 100644 --- a/src/mainboard/lenovo/t420s/acpi/platform.asl +++ b/src/mainboard/lenovo/t420s/acpi/platform.asl @@ -61,7 +61,7 @@ Method(_PIC, 1) Method(_PTS,1) { - + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/t430s/acpi/platform.asl b/src/mainboard/lenovo/t430s/acpi/platform.asl index f937dc5..c59e26a 100644 --- a/src/mainboard/lenovo/t430s/acpi/platform.asl +++ b/src/mainboard/lenovo/t430s/acpi/platform.asl @@ -61,7 +61,7 @@ Method(_PIC, 1) Method(_PTS,1) { - + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index f937dc5..c59e26a 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -61,7 +61,7 @@ Method(_PIC, 1) Method(_PTS,1) { - + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index 72b9dbf..3ce4a5e 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -61,7 +61,7 @@ Method(_PIC, 1) Method(_PTS,1) { - + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/t60/acpi/platform.asl b/src/mainboard/lenovo/t60/acpi/platform.asl index 59df530..8b50776 100644 --- a/src/mainboard/lenovo/t60/acpi/platform.asl +++ b/src/mainboard/lenovo/t60/acpi/platform.asl @@ -27,6 +27,7 @@ Method(_PTS,1) { \_SB.PCI0.LPCB.EC.MUTE(1) \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/x200/acpi/platform.asl b/src/mainboard/lenovo/x200/acpi/platform.asl index 2aa556f..d8f7a21 100644 --- a/src/mainboard/lenovo/x200/acpi/platform.asl +++ b/src/mainboard/lenovo/x200/acpi/platform.asl @@ -69,6 +69,7 @@ Method(_PTS,1) { // Call a trap so SMI can prepare for Sleep as well. // TRAP(0x55) + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 1370117..720e627 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -61,6 +61,7 @@ Method(_PTS,1) { \_SB.PCI0.LPCB.EC.MUTE(1) \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index 72b9dbf..3ce4a5e 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -61,7 +61,7 @@ Method(_PIC, 1) Method(_PTS,1) { - + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index 72b9dbf..3ce4a5e 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -61,7 +61,7 @@ Method(_PIC, 1) Method(_PTS,1) { - + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ diff --git a/src/mainboard/lenovo/x60/acpi/platform.asl b/src/mainboard/lenovo/x60/acpi/platform.asl index 59df530..8b50776 100644 --- a/src/mainboard/lenovo/x60/acpi/platform.asl +++ b/src/mainboard/lenovo/x60/acpi/platform.asl @@ -27,6 +27,7 @@ Method(_PTS,1) { \_SB.PCI0.LPCB.EC.MUTE(1) \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) } /* The _WAK method is called on system wakeup */ [View Less]

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New patch to review for coreboot: 8925970 x230: Fix VGA PCIIDs.
by Vladimir Serbinenko 13 May '15

13 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10189 -gerrit commit 8925970a266cc17ab5b4be2bc5785f283a360bb3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue May 12 14:43:16 2015 +0200 x230: Fix VGA PCIIDs. x230 is ivy, not sandy. Fix copy-paste error. Change-Id: Ic462bab39ddac0e1e6fef1e043970957e45fb6ed Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com&… [View More]

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Patch merged into coreboot/master: e7366da Include back the 306ax microcode again.
by gerrit＠coreboot.org 13 May '15

13 May '15

the following patch was just integrated into master: commit e7366daf2ed322aca1a44297c6bd586c8d634316 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue May 12 12:16:08 2015 +0200 Include back the 306ax microcode again. In ee89435798022021026f511deddf0e3b401ad031 microcode for 306ax was forgotten in migration. Without microcode update my machine experiences random hangs and various misbehaviour. Change-Id: … [View More]

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Patch set updated for coreboot: 20d5e63 Include back the 306ax microcode again.
by Vladimir Serbinenko 13 May '15

13 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10180 -gerrit commit 20d5e6348b4fc9394c59c2c2c82df05407884ec3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue May 12 12:16:08 2015 +0200 Include back the 306ax microcode again. In ee89435798022021026f511deddf0e3b401ad031 microcode for 306ax was forgotten in migration. Without microcode update my machine experiences random … [View More]

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Patch set updated for coreboot: 8cceae0 Include back the 306ax microcode again.
by Vladimir Serbinenko 13 May '15

13 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10180 -gerrit commit 8cceae0b1c3a31cc340a605326799bfc5bb1e00b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue May 12 12:16:08 2015 +0200 Include back the 306ax microcode again. mrnuke's migration to 3rdparty forgot to include microcode for 306ax. Breaking commit is ee89435798022021026f511deddf0e3b401ad031. Without … [View More]

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New patch to review for coreboot: 8d8305d console: Bring back newline translation
by Kyösti Mälkki 13 May '15

13 May '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10188 -gerrit commit 8d8305d7106c114d0899480a9e4180150a2053eb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 13 20:20:00 2015 +0300 console: Bring back newline translation Change-Id: Ib42f4a9eeb48dfb1a04e332aeb8f83dc4c4eef91 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 8 ++++… [View More]

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Patch merged into coreboot/master: 522149c cbmem: Add initial allocation support
by gerrit＠coreboot.org 13 May '15

13 May '15

the following patch was just integrated into master: commit 522149c310ad8885cd0b58a88cacac24852a541f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri May 8 11:33:55 2015 -0700 cbmem: Add initial allocation support Add support to allocate a region just below CBMEM root. This region is reserved for FSP 1.1 to use for its stack and variables. BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: … [View More]

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Patch merged into coreboot/master: 0a50d9b libpayload: x86: correct types used for IO
by gerrit＠coreboot.org 13 May '15

13 May '15

the following patch was just integrated into master: commit 0a50d9b35334d03f13b38e21497ba0aae8b16712 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 12 16:46:27 2015 -0500 libpayload: x86: correct types used for IO libpayload on x86 defines u32 and uint32_t as typedefs of unsigned int. However, the readl/writel routines use long. With alias checking this throws type punning errors. Align the readl/writel/inl/outl types with the 32-bit fixed width … [View More]

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Patch set updated for coreboot: 548e5fc Add 82945G/GC/GZ Integrated Graphics Controller PCI IDs.
by HAOUAS Elyes 13 May '15

13 May '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9804 -gerrit commit 548e5fc19770526022f0dc3dab4d44ac4f6025b5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue May 12 22:30:11 2015 +0200 Add 82945G/GC/GZ Integrated Graphics Controller PCI IDs. Change-Id: I548368ca580c2c4ec98d90778054ec12ad5b290e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/gma.c | 17 +++… [View More]

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coreboot-gerrit May 2015