coreboot-gerrit May 2015

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New patch to review for coreboot: ab3efce mainboard/google/cyan: Cyan board support
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10182 -gerrit commit ab3efcead4fdedc29ad2cc549cf611700ca7e458 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 11 17:24:31 2015 -0700 mainboard/google/cyan: Cyan board support Add initial files for the cyan board. BRANCH=none BUG=None Test=Build and run on cyan Change-Id: I935839be033c25e197e78fbee306104b4162a99a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/google/cyan/Kconfig | 62 +++++ src/mainboard/google/cyan/Kconfig.name | 2 + src/mainboard/google/cyan/Makefile.inc | 33 +++ src/mainboard/google/cyan/acpi/chromeos.asl | 37 +++ src/mainboard/google/cyan/acpi/dptf.asl | 93 +++++++ src/mainboard/google/cyan/acpi/ec.asl | 25 ++ src/mainboard/google/cyan/acpi/mainboard.asl | 266 +++++++++++++++++++++ src/mainboard/google/cyan/acpi/superio.asl | 34 +++ src/mainboard/google/cyan/acpi_tables.c | 236 ++++++++++++++++++ src/mainboard/google/cyan/chromeos.c | 142 +++++++++++ src/mainboard/google/cyan/cmos.layout | 140 +++++++++++ src/mainboard/google/cyan/com_init.c | 48 ++++ src/mainboard/google/cyan/devicetree.cb | 68 ++++++ src/mainboard/google/cyan/dsdt.asl | 58 +++++ src/mainboard/google/cyan/ec.c | 55 +++++ src/mainboard/google/cyan/ec.h | 69 ++++++ src/mainboard/google/cyan/fadt.c | 51 ++++ src/mainboard/google/cyan/fsp.c | 74 ++++++ src/mainboard/google/cyan/gpio.c | 266 +++++++++++++++++++++ src/mainboard/google/cyan/irqroute.c | 23 ++ src/mainboard/google/cyan/irqroute.h | 64 +++++ src/mainboard/google/cyan/mainboard.c | 27 +++ src/mainboard/google/cyan/onboard.h | 81 +++++++ src/mainboard/google/cyan/romstage.c | 43 ++++ src/mainboard/google/cyan/smihandler.c | 166 +++++++++++++ src/mainboard/google/cyan/spd/Makefile.inc | 42 ++++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 +++ src/mainboard/google/cyan/spd/spd.c | 115 +++++++++ src/mainboard/google/cyan/w25q64.c | 75 ++++++ 31 files changed, 2491 insertions(+) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig new file mode 100644 index 0000000..dd4543c --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig @@ -0,0 +1,62 @@ +if BOARD_GOOGLE_CYAN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 +# select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select VIRTUAL_DEV_SWITCH + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default google/cyan + +config MAINBOARD_PART_NUMBER + string + default "Cyan" + +config MAINBOARD_VENDOR + string + default "Google" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT + +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif + +endif # BOARD_GOOGLE_CYAN diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name new file mode 100644 index 0000000..a4562d3 --- /dev/null +++ b/src/mainboard/google/cyan/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_CYAN + bool "Cyan" diff --git a/src/mainboard/google/cyan/Makefile.inc b/src/mainboard/google/cyan/Makefile.inc new file mode 100755 index 0000000..840b43f --- /dev/null +++ b/src/mainboard/google/cyan/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c +romstage-y += fsp.c + +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += irqroute.c +ramstage-y += w25q64.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/cyan/acpi/chromeos.asl b/src/mainboard/google/cyan/acpi/chromeos.asl new file mode 100644 index 0000000..04edefa --- /dev/null +++ b/src/mainboard/google/cyan/acpi/chromeos.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: We need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + +Name(OIPG, Package() { + /* No physical recovery button */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, + Package () { 0x0003, 1, 0x2006, "Braswell" }, +}) diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl new file mode 100755 index 0000000..67bdbb4 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/braswell/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/cyan/acpi/ec.asl b/src/mainboard/google/cyan/acpi/ec.asl new file mode 100644 index 0000000..5736c27 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/cyan/acpi/mainboard.asl b/src/mainboard/google/cyan/acpi/mainboard.asl new file mode 100755 index 0000000..831453d --- /dev/null +++ b/src/mainboard/google/cyan/acpi/mainboard.asl @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <mainboard/google/cyan/onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} + +Scope (\_SB.I2C1) +{ + Device (ETSA) + { + Name (_HID, "ELAN0001") + Name (_DDN, "Elan Touchscreen ") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_TOUCH_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + /* Maxim Audio Codec */ + Device (MAXM) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + Device (TISW) /* TI Switch driver I2C */ + { + Name (_ADR, 0) + Name (_HID, TI_SWITCH_HID) + Name (_CID, TI_SWITCH_CID) + Name (_DDN, TI_SWITCH_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + TI_SWITCH_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSW") { CYAN_JACK_TI_GPIO_INDEX } + + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C5", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C6", /* ResourceSource */ + ) + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_TRACKPAD_GPIO_INDEX } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { CYAN_JACK_MAXIM_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, NotSerialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { CYAN_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/google/cyan/acpi/superio.asl b/src/mainboard/google/cyan/acpi/superio.asl new file mode 100755 index 0000000..018fdb0 --- /dev/null +++ b/src/mainboard/google/cyan/acpi/superio.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/google/cyan/ec.h> +#include <mainboard/google/cyan/onboard.h> + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Override default IRQ settings */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ + BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c new file mode 100755 index 0000000..4c77deb --- /dev/null +++ b/src/mainboard/google/cyan/acpi_tables.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> + +extern const unsigned char AmlCode[]; + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Enable DPTF */ + gnvs->dpte = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT (current = (ALIGN(current, 16))) + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + +#if CONFIG_GOP_SUPPORT + igd_opregion_t *opregion; + + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + ALIGN_CURRENT; +#endif + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i = 0; i < dsdt->length; i++) { + if (*(u32 *)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, + "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> %p\n", + i, gnvs); + *(u32 *)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ +#if IS_ENABLED(CONFIG_SMM_MODULES) + smm_setup_structures(gnvs, NULL, NULL); +#endif + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/google/cyan/chromeos.c b/src/mainboard/google/cyan/chromeos.c new file mode 100644 index 0000000..07de630 --- /dev/null +++ b/src/mainboard/google/cyan/chromeos.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ +#define WP_STATUS_PAD 36 + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + /* Default to force open. */ + return 1; +#endif +} + +static void fill_lb_gpio(struct lb_gpio *gpio, int port, int polarity, + const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = port; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + recovery_mode_enabled()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif /* ENV_RAMSTAGE */ + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + u32 ec_events; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int clear_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + const uint32_t kb_rec_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + /* Unconditionally clear the EC recovery request. */ + return google_chromeec_clear_events_b(kb_rec_mask); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ +#if ENV_ROMSTAGE + ssus_disable_internal_pull(WP_STATUS_PAD); +#endif + + /* WP is enabled when the pin is reading high. */ + return ssus_get_gpio(WP_STATUS_PAD); +} diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout new file mode 100644 index 0000000..18bf4ce --- /dev/null +++ b/src/mainboard/google/cyan/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/cyan/com_init.c b/src/mainboard/google/cyan/com_init.c new file mode 100644 index 0000000..b07b205 --- /dev/null +++ b/src/mainboard/google/cyan/com_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void mainboard_pre_console_init(struct romstage_params *params) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function for Cyan + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Set Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Set Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); +} diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb new file mode 100755 index 0000000..6ee81c3 --- /dev/null +++ b/src/mainboard/google/cyan/devicetree.cb @@ -0,0 +1,68 @@ +chip soc/intel/braswell + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 on end # 8086 22c3 - I2C Port 3 + device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 on end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 on end # 8086 2290 - SPI 2 + device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl new file mode 100755 index 0000000..9f1db24 --- /dev/null +++ b/src/mainboard/google/cyan/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/braswell/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/braswell/acpi/globalnvs.asl> + + #include <soc/intel/braswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* #include <soc/intel/braswell/acpi/northcluster.asl> */ + #include <soc/intel/braswell/acpi/southcluster.asl> + #include <soc/intel/braswell/acpi/dptf/cpu.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/braswell/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/cyan/ec.c b/src/mainboard/google/cyan/ec.c new file mode 100755 index 0000000..e233408 --- /dev/null +++ b/src/mainboard/google/cyan/ec.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + google_chromeec_set_wake_mask(0); +#endif + + post_code(0xf1); +} diff --git a/src/mainboard/google/cyan/ec.h b/src/mainboard/google/cyan/ec.h new file mode 100755 index 0000000..7e70d48 --- /dev/null +++ b/src/mainboard/google/cyan/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */ +#define EC_SCI_GPI 16 +/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 19 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c new file mode 100644 index 0000000..45a680a --- /dev/null +++ b/src/mainboard/google/cyan/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/cyan/fsp.c b/src/mainboard/google/cyan/fsp.c new file mode 100644 index 0000000..6cd5210 --- /dev/null +++ b/src/mainboard/google/cyan/fsp.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <lib.h> /* hexdump */ +#include <soc/romstage.h> + +#define BSW_SVID_CONFIG1 1 +#define BSW_SVID_CONFIG3 3 + +void board_fsp_memory_init_params( + struct romstage_params *params, + FSP_INFO_HEADER *fsp_header, + FSP_MEMORY_INIT_PARAMS *fsp_memory_init_params) +{ + FSP_INIT_RT_COMMON_BUFFER *rt_buffer; + UPD_DATA_REGION *upd_ptr; + + /* Initialize pointers to UPD and RT buffers */ + rt_buffer = fsp_memory_init_params->RtBufferPtr; + upd_ptr = rt_buffer->UpdDataRgnPtr; + + /* Update SPD and memory configuration data */ + upd_ptr->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + upd_ptr->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + upd_ptr->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +#if IS_ENABLED(CONFIG_GOP_SUPPORT) + /* Passing VBT table to FSP */ + upd_ptr->PcdGraphicsConfigPtr = (u32)params->pei_data->vbt_data; +#endif + + /* Set the I/O map */ + upd_ptr->PcdMrcInitTsegSize = 8; /* Use 8MB by default */ + + /* Enable/disable the devices */ + upd_ptr->PcdSdcardMode = params->pei_data->sdcard_mode; + upd_ptr->PcdEmmcMode = params->pei_data->emmc_mode; + upd_ptr->PcdEnableAzalia = params->pei_data->enable_azalia; + + /* Enable SVID and set the config policy */ + upd_ptr->PunitPwrConfigDisable = 0; + +#if CONFIG_DYNAMIC_VNN_SUPPORT + upd_ptr->ChvSvidConfig = BSW_SVID_CONFIG1; +#else + upd_ptr->ChvSvidConfig = BSW_SVID_CONFIG3; +#endif + + /* Disable IUNIT */ + upd_ptr->ISPEnable = 0; + + /* Disable FSP from locking access to the RTC NVRAM */ + upd_ptr->PcdRtcLock = 0; + + /* Disable SATA */ + upd_ptr->PcdEnableSata = 0; +} diff --git a/src/mainboard/google/cyan/gpio.c b/src/mainboard/google/cyan/gpio.c new file mode 100644 index 0000000..e754899 --- /dev/null +++ b/src/mainboard/google/cyan/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 78 HSIC AUX1 / SV Mode/ SATA_GP2 */ + Native_M1, /* 79 MF_SMB_ALERTB */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + GPIO_INPUT_PU_20K, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPO_FUNC(0, 0), /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + GPIO_NC, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/google/cyan/irqroute.c b/src/mainboard/google/cyan/irqroute.c new file mode 100644 index 0000000..83207d9 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/google/cyan/irqroute.h b/src/mainboard/google/cyan/irqroute.h new file mode 100644 index 0000000..5353d42 --- /dev/null +++ b/src/mainboard/google/cyan/irqroute.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/cyan/mainboard.c b/src/mainboard/google/cyan/mainboard.c new file mode 100755 index 0000000..f155a04 --- /dev/null +++ b/src/mainboard/google/cyan/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootstate.h> +#include <device/device.h> +#include <soc/gpio.h> + +struct chip_operations mainboard_ops = { +}; diff --git a/src/mainboard/google/cyan/onboard.h b/src/mainboard/google/cyan/onboard.h new file mode 100755 index 0000000..00ff28e --- /dev/null +++ b/src/mainboard/google/cyan/onboard.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +/* ToDO: change kbd irq to gpio bank index */ +#define CYAN_KBD_IRQ 182 + + +/* SCI: Gpio index in N bank */ +#define CYAN_SCI_GPIO_INDEX 15 +/* Trackpad: Gpio index in N bank */ +#define CYAN_TRACKPAD_GPIO_INDEX 18 +/* Touch: Gpio index in SW bank */ +#define CYAN_TOUCH_GPIO_INDEX 76 +/* TI Audio: Gpio index in SW bank */ +#define CYAN_JACK_TI_GPIO_INDEX 34 +/* MAXIM Audio: Gpio index in SE bank */ +#define CYAN_JACK_MAXIM_GPIO_INDEX 77 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#define BOARD_I8042_IRQ CYAN_KBD_IRQ +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "193C9890" +#define AUDIO_CODEC_CID "193C9890" +#define AUDIO_CODEC_DDN "Maxim 98090 Codec " +#define AUDIO_CODEC_I2C_ADDR 0x10 + +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_I2C_ADDR 0x3B +#endif diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c new file mode 100755 index 0000000..e2cf12d --- /dev/null +++ b/src/mainboard/google/cyan/romstage.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Set device state/enable information */ + ps->sdcard_mode = PCH_ACPI_MODE; + ps->emmc_mode = PCH_ACPI_MODE; + ps->enable_azalia = 1; + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c new file mode 100644 index 0000000..5af0421 --- /dev/null +++ b/src/mainboard/google/cyan/smihandler.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} +#endif + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +#endif + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case 5: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); +#endif + break; + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); +#endif + break; + case APM_CNT_ACPI_DISABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); +#endif + break; + } + return 0; +} diff --git a/src/mainboard/google/cyan/spd/Makefile.inc b/src/mainboard/google/cyan/spd/Makefile.inc new file mode 100644 index 0000000..40a3e0d --- /dev/null +++ b/src/mainboard/google/cyan/spd/Makefile.inc @@ -0,0 +1,42 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100644 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100644 index 0000000..fdd1a43 --- /dev/null +++ b/src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 +43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF diff --git a/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100644 index 0000000..e0b0ac5 --- /dev/null +++ b/src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 +88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c new file mode 100644 index 0000000..01f4dd7 --- /dev/null +++ b/src/mainboard/google/cyan/spd/spd.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> + +#define SPD_SIZE 256 +#define SATA_GP3_PAD_CFG0 0x5828 +#define I2C3_SCL_PAD_CFG0 0x5438 +#define MF_PLT_CLK1_PAD_CFG0 0x4410 +#define I2C3_SDA_PAD_CFG0 0x5420 + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = (1 << 0); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; + ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) + << 2; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + + /* + * There are only 2 SPDs supported on Cyan Board: + * Samsung 4G:0000 & Hynix 2G:0011 + */ + + /* + * RAMID0 on the first boot does not read the correct value,so checking + * bit 1 is enough as WA + */ + if (ram_id > 0) + ram_id = 3; + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + + if (ram_id >= total_spds) + return NULL; + + /* Single channel configs */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + struct cbfs_file *spd_file; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_SIZE); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} diff --git a/src/mainboard/google/cyan/w25q64.c b/src/mainboard/google/cyan/w25q64.c new file mode 100644 index 0000000..4399d88 --- /dev/null +++ b/src/mainboard/google/cyan/w25q64.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}

1 0

Patch set updated for coreboot: 5a20b9b DO NOT MERGE: Strago configuration file
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10055 -gerrit commit 5a20b9be3ad5f14834a9b1891fdc9b2f61d70e99 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:33:07 2015 -0700 DO NOT MERGE: Strago configuration file Add .config file to build for strago BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I145d1248e074ceeea9116997562f5f8777ba927c Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- .config | 542 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 542 insertions(+) diff --git a/.config b/.config new file mode 100644 index 0000000..737d98a --- /dev/null +++ b/.config @@ -0,0 +1,542 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +# CONFIG_EXPERT is not set +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +CONFIG_ANY_TOOLCHAIN=y +# CONFIG_CCACHE is not set +# CONFIG_USE_OPTION_TABLE is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +CONFIG_COLLECT_TIMESTAMPS=y +CONFIG_USE_BLOBS=y +# CONFIG_COVERAGE is not set +CONFIG_RELOCATABLE_MODULES=y +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="intel/strago" +CONFIG_MAINBOARD_PART_NUMBER="Strago" +CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_MAX_CPUS=4 +CONFIG_VGA_BIOS_ID="8086,22b0" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_DCACHE_RAM_BASE=0xfef00000 +CONFIG_DCACHE_RAM_SIZE=0x4000 +CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/intel/strago/vgabios.bin" +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Google" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_HAVE_IFD_BIN=y +CONFIG_HAVE_ME_BIN=y +CONFIG_BOOT_MEDIA_SPI_BUS=0 +CONFIG_TTYS0_LCS=3 +# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set +# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set +# CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set +# CONFIG_BOARD_INTEL_D810E2CB is not set +# CONFIG_BOARD_INTEL_D945GCLF is not set +# CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set +# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set +# CONFIG_BOARD_INTEL_MINNOWMAX is not set +# CONFIG_BOARD_INTEL_MOHONPEAK is not set +# CONFIG_BOARD_INTEL_MTARVON is not set +CONFIG_BOARD_INTEL_STRAGO=y +# CONFIG_BOARD_INTEL_TRUXTON is not set +# CONFIG_BOARD_INTEL_WTM2 is not set +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x100000 +CONFIG_FSP_FILE="3rdparty/mainboard/$(MAINBOARDDIR)/fsp/BSWFSP.fd" +CONFIG_CBFS_SIZE=0x100000 +CONFIG_VIRTUAL_ROM_SIZE=0x800000 +CONFIG_POST_IO=y +CONFIG_POST_DEVICE=y +CONFIG_SEABIOS_MALLOC_UPPERMEMORY=y +# CONFIG_DISPLAY_SPD_DATA is not set +# CONFIG_DYNAMIC_VNN_SUPPORT is not set +CONFIG_VBOOT_RAMSTAGE_INDEX=0x2 +CONFIG_VBOOT_REFCODE_INDEX=0x3 +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_USE_SECURE_MONITOR is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_BOOTBLOCK_CUSTOM is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_BOOTBLOCK_CUSTOM is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_BOOTBLOCK_CUSTOM is not set +# CONFIG_CPU_HAS_BOOTBLOCK_INIT is not set +# CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_VIRTUAL_DEV_SWITCH=y +# CONFIG_SYSTEM_TYPE_LAPTOP is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_CPU_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/braswell/bootblock/bootblock.c" +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF4C000 +CONFIG_IED_REGION_SIZE=0x400000 +CONFIG_SMM_RESERVED_SIZE=0x100000 +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +CONFIG_TSC_CONSTANT_RATE=y +CONFIG_TSC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +CONFIG_SMM_TSEG=y +CONFIG_SMM_MODULES=y +CONFIG_SMM_MODULE_HEAP_SIZE=0x4000 +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +CONFIG_PARALLEL_MP=y +CONFIG_BACKUP_DEFAULT_SMM_REGION=y +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_FSP_LOC=0xFFF6E000 +CONFIG_MRC_CACHE_SIZE=0x10000 +CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE=0x800 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_BUILD_WITH_FAKE_IFD is not set +CONFIG_IFD_BIN_PATH="3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set + +# +# Super I/O +# + +# +# Embedded Controllers +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_ENABLE_BUILTIN_COM1=y +CONFIG_SOC_INTEL_BRASWELL=y +CONFIG_CACHE_MRC_SETTINGS=y +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_SOC_INTEL_COMMON=y +CONFIG_CHIPSET_RESERVED_MEM_BYTES=0x0 +CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT=y +CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE=y +CONFIG_SOC_INTEL_COMMON_RESET=y +CONFIG_SOC_INTEL_COMMON_STACK=y +CONFIG_SOC_INTEL_COMMON_STAGE_CACHE=y +CONFIG_ROMSTAGE_RAM_STACK_SIZE=0x5000 +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set +CONFIG_HAVE_FSP_BIN=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_MRC_CACHE_LOC=0xfff50000 +CONFIG_USE_GENERIC_FSP_CAR_INC=y +# CONFIG_FSP_USES_UPD is not set + +# +# Devices +# +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_ALWAYS_LOAD_OPROM=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set + +# +# Intel FSP +# +CONFIG_PLATFORM_USES_FSP1_1=y +CONFIG_CPU_MICROCODE_CBFS_LEN=0x33FC0 +CONFIG_FSP_IMAGE_ID_DWORD0=0x57534224 +CONFIG_FSP_IMAGE_ID_DWORD1=0x24505346 +CONFIG_FSP_INCLUDE_PATH="3rdparty/mainboard/$(MAINBOARDDIR)/fsp" +CONFIG_MRC_CACHE_FILE="" +# CONFIG_DISPLAY_FAST_BOOT_DATA is not set +CONFIG_DISPLAY_HOBS=y +# CONFIG_DISPLAY_VBT is not set +CONFIG_DISPLAY_FSP_ENTRY_POINTS=y +# CONFIG_DISPLAY_UPD_DATA is not set +CONFIG_GOP_SUPPORT=y +CONFIG_VBT_FILE="3rdparty/mainboard/$(MAINBOARDDIR)/vbt.bin" +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_ATOMIC_SEQUENCING=y +CONFIG_SPI_FLASH_MEMORY_MAPPED=y +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +CONFIG_DEVICE_SPECIFIC_OPTIONS=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_HAVE_ACPI_RESUME is not set +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +# CONFIG_IOAPIC is not set +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +# CONFIG_PER_DEVICE_ACPI_TABLES is not set +# CONFIG_COMMON_FADT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Strago" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_LINUX is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_SEABIOS_STABLE=y +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3

1 0

Patch set updated for coreboot: 0cd1ca9 mainboard/intel/strago: Intel Braswell RVP support
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10052 -gerrit commit 0cd1ca9f9dd2d9635ecc287530f99b59d8c8fcea Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri May 1 10:34:54 2015 -0700 mainboard/intel/strago: Intel Braswell RVP support Initial files to support the Intel RVP for Braswell BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: I5cb2efe3d8adf919165c62b25e08c544b316a05a Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/strago/Kconfig | 61 +++++ src/mainboard/intel/strago/Kconfig.name | 2 + src/mainboard/intel/strago/Makefile.inc | 33 +++ src/mainboard/intel/strago/acpi/chromeos.asl | 37 +++ src/mainboard/intel/strago/acpi/dptf.asl | 93 +++++++ src/mainboard/intel/strago/acpi/ec.asl | 25 ++ src/mainboard/intel/strago/acpi/mainboard.asl | 259 ++++++++++++++++++++ src/mainboard/intel/strago/acpi/superio.asl | 34 +++ src/mainboard/intel/strago/acpi_tables.c | 236 ++++++++++++++++++ src/mainboard/intel/strago/chromeos.c | 142 +++++++++++ src/mainboard/intel/strago/cmos.layout | 140 +++++++++++ src/mainboard/intel/strago/com_init.c | 57 +++++ src/mainboard/intel/strago/devicetree.cb | 68 ++++++ src/mainboard/intel/strago/dsdt.asl | 58 +++++ src/mainboard/intel/strago/ec.c | 55 +++++ src/mainboard/intel/strago/ec.h | 69 ++++++ src/mainboard/intel/strago/fadt.c | 51 ++++ src/mainboard/intel/strago/fsp.c | 74 ++++++ src/mainboard/intel/strago/gpio.c | 266 +++++++++++++++++++++ src/mainboard/intel/strago/irqroute.c | 23 ++ src/mainboard/intel/strago/irqroute.h | 64 +++++ src/mainboard/intel/strago/mainboard.c | 27 +++ src/mainboard/intel/strago/onboard.h | 92 +++++++ src/mainboard/intel/strago/romstage.c | 43 ++++ src/mainboard/intel/strago/smihandler.c | 166 +++++++++++++ src/mainboard/intel/strago/spd/Makefile.inc | 41 ++++ .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 +++ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 +++ src/mainboard/intel/strago/spd/spd.c | 115 +++++++++ src/mainboard/intel/strago/w25q64.c | 75 ++++++ 31 files changed, 2502 insertions(+) diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig new file mode 100755 index 0000000..9d00969 --- /dev/null +++ b/src/mainboard/intel/strago/Kconfig @@ -0,0 +1,61 @@ +if BOARD_INTEL_STRAGO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ALWAYS_LOAD_OPROM + select BOARD_ROMSIZE_KB_8192 +# select ENABLE_BUILTIN_COM1 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select VIRTUAL_DEV_SWITCH + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory configuration data. + +config DISPLAY_SPD_DATA + bool "Display Memory Serial Presence Detect Data" + default n + help + When enabled displays the memory SPD data. + +config DYNAMIC_VNN_SUPPORT + bool "Enables support for Dynamic VNN" + default n + +config MAINBOARD_DIR + string + default intel/strago + +config MAINBOARD_PART_NUMBER + string + default "Strago" + +config MAINBOARD_VENDOR + string + default "Intel" + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +if !CONFIG_GOP_SUPPORT +config VGA_BIOS_FILE + string + default "3rdparty/mainboard/intel/strago/vgabios_c0.bin" if C0_DISP_SUPPORT + default "3rdparty/mainboard/intel/strago/vgabios.bin" if !C0_DISP_SUPPORT + +config VGA_BIOS_ID + string + default "8086,22b1" if C0_DISP_SUPPORT + default "8086,22b0" if !C0_DISP_SUPPORT +endif + +endif # BOARD_INTEL_STRAGO diff --git a/src/mainboard/intel/strago/Kconfig.name b/src/mainboard/intel/strago/Kconfig.name new file mode 100644 index 0000000..aae2379 --- /dev/null +++ b/src/mainboard/intel/strago/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_STRAGO + bool "Strago" diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc new file mode 100755 index 0000000..840b43f --- /dev/null +++ b/src/mainboard/intel/strago/Makefile.inc @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += spd + +romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c +romstage-y += fsp.c + +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c +ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c +ramstage-y += irqroute.c +ramstage-y += w25q64.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl new file mode 100644 index 0000000..04edefa --- /dev/null +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: We need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + +Name(OIPG, Package() { + /* No physical recovery button */ + Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, + Package () { 0x0003, 1, 0x2006, "Braswell" }, +}) diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl new file mode 100755 index 0000000..67bdbb4 --- /dev/null +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6200, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/braswell/acpi/dptf/dptf.asl> diff --git a/src/mainboard/intel/strago/acpi/ec.asl b/src/mainboard/intel/strago/acpi/ec.asl new file mode 100755 index 0000000..4733a60 --- /dev/null +++ b/src/mainboard/intel/strago/acpi/ec.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2105 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/intel/strago/ec.h> + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl new file mode 100755 index 0000000..3528467 --- /dev/null +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -0,0 +1,259 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <mainboard/intel/strago/onboard.h> + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + Return (\LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> +} +Scope (\_SB.I2C1) +{ + Device (ATSB) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen Bootloader") + Name (_UID, 4) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x26, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C1", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.I2C2) +{ + /* Realtek Audio Codec */ + Device (RTEK) /* Audio Codec driver I2C */ + { + Name (_ADR, 0) + Name (_HID, AUDIO_CODEC_HID) + Name (_CID, AUDIO_CODEC_CID) + Name (_DDN, AUDIO_CODEC_DDN) + Name (_UID, 1) + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, /* SlaveAddress: bus address */ + ControllerInitiated, /* SlaveMode: default to ControllerInitiated */ + 400000, /* ConnectionSpeed: in Hz */ + AddressingMode7Bit, /* Addressing Mode: default to 7 bit */ + "\\_SB.I2C2", /* ResourceSource: I2C bus controller name */ + ) + + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_CODEC_IRQ + } + + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { JACK_DETECT_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C5", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C6) +{ + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x15, /* SlaveAddress */ + ControllerInitiated, /* SlaveMode */ + 400000, /* ConnectionSpeed */ + AddressingMode7Bit, /* AddressingMode */ + "\\_SB.I2C6", /* ResourceSource */ + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } +} + +Scope (\_SB.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { JACK_DETECT_GPIO_INDEX } + }) +} diff --git a/src/mainboard/intel/strago/acpi/superio.asl b/src/mainboard/intel/strago/acpi/superio.asl new file mode 100755 index 0000000..931678b --- /dev/null +++ b/src/mainboard/intel/strago/acpi/superio.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* mainboard configuration */ +#include <mainboard/intel/strago/ec.h> +#include <mainboard/intel/strago/onboard.h> + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Override default IRQ settings */ +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\ + BOARD_I8042_IRQ} + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c new file mode 100755 index 0000000..4c77deb --- /dev/null +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> + +extern const unsigned char AmlCode[]; + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Enable DPTF */ + gnvs->dpte = 1; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT (current = (ALIGN(current, 16))) + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + global_nvs_t *gnvs; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_intel_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + +#if CONFIG_GOP_SUPPORT + igd_opregion_t *opregion; + + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + ALIGN_CURRENT; +#endif + + /* Update GNVS pointer into CBMEM */ + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_DEBUG, "ACPI: Could not find CBMEM GNVS\n"); + gnvs = (global_nvs_t *)current; + } + + for (i = 0; i < dsdt->length; i++) { + if (*(u32 *)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, + "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> %p\n", + i, gnvs); + *(u32 *)(((u32)dsdt) + i) = (unsigned long)gnvs; + acpi_save_gnvs((unsigned long)gnvs); + break; + } + } + + /* And fill it */ + acpi_create_gnvs(gnvs); + + /* And tell SMI about it */ +#if IS_ENABLED(CONFIG_SMM_MODULES) + smm_setup_structures(gnvs, NULL, NULL); +#endif + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c new file mode 100755 index 0000000..07de630 --- /dev/null +++ b/src/mainboard/intel/strago/chromeos.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#endif +#include <soc/gpio.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ +#define WP_STATUS_PAD 36 + +#if ENV_RAMSTAGE +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +static int get_lid_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + return !!(ec_switches & EC_SWITCH_LID_OPEN); +#else + /* Default to force open. */ + return 1; +#endif +} + +static void fill_lb_gpio(struct lb_gpio *gpio, int port, int polarity, + const char *name, int force) +{ + memset(gpio, 0, sizeof(*gpio)); + gpio->port = port; + gpio->polarity = polarity; + if (force >= 0) + gpio->value = force; + strncpy((char *)gpio->name, name, GPIO_MAX_NAME_LENGTH); +} + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", + recovery_mode_enabled()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", get_lid_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", oprom_is_loaded); +} +#endif /* ENV_RAMSTAGE */ + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + u8 ec_switches; + u32 ec_events; + + mec_io_bytes(0, EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES, 1, + &ec_switches, NULL); + + /* If a switch is set, we don't need to look at events. */ + if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY)) + return 1; + + /* Else check if the EC has posted the keyboard recovery event. */ + ec_events = google_chromeec_get_events_b(); + + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +#else + return 0; +#endif +} + +int clear_recovery_mode_switch(void) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + const uint32_t kb_rec_mask = + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY); + /* Unconditionally clear the EC recovery request. */ + return google_chromeec_clear_events_b(kb_rec_mask); +#else + return 0; +#endif +} + +int get_write_protect_state(void) +{ + /* + * The vboot loader queries this function in romstage. The GPIOs have + * not been set up yet as that configuration is done in ramstage. The + * hardware defaults to an input but there is a 20K pulldown. Externally + * there is a 10K pullup. Disable the internal pull in romstage so that + * there isn't any ambiguity in the reading. + */ +#if ENV_ROMSTAGE + ssus_disable_internal_pull(WP_STATUS_PAD); +#endif + + /* WP is enabled when the pin is reading high. */ + return ssus_get_gpio(WP_STATUS_PAD); +} diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout new file mode 100644 index 0000000..18bf4ce --- /dev/null +++ b/src/mainboard/intel/strago/cmos.layout @@ -0,0 +1,140 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/intel/strago/com_init.c b/src/mainboard/intel/strago/com_init.c new file mode 100755 index 0000000..c982178 --- /dev/null +++ b/src/mainboard/intel/strago/com_init.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +/* + * return family number and internal pad number in that community + * by pad number and which community it is in. + */ + + + + /* family number in high byte and inner pad number in lowest byte */ + +void mainboard_pre_console_init(struct romstage_params *params) +{ + uint32_t reg; + uint32_t *pad_config_reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* + * Set up the pads to select the UART function for Strago + * AD12 SW16(UART1_DATAIN/UART0_DATAIN) - Setting Mode 2 for UART0_RXD + * AD10 SW20(UART1_DATAOUT/UART0_DATAOUT) - Setting Mode 2 for UART0_TXD + */ + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_RXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); + + pad_config_reg = gpio_pad_config_reg(GP_SOUTHWEST, UART1_TXD_PAD); + write32(pad_config_reg, SET_PAD_MODE_SELECTION(PAD_CONFIG0_DEFAULT0, + M2)); +} diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb new file mode 100755 index 0000000..6ee81c3 --- /dev/null +++ b/src/mainboard/intel/strago/devicetree.cb @@ -0,0 +1,68 @@ +chip soc/intel/braswell + + # LPE audio codec settings + register "lpe_codec_clk_freq" = "25" # 25MHz clock + register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + + # Enable devices in ACPI mode + register "lpss_acpi_mode" = "1" + register "emmc_acpi_mode" = "1" + register "sd_acpi_mode" = "1" + register "lpe_acpi_mode" = "1" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + # EDS Table 24-4, Figure 24-5 + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 on end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 on end # 8086 22dc - ? + device pci 10.0 on end # 8086 2294 - MMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port + device pci 13.0 off end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 on end # 8086 22c3 - I2C Port 3 + device pci 18.4 on end # 8086 22c4 - I2C Port 4 + device pci 18.5 on end # 8086 22c5 - I2C Port 5 + device pci 18.6 on end # 8086 22c6 - I2C Port 6 + device pci 18.7 on end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 0F18 - Trusted Execution Engine + device pci 1b.0 on end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 0000 - PCIe Root Port 2 + device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3 + device pci 1c.3 on end # 8086 0000 - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.1 off end # 8086 0F08 - PWM 1 + device pci 1e.2 off end # 8086 0F09 - PWM 2 + device pci 1e.3 on end # 8086 228a - HSUART 1 + device pci 1e.4 on end # 8086 228c - HSUART 2 + device pci 1e.5 on end # 8086 228e - SPI 1 + device pci 1e.6 on end # 8086 2290 - SPI 2 + device pci 1e.7 on end # 8086 22ac - SPI 3 + device pci 1f.0 on # 8086 229c - LPC bridge + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC Bridge + device pci 1f.3 off end # 8086 0F12 - SMBus 0 + end +end diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl new file mode 100755 index 0000000..9f1db24 --- /dev/null +++ b/src/mainboard/intel/strago/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, /* DSDT revision: ACPI v5.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + /* Some generic macros */ + #include <soc/intel/braswell/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/braswell/acpi/globalnvs.asl> + + #include <soc/intel/braswell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* #include <soc/intel/braswell/acpi/northcluster.asl> */ + #include <soc/intel/braswell/acpi/southcluster.asl> + #include <soc/intel/braswell/acpi/dptf/cpu.asl> + } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" + } + + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + /* Chipset specific sleep states */ + #include <soc/intel/braswell/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/strago/ec.c b/src/mainboard/intel/strago/ec.c new file mode 100755 index 0000000..8debaa4 --- /dev/null +++ b/src/mainboard/intel/strago/ec.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include "ec.h" +#include <vendorcode/google/chromeos/chromeos.h> +#include <types.h> + +void mainboard_ec_init(void) +{ + printk(BIOS_DEBUG, "mainboard_ec_init\n"); + post_code(0xf0); + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Restore SCI event mask on resume. */ + if (acpi_slp_type == 3) { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S3_WAKE_EVENTS); + + /* Disable SMI and wake events */ + google_chromeec_set_smi_mask(0); + + /* Clear pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + } else { + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | + MAINBOARD_EC_S5_WAKE_EVENTS); + } + + /* Clear wake events, these are enabled on entry to sleep */ + google_chromeec_set_wake_mask(0); +#endif + post_code(0xf1); +} diff --git a/src/mainboard/intel/strago/ec.h b/src/mainboard/intel/strago/ec.h new file mode 100755 index 0000000..7e70d48 --- /dev/null +++ b/src/mainboard/intel/strago/ec.h @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPIO_S0_000 is EC_SCI#, but it is bit 16 in GPE_STS */ +#define EC_SCI_GPI 16 +/* GPIO_S5_07 is EC_SMI#, but it is bit 19 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 19 + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c new file mode 100755 index 0000000..45a680a --- /dev/null +++ b/src/mainboard/intel/strago/fadt.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/intel/strago/fsp.c b/src/mainboard/intel/strago/fsp.c new file mode 100755 index 0000000..6cd5210 --- /dev/null +++ b/src/mainboard/intel/strago/fsp.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <lib.h> /* hexdump */ +#include <soc/romstage.h> + +#define BSW_SVID_CONFIG1 1 +#define BSW_SVID_CONFIG3 3 + +void board_fsp_memory_init_params( + struct romstage_params *params, + FSP_INFO_HEADER *fsp_header, + FSP_MEMORY_INIT_PARAMS *fsp_memory_init_params) +{ + FSP_INIT_RT_COMMON_BUFFER *rt_buffer; + UPD_DATA_REGION *upd_ptr; + + /* Initialize pointers to UPD and RT buffers */ + rt_buffer = fsp_memory_init_params->RtBufferPtr; + upd_ptr = rt_buffer->UpdDataRgnPtr; + + /* Update SPD and memory configuration data */ + upd_ptr->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + upd_ptr->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + upd_ptr->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +#if IS_ENABLED(CONFIG_GOP_SUPPORT) + /* Passing VBT table to FSP */ + upd_ptr->PcdGraphicsConfigPtr = (u32)params->pei_data->vbt_data; +#endif + + /* Set the I/O map */ + upd_ptr->PcdMrcInitTsegSize = 8; /* Use 8MB by default */ + + /* Enable/disable the devices */ + upd_ptr->PcdSdcardMode = params->pei_data->sdcard_mode; + upd_ptr->PcdEmmcMode = params->pei_data->emmc_mode; + upd_ptr->PcdEnableAzalia = params->pei_data->enable_azalia; + + /* Enable SVID and set the config policy */ + upd_ptr->PunitPwrConfigDisable = 0; + +#if CONFIG_DYNAMIC_VNN_SUPPORT + upd_ptr->ChvSvidConfig = BSW_SVID_CONFIG1; +#else + upd_ptr->ChvSvidConfig = BSW_SVID_CONFIG3; +#endif + + /* Disable IUNIT */ + upd_ptr->ISPEnable = 0; + + /* Disable FSP from locking access to the RTC NVRAM */ + upd_ptr->PcdRtcLock = 0; + + /* Disable SATA */ + upd_ptr->PcdEnableSata = 0; +} diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c new file mode 100755 index 0000000..aa9d587 --- /dev/null +++ b/src/mainboard/intel/strago/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + Native_M1,/* MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ + GPIO_NC, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* PWM0 05 */ + GPIO_NC, /* 06 MF_PLT_CLK5 */ + GPIO_NC, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + Native_M1, /* 16 SDMMC1_CLK */ + NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ + NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ + NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ + Native_M1, /* 31 SDMMC3_CLK */ + NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ + NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ + NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ + NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + Native_M1, /* 48 LPC_FRAMEB */ + Native_M1, /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + Native_M1,/* SPI1_MISO */ + Native_M1, /* 61 SPI1_CS0_B */ + Native_M1, /* SPI1_CLK */ + NATIVE_PU20K(1), /* 63 MMC1_D6 */ + Native_M1, /* 62 SPI1_MOSI */ + NATIVE_PU20K(1), /* 65 MMC1_D5 */ + GPIO_NC, /* SPI1_CS1_B 66 */ + NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ + NATIVE_PU20K(1), /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + Native_M1, /* 75 GPO USB_OC1_B */ + Native_M1, /* 76 PMU_RESETBUTTON_B */ + GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), + /* GPIO_ALERT 77 */ + Native_M1, /* 78 SDMMC3_PWR_EN_B */ + GPIO_NC, /* 79 GPI ILB_SERIRQ */ + Native_M1, /* 80 USB_OC0_B */ + NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPIO_NC, /* 82 spkr asummed gpio number */ + Native_M1, /* 83 SUSPWRDNACK */ + SPARE_PIN,/* 84 spare pin */ + Native_M1, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + GPIO_NC, /* 00 FST_SPI_D2 */ + Native_M1, /* 01 FST_SPI_D0 */ + Native_M1, /* 02 FST_SPI_CLK */ + GPIO_NC, /* 03 FST_SPI_D3 */ + GPIO_NC, /* GPO FST_SPI_CS1_B */ + Native_M1, /* 05 FST_SPI_D1 */ + Native_M1, /* 06 FST_SPI_CS0_B */ + GPIO_OUT_HIGH, /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + Native_M2, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + Native_M2, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + GPIO_NC, /* 22 UART2_CTS_B */ + GPIO_NC, /* 30 MF_HDA_CLK */ + GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ + GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + GPIO_NC, /* 33 MF_HDA_SDO */ + GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 34 MF_HDA_DOCKRSTB */ + GPIO_NC, /* 35 MF_HDA_SYNC */ + GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), + /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ + GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ + GPIO_NC, /* 49 I2C_NFC_SDA */ + GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ + GPIO_NC, /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ + GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ + NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ + GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ + GPIO_OUT_HIGH, /* 75 SATA_GP0 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 76 GPI SATA_GP1 */ + Native_M1, /* 77 SATA_LEDN */ + GPIO_NC, /* 80 SATA_GP3 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ + Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ + Native_M1, /* 90 PCIE_CLKREQ0B */ + GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ + Native_M1, /* 92 GP_SSP_2_CLK */ + GPIO_INPUT_PU_20K, /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ + Native_M1, /* 94 GP_SSP_2_RXD */ + GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), + /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ + Native_M1, /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + Native_M5, /* 00 GPIO_DFX0 */ + Native_M5, /* 01 GPIO_DFX3 */ + Native_M1, /* 02 GPIO_DFX7 */ + Native_M5, /* 03 GPIO_DFX1 */ + Native_M1, /* 04 GPIO_DFX5 */ + Native_M1, /* 05 GPIO_DFX4 */ + GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), + /* 06 GPIO_DFX8 */ + Native_M5, /* 07 GPIO_DFX2 */ + Native_M8, /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ + GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 18 GPIO_SUS7 */ + GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPIO_NC, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 22 GPIO_SUS4 */ + GPIO_NC, + /* 23 SEC_GPIO_SUS8 */ + Native_M6, /* 24 GPIO_SUS2 */ + GPIO_SCI(L6),/* 25 GPIO_SUS6 */ + Native_M1, /* 26 CX_PREQ_B */ + GPIO_NC, /* 27 SEC_GPIO_SUS9 */ + Native_M1, /* 30 TRST_B */ + Native_M1, /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + Native_M1, /* 34 TMS */ + GPIO_NC, /* 35 CX_PRDY_B_2 */ + GPIO_NC, /* 36 TDO_2 */ + Native_M1, /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + Native_M1, /* 41 TDI */ + Native_M2, /* 45 GP_CAMERASB05 */ + Native_M2, /* 46 GP_CAMERASB02 */ + Native_M2, /* 47 GP_CAMERASB08 */ + Native_M2, /* 48 GP_CAMERASB00 */ + Native_M2, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + Native_M2, /* 51 GP_CAMERASB03 */ + GPIO_NC, /* 52 GP_CAMERASB09 */ + Native_M2, /* 53 GP_CAMERASB01 */ + Native_M2, /* 54 GP_CAMERASB07 */ + GPIO_NC, /* 55 GP_CAMERASB11 */ + Native_M2, /* 56 GP_CAMERASB04 */ + GPIO_NC, /* 60 PANEL0_BKLTEN */ + Native_M1, /* 61 HV_DDI0_HPD */ + NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ + GPIO_NC, /* 65 PANEL0_BKLTCTL */ + GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ + NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ + GPIO_NC, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + Native_M1, /* 00 PMU_SLP_S3_B */ + GPIO_NC, /* 01 PMU_BATLOW_B */ + Native_M1, /* 02 SUS_STAT_B */ + Native_M1, /* 03 PMU_SLP_S0IX_B */ + Native_M1, /* 04 PMU_AC_PRESENT */ + Native_M1, /* 05 PMU_PLTRST_B */ + Native_M1, /* 06 PMU_SUSCLK */ + GPIO_NC, /* 07 PMU_SLP_LAN_B */ + Native_M1, /* 08 PMU_PWRBTN_B */ + Native_M1, /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + GPIO_NC, /* 15 MF_GPIO_3 */ + GPIO_NC, /* 16 MF_GPIO_7 */ + GPIO_NC, /* 17 MF_I2C1_SCL */ + GPIO_NC, /* 18 MF_GPIO_1 */ + GPIO_NC, /* 19 MF_GPIO_5 */ + GPIO_NC, /* 20 MF_GPIO_9 */ + GPIO_NC, /* 21 MF_GPIO_0 */ + GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_NC, /* 23 MF_GPIO_8 */ + GPIO_NC, /* 24 MF_GPIO_2 */ + GPIO_NC, /* 25 MF_GPIO_6 */ + GPIO_NC, /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/intel/strago/irqroute.c b/src/mainboard/intel/strago/irqroute.c new file mode 100644 index 0000000..83207d9 --- /dev/null +++ b/src/mainboard/intel/strago/irqroute.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/strago/irqroute.h b/src/mainboard/intel/strago/irqroute.h new file mode 100644 index 0000000..5353d42 --- /dev/null +++ b/src/mainboard/intel/strago/irqroute.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, DISABLE), \ + PIRQ_PIC(B, DISABLE), \ + PIRQ_PIC(C, DISABLE), \ + PIRQ_PIC(D, DISABLE), \ + PIRQ_PIC(E, DISABLE), \ + PIRQ_PIC(F, DISABLE), \ + PIRQ_PIC(G, DISABLE), \ + PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c new file mode 100755 index 0000000..f155a04 --- /dev/null +++ b/src/mainboard/intel/strago/mainboard.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootstate.h> +#include <device/device.h> +#include <soc/gpio.h> + +struct chip_operations mainboard_ops = { +}; diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h new file mode 100755 index 0000000..7ae593a --- /dev/null +++ b/src/mainboard/intel/strago/onboard.h @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + +/* + * gpio based irq for kbd, 17th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 18 + */ +#define STRAGO_KBD_IRQ 230 + +/* + * gpio based irq for trackpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define STRAGO_TRACKPAD_IRQ 231 + +/* + * gpio based irq for touchscreen, 76th index in SW Bank + * MAX_DIRECT_IRQ + 77 + */ +#define STRAGO_TOUCH_IRQ 191 + +/* Gpio index or offset number in SE bank */ +#define JACK_DETECT_GPIO_INDEX 77 + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ STRAGO_TRACKPAD_IRQ +#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1) +#define BOARD_TRACKPAD_I2C_BUS 5 +#define BOARD_TRACKPAD_I2C_ADDR 0x15 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ STRAGO_TOUCH_IRQ +#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2) +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#define BOARD_I8042_IRQ STRAGO_KBD_IRQ +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) + +/* + * gpio based irq for codec irq, 77th index in GPSE Bank + * MAX_DIRECT_IRQ+GPSW_SIZE+GPNC_SIZE +GPEC_SIZE + 78 + */ +#define BOARD_CODEC_IRQ 390 + +/* SD CARD gpio */ +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "193C9890" +#define AUDIO_CODEC_CID "193C9890" +#define AUDIO_CODEC_DDN "Maxim 98090 Codec " +#define AUDIO_CODEC_I2C_ADDR 0x10 + +#define AUDIO_JACK_IRQ 149 +#define TI_SWITCH_HID "104C227E" +#define TI_SWITCH_CID "104C227E" +#define TI_SWITCH_DDN "TI SWITCH " +#define TI_SWITCH_I2C_ADDR 0x3B +#endif diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c new file mode 100755 index 0000000..e2cf12d --- /dev/null +++ b/src/mainboard/intel/strago/romstage.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <string.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Set device state/enable information */ + ps->sdcard_mode = PCH_ACPI_MODE; + ps->emmc_mode = PCH_ACPI_MODE; + ps->enable_azalia = 1; + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c new file mode 100755 index 0000000..5af0421 --- /dev/null +++ b/src/mainboard/intel/strago/smihandler.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include "ec.h" +#include <ec/google/chromeec/ec.h> +#include <elog.h> +#include <soc/nvs.h> +#include <soc/pm.h> + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if IS_ENABLED(CONFIG_ELOG_GSMI) + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} +#endif + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); +#endif + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case 5: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); +#endif + break; + } + +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0) + ; +#endif +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); +#endif + break; + case APM_CNT_ACPI_DISABLE: +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0) + ; + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS); +#endif + break; + } + return 0; +} diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc new file mode 100755 index 0000000..86808af --- /dev/null +++ b/src/mainboard/intel/strago/spd/Makefile.inc @@ -0,0 +1,41 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c +SPD_BIN = $(obj)/spd.bin + +SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR +SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 +SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex new file mode 100755 index 0000000..ff4fd29 --- /dev/null +++ b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex @@ -0,0 +1,32 @@ +92 12 0b 03 04 19 02 02 +03 52 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 81 +20 08 3c 3c 01 40 83 01 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 ad 01 +00 00 00 00 00 00 ff ab +48 4d 54 34 32 35 53 36 +41 46 52 36 41 2d 50 42 +20 20 4e 30 80 ad 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex new file mode 100755 index 0000000..fdd1a43 --- /dev/null +++ b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex @@ -0,0 +1,32 @@ +92 13 0B 03 04 19 02 02 +03 52 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 01 +00 00 00 00 00 00 00 00 +00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 11 62 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 +00 00 00 00 00 00 C9 C0 +48 4D 54 34 32 35 53 36 +43 46 52 36 41 2D 50 42 +20 20 4E 30 80 AD 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF diff --git a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex new file mode 100755 index 0000000..e0b0ac5 --- /dev/null +++ b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex @@ -0,0 +1,32 @@ +92 12 0B 03 04 19 02 02 +03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 +20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 +88 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 +00 00 00 00 00 00 6C F9 +4D 34 37 31 42 35 36 37 +34 51 48 30 2D 59 4B 30 +20 20 00 00 80 CE 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c new file mode 100755 index 0000000..01f4dd7 --- /dev/null +++ b/src/mainboard/intel/strago/spd/spd.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <lib.h> +#include <soc/gpio.h> +#include <soc/romstage.h> +#include <string.h> + +#define SPD_SIZE 256 +#define SATA_GP3_PAD_CFG0 0x5828 +#define I2C3_SCL_PAD_CFG0 0x5438 +#define MF_PLT_CLK1_PAD_CFG0 0x4410 +#define I2C3_SDA_PAD_CFG0 0x5420 + +/* + * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz + * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz + */ +static const uint32_t dual_channel_config = (1 << 0); + +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) +{ + int ram_id = 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; + ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) + << 2; + ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; + + /* + * There are only 2 SPDs supported on Cyan Board: + * Samsung 4G:0000 & Hynix 2G:0011 + */ + + /* + * RAMID0 on the first boot does not read the correct value,so checking + * bit 1 is enough as WA + */ + if (ram_id > 0) + ram_id = 3; + printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); + + if (ram_id >= total_spds) + return NULL; + + /* Single channel configs */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + + return &spd_file_content[SPD_SIZE * ram_id]; +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + struct cbfs_file *spd_file; + void *spd_content; + int dual_channel = 0; + + /* Find the SPD data in CBFS. */ + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + + /* + * Both channels are always present in SPD data. Always use matched + * DIMMs so use the same SPD data for each DIMM. + */ + spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), + ntohl(spd_file->len) / SPD_SIZE, + &dual_channel); + if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { + printk(BIOS_DEBUG, "SPD Data:\n"); + hexdump(spd_content, SPD_SIZE); + printk(BIOS_DEBUG, "\n"); + } + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + if (spd_content != NULL) { + ps->spd_data_ch0 = spd_content; + ps->spd_ch0_config = 1; + if (dual_channel) { + ps->spd_data_ch1 = spd_content; + ps->spd_ch1_config = 1; + } else { + ps->spd_ch1_config = 2; + } + } +} diff --git a/src/mainboard/intel/strago/w25q64.c b/src/mainboard/intel/strago/w25q64.c new file mode 100755 index 0000000..4399d88 --- /dev/null +++ b/src/mainboard/intel/strago/w25q64.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <soc/spi.h> +#include <string.h> + +/* + * SPI lockdown configuration W25Q64FW. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0)) +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0)) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0)) +#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB) + +static const struct spi_config spi_config = { + .preop = SPI_OPPREFIX, + .optype = SPI_OPTYPE, + .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER }, + .lvscc = SPI_VSCC, + .uvscc = SPI_VSCC, +}; + +int mainboard_get_spi_config(struct spi_config *cfg) +{ + memcpy(cfg, &spi_config, sizeof(*cfg)); + + return 0; +}

1 0

Patch set updated for coreboot: 3f2536d Braswell: Add Braswell SOC support
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10051 -gerrit commit 3f2536d799d28f61b671111b6ed2ff6c20cd1ad5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:20:28 2015 -0700 Braswell: Add Braswell SOC support Add the files to support the Braswell SOC. BRANCH=none BUG=None TEST=Build for a Braswell platform Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/braswell/Kconfig | 159 ++--- src/soc/intel/braswell/Makefile.inc | 99 +-- src/soc/intel/braswell/acpi.c | 159 +++-- src/soc/intel/braswell/acpi/cpu.asl | 50 +- src/soc/intel/braswell/acpi/device_nvs.asl | 110 +-- src/soc/intel/braswell/acpi/dptf/cpu.asl | 86 ++- src/soc/intel/braswell/acpi/dptf/dptf.asl | 11 +- src/soc/intel/braswell/acpi/dptf/thermal.asl | 12 +- src/soc/intel/braswell/acpi/dptf/wifi.asl | 16 + src/soc/intel/braswell/acpi/dptf/wwan.asl | 16 + src/soc/intel/braswell/acpi/globalnvs.asl | 65 +- src/soc/intel/braswell/acpi/gpio.asl | 69 +- src/soc/intel/braswell/acpi/irqlinks.asl | 145 ++-- src/soc/intel/braswell/acpi/irqroute.asl | 6 +- src/soc/intel/braswell/acpi/lpc.asl | 42 +- src/soc/intel/braswell/acpi/lpe.asl | 6 +- src/soc/intel/braswell/acpi/lpss.asl | 24 +- src/soc/intel/braswell/acpi/pcie.asl | 109 --- src/soc/intel/braswell/acpi/platform.asl | 18 +- src/soc/intel/braswell/acpi/scc.asl | 12 +- src/soc/intel/braswell/acpi/sleepstates.asl | 2 +- src/soc/intel/braswell/acpi/southcluster.asl | 78 +- src/soc/intel/braswell/bootblock/Makefile.inc | 2 +- src/soc/intel/braswell/bootblock/bootblock.c | 9 +- src/soc/intel/braswell/bootblock/timestamp.inc | 7 +- src/soc/intel/braswell/chip.c | 45 +- src/soc/intel/braswell/chip.h | 39 +- src/soc/intel/braswell/cpu.c | 119 ++-- src/soc/intel/braswell/dptf.c | 52 -- src/soc/intel/braswell/ehci.c | 181 ----- src/soc/intel/braswell/elog.c | 49 +- src/soc/intel/braswell/emmc.c | 29 +- src/soc/intel/braswell/gfx.c | 350 +-------- src/soc/intel/braswell/gpio.c | 427 ++++++----- src/soc/intel/braswell/gpio_support.c | 87 +++ src/soc/intel/braswell/hda.c | 77 +- src/soc/intel/braswell/include/chipset_fsp_util.h | 42 ++ src/soc/intel/braswell/include/soc/acpi.h | 17 +- src/soc/intel/braswell/include/soc/device_nvs.h | 8 +- src/soc/intel/braswell/include/soc/efi_wrapper.h | 52 -- src/soc/intel/braswell/include/soc/ehci.h | 24 +- src/soc/intel/braswell/include/soc/gfx.h | 62 +- src/soc/intel/braswell/include/soc/gpio.h | 827 ++++++++++++---------- src/soc/intel/braswell/include/soc/hda.h | 45 ++ src/soc/intel/braswell/include/soc/iomap.h | 20 +- src/soc/intel/braswell/include/soc/iosf.h | 266 ++----- src/soc/intel/braswell/include/soc/irq.h | 158 +++-- src/soc/intel/braswell/include/soc/lpc.h | 9 +- src/soc/intel/braswell/include/soc/mrc_wrapper.h | 107 --- src/soc/intel/braswell/include/soc/msr.h | 19 +- src/soc/intel/braswell/include/soc/nvs.h | 15 +- src/soc/intel/braswell/include/soc/pattrs.h | 24 +- src/soc/intel/braswell/include/soc/pci_devs.h | 87 ++- src/soc/intel/braswell/include/soc/pcie.h | 11 +- src/soc/intel/braswell/include/soc/pei_data.h | 68 ++ src/soc/intel/braswell/include/soc/pei_wrapper.h | 30 + src/soc/intel/braswell/include/soc/pm.h | 267 +++++++ src/soc/intel/braswell/include/soc/pmc.h | 303 -------- src/soc/intel/braswell/include/soc/ramstage.h | 25 +- src/soc/intel/braswell/include/soc/reset.h | 36 - src/soc/intel/braswell/include/soc/romstage.h | 39 +- src/soc/intel/braswell/include/soc/sata.h | 135 +++- src/soc/intel/braswell/include/soc/smm.h | 22 +- src/soc/intel/braswell/include/soc/spi.h | 8 +- src/soc/intel/braswell/include/soc/xhci.h | 15 +- src/soc/intel/braswell/iosf.c | 261 +++---- src/soc/intel/braswell/lpe.c | 44 +- src/soc/intel/braswell/lpss.c | 45 +- src/soc/intel/braswell/memmap.c | 60 +- src/soc/intel/braswell/microcode/Makefile.inc | 14 +- src/soc/intel/braswell/microcode/microcode_blob.c | 2 +- src/soc/intel/braswell/northcluster.c | 83 ++- src/soc/intel/braswell/pcie.c | 141 ++-- src/soc/intel/braswell/perf_power.c | 292 -------- src/soc/intel/braswell/placeholders.c | 3 - src/soc/intel/braswell/pmutil.c | 28 +- src/soc/intel/braswell/ramstage.c | 78 +- src/soc/intel/braswell/refcode.c | 148 ---- src/soc/intel/braswell/reset.c | 47 -- src/soc/intel/braswell/romstage/Makefile.inc | 9 +- src/soc/intel/braswell/romstage/cache_as_ram.inc | 285 -------- src/soc/intel/braswell/romstage/early_spi.c | 19 +- src/soc/intel/braswell/romstage/gfx.c | 50 -- src/soc/intel/braswell/romstage/pmc.c | 51 +- src/soc/intel/braswell/romstage/raminit.c | 191 ----- src/soc/intel/braswell/romstage/romstage.c | 301 ++------ src/soc/intel/braswell/romstage/uart.c | 38 - src/soc/intel/braswell/sata.c | 188 +---- src/soc/intel/braswell/scc.c | 82 +-- src/soc/intel/braswell/sd.c | 14 +- src/soc/intel/braswell/smihandler.c | 192 ++--- src/soc/intel/braswell/smm.c | 24 +- src/soc/intel/braswell/southcluster.c | 356 ++++------ src/soc/intel/braswell/spi.c | 129 ++-- src/soc/intel/braswell/spi_loading.c | 154 ++++ src/soc/intel/braswell/stage_cache.c | 35 - src/soc/intel/braswell/tsc_freq.c | 54 +- src/soc/intel/braswell/xhci.c | 213 +----- 98 files changed, 3546 insertions(+), 5593 deletions(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 3f938c3..da81fd0 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -1,32 +1,44 @@ config SOC_INTEL_BRASWELL bool help - Bay Trail M/D part support. + Braswell M/D part support. if SOC_INTEL_BRASWELL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_ROM select CAR_MIGRATION select COLLECT_TIMESTAMPS + select CPU_MICROCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select SUPPORT_CPU_UCODE_IN_CBFS + select DYNAMIC_CBMEM + select ENABLE_MRC_CACHE + select HAS_PRECBMEM_TIMESTAMP_REGION + select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES - select RELOCATABLE_RAMSTAGE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select PLATFORM_USES_FSP1_1 select REG_SCRIPT + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_FSP_RAM_INIT + select SOC_INTEL_COMMON_FSP_ROMSTAGE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_STACK + select SOC_INTEL_COMMON_STAGE_CACHE select SMM_MODULES select SMM_TSEG select SMP @@ -37,14 +49,14 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select SOC_INTEL_COMMON + select USE_GENERIC_FSP_CAR_INC config BOOTBLOCK_CPU_INIT string - default "soc/intel/baytrail/bootblock/bootblock.c" + default "soc/intel/braswell/bootblock/bootblock.c" config MMCONF_BASE_ADDRESS - hex + hex "PCIe CFG Base Address" default 0xe0000000 config MAX_CPUS @@ -63,39 +75,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 -config HAVE_MRC - bool "Add a Memory Reference Code binary" - default y - help - Select this option to add a blob containing - memory reference code. - Note: Without this binary coreboot will not work - -if HAVE_MRC - -config MRC_FILE - string "Intel memory refeference code path and filename" - default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" - help - The path and filename of the file to use as System Agent - binary. Note that this points to the sandybridge binary file - which is will not work, but it serves its purpose to do builds. - -config MRC_BIN_ADDRESS - hex - default 0xfffa0000 - -config MRC_RMT - bool "Enable MRC RMT training + debug prints" - default n - -endif # HAVE_MRC - # Cache As RAM region layout: # -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE -# | MRC usage | -# | | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE # | Stack |\ # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE @@ -106,42 +87,32 @@ endif # HAVE_MRC # | CAR Globals | # +-------------+ DCACHE_RAM_BASE # -# Note that the MRC binary is linked to assume the region marked as "MRC usage" -# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then -# a new MRC binary needs to be produced with the updated start and size -# information. config DCACHE_RAM_BASE - hex - default 0xfe000000 + hex "Temporary RAM Base Address" + default 0xfef00000 config DCACHE_RAM_SIZE - hex - default 0x8000 + hex "Temporary RAM Size" + default 0x4000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config DCACHE_RAM_MRC_VAR_SIZE - hex - default 0x8000 - help - The amount of cache-as-ram region required by the reference code. - config DCACHE_RAM_ROMSTAGE_STACK_SIZE hex default 0x800 help The amount of anticipated stack usage from the data cache - during pre-RAM ROM stage execution. + during pre-ram rom stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n depends on RELOCATABLE_RAMSTAGE help - The baytrail romstage code caches the loaded ramstage program + The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected @@ -152,14 +123,27 @@ config CBFS_SIZE hex "Size of CBFS filesystem in ROM" default 0x100000 help - On Bay Trail systems the firmware image has to store a lot more - than just coreboot, including: + The firmware image has to store a lot more than just coreboot, + including: - a firmware descriptor - Intel Management Engine firmware - MRC cache information This option allows to limit the size of the CBFS portion in the firmware image. +config LOCK_MANAGEMENT_ENGINE + bool "Lock Management Engine section" + default n + help + The Intel Management Engine supports preventing write accesses + from the host to the Management Engine section in the firmware + descriptor. If the ME section is locked, it can only be overwritten + with an external SPI flash programmer. You will want this if you + want to increase security of your ROM image once you are sure + that the ME firmware is no longer going to change. + + If unsure, say N. + config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n @@ -168,22 +152,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console. -config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" - default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. - -config ME_BIN_PATH - string "Path to management engine firmware" - depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" - config HAVE_IFD_BIN bool default y @@ -205,6 +173,26 @@ config BUILD_WITH_FAKE_IFD [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + default y + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config IED_REGION_SIZE + hex + default 0x400000 + +config IFD_BIN_PATH + string "Path to intel firmware descriptor" + depends on !BUILD_WITH_FAKE_IFD + default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD string @@ -220,26 +208,9 @@ config IFD_PLATFORM_SECTION string default "" -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" - -config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index 0806bbb..bf33b41 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += bootblock subdirs-y += microcode subdirs-y += romstage +subdirs-y += ../common subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -10,56 +11,62 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -ramstage-y += memmap.c +romstage-y += gpio_support.c +romstage-y += iosf.c romstage-y += memmap.c -ramstage-y += tsc_freq.c romstage-y += tsc_freq.c -smm-y += tsc_freq.c -ramstage-y += spi.c -smm-y += spi.c + +ramstage-y += acpi.c ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += emmc.c +ramstage-y += gpio.c +ifeq ($(CONFIG_GOP_SUPPORT),n) ramstage-y += gfx.c +endif +ramstage-y += hda.c ramstage-y += iosf.c -romstage-y += iosf.c -smm-y += iosf.c +ramstage-y += lpe.c +ramstage-y += lpss.c +ramstage-y += memmap.c ramstage-y += northcluster.c -ramstage-y += ramstage.c -ramstage-y += gpio.c -romstage-y += reset.c -ramstage-y += reset.c -ramstage-y += cpu.c +ramstage-y += pcie.c ramstage-y += pmutil.c -smm-y += pmutil.c -smm-y += smihandler.c -ramstage-y += smm.c -ramstage-y += ehci.c -ramstage-y += xhci.c -ramstage-y += southcluster.c -ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c +ramstage-y += ramstage.c ramstage-y += sata.c -ramstage-y += acpi.c -ramstage-y += lpe.c ramstage-y += scc.c -ramstage-y += emmc.c -ramstage-y += lpss.c -ramstage-y += pcie.c ramstage-y += sd.c -ramstage-y += dptf.c -ramstage-y += perf_power.c -ramstage-y += stage_cache.c -romstage-y += stage_cache.c -ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += hda.c +ramstage-y += smm.c +ramstage-y += southcluster.c +ramstage-y += spi.c +ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c +ramstage-y += tsc_freq.c +ramstage-y += xhci.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c -CPPFLAGS_common += -Isrc/soc/intel/baytrail/include +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += spi.c +smm-y += tsc_freq.c + +CPPFLAGS_common += -I$(src)/arch/x86/include/ +CPPFLAGS_common += -I$(src)/soc/intel/braswell/ +CPPFLAGS_common += -I$(src)/soc/intel/braswell/include + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp1_1 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4 +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include +CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Ia32 +CPPFLAGS_common += -I$(CONFIG_FSP_INCLUDE_PATH) # Run an intermediate step when producing coreboot.rom # that adds additional components to the final firmware # image outside of CBFS -INTERMEDIATE:=baytrail_add_me +INTERMEDIATE := pch_add_me ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) IFD_BIN_PATH := $(objgenerated)/ifdfake.bin @@ -70,7 +77,7 @@ else IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) endif -baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +pch_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) printf "\n** WARNING **\n" printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" @@ -80,28 +87,30 @@ ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) endif printf " DD Adding Intel Firmware Descriptor\n" + printf "CONFIG_IFD_BIN_PATH: $(CONFIG_IFD_BIN_PATH)\n" + printf "IFD_BIN_PATH: $(IFD_BIN_PATH)\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 + printf "CONFIG_HAVE_ME_BIN: $(CONFIG_HAVE_ME_BIN)\n" ifeq ($(CONFIG_HAVE_ME_BIN),y) printf " IFDTOOL me.bin -> coreboot.pre\n" + printf "CONFIG_ME_BIN_PATH: $(CONFIG_ME_BIN_PATH)\n" $(objutil)/ifdtool/ifdtool \ -i ME:$(CONFIG_ME_BIN_PATH) \ $(obj)/coreboot.pre mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre endif -# If an MRC file is an ELF file determine the entry address and first loadable -# section offset in the file. Subtract the offset from the entry address to -# determine the final location. -mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) -mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') - -# Add memory reference code blob. -cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin -mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) -mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) -mrc.bin-type := mrc +ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y) + printf " IFDTOOL Locking Management Engine\n" + $(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +else + printf " IFDTOOL Unlocking Management Engine\n" + $(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif -PHONY += baytrail_add_me +PHONY += pch_add_me endif diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 74e7336..7acac9d 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,27 +21,30 @@ #include <arch/acpi.h> #include <arch/acpigen.h> +#include <arch/cpu.h> #include <arch/io.h> #include <arch/smp/mpspec.h> +#include <cbfs_core.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/x86/smm.h> -#include <console/console.h> -#include <types.h> -#include <string.h> -#include <arch/cpu.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> +#include <cpu/x86/smm.h> #include <cpu/x86/tsc.h> -#include <cpu/intel/turbo.h> - +#include <device/pci.h> +#include <device/pci_ids.h> +#include <ec/google/chromeec/ec.h> +#include <fsp_gop.h> #include <soc/acpi.h> +#include <soc/gfx.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> #include <soc/pattrs.h> -#include <soc/pmc.h> - -#include <ec/google/chromeec/ec.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <string.h> +#include <types.h> #include <vendorcode/google/chromeos/gnvs.h> #define MWAIT_RES(state, sub_state) \ @@ -89,15 +93,15 @@ void acpi_init_gnvs(global_nvs_t *gnvs) /* Top of Low Memory (start of resource allocation) */ gnvs->tolm = nc_read_top_of_low_memory(); -#if CONFIG_CONSOLE_CBMEM +#if IS_ENABLED(CONFIG_CONSOLE_CBMEM) /* Update the mem console pointer. */ gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); #endif -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Initialize Verified Boot data */ chromeos_init_vboot(&(gnvs->chromeos)); -#if CONFIG_EC_GOOGLE_CHROMEEC +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) gnvs->chromeos.vbt2 = google_ec_running_ro() ? ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; #endif @@ -106,7 +110,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs) static int acpi_sci_irq(void) { - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + void *actl = (void *)(ILB_BASE_ADDRESS + ACTL); int scis; static int sci_irq; @@ -137,7 +141,7 @@ static int acpi_sci_irq(void) return sci_irq; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) +void acpi_create_intel_hpet(acpi_hpet_t *hpet) { acpi_header_t *header = &(hpet->header); acpi_addr_t *addr = &(hpet->addr); @@ -284,7 +288,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } -static acpi_tstate_t baytrail_tss_table[] = { +static acpi_tstate_t braswell_tss_table[] = { { 100, 1000, 0, 0x00, 0 }, { 88, 875, 0, 0x1e, 0 }, { 75, 750, 0, 0x1c, 0 }, @@ -295,7 +299,7 @@ static acpi_tstate_t baytrail_tss_table[] = { { 13, 125, 0, 0x12, 0 }, }; -static int generate_T_state_entries(int core, int cores_per_package) +static int generate_t_state_entries(int core, int cores_per_package) { int len; @@ -310,7 +314,7 @@ static int generate_T_state_entries(int core, int cores_per_package) /* Write TSS table for MSR access */ len += acpigen_write_TSS_package( - ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); + ARRAY_SIZE(braswell_tss_table), braswell_tss_table); return len; } @@ -336,7 +340,7 @@ static int calculate_power(int tdp, int p1_ratio, int ratio) return (int)power; } -static int generate_P_state_entries(int core, int cores_per_package) +static int generate_p_state_entries(int core, int cores_per_package) { int len, len_pss; int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; @@ -396,12 +400,12 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Add entry for Turbo ratio */ len_pss += acpigen_write_PSS_package( - clock_max + 1, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ + clock_max + 1, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ } else { /* _PSS package count without Turbo */ len_pss = acpigen_write_package(num_entries + 1); @@ -412,12 +416,12 @@ static int generate_P_state_entries(int core, int cores_per_package) /* First regular entry is max non-turbo ratio */ control_status = (ratio_max << 8) | vid_max; len_pss += acpigen_write_PSS_package( - clock_max, /*MHz*/ - power_max, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control */ - control_status); /*status*/ + clock_max, /* MHz */ + power_max, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ /* Set up ratio and vid ranges for VID calculation */ ratio_range_2 = (ratio_turbo - ratio_min) * 2; @@ -440,12 +444,12 @@ static int generate_P_state_entries(int core, int cores_per_package) control_status = (ratio << 8) | (vid & 0xff); len_pss += acpigen_write_PSS_package( - clock, /*MHz*/ - power, /*mW*/ - 10, /*lat1*/ - 10, /*lat2*/ - control_status, /*control*/ - control_status); /*status*/ + clock, /* MHz */ + power, /* mW */ + 10, /* lat1 */ + 10, /* lat2 */ + control_status, /* control */ + control_status); /* status */ } /* Fix package length */ @@ -461,7 +465,7 @@ void generate_cpu_entries(void) int pcontrol_blk = get_pmbase(), plen = 6; const struct pattrs *pattrs = pattrs_get(); - for (core=0; core<pattrs->num_cpus; core++) { + for (core = 0; core < pattrs->num_cpus; core++) { if (core > 0) { pcontrol_blk = 0; plen = 0; @@ -472,7 +476,7 @@ void generate_cpu_entries(void) core, pcontrol_blk, plen); /* Generate P-state tables */ - len_pr += generate_P_state_entries( + len_pr += generate_p_state_entries( core, pattrs->num_cpus); /* Generate C-state tables */ @@ -480,7 +484,7 @@ void generate_cpu_entries(void) cstate_map, ARRAY_SIZE(cstate_map)); /* Generate T-state tables */ - len_pr += generate_T_state_entries( + len_pr += generate_t_state_entries( core, pattrs->num_cpus); len_pr--; @@ -505,7 +509,80 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, - sci_flags); + sci_flags); return current; } + +#if CONFIG_GOP_SUPPORT +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); +} + +/* Initialize IGD OpRegion, called from ACPI code */ +int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (u32)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} +#endif diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl index f7e404d..401242b 100644 --- a/src/soc/intel/braswell/acpi/cpu.asl +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -19,22 +19,34 @@ * MA 02110-1301 USA */ +/* CPU */ +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + /* These devices are created at runtime */ -External (\_PR.CP00, DeviceObj) -External (\_PR.CP01, DeviceObj) -External (\_PR.CP02, DeviceObj) -External (\_PR.CP03, DeviceObj) +External (\_PR.CPU0, DeviceObj) +External (\_PR.CPU1, DeviceObj) +External (\_PR.CPU2, DeviceObj) +External (\_PR.CPU3, DeviceObj) + /* Notify OS to re-read CPU tables, assuming ^2 CPU count */ Method (PNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x81) // _CST - Notify (\_PR.CP01, 0x81) // _CST + Notify (\_PR.CPU0, 0x81) /* _CST */ + Notify (\_PR.CPU1, 0x81) /* _CST */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x81) // _CST - Notify (\_PR.CP03, 0x81) // _CST + Notify (\_PR.CPU2, 0x81) /* _CST */ + Notify (\_PR.CPU3, 0x81) /* _CST */ } } @@ -42,12 +54,12 @@ Method (PNOT) Method (PPCN) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x80) // _PPC - Notify (\_PR.CP01, 0x80) // _PPC + Notify (\_PR.CPU0, 0x80) /* _PPC */ + Notify (\_PR.CPU1, 0x80) /* _PPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x80) // _PPC - Notify (\_PR.CP03, 0x80) // _PPC + Notify (\_PR.CPU2, 0x80) /* _PPC */ + Notify (\_PR.CPU3, 0x80) /* _PPC */ } } @@ -55,12 +67,12 @@ Method (PPCN) Method (TNOT) { If (LGreaterEqual (\PCNT, 2)) { - Notify (\_PR.CP00, 0x82) // _TPC - Notify (\_PR.CP01, 0x82) // _TPC + Notify (\_PR.CPU0, 0x82) /* _TPC */ + Notify (\_PR.CPU1, 0x82) /* _TPC */ } If (LGreaterEqual (\PCNT, 4)) { - Notify (\_PR.CP02, 0x82) // _TPC - Notify (\_PR.CP03, 0x82) // _TPC + Notify (\_PR.CPU2, 0x82) /* _TPC */ + Notify (\_PR.CPU3, 0x82) /* _TPC */ } } @@ -68,10 +80,10 @@ Method (TNOT) Method (PPKG) { If (LGreaterEqual (\PCNT, 4)) { - Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) + Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3}) } ElseIf (LGreaterEqual (\PCNT, 2)) { - Return (Package() {\_PR.CP00, \_PR.CP01}) + Return (Package() {\_PR.CPU0, \_PR.CPU1}) } Else { - Return (Package() {\_PR.CP00}) + Return (Package() {\_PR.CPU0}) } } diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl index fce7b53..c9254b5 100644 --- a/src/soc/intel/braswell/acpi/device_nvs.asl +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -21,67 +21,67 @@ /* Device Enabled in ACPI Mode */ -S0EN, 8, // SDMA Enable -S1EN, 8, // I2C1 Enable -S2EN, 8, // I2C2 Enable -S3EN, 8, // I2C3 Enable -S4EN, 8, // I2C4 Enable -S5EN, 8, // I2C5 Enable -S6EN, 8, // I2C6 Enable -S7EN, 8, // I2C7 Enable -S8EN, 8, // SDMA2 Enable -S9EN, 8, // SPI Enable -SAEN, 8, // PWM1 Enable -SBEN, 8, // PWM2 Enable -SCEN, 8, // UART2 Enable -SDEN, 8, // UART2 Enable -C0EN, 8, // MMC Enable -C1EN, 8, // SDIO Enable -C2EN, 8, // SD Card Enable -LPEN, 8, // LPE Enable +S0EN, 8, /* SDMA Enable */ +S1EN, 8, /* I2C1 Enable */ +S2EN, 8, /* I2C2 Enable */ +S3EN, 8, /* I2C3 Enable */ +S4EN, 8, /* I2C4 Enable */ +S5EN, 8, /* I2C5 Enable */ +S6EN, 8, /* I2C6 Enable */ +S7EN, 8, /* I2C7 Enable */ +S8EN, 8, /* SDMA2 Enable */ +S9EN, 8, /* SPI Enable */ +SAEN, 8, /* PWM1 Enable */ +SBEN, 8, /* PWM2 Enable */ +SCEN, 8, /* UART2 Enable */ +SDEN, 8, /* UART2 Enable */ +C0EN, 8, /* MMC Enable */ +C1EN, 8, /* SDIO Enable */ +C2EN, 8, /* SD Card Enable */ +LPEN, 8, /* LPE Enable */ /* BAR 0 */ -S0B0, 32, // SDMA BAR0 -S1B0, 32, // I2C1 BAR0 -S2B0, 32, // I2C2 BAR0 -S3B0, 32, // I2C3 BAR0 -S4B0, 32, // I2C4 BAR0 -S5B0, 32, // I2C5 BAR0 -S6B0, 32, // I2C6 BAR0 -S7B0, 32, // I2C7 BAR0 -S8B0, 32, // SDMA2 BAR0 -S9B0, 32, // SPI BAR0 -SAB0, 32, // PWM1 BAR0 -SBB0, 32, // PWM2 BAR0 -SCB0, 32, // UART1 BAR0 -SDB0, 32, // UART2 BAR0 -C0B0, 32, // MMC BAR0 -C1B0, 32, // SDIO BAR0 -C2B0, 32, // SD Card BAR0 -LPB0, 32, // LPE BAR0 +S0B0, 32, /* SDMA BAR0 */ +S1B0, 32, /* I2C1 BAR0 */ +S2B0, 32, /* I2C2 BAR0 */ +S3B0, 32, /* I2C3 BAR0 */ +S4B0, 32, /* I2C4 BAR0 */ +S5B0, 32, /* I2C5 BAR0 */ +S6B0, 32, /* I2C6 BAR0 */ +S7B0, 32, /* I2C7 BAR0 */ +S8B0, 32, /* SDMA2 BAR0 */ +S9B0, 32, /* SPI BAR0 */ +SAB0, 32, /* PWM1 BAR0 */ +SBB0, 32, /* PWM2 BAR0 */ +SCB0, 32, /* UART1 BAR0 */ +SDB0, 32, /* UART2 BAR0 */ +C0B0, 32, /* MMC BAR0 */ +C1B0, 32, /* SDIO BAR0 */ +C2B0, 32, /* SD Card BAR0 */ +LPB0, 32, /* LPE BAR0 */ /* BAR 1 */ -S0B1, 32, // SDMA BAR1 -S1B1, 32, // I2C1 BAR1 -S2B1, 32, // I2C2 BAR1 -S3B1, 32, // I2C3 BAR1 -S4B1, 32, // I2C4 BAR1 -S5B1, 32, // I2C5 BAR1 -S6B1, 32, // I2C6 BAR1 -S7B1, 32, // I2C7 BAR1 -S8B1, 32, // SDMA2 BAR1 -S9B1, 32, // SPI BAR1 -SAB1, 32, // PWM1 BAR1 -SBB1, 32, // PWM2 BAR1 -SCB1, 32, // UART1 BAR1 -SDB1, 32, // UART2 BAR1 -C0B1, 32, // MMC BAR1 -C1B1, 32, // SDIO BAR1 -C2B1, 32, // SD Card BAR1 -LPB1, 32, // LPE BAR1 +S0B1, 32, /* SDMA BAR1 */ +S1B1, 32, /* I2C1 BAR1 */ +S2B1, 32, /* I2C2 BAR1 */ +S3B1, 32, /* I2C3 BAR1 */ +S4B1, 32, /* I2C4 BAR1 */ +S5B1, 32, /* I2C5 BAR1 */ +S6B1, 32, /* I2C6 BAR1 */ +S7B1, 32, /* I2C7 BAR1 */ +S8B1, 32, /* SDMA2 BAR1 */ +S9B1, 32, /* SPI BAR1 */ +SAB1, 32, /* PWM1 BAR1 */ +SBB1, 32, /* PWM2 BAR1 */ +SCB1, 32, /* UART1 BAR1 */ +SDB1, 32, /* UART2 BAR1 */ +C0B1, 32, /* MMC BAR1 */ +C1B1, 32, /* SDIO BAR1 */ +C2B1, 32, /* SD Card BAR1 */ +LPB1, 32, /* LPE BAR1 */ /* Extra */ -LPFW, 32, // LPE BAR2 Firmware +LPFW, 32, /* LPE BAR2 Firmware */ diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl index 58c1c7b..9b1930b 100644 --- a/src/soc/intel/braswell/acpi/dptf/cpu.asl +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -1,13 +1,13 @@ -External (\_PR.CP00._TSS, MethodObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) -External (\_PR.CP00._PSS, MethodObj) - -Device (TCPU) +External (\_PR.CPU0._TSS, MethodObj) +External (\_PR.CPU0._TPC, MethodObj) +External (\_PR.CPU0._PTC, PkgObj) +External (\_PR.CPU0._TSD, PkgObj) +External (\_PR.CPU0._PSS, MethodObj) +External (\_SB.DPTF.CTOK, MethodObj) + +Device (B0DB) { - Name (_HID, EISAID ("INT3401")) - Name (_UID, 0) + Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */ Method (_STA) { @@ -24,8 +24,8 @@ Device (TCPU) Method (_TSS) { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) + If (CondRefOf (\_PR.CPU0._TSS)) { + Return (\_PR.CPU0._TSS) } Else { Return (Package () { @@ -36,8 +36,8 @@ Device (TCPU) Method (_TPC) { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) + If (CondRefOf (\_PR.CPU0._TPC)) { + Return (\_PR.CPU0._TPC) } Else { Return (0) } @@ -45,8 +45,8 @@ Device (TCPU) Method (_PTC) { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) + If (CondRefOf (\_PR.CPU0._PTC)) { + Return (\_PR.CPU0._PTC) } Else { Return (Package () { @@ -58,8 +58,8 @@ Device (TCPU) Method (_TSD) { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) + If (CondRefOf (\_PR.CPU0._TSD)) { + Return (\_PR.CPU0._TSD) } Else { Return (Package () { @@ -70,8 +70,8 @@ Device (TCPU) Method (_TDL) { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS ()), Local0) + If (CondRefOf (\_PR.CPU0._TSS)) { + Store (SizeOf (\_PR.CPU0._TSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -98,8 +98,8 @@ Device (TCPU) Method (_PSS) { - If (CondRefOf (\_PR.CP00._PSS)) { - Return (\_PR.CP00._PSS) + If (CondRefOf (\_PR.CPU0._PSS)) { + Return (\_PR.CPU0._PSS) } Else { Return (Package () { @@ -113,8 +113,8 @@ Device (TCPU) /* Check for mainboard specific _PDL override */ If (CondRefOf (\_SB.MPDL)) { Return (\_SB.MPDL) - } ElseIf (CondRefOf (\_PR.CP00._PSS)) { - Store (SizeOf (\_PR.CP00._PSS ()), Local0) + } ElseIf (CondRefOf (\_PR.CPU0._PSS)) { + Store (SizeOf (\_PR.CPU0._PSS ()), Local0) Decrement (Local0) Return (Local0) } Else { @@ -127,18 +127,52 @@ Device (TCPU) { Return (\_SB.MPPC) } - #ifdef DPTF_CPU_CRITICAL Method (_CRT) { - Return (^^CTOK (DPTF_CPU_CRITICAL)) + Return (\_SB.DPTF.CTOK(DPTF_CPU_CRITICAL)) } #endif #ifdef DPTF_CPU_PASSIVE Method (_PSV) { - Return (^^CTOK (DPTF_CPU_PASSIVE)) + Return (\_SB.DPTF.CTOK(DPTF_CPU_PASSIVE)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4)) } #endif } diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl index 9ebfb8c..f8d8347 100644 --- a/src/soc/intel/braswell/acpi/dptf/dptf.asl +++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl @@ -1,3 +1,4 @@ + Device (DPTF) { Name (_HID, EISAID ("INT3400")) @@ -24,7 +25,8 @@ Device (DPTF) } } - /* Arg0: Buffer containing UUID + /* + * Arg0: Buffer containing UUID * Arg1: Integer containing Revision ID of buffer format * Arg2: Integer containing count of entries in Arg3 * Arg3: Buffer containing list of DWORD capabilities @@ -65,9 +67,6 @@ Device (DPTF) Return (Local0) } - /* Include CPU Participant */ - #include "cpu.asl" - /* Include Thermal Participants */ #include "thermal.asl" @@ -75,4 +74,8 @@ Device (DPTF) /* Include Charger Participant */ #include "charger.asl" #endif + + /* Include Network Participants */ + #include "wifi.asl" + #include "wwan.asl" } diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl index 7113215..b123fb6 100644 --- a/src/soc/intel/braswell/acpi/dptf/thermal.asl +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -60,12 +60,12 @@ Device (TSR0) Method (_PSV) { - Return (^^CTOK (DPTF_TSR0_PASSIVE)) + Return (CTOK (DPTF_TSR0_PASSIVE)) } Method (_CRT) { - Return (^^CTOK (DPTF_TSR0_CRITICAL)) + Return (CTOK (DPTF_TSR0_CRITICAL)) } Name (PATC, 2) @@ -116,12 +116,12 @@ Device (TSR1) Method (_PSV) { - Return (^^CTOK (DPTF_TSR1_PASSIVE)) + Return (CTOK (DPTF_TSR1_PASSIVE)) } Method (_CRT) { - Return (^^CTOK (DPTF_TSR1_CRITICAL)) + Return (CTOK (DPTF_TSR1_CRITICAL)) } Name (PATC, 2) @@ -172,12 +172,12 @@ Device (TSR2) Method (_PSV) { - Return (^^CTOK (DPTF_TSR2_PASSIVE)) + Return (CTOK (DPTF_TSR2_PASSIVE)) } Method (_CRT) { - Return (^^CTOK (DPTF_TSR2_CRITICAL)) + Return (CTOK (DPTF_TSR2_CRITICAL)) } Name (PATC, 2) diff --git a/src/soc/intel/braswell/acpi/dptf/wifi.asl b/src/soc/intel/braswell/acpi/dptf/wifi.asl new file mode 100644 index 0000000..28da69a --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/wifi.asl @@ -0,0 +1,16 @@ +Device (WIFI) +{ + Name (_HID, "INT3408") + Name (_UID, 0) + Name (PTYP, 0x07) + Name (_STR, Unicode("WIFI wireless device")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/src/soc/intel/braswell/acpi/dptf/wwan.asl b/src/soc/intel/braswell/acpi/dptf/wwan.asl new file mode 100644 index 0000000..f205b8a --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/wwan.asl @@ -0,0 +1,16 @@ +Device (WWAN) +{ + Name (_HID, "INT3408") + Name (_UID, 0) + Name (PTYP, 0xF) + Name (_STR, Unicode("Wireless Wide Area Network")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index a201c03..cc3f09b 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -21,9 +21,10 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 +Name(\PICM, 0) /* IOAPIC/8259 */ -/* Global ACPI memory region. This region is used for passing information +/* + * Global ACPI memory region. This region is used for passing information * between coreboot (aka "the system bios"), ACPI, and the SMI handler. * Since we don't know where this will end up in memory at ACPI compile time, * we have to fix it up in coreboot's ACPI creation phase. @@ -35,48 +36,48 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ Offset (0x00), - OSYS, 16, // 0x00 - Operating System - SMIF, 8, // 0x02 - SMI function - PRM0, 8, // 0x03 - SMI function parameter - PRM1, 8, // 0x04 - SMI function parameter - SCIF, 8, // 0x05 - SCI function - PRM2, 8, // 0x06 - SCI function parameter - PRM3, 8, // 0x07 - SCI function parameter - LCKF, 8, // 0x08 - Global Lock function for EC - PRM4, 8, // 0x09 - Lock function parameter - PRM5, 8, // 0x0a - Lock function parameter - P80D, 32, // 0x0b - Debug port (IO 0x80) value - LIDS, 8, // 0x0f - LID state (open = 1) - PWRS, 8, // 0x10 - Power State (AC = 1) - PCNT, 8, // 0x11 - Processor count - TPMP, 8, // 0x12 - TPM Present and Enabled - TLVL, 8, // 0x13 - Throttle Level - PPCM, 8, // 0x14 - Maximum P-state usable by OS - PM1I, 32, // 0x15 - System Wake Source - PM1 Index + OSYS, 16, /* 0x00 - Operating System */ + SMIF, 8, /* 0x02 - SMI function */ + PRM0, 8, /* 0x03 - SMI function parameter */ + PRM1, 8, /* 0x04 - SMI function parameter */ + SCIF, 8, /* 0x05 - SCI function */ + PRM2, 8, /* 0x06 - SCI function parameter */ + PRM3, 8, /* 0x07 - SCI function parameter */ + LCKF, 8, /* 0x08 - Global Lock function for EC */ + PRM4, 8, /* 0x09 - Lock function parameter */ + PRM5, 8, /* 0x0a - Lock function parameter */ + P80D, 32, /* 0x0b - Debug port (IO 0x80) value */ + LIDS, 8, /* 0x0f - LID state (open = 1) */ + PWRS, 8, /* 0x10 - Power State (AC = 1) */ + PCNT, 8, /* 0x11 - Processor count */ + TPMP, 8, /* 0x12 - TPM Present and Enabled */ + TLVL, 8, /* 0x13 - Throttle Level */ + PPCM, 8, /* 0x14 - Maximum P-state usable by OS */ + PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ /* Device Config */ Offset (0x20), - S5U0, 8, // 0x20 - Enable USB0 in S5 - S5U1, 8, // 0x21 - Enable USB1 in S5 - S3U0, 8, // 0x22 - Enable USB0 in S3 - S3U1, 8, // 0x23 - Enable USB1 in S3 - TACT, 8, // 0x24 - Thermal Active trip point - TPSV, 8, // 0x25 - Thermal Passive trip point - TCRT, 8, // 0x26 - Thermal Critical trip point - DPTE, 8, // 0x27 - Enable DPTF + S5U0, 8, /* 0x20 - Enable USB0 in S5 */ + S5U1, 8, /* 0x21 - Enable USB1 in S5 */ + S3U0, 8, /* 0x22 - Enable USB0 in S3 */ + S3U1, 8, /* 0x23 - Enable USB1 in S3 */ + TACT, 8, /* 0x24 - Thermal Active trip point */ + TPSV, 8, /* 0x25 - Thermal Passive trip point */ + TCRT, 8, /* 0x26 - Thermal Critical trip point */ + DPTE, 8, /* 0x27 - Enable DPTF */ /* Base addresses */ Offset (0x30), - CMEM, 32, // 0x30 - CBMEM TOC - TOLM, 32, // 0x34 - Top of Low Memory - CBMC, 32, // 0x38 - coreboot mem console pointer + CMEM, 32, /* 0x30 - CBMEM TOC */ + TOLM, 32, /* 0x34 - Top of Low Memory */ + CBMC, 32, /* 0x38 - coreboot mem console pointer */ /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> Offset (0x1000), - #include <soc/intel/baytrail/acpi/device_nvs.asl> + #include <soc/intel/braswell/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl index aa6af71..a44bc28 100644 --- a/src/soc/intel/braswell/acpi/gpio.asl +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -22,26 +22,26 @@ #include <soc/iomap.h> #include <soc/irq.h> -/* SouthCluster GPIO */ -Device (GPSC) +/* GPIO SouthWest Community */ +Device (GPSW) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 1) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_SC_IRQ + GPIO_SW_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHWEST, RBAS) Return (^RBUF) } @@ -51,26 +51,26 @@ Device (GPSC) } } -/* NorthCluster GPIO */ +/* GPIO North Community */ Device (GPNC) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 2) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_NC_IRQ + GPIO_N_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPNORTH, RBAS) Return (^RBUF) } @@ -80,26 +80,55 @@ Device (GPNC) } } -/* SUS GPIO */ -Device (GPSS) +/* GPIO East Community */ +Device (GPEC) { - Name (_HID, "INT33FC") - Name (_CID, "INT33FC") + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") Name (_UID, 3) Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) { - GPIO_SUS_IRQ + GPIO_E_IRQ } }) Method (_CRS) { CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) - Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPEAST, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* GPIO SouthEast Community */ +Device (GPSE) +{ + Name (_HID, "INT33FF") + Name (_CID, "INT33FF") + Name (_UID, 4) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x8000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SE_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, COMMUNITY_OFFSET_GPSOUTHEAST, RBAS) Return (^RBUF) } diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl index 21f1ada..ab6427f 100644 --- a/src/soc/intel/braswell/acpi/irqlinks.asl +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -24,20 +24,20 @@ Device (LNKA) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 1) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTA) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLA, ResourceTemplate() @@ -46,28 +46,28 @@ Device (LNKA) }) CreateWordField(RTLA, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTA + /* Set the bit from PRTA */ ShiftLeft(1, And(PRTA, 0x0f), IRQ0) Return (RTLA) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTA) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTA, 0x80)) { @@ -83,20 +83,20 @@ Device (LNKB) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 2) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTB) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLB, ResourceTemplate() @@ -105,28 +105,28 @@ Device (LNKB) }) CreateWordField(RTLB, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTB + /* Set the bit from PRTB */ ShiftLeft(1, And(PRTB, 0x0f), IRQ0) Return (RTLB) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTB) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTB, 0x80)) { @@ -142,20 +142,20 @@ Device (LNKC) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 3) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTC) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLC, ResourceTemplate() @@ -164,28 +164,28 @@ Device (LNKC) }) CreateWordField(RTLC, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTC + /* Set the bit from PRTC */ ShiftLeft(1, And(PRTC, 0x0f), IRQ0) Return (RTLC) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTC) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTC, 0x80)) { @@ -201,20 +201,20 @@ Device (LNKD) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 4) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTD) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLD, ResourceTemplate() @@ -223,28 +223,28 @@ Device (LNKD) }) CreateWordField(RTLD, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTD + /* Set the bit from PRTD */ ShiftLeft(1, And(PRTD, 0x0f), IRQ0) Return (RTLD) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTD) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTD, 0x80)) { @@ -260,20 +260,20 @@ Device (LNKE) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 5) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTE) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLE, ResourceTemplate() @@ -282,28 +282,28 @@ Device (LNKE) }) CreateWordField(RTLE, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTE + /* Set the bit from PRTE */ ShiftLeft(1, And(PRTE, 0x0f), IRQ0) Return (RTLE) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTE) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTE, 0x80)) { @@ -319,20 +319,20 @@ Device (LNKF) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 6) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTF) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLF, ResourceTemplate() @@ -341,28 +341,28 @@ Device (LNKF) }) CreateWordField(RTLF, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTF + /* Set the bit from PRTF */ ShiftLeft(1, And(PRTF, 0x0f), IRQ0) Return (RTLF) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTF) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTF, 0x80)) { @@ -378,20 +378,20 @@ Device (LNKG) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 7) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTG) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLG, ResourceTemplate() @@ -400,28 +400,28 @@ Device (LNKG) }) CreateWordField(RTLG, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTG + /* Set the bit from PRTG */ ShiftLeft(1, And(PRTG, 0x0f), IRQ0) Return (RTLG) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTG) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTG, 0x80)) { @@ -437,20 +437,20 @@ Device (LNKH) Name (_HID, EISAID("PNP0C0F")) Name (_UID, 8) - // Disable method + /* Disable method */ Method (_DIS, 0, Serialized) { Store (0x80, PRTH) } - // Possible Resource Settings for this Link + /* Possible Resource Settings for this Link */ Name (_PRS, ResourceTemplate() { IRQ(Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 } }) - // Current Resource Settings for this link + /* Current Resource Settings for this link */ Method (_CRS, 0, Serialized) { Name (RTLH, ResourceTemplate() @@ -459,28 +459,28 @@ Device (LNKH) }) CreateWordField(RTLH, 1, IRQ0) - // Clear the WordField + /* Clear the WordField */ Store (Zero, IRQ0) - // Set the bit from PRTH + /* Set the bit from PRTH */ ShiftLeft(1, And(PRTH, 0x0f), IRQ0) Return (RTLH) } - // Set Resource Setting for this IRQ link + /* Set Resource Setting for this IRQ link */ Method (_SRS, 1, Serialized) { CreateWordField(Arg0, 1, IRQ0) - // Which bit is set? + /* Which bit is set? */ FindSetRightBit(IRQ0, Local0) Decrement(Local0) Store(Local0, PRTH) } - // Status + /* Status */ Method (_STA, 0, Serialized) { If(And(PRTH, 0x80)) { @@ -490,3 +490,4 @@ Device (LNKH) } } } + diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl index 23987d7..db2b228 100644 --- a/src/soc/intel/braswell/acpi/irqroute.asl +++ b/src/soc/intel/braswell/acpi/irqroute.asl @@ -18,19 +18,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// PCI Interrupt Routing +/* PCI Interrupt Routing */ Method(_PRT) { If (PICM) { Return (Package() { #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> + #include <soc/intel/braswell/acpi/irq_helper.h> PCI_DEV_PIRQ_ROUTES }) } Else { Return (Package() { #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> + #include <soc/intel/braswell/acpi/irq_helper.h> PCI_DEV_PIRQ_ROUTES }) } diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl index 408d2b4..7961a9a 100644 --- a/src/soc/intel/braswell/acpi/lpc.asl +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -20,7 +20,7 @@ * MA 02110-1301 USA */ -// Intel LPC Bus Device - 0:1f.0 +/* Intel LPC Bus Device - 0:1f.0 */ Device (LPCB) { @@ -30,7 +30,7 @@ Device (LPCB) #include "acpi/ec.asl" - Device (DMAC) // DMA Controller + Device (DMAC) /* DMA Controller */ { Name(_HID, EISAID("PNP0200")) Name(_CRS, ResourceTemplate() @@ -43,7 +43,7 @@ Device (LPCB) }) } - Device (FWH) // Firmware Hub + Device (FWH) /* Firmware Hub */ { Name (_HID, EISAID("INT0800")) Name (_CRS, ResourceTemplate() @@ -57,9 +57,9 @@ Device (LPCB) Name (_HID, EISAID("PNP0103")) Name (_CID, 0x010CD041) - Method (_STA, 0) // Device Status + Method (_STA, 0) /* Device Status */ { - Return (0xf) // Enable and show device + Return (0xf) /* Enable and show device */ } Name(_CRS, ResourceTemplate() @@ -68,7 +68,7 @@ Device (LPCB) }) } - Device(PIC) // 8259 Interrupt Controller + Device(PIC) /* 8259 Interrupt Controller */ { Name(_HID,EISAID("PNP0000")) Name(_CRS, ResourceTemplate() @@ -94,20 +94,20 @@ Device (LPCB) }) } - Device(LDRC) // LPC device: Resource consumption + Device(LDRC) /* LPC device: Resource consumption */ { Name (_HID, EISAID("PNP0C02")) Name (_UID, 2) Name (RBUF, ResourceTemplate() { - IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status - IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post - IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved - IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ + IO (Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ + IO (Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ }) Method (_CRS, 0, NotSerialized) @@ -116,18 +116,20 @@ Device (LPCB) } } - Device (RTC) // Real Time Clock + Device (RTC) /* Real Time Clock */ { Name (_HID, EISAID("PNP0B00")) Name (_CRS, ResourceTemplate() { IO (Decode16, 0x70, 0x70, 1, 8) -// Disable as Windows doesn't like it, and systems don't seem to use it. -// IRQNoFlags() { 8 } +/* + * Disable as Windows doesn't like it, and systems don't seem to use it. + * IRQNoFlags() { 8 } + */ }) } - Device (TIMR) // Intel 8254 timer + Device (TIMR) /* Intel 8254 timer */ { Name(_HID, EISAID("PNP0100")) Name(_CRS, ResourceTemplate() @@ -138,11 +140,11 @@ Device (LPCB) }) } - // Include mainboard's superio.asl file. + /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" #ifdef ENABLE_TPM - Device (TPM) // Trusted Platform Module + Device (TPM) /* Trusted Platform Module */ { Name(_HID, EISAID("IFX0102")) Name(_CID, 0x310cd041) diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl index dfa555c..1c6c50a 100644 --- a/src/soc/intel/braswell/acpi/lpe.asl +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -21,10 +21,10 @@ Device (LPEA) { - Name (_HID, "80860F28") - Name (_CID, "80860F28") + Name (_HID, "808622A8") + Name (_CID, "808622A8") Name (_UID, 1) - Name (_DDN, "Low Power Audio Controller") + Name (_DDN, "Intel(R) Low Power Audio Controller - 808622A8") Name (_PR0, Package () { PLPE }) Name (RBUF, ResourceTemplate() diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 0f8f746..3af3179 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -85,7 +85,7 @@ Device (SDM2) Device (I2C1) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 1) Name (_DDN, "I2C Controller #1") @@ -144,7 +144,7 @@ Device (I2C1) Device (I2C2) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 2) Name (_DDN, "I2C Controller #2") @@ -203,7 +203,7 @@ Device (I2C2) Device (I2C3) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 3) Name (_DDN, "I2C Controller #3") @@ -262,7 +262,7 @@ Device (I2C3) Device (I2C4) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 4) Name (_DDN, "I2C Controller #4") @@ -321,7 +321,7 @@ Device (I2C4) Device (I2C5) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 5) Name (_DDN, "I2C Controller #5") @@ -380,7 +380,7 @@ Device (I2C5) Device (I2C6) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 6) Name (_DDN, "I2C Controller #6") @@ -439,7 +439,7 @@ Device (I2C6) Device (I2C7) { - Name (_HID, "80860F41") + Name (_HID, "808622C1") Name (_UID, 7) Name (_DDN, "I2C Controller #7") @@ -498,7 +498,7 @@ Device (I2C7) Device (SPI1) { - Name (_HID, "80860F0E") + Name (_HID, "8086228E") Name (_UID, 1) Name (_DDN, "SPI Controller #2") @@ -551,7 +551,7 @@ Device (SPI1) Device (PWM1) { - Name (_HID, "80860F09") + Name (_HID, "80862288") Name (_UID, 1) Name (_DDN, "PWM Controller #1") @@ -579,7 +579,7 @@ Device (PWM1) Device (PWM2) { - Name (_HID, "80860F09") + Name (_HID, "80862288") Name (_UID, 2) Name (_DDN, "PWM Controller #2") @@ -607,7 +607,7 @@ Device (PWM2) Device (UAR1) { - Name (_HID, "80860F0A") + Name (_HID, "8086228A") Name (_UID, 1) Name (_DDN, "HS-UART Controller #1") @@ -660,7 +660,7 @@ Device (UAR1) Device (UAR2) { - Name (_HID, "80860F0A") + Name (_HID, "8086228A") Name (_UID, 2) Name (_DDN, "HS-UART Controller #2") diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl deleted file mode 100644 index 5ad4e78..0000000 --- a/src/soc/intel/braswell/acpi/pcie.asl +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* Intel SOC PCIe support */ - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) - }) - } - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) - }) - } - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) - }) - } - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - Method (_PRT) - { - If (PICM) { - Return (Package() { - #undef PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) - }) - } Else { - Return (Package() { - #define PIC_MODE - #include <soc/intel/baytrail/acpi/irq_helper.h> - PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) - }) - } - } -} diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl index e32880e..a8b331b 100644 --- a/src/soc/intel/braswell/acpi/platform.asl +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -23,8 +23,8 @@ OperationRegion (APMP, SystemIO, 0xb2, 2) Field (APMP, ByteAcc, NoLock, Preserve) { - APMC, 8, // APM command - APMS, 8 // APM status + APMC, 8, /* APM command */ + APMS, 8 /* APM status */ } /* Port 80 POST */ @@ -38,12 +38,13 @@ Field (POST, ByteAcc, Lock, Preserve) /* SMI I/O Trap */ Method(TRAP, 1, Serialized) { - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ } -/* The _PIC method is called by the OS to choose between interrupt +/* + * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * * _PIC is called with a parameter of 0 for i8259 configuration and @@ -52,11 +53,12 @@ Method(TRAP, 1, Serialized) Method(_PIC, 1) { - // Remember the OS' IRQ routing choice. + /* Remember the OS' IRQ routing choice. */ Store(Arg0, PICM) } -/* The _PTS method (Prepare To Sleep) is called before the OS is +/* + * The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 */ diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl index 7181fb1..bb8234e 100644 --- a/src/soc/intel/braswell/acpi/scc.asl +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -136,18 +136,18 @@ Device (SDIO) Device (SDCD) { - Name (_HID, "80860F16") + Name (_HID, "INT33BB") Name (_CID, "PNP0D40") Name (_UID, 3) Name (_DDN, "SD Card Controller") Name (RBUF, ResourceTemplate() { - Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) - Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) - { - SCC_SD_IRQ - } + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR0) + Interrupt(ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + {SCC_SD_IRQ} /* SD Card IRQ */ + GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 10000, "\\_SB.GPSE", 0, ResourceConsumer, , ) + {SDCARD_CD} /* SE81 */ }) Method (_CRS) diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl index 8abeb2d..7dd2d51 100644 --- a/src/soc/intel/braswell/acpi/sleepstates.asl +++ b/src/soc/intel/braswell/acpi/sleepstates.asl @@ -20,7 +20,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) Name(\_S3, Package(){0x5,0x5,0x0,0x0}) Name(\_S4, Package(){0x6,0x6,0x0,0x0}) Name(\_S5, Package(){0x7,0x7,0x0,0x0}) + diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index 9092562..fba8c64 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -24,16 +24,16 @@ Scope(\) { - // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */ OperationRegion(IO_T, SystemIO, 0x800, 0x10) Field(IO_T, ByteAcc, NoLock, Preserve) { Offset(0x8), - TRP0, 8 // IO-Trap at 0x808 + TRP0, 8 /* IO-Trap at 0x808 */ } - // Intel Legacy Block + /* Intel Legacy Block */ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) Field (ILBS, AnyAcc, NoLock, Preserve) { @@ -49,8 +49,8 @@ Scope(\) } } -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI +Name(_HID,EISAID("PNP0A08")) /* PCIe */ +Name(_CID,EISAID("PNP0A03")) /* PCI */ Name(_ADR, 0) Name(_BBN, 0) @@ -59,126 +59,125 @@ Method (_CRS, 0, Serialized) { Name (MCRS, ResourceTemplate() { - // Bus Numbers + /* Bus Numbers */ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - // IO Region 0 + /* IO Region 0 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - // PCI Config Space + /* PCI Config Space */ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - // IO Region 1 + /* IO Region 1 */ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - // VGA memory (0xa0000-0xbffff) + /* VGA memory (0xa0000-0xbffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,, ASEG) - // OPROM reserved (0xc0000-0xc3fff) + /* OPROM reserved (0xc0000-0xc3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, 0x00004000,,, OPR0) - // OPROM reserved (0xc4000-0xc7fff) + /* OPROM reserved (0xc4000-0xc7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, 0x00004000,,, OPR1) - // OPROM reserved (0xc8000-0xcbfff) + /* OPROM reserved (0xc8000-0xcbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, 0x00004000,,, OPR2) - // OPROM reserved (0xcc000-0xcffff) + /* OPROM reserved (0xcc000-0xcffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, 0x00004000,,, OPR3) - // OPROM reserved (0xd0000-0xd3fff) + /* OPROM reserved (0xd0000-0xd3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, 0x00004000,,, OPR4) - // OPROM reserved (0xd4000-0xd7fff) + /* OPROM reserved (0xd4000-0xd7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, 0x00004000,,, OPR5) - // OPROM reserved (0xd8000-0xdbfff) + /* OPROM reserved (0xd8000-0xdbfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, 0x00004000,,, OPR6) - // OPROM reserved (0xdc000-0xdffff) + /* OPROM reserved (0xdc000-0xdffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, 0x00004000,,, OPR7) - // BIOS Extension (0xe0000-0xe3fff) + /* BIOS Extension (0xe0000-0xe3fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, 0x00004000,,, ESG0) - // BIOS Extension (0xe4000-0xe7fff) + /* BIOS Extension (0xe4000-0xe7fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, 0x00004000,,, ESG1) - // BIOS Extension (0xe8000-0xebfff) + /* BIOS Extension (0xe8000-0xebfff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, 0x00004000,,, ESG2) - // BIOS Extension (0xec000-0xeffff) + /* BIOS Extension (0xec000-0xeffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000ec000, 0x000effff, 0x00000000, 0x00004000,,, ESG3) - // System BIOS (0xf0000-0xfffff) + /* System BIOS (0xf0000-0xfffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, 0x00010000,,, FSEG) - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + /* PCI Memory Region (Top of memory-0xfeafffff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) + 0x00000000, 0xfea00000, 0xfeafffff, 0x00000000, + 0x00100000,,, PMEM) - // TPM Area (0xfed40000-0xfed44fff) + /* TPM Area (0xfed40000-0xfed44fff) */ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00005000,,, TPMR) }) - // Update PCI resource area + /* Update PCI resource area */ CreateDwordField(MCRS, PMEM._MIN, PMIN) CreateDwordField(MCRS, PMEM._MAX, PMAX) CreateDwordField(MCRS, PMEM._LEN, PLEN) - // TOLM is BMBOUND accessible from IOSF so is saved in NVS + /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ Store (\TOLM, PMIN) - Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) Add (Subtract (PMAX, PMIN), 1, PLEN) Return (MCRS) @@ -201,7 +200,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) }) - // Current Resource Settings + /* Current Resource Settings */ Method (_CRS, 0, Serialized) { Return(PDRS) @@ -246,29 +245,26 @@ Device (IOSF) } } -// LPC Bridge 0:1f.0 +/* LPC Bridge 0:1f.0 */ #include "lpc.asl" -// USB XHCI 0:14.0 +/* USB XHCI 0:14.0 */ #include "xhci.asl" -// IRQ routing for each PCI device +/* IRQ routing for each PCI device */ #include "irqroute.asl" -// PCI Express Ports 0:1c.x -#include "pcie.asl" - Scope (\_SB) { - // GPIO Devices + /* GPIO Devices */ #include "gpio.asl" - // LPSS Devices + /* LPSS Devices */ #include "lpss.asl" - // SCC Devices + /* SCC Devices */ #include "scc.asl" - // LPE Device + /* LPE Device */ #include "lpe.asl" } diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc index 3a40251..17d1ee8 100644 --- a/src/soc/intel/braswell/bootblock/Makefile.inc +++ b/src/soc/intel/braswell/bootblock/Makefile.inc @@ -1 +1 @@ -chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc +chipset_bootblock_inc += $(src)/soc/intel/braswell/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 9d7f19c..9a6004d 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -54,10 +55,12 @@ static void setup_mmconfig(void) { uint32_t reg; - /* Set up the MMCONF range. The register lives in the BUNIT. The + /* + * Set up the MMCONF range. The register lives in the BUNIT. The * IO variant of the config access needs to be used initially to * properly configure as the IOSF access registers live in PCI - * config space. */ + * config space. + */ reg = 0; /* Clear the extended register. */ pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); diff --git a/src/soc/intel/braswell/bootblock/timestamp.inc b/src/soc/intel/braswell/bootblock/timestamp.inc index 3db5c35..e504132 100644 --- a/src/soc/intel/braswell/bootblock/timestamp.inc +++ b/src/soc/intel/braswell/bootblock/timestamp.inc @@ -1,6 +1,8 @@ -/* Store the initial timestamp for booting in mmx registers. This works +/* + * Store the initial timestamp for booting in mmx registers. This works * because the bootblock isn't being compiled with MMX support so mm0 and - * mm1 will be preserved into romstage. */ + * mm1 will be preserved into romstage. + */ .code32 .global stash_timestamp @@ -16,3 +18,4 @@ stash_timestamp: /* Restore the BIST value to %eax */ movl %ebp, %eax + diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 281019a..d363224 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,17 +18,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "chip.h" #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <arch/pci_ops.h> - +#include <fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include "chip.h" static void pci_domain_set_resources(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); assign_resources(dev->link_list); } @@ -40,17 +42,35 @@ static struct device_operations pci_domain_ops = { .ops_pci_bus = pci_bus_default_ops, }; +static void cpu_bus_noop(device_t dev) { } + static struct device_operations cpu_bus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = DEVICE_NOOP, - .init = baytrail_init_cpus, - .scan_bus = NULL, + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = braswell_init_cpus }; static void enable_dev(device_t dev) { + printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n", + __FILE__, __func__, + dev_name(dev), dev->path.type); + printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", + pci_read_config16(dev, PCI_VENDOR_ID), + pci_read_config16(dev, PCI_DEVICE_ID)); + printk(BIOS_SPEW, "class: 0x%02x %s\n" + "subclass: 0x%02x %s\n" + "prog: 0x%02x\n" + "revision: 0x%02x\n", + pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, + get_pci_class_name(dev), + pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, + get_pci_subclass_name(dev), + pci_read_config8(dev, PCI_CLASS_PROG), + pci_read_config8(dev, PCI_REVISION_ID)); + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; @@ -68,17 +88,20 @@ static void enable_dev(device_t dev) /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ static void soc_init(void *chip_info) { - baytrail_init_pre_device(chip_info); + printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); + braswell_init_pre_device(chip_info); } -struct chip_operations soc_intel_baytrail_ops = { - CHIP_NAME("Intel BayTrail SoC") +struct chip_operations soc_intel_braswell_ops = { + CHIP_NAME("Intel Braswell SoC") .enable_dev = enable_dev, .init = soc_init, }; static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { + printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + __FILE__, __func__, dev_name(dev), vendor, device); if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_read_config32(dev, PCI_VENDOR_ID)); diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index ecf1ce3..4356451 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,21 +18,40 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* The devicetree parser expects chip.h to reside directly in the path - * specified by the devicetree. */ +/* + * The devicetree parser expects chip.h to reside directly in the path + * specified by the devicetree. + */ -#ifndef _BAYTRAIL_CHIP_H_ -#define _BAYTRAIL_CHIP_H_ +#ifndef _BRASWELL_CHIP_H_ +#define _BRASWELL_CHIP_H_ #include <stdint.h> -struct soc_intel_baytrail_config { +struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t sata_port_map; uint8_t sata_ahci; uint8_t ide_legacy_combined; uint8_t clkreq_enable; + /* + * Enable SATA features + * Bits 15-12: Reserved + * Bits 11-10: OROM UI Normal Delay in seconds: 00=2, 01=4, 10=6, 11=8 + * Bit 9: Smart Response Technology + * Bit 8: RRT only on eSATA + * Bit 7: LED Locate + * Bit 6: HDD unlock + * Bit 5: Option ROM UI and banner + * Bit 4: Rapid Recovery Technology (RRT) + * Bit 3: RAID 5 + * Bit 2: RAID 10 + * Bit 1: RAID 1 + * Bit 0: RAID 0 + */ + uint32_t sata_software_feature_mask; + /* VR low power settings -- enable PS2 mode for gfx and core */ int vnn_ps2_enable; int vcc_ps2_enable; @@ -55,7 +75,6 @@ struct soc_intel_baytrail_config { uint32_t usb2_per_port_rcomp_hs_pullup2; uint32_t usb2_per_port_lane3; uint32_t usb2_per_port_rcomp_hs_pullup3; - uint32_t usb2_comp_bg; /* LPE Audio Clock configuration. */ int lpe_codec_clk_freq; /* 19 or 25 are valid. */ @@ -67,7 +86,8 @@ struct soc_intel_baytrail_config { /* Enable devices in ACPI mode */ int lpss_acpi_mode; - int scc_acpi_mode; + int emmc_acpi_mode; + int sd_acpi_mode; int lpe_acpi_mode; /* Allow PCIe devices to wake system from suspend. */ @@ -88,8 +108,7 @@ struct soc_intel_baytrail_config { uint16_t gpu_pipeb_light_off_delay; uint16_t gpu_pipeb_power_cycle_delay; int gpu_pipeb_pwm_freq_hz; - int disable_ddr_2x_refresh_rate; }; -extern struct chip_operations soc_intel_baytrail_ops; -#endif /* _BAYTRAIL_CHIP_H_ */ +extern struct chip_operations soc_intel_braswell_ops; +#endif /* _BRASWELL_CHIP_H_ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index f4d752e..bee7c8c 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,75 +18,51 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> -#include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> -#include <reg_script.h> - -#include <soc/iosf.h> +#include <soc/intel/common/memmap.h> #include <soc/msr.h> #include <soc/pattrs.h> #include <soc/ramstage.h> #include <soc/smm.h> +#include <stdlib.h> static void smm_relocate(void *unused); static void enable_smis(void *unused); +static void pre_smm_relocation(void *unused); static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(pre_smm_relocation, NULL, pre_smm_relocation, NULL), MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), /* Wait for APs to finish initialization before proceeding. */ MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), }; -/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +/* The APIC id space is sparse. Each id is separated by 2. */ static int adjust_apic_id(int index, int apic_id) { return 2 * index; } -/* Package level MSRs */ -const struct reg_script package_msr_script[] = { - /* Set Package TDP to ~7W */ - REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), - REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), - REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), - REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), - REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), - REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), - REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), - REG_SCRIPT_END -}; -/* Core level MSRs */ -const struct reg_script core_msr_script[] = { - /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), - REG_MSR_RMW(MSR_POWER_MISC, - ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), - /* Disable C1E */ - REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), - REG_MSR_OR(MSR_POWER_MISC, 0x44), - REG_SCRIPT_END -}; - -void baytrail_init_cpus(device_t dev) +void braswell_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; const struct pattrs *pattrs = pattrs_get(); struct mp_params mp_params; - uint32_t bsmrwac; void *default_smm_area; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Set up MTRRs based on physical address size. */ x86_setup_fixed_mtrrs(); x86_setup_var_mtrrs(pattrs->address_bits, 2); @@ -100,52 +77,20 @@ void baytrail_init_cpus(device_t dev) default_smm_area = backup_default_smm_area(); - /* - * Configure the BUNIT to allow dirty cache line evictions in non-SMM - * mode for the lines that were dirtied while in SMM mode. Otherwise - * the writes would be silently dropped. - */ - bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; - iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); - - /* Set package MSRs */ - reg_script_run(package_msr_script); - - /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ - enable_turbo(); - - if (mp_init(cpu_bus, &mp_params)) { + if (mp_init(cpu_bus, &mp_params)) printk(BIOS_ERR, "MP initialization failure.\n"); - } restore_default_smm_area(default_smm_area); } -static void baytrail_core_init(device_t cpu) -{ - printk(BIOS_DEBUG, "Init BayTrail core.\n"); - - /* On bay trail the turbo disable bit is actually scoped at building - * block level -- not package. For non-bsp cores that are within a - * building block enable turbo. The cores within the BSP's building - * block will just see it already enabled and move on. */ - if (lapicid()) - enable_turbo(); - - /* Set core MSRs */ - reg_script_run(core_msr_script); - - /* Set this core to max frequency ratio */ - set_max_freq(); -} static struct device_operations cpu_dev_ops = { - .init = baytrail_core_init, + .init = NULL, }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x30673 }, - { X86_VENDOR_INTEL, 0x30678 }, + { X86_VENDOR_INTEL, 0x406C3 }, + { X86_VENDOR_INTEL, 0x406C2 }, { 0, 0 }, }; @@ -202,9 +147,11 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) smrr.hi = 0; wrmsr(SMRRphysMask_MSR, smrr); - /* The relocated handler runs with all CPUs concurrently. Therefore + /* + * The relocated handler runs with all CPUs concurrently. Therefore * stagger the entry points adjusting SMBASE downwards by save state - * size * CPU num. */ + * size * CPU num. + */ smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); @@ -232,8 +179,10 @@ static int install_relocation_handler(int num_cpus) static int install_permanent_handler(int num_cpus) { - /* There are num_cpus concurrent stacks and num_cpus concurrent save - * state areas. Lastly, set the stack size to the save state size. */ + /* + * There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. + */ int save_state_size = sizeof(em64t100_smm_state_save_area_t); struct smm_loader_params smm_params = { .per_cpu_stack_size = save_state_size, @@ -241,11 +190,15 @@ static int install_permanent_handler(int num_cpus) .per_cpu_save_state_size = save_state_size, .num_concurrent_save_states = num_cpus, }; - const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + void *smm_base; + size_t smm_size; + int tseg_size; printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", relo_attrs.smbase); + smm_region(&smm_base, &smm_size); + tseg_size = smm_size - CONFIG_SMM_RESERVED_SIZE; if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) return -1; @@ -259,11 +212,14 @@ static int smm_load_handlers(void) /* All range registers are aligned to 4KiB */ const uint32_t rmask = ~((1 << 12) - 1); const struct pattrs *pattrs = pattrs_get(); + void *smm_base; + size_t smm_size; /* Initialize global tracking state. */ - relo_attrs.smbase = (uint32_t)smm_region_start(); + smm_region(&smm_base, &smm_size); + relo_attrs.smbase = (uint32_t)smm_base; relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; - relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; + relo_attrs.smrr_mask = ~(smm_size - 1) & rmask; relo_attrs.smrr_mask |= MTRRphysMaskValid; /* Install handlers. */ @@ -283,6 +239,17 @@ static int smm_load_handlers(void) return 0; } +static void pre_smm_relocation(void *unused) +{ + const struct pattrs *pattrs = pattrs_get(); + msr_t msr_value; + + /* Need to make sure that all cores have microcode loaded. */ + msr_value = rdmsr(MSR_IA32_BIOS_SIGN_ID); + if (msr_value.hi == 0) + intel_microcode_load_unlocked(pattrs->microcode_patch); +} + static void smm_relocate(void *unused) { const struct pattrs *pattrs = pattrs_get(); diff --git a/src/soc/intel/braswell/dptf.c b/src/soc/intel/braswell/dptf.c deleted file mode 100644 index 20d3420..0000000 --- a/src/soc/intel/braswell/dptf.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <bootstate.h> -#include <console/console.h> -#include <reg_script.h> -#include <soc/iosf.h> - -static const struct reg_script dptf_init_settings[] = { - /* SocThermInit */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), - /* ratio 11 = 1466mhz for mid and entry celeron */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), - REG_SCRIPT_END, -}; - -static void dptf_init(void *unused) -{ - printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n"); - reg_script_run(dptf_init_settings); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/braswell/ehci.c b/src/soc/intel/braswell/ehci.c deleted file mode 100644 index 7cf5e2b..0000000 --- a/src/soc/intel/braswell/ehci.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/acpi.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <stdint.h> -#include <reg_script.h> - -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/ramstage.h> -#include <soc/ehci.h> - -#include "chip.h" - -static const struct reg_script ehci_init_script[] = { - /* Enable S0 PLL shutdown - * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ - REG_PCI_OR16(0x7a, 0x14de), - /* Enable SB local clock gating - * D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */ - REG_PCI_OR32(0x7c, 0x0000000c), - REG_PCI_OR32(0x8c, 0x00000001), - /* Enable dynamic clock gating 0x4001=0xCE */ - REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE), - /* Magic RCBA register set sequence */ - /* RCBA + 0x200=0x1 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001), - /* RCBA + 0x204=0x2 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002), - /* RCBA + 0x208=0x0 */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000), - /* RCBA + 0x240[4,3,2,1,0]=00000b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0), - /* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007), - /* RCBA + 0x31c[3,2,1,0]=0011b */ - REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_clock_gating_script[] = { - /* Enable SB local clock gating */ - REG_PCI_OR32(0x7c, 0x00004000), - /* RCBA + 0x284=0xbe (step B0+) */ - REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_disable_script[] = { - /* Clear Run/Stop Bit */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), - /* Wait for HC Halted */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, - USB2STS_HCHALT, USB2STS_HCHALT, 10000), - /* Disable Interrupts */ - REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), - /* Disable Asynchronous and Periodic Scheduler */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, - ~(USB2CMD_ASE | USB2CMD_PSE), 0), - /* Disable port wake */ - REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), - /* Set Function Disable bit in RCBA */ - REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), - REG_SCRIPT_END -}; - -static const struct reg_script ehci_hc_reset[] = { - REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), - REG_SCRIPT_END -}; - -static void usb2_phy_init(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ? - 0x4700 : config->usb2_comp_bg); - struct reg_script usb2_phy_script[] = { - /* USB3PHYInit() */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, - usb2_comp_bg), - /* Per port phy settings, set in devicetree.cb */ - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, - config->usb2_per_port_lane0), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP0, - config->usb2_per_port_rcomp_hs_pullup0), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, - config->usb2_per_port_lane1), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP1, - config->usb2_per_port_rcomp_hs_pullup1), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, - config->usb2_per_port_lane2), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP2, - config->usb2_per_port_rcomp_hs_pullup2), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, - config->usb2_per_port_lane3), - REG_IOSF_WRITE(IOSF_PORT_USBPHY, - USBPHY_PER_PORT_RCOMP_HS_PULLUP3, - config->usb2_per_port_rcomp_hs_pullup3), - REG_SCRIPT_END - }; - reg_script_run(usb2_phy_script); -} - -static void ehci_init(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ehci_hc_init[] = { - /* Controller init */ - REG_SCRIPT_NEXT(ehci_init_script), - /* Enable clock gating */ - REG_SCRIPT_NEXT(ehci_clock_gating_script), - /* - * Disable ports if requested - */ - /* Open per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), - REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask), - /* Close per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), - REG_SCRIPT_END - }; - - /* Don't reset controller in S3 resume path */ - if (!acpi_is_wakeup_s3()) - reg_script_run_on_dev(dev, ehci_hc_reset); - - /* Disable controller if ports are routed to XHCI */ - if (config->usb_route_to_xhci) { - /* Disable controller */ - reg_script_run_on_dev(dev, ehci_disable_script); - - /* Hide device with southcluster function */ - dev->enabled = 0; - southcluster_enable_dev(dev); - } else { - /* Initialize EHCI controller */ - reg_script_run_on_dev(dev, ehci_hc_init); - } - - /* Setup USB2 PHY based on board config */ - usb2_phy_init(dev); -} - -static struct device_operations ehci_device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .ops_pci = &soc_pci_ops, -}; - -static const struct pci_driver baytrail_ehci __pci_driver = { - .ops = &ehci_device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = EHCI_DEVID -}; diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index f20dc97..892d209 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -21,15 +22,15 @@ #include <arch/io.h> #include <arch/acpi.h> -#include <stdint.h> -#include <console/console.h> #include <cbmem.h> +#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> #include <elog.h> #include <soc/iomap.h> -#include <soc/pmc.h> +#include <soc/pm.h> +#include <stdint.h> static void log_power_and_resets(const struct chipset_power_state *ps) { @@ -38,29 +39,23 @@ static void log_power_and_resets(const struct chipset_power_state *ps) elog_add_event(ELOG_TYPE_PWROK_FAIL); } - if (ps->gen_pmcon1 & SUS_PWR_FLR) { + if (ps->gen_pmcon1 & SUS_PWR_FLR) elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - } - if (ps->gen_pmcon1 & RPS) { + if (ps->gen_pmcon1 & RPS) elog_add_event(ELOG_TYPE_RTC_RESET); - } - if (ps->tco_sts & SECOND_TO_STS) { + if (ps->tco_sts & SECOND_TO_STS) elog_add_event(ELOG_TYPE_TCO_RESET); - } - if (ps->pm1_sts & PRBTNOR_STS) { + if (ps->pm1_sts & PRBTNOR_STS) elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - } - if (ps->gen_pmcon1 & SRS) { + if (ps->gen_pmcon1 & SRS) elog_add_event(ELOG_TYPE_RESET_BUTTON); - } - if (ps->gen_pmcon1 & GEN_RST_STS) { + if (ps->gen_pmcon1 & GEN_RST_STS) elog_add_event(ELOG_TYPE_SYSTEM_RESET); - } } static void log_wake_events(const struct chipset_power_state *ps) @@ -75,33 +70,27 @@ static void log_wake_events(const struct chipset_power_state *ps) /* Mask off disabled events. */ gpe0_sts = ps->gpe0_sts & ps->gpe0_en; - if (ps->pm1_sts & WAK_STS) { + if (ps->pm1_sts & WAK_STS) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - } + acpi_slp_type == 3 ? 3 : 5); - if (ps->pm1_sts & PWRBTN_STS) { + if (ps->pm1_sts & PWRBTN_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); - } - if (ps->pm1_sts & RTC_STS) { + if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - } - if (gpe0_sts & PME_B0_EN) { + if (gpe0_sts & PME_B0_EN) elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - } - if (gpe0_sts & pcie_wake_mask) { + if (gpe0_sts & pcie_wake_mask) elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - } gpio_mask = SUS_GPIO_STS0; i = 0; while (gpio_mask) { - if (gpio_mask & gpe0_sts) { + if (gpio_mask & gpe0_sts) elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } gpio_mask <<= 1; i++; } @@ -112,8 +101,8 @@ void southcluster_log_state(void) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); if (ps == NULL) { - printk(BIOS_DEBUG, "Not logging power state information. " - "Power state not found in cbmem.\n"); + printk(BIOS_DEBUG, + "Not logging power state information. Power state not found in cbmem.\n"); return; } diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 1708428..016f82a 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,46 +33,34 @@ #include "chip.h" static const struct reg_script emmc_ops[] = { - /* Enable 2ms card stable feature. */ - REG_PCI_OR32(0xa8, (1 << 24)), - /* Enable HS200 */ - REG_PCI_WRITE32(0xa0, 0x446cc801), - REG_PCI_WRITE32(0xa4, 0x80000807), - /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ - REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), - /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ - REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), - /* Set slew for HS200 */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), - /* Max timeout */ - REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), REG_SCRIPT_END, }; static void emmc_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); - if (config->scc_acpi_mode) + if (config->emmc_acpi_mode) { + printk(BIOS_DEBUG, "Enabling ACPI mode\n"); scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + } } -static struct device_operations device_ops = { +static struct device_operations emmc_device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = emmc_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; static const struct pci_driver southcluster __pci_driver = { - .ops = &device_ops, + .ops = &emmc_device_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = MMC_DEVID, }; diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index 0601e94..95462fd 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,250 +18,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "chip.h" #include <arch/io.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <reg_script.h> -#include <stdlib.h> - #include <soc/gfx.h> -#include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include "chip.h" - -#define GFX_TIMEOUT 100000 /* 100ms */ - -/* - * Lock Power Context Base Register to point to a 24KB block - * of memory in GSM. Power context save data is stored here. - */ -static void gfx_lock_pcbase(device_t dev) -{ - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, - 288,320,352,384,416,448,480,512 }; - u32 pcsize = 24 << 10; /* 24KB */ - u32 wopcmsz = 0x100000; /* PAVP offset */ - u32 gms, gmsize, pcbase; - - gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK; - gms >>= 3; - if (gms > ARRAY_SIZE(gms_size_map)) - return; - gmsize = gms_size_map[gms]; - - /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ - pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; - pcbase += (gmsize-1) * wopcmsz - pcsize; - pcbase |= 1; /* Lock */ - - write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); -} - -static const struct reg_script gfx_init_script[] = { - /* Allow-Wake render/media wells */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), - /* Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, - GFX_TIMEOUT), - /* Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, - GFX_TIMEOUT), - /* Workaround - X0:261954/A0:261955 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), - - /* - * PowerMeter Weights - */ - - /* SET1 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000), - /* SET2 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), - /* SET3 */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), - /* Enable PowerMeter Counters */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), - - /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ - /* SDP Profile 4 == 0x11940, others 0xcf08 */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), - - /* GfxPause */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), - - /* Dynamic EU Control Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), - - /* Lock ECO Bit Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), - - /* DOP Clock Gating */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), - - /* MBCunit will send the VCR (Fuse) writes as NP-W */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000), - - /* - * RC6 Settings - */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000), - /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019), - /* RC Sleep / RCx Thresholds */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557), - - /* - * Turbo Settings - */ - - /* Render/Video/Blitter Idle Max Count */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A), - /* RP Down Timeout */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240), - - /* - * Turbo Control Settings - */ - - /* RP Up/Down Threshold */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08), - /* RP Up/Down EI */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0), - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730), - - /* RP Idle Hysteresis */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), - - /* HW RC6 Control Settings */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000), - - /* RP Control */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592), - - /* Enable PM Interrupts */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e), - - /* Aggressive Clock Gating */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), - - /* Enable Gfx Turbo. */ - REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG, - ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0), - REG_SCRIPT_END -}; - static const struct reg_script gpu_pre_vbios_script[] = { /* Make sure GFX is bus master with MMIO access */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), - /* Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, - GFX_TIMEOUT), - /* Tx/Rx Lanes */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, - GFX_TIMEOUT), - /* Common Lane */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, - GFX_TIMEOUT), - /* Ungating Tx only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, - GFX_TIMEOUT), - /* Ungating Common Lane only */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, - GFX_TIMEOUT), - /* Ungating Display */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), - REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, - GFX_TIMEOUT), REG_SCRIPT_END }; static const struct reg_script gfx_post_vbios_script[] = { - /* Deassert Render Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), - /* Deassert Media Force-Wake */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), - REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), /* Set Lock bits */ - REG_PCI_RMW32(GGC, 0xffffffff, 1), - REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), - REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK), REG_SCRIPT_END }; @@ -271,111 +50,28 @@ static inline void gfx_run_script(device_t dev, const struct reg_script *ops) static void gfx_pre_vbios_init(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); } -static void gfx_pm_init(device_t dev) -{ - printk(BIOS_INFO, "GFX: Power Management Init\n"); - gfx_run_script(dev, gfx_init_script); - - /* Lock power context base */ - gfx_lock_pcbase(dev); -} - static void gfx_post_vbios_init(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); } -static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) -{ - int divider; - struct resource *res; - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - - if (res == NULL) - return; - - /* Default to 200 Hz if nothing is set. */ - if (req_hz == 0) - req_hz = 200; - - /* Base clock is 25MHz */ - divider = 25 * 1000 * 1000 / (16 * req_hz); - - /* Do not set duty cycle (lower 16 bits). Just set the divider. */ - write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16); -} - -static void gfx_panel_setup(device_t dev) -{ - struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script gfx_pipea_init[] = { - /* CONTROL */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), - PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), - /* POWER ON */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), - (config->gpu_pipea_port_select << 30 | - config->gpu_pipea_power_on_delay << 16 | - config->gpu_pipea_light_on_delay)), - /* POWER OFF */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), - (config->gpu_pipea_power_off_delay << 16 | - config->gpu_pipea_light_off_delay)), - /* DIVISOR */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), - ~0x1f, config->gpu_pipea_power_cycle_delay), - REG_SCRIPT_END - }; - struct reg_script gfx_pipeb_init[] = { - /* CONTROL */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), - PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), - /* POWER ON */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), - (config->gpu_pipeb_port_select << 30 | - config->gpu_pipeb_power_on_delay << 16 | - config->gpu_pipeb_light_on_delay)), - /* POWER OFF */ - REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), - (config->gpu_pipeb_power_off_delay << 16 | - config->gpu_pipeb_light_off_delay)), - /* DIVISOR */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), - ~0x1f, config->gpu_pipeb_power_cycle_delay), - REG_SCRIPT_END - }; - - if (config->gpu_pipea_port_select) { - printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); - reg_script_run_on_dev(dev, gfx_pipea_init); - set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL), - config->gpu_pipea_pwm_freq_hz); - } - - if (config->gpu_pipeb_port_select) { - printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); - reg_script_run_on_dev(dev, gfx_pipeb_init); - set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL), - config->gpu_pipeb_pwm_freq_hz); - } -} - static void gfx_init(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); - /* Power Management Init */ - gfx_pm_init(dev); - - gfx_panel_setup(dev); - /* Run VBIOS */ pci_dev_init(dev); @@ -383,8 +79,28 @@ static void gfx_init(device_t dev) gfx_post_vbios_init(dev); } +static void gfx_read_resources(device_t dev) +{ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + + pci_dev_read_resources(dev); + +#if IS_ENABLED(CONFIG_MARK_GRAPHICS_MEM_WRCOMB) + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "GFX: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct device_operations gfx_device_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gfx_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gfx_init, diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c old mode 100644 new mode 100755 index e4cc59a..7790132 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,228 +18,302 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/pci.h> + #include <console/console.h> +#include <device/pci.h> #include <soc/gpio.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smm.h> -/* GPIO-to-Pad LUTs */ -static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ - 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ - 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ - 2, 5, 9 }; /* [24:26] */ - -static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = - { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ - 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ - 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ - 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ - 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ - 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ - 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ - 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ - 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ - 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ - 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ - 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ - 106, 87, 91, 104, 97, 100 }; /* [96:101] */ - -static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = - { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ - 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ - 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ - 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ - 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ - 52, 53, 59, 40 }; /* [40:43] */ - -/* GPIO bank descriptions */ -static const struct gpio_bank gpncore_bank = { - .gpio_count = GPNCORE_COUNT, - .gpio_to_pad = gpncore_gpio_to_pad, - .legacy_base = GP_LEGACY_BASE_NONE, - .pad_base = GPNCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, + +#define GPIO_DEBUG + +/* gpio map to pad number LUTs */ + +static const u8 gpncommunity_gpio_to_pad[GP_NORTH_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 30, 31, 32, 33, 34, 35, 36, 37, + 38, 39, 40, 41, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55, 56, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72 }; + +static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 15, 16, + 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, + 30, 31, 32, 33, 34, 35, 45, 46, 47, 48, + 49, 50, 51, 52, 60, 61, 62, 63, 64, 65, + 66, 67, 68, 69, 75, 76, 77, 78, 79, 80, + 81, 82, 83, 84, 85 }; + + +static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 15, 16, + 17, 18, 19, 20, 21, 22, 30, 31, 32, 33, + 34, 35, 36, 37, 45, 46, 47, 48, 49, 50, + 51, 52, 60, 61, 62, 63, 64, 65, 66, 67, + 75, 76, 77, 78, 79, 80, 81, 82, 90, 91, + 92, 93, 94, 95, 96, 97 }; + +static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, + 10, 11, 15, 16, 17, 18, 19, 20, 21, 22, + 23, 24, 25, 26 }; + +/* GPIO Community descriptions */ +static const struct gpio_bank gpnorth_community = { + .gpio_count = GP_NORTH_COUNT, + .gpio_to_pad = gpncommunity_gpio_to_pad , + .pad_base = COMMUNITY_GPNORTH_BASE , + .has_gpe_en = GPE_CAPABLE , + .has_wake_en = 1, }; -static const struct gpio_bank gpscore_bank = { - .gpio_count = GPSCORE_COUNT, - .gpio_to_pad = gpscore_gpio_to_pad, - .legacy_base = GPSCORE_LEGACY_BASE, - .pad_base = GPSCORE_PAD_BASE, - .has_wake_en = 0, - .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, +static const struct gpio_bank gpsoutheast_community = { + .gpio_count = GP_SOUTHEAST_COUNT, + .gpio_to_pad = gpsecommunity_gpio_to_pad, + .pad_base = COMMUNITY_GPSOUTHEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, + .has_wake_en = 1, }; -static const struct gpio_bank gpssus_bank = { - .gpio_count = GPSSUS_COUNT, - .gpio_to_pad = gpssus_gpio_to_pad, - .legacy_base = GPSSUS_LEGACY_BASE, - .pad_base = GPSSUS_PAD_BASE, +static const struct gpio_bank gpsouthwest_community = { + .gpio_count = GP_SOUTHWEST_COUNT, + .gpio_to_pad = gpswcommunity_gpio_to_pad, + .pad_base = COMMUNITY_GPSOUTHWEST_BASE, + .has_gpe_en = GPE_CAPABLE, .has_wake_en = 1, - .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, - .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, }; +static const struct gpio_bank gpeast_community = { + .gpio_count = GP_EAST_COUNT, + .gpio_to_pad = gpecommunity_gpio_to_pad, + .pad_base = COMMUNITY_GPEAST_BASE, + .has_gpe_en = GPE_CAPABLE_NONE, + .has_wake_en = 1, +}; + +static void setup_gpio_route(const struct soc_gpio_map *sw_gpios, + const struct soc_gpio_map *n_gpios) +{ + const struct soc_gpio_map *n_config; + const struct soc_gpio_map *sw_config; + uint32_t route_reg = 0; + uint32_t int_selection = 0; + uint32_t alt_gpio_smi = 0; + uint32_t gpe0a_en = 0; + int gpio = 0; + int north_done = 0; + int south_done = 0; + + for (sw_config = sw_gpios, n_config = n_gpios; + (!north_done || !south_done); sw_config++, n_config++, gpio++) { + + /* when north config is done */ + if ((gpio > GP_NORTH_COUNT) || + (n_config->pad_conf0 == GPIO_LIST_END)) + north_done = 1; + + /* when sw is done */ + if ((gpio > GP_SOUTHWEST_COUNT) || + (sw_config->pad_conf0 == GPIO_LIST_END)) + south_done = 1; + + /* route north gpios */ + if (!north_done) { + /* Int select from 8 to 15 */ + int_selection = ((n_config->pad_conf0 >> 28) & 0xf); + if (n_config->gpe == SMI) { + /* + * Set the corresponding bits (01) as + * per the interrupt line + */ + route_reg |= (1 << ((int_selection - 8) * 2)); + /* reset the higher bit */ + route_reg &= + ~(1 << ((int_selection - 8) * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 8)); + } else if (n_config->gpe == SCI) { + /* + * Set the corresponding bits as per the + * interrupt line + */ + route_reg |= + (1 << (((int_selection - 8) * 2) + 1)); + /* reset the bit */ + route_reg &= ~(1 << ((int_selection - 8) * 2)); + gpe0a_en |= (1 << (int_selection + 8)); + } + } + + /* route southwest gpios */ + if (!south_done) { + /* Int select from 8 to 15 */ + int_selection = ((sw_config->pad_conf0 >> 28) & 0xf); + if (sw_config->gpe == SMI) { + /* + * Set the corresponding bits (10) as + * per the interrupt line + */ + route_reg |= (1 << (int_selection * 2)); + route_reg &= ~(1 << (int_selection * 2 + 1)); + alt_gpio_smi |= (1 << (int_selection + 16)); + } else if (sw_config->gpe == SCI) { + /* + * Set the corresponding bits as + * per the interrupt line + */ + route_reg |= (1 << ((int_selection * 2) + 1)); + /* reset the bit */ + route_reg &= ~(1 << (int_selection * 2)); + gpe0a_en |= (1 << (int_selection + 16)); + } + } + } + + /* enable gpe bits in GPE0A_EN_REG */ + outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG); + + /* enable sci bit (bit 0) in PM1_CNT */ + outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) | 0x1, + ACPI_BASE_ADDRESS + PM1_CNT); + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n", + route_reg, alt_gpio_smi, gpe0a_en); +#endif + /* Save as an smm param */ + southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); +} + + static void setup_gpios(const struct soc_gpio_map *gpios, - const struct gpio_bank *bank) + const struct gpio_bank *community) { const struct soc_gpio_map *config; int gpio = 0; - u32 reg, pad_conf0; - u8 set, bit; - - u32 use_sel[4] = {0}; - u32 io_sel[4] = {0}; - u32 gp_lvl[4] = {0}; - u32 tpe[4] = {0}; - u32 tne[4] = {0}; - u32 wake_en[4] = {0}; + u32 reg, family, internal_pad_num; + u32 mmio_addr, int_selection; + u32 gpio_wake0 = 0; + u32 gpio_wake1 = 0; + u32 gpio_int_mask = 0; if (!gpios) return; - for (config = gpios; config->pad_conf0 != GPIO_LIST_END; config++, gpio++) { - if (gpio > bank->gpio_count) + if (gpio > community->gpio_count) break; - set = gpio >> 5; - bit = gpio % 32; - - if (bank->legacy_base != GP_LEGACY_BASE_NONE) { - /* Legacy IO configuration */ - use_sel[set] |= config->use_sel << bit; - io_sel[set] |= config->io_sel << bit; - gp_lvl[set] |= config->gp_lvl << bit; - tpe[set] |= config->tpe << bit; - tne[set] |= config->tne << bit; - - /* Some banks do not have wake_en ability */ - if (bank->has_wake_en) - wake_en[set] |= config->wake_en << bit; - } - /* Pad configuration registers */ - reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; - - /* Add correct func to GPIO pad config */ - pad_conf0 = config->pad_conf0; - if (config->is_gpio) - { - if (gpio >= bank->gpio_f1_range_start && - gpio <= bank->gpio_f1_range_end) - pad_conf0 |= PAD_FUNC1; - else - pad_conf0 |= PAD_FUNC0; - } - + family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO; + internal_pad_num = community->gpio_to_pad[gpio] % + MAX_FAMILY_PAD_GPIO_NO; + + /* + * Calculate the MMIO Address for specific GPIO pin + * control register pointed by index. + * REG = (IOBASE + COMMUNITY_BASE + (0X04400)) + + * (0X400*FAMILY_NUM) + (8 * PAD_NUM) + */ + mmio_addr = FAMILY_PAD_REGS_OFF + + (FAMILY_PAD_REGS_SIZE * family) + + (GPIO_REGS_SIZE * internal_pad_num); + + reg = community->pad_base + mmio_addr; + + /* get int selection value */ + int_selection = ((config->pad_conf0 >> 28) & 0xf); + + /* get int mask register value */ + gpio_int_mask |= (config->int_mask << int_selection); + + /* + * wake capable programming + * some communities have 2 wake regs + */ + if (gpio > 31) + gpio_wake1 |= config->wake_mask << (gpio % 32); + else + gpio_wake0 |= config->wake_mask << gpio; + + if (!config->skip_config) { #ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n", - reg, pad_conf0, config->pad_conf1, config->pad_val); + printk(BIOS_DEBUG, + "Write Pad: Base(%x) - conf0 = %x conf1= %x gpio #- %d pad # = %d\n", + reg, config->pad_conf0, config->pad_conf1, + community->gpio_to_pad[gpio], gpio); #endif - - write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0); - write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1); - write32((u32 *)(reg + PAD_VAL_REG), config->pad_val); + /* + * write pad configurations to conf0 and conf1 register + */ + write32((void *)(reg + PAD_CONF0_REG), + config->pad_conf0); + write32((void *)(reg + PAD_CONF1_REG), + config->pad_conf1); + } } - if (bank->legacy_base != GP_LEGACY_BASE_NONE) - for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { - reg = bank->legacy_base + 0x20 * set; - #ifdef GPIO_DEBUG - printk(BIOS_DEBUG, - "Write GPIO: Reg(%x) - %x %x %x %x %x\n", - reg, use_sel[set], io_sel[set], gp_lvl[set], - tpe[set], tne[set]); + printk(BIOS_DEBUG, + "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n", + gpio_wake0, gpio_wake1, gpio_int_mask); #endif - outl(use_sel[set], reg + LEGACY_USE_SEL_REG); - outl(io_sel[set], reg + LEGACY_IO_SEL_REG); - outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); - outl(tpe[set], reg + LEGACY_TPE_REG); - outl(tne[set], reg + LEGACY_TNE_REG); + /* Wake */ + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), + gpio_wake0); - /* TS registers are WOC */ - outl(0, reg + LEGACY_TS_REG); + /* wake mask config for communities with 2 regs */ + if (community->gpio_count > 32) + write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), + gpio_wake1); - if (bank->has_wake_en) - outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); - } -} + /* Interrupt */ + write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), + gpio_int_mask); -static void setup_gpio_route(const struct soc_gpio_map *sus, - const struct soc_gpio_map *core) -{ - uint32_t route_reg = 0; - int i; - - for (i = 0; i < 8; i++) { - /* SMI takes precedence and wake_en implies SCI. */ - if (sus[i].smi) { - route_reg |= ROUTE_SMI << (2 * i); - } else if (sus[i].sci) { - route_reg |= ROUTE_SCI << (2 * i); - } - - if (core[i].smi) { - route_reg |= ROUTE_SMI << (2 * (i + 8)); - } else if (core[i].sci) { - route_reg |= ROUTE_SCI << (2 * (i + 8)); - } - } - southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); } -static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], - const struct gpio_bank *bank) -{ - u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); - u32 val; - int i; - - /* Write all four DIRQ registers */ - for (i=0; i<4; ++i) { - val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | - dirq[i * 4 + 1] << 8 | dirq[i * 4]; - write32(reg + i, val); -#ifdef GPIO_DEBUG - printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", - reg + i, val); -#endif - } -} void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) { + if (config) { - setup_gpios(config->ncore, &gpncore_bank); - setup_gpios(config->score, &gpscore_bank); - setup_gpios(config->ssus, &gpssus_bank); - setup_gpio_route(config->ssus, config->score); - - if (config->core_dirq) - setup_dirqs(*config->core_dirq, &gpscore_bank); - if (config->sus_dirq) - setup_dirqs(*config->sus_dirq, &gpssus_bank); + + /* + * Write the default value 0xffffff to the SW + * write_access_policy_interrupt_reg to allow the SW interrupt + * mask register to be set + */ + write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), + 0xffffffff); + + printk(BIOS_DEBUG, "north\n"); + setup_gpios(config->north, &gpnorth_community); + + printk(BIOS_DEBUG, "southwest\n"); + setup_gpios(config->southwest, &gpsouthwest_community); + + printk(BIOS_DEBUG, "southeast\n"); + setup_gpios(config->southeast, &gpsoutheast_community); + + printk(BIOS_DEBUG, "east\n"); + setup_gpios(config->east, &gpeast_community); + + printk(BIOS_DEBUG, "Routing SW and N gpios\n"); + setup_gpio_route(config->southwest, config->north); } - /* Set on die termination feature with pull up value and + /* + * Set on die termination feature with pull up value and * drive the pad high for TAP_TDO and TAP_TMS */ - if (!enable_xdp_tap) { + if (!enable_xdp_tap) printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); - write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc); - write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc); - } } -struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +__attribute__((weak)) struct soc_gpio_config *mainboard_get_gpios(void) { printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c new file mode 100644 index 0000000..a0311af --- /dev/null +++ b/src/soc/intel/braswell/gpio_support.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <soc/gpio.h> + +/* + * Return family number and internal pad number in that community by pad number + * and which community it is in. + */ +uint16_t gpio_family_number(uint8_t community, uint8_t pad) +{ + /* + * Refer to BSW BIOS Writers Guide, Table "Family Number". + * BSW has 4 GPIO communities. Each community has up to 7 families and + * each family contains a range of Pad numbers. The number in the array + * is the maximum no. of that range. + * For example: East community, family 0, Pad 0~11. + */ + static const uint8_t community_base[GPIO_COMMUNITY_COUNT] + [GPIO_FAMILIES_MAX_PER_COMM + 1] = { + {0, 8, 16, 24, 32, 40, 48, 56}, /* Southwest */ + {0, 9, 22, 34, 46, 59, 59, 59}, /* North */ + {0, 12, 24, 24, 24, 24, 24, 24}, /* East */ + {0, 8, 20, 26, 34, 44, 55, 55} /* Southeast */ + }; + const uint8_t *base; + uint8_t i; + + /* Validate the pad number */ + if (pad > community_base[community][7]) + die("Pad number is out of range!"); + + /* Locate the family number for the pad */ + base = &community_base[community][0]; + for (i = 0; i < 7; i++) { + if ((pad >= base[0]) && (pad < base[1])) + break; + base++; + } + + /* Family number in high byte and inner pad number in lowest byte */ + return (i << 8) + pad - *base; +} + +/* + * Return pad configuration register offset by pad number and which community + * it is in. + */ +uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad) +{ + uint16_t fpad; + uint32_t *pad_config_reg; + + /* Get the GPIO family number */ + fpad = gpio_family_number(community, pad); + + /* + * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space + * Registers Addresses" for the Pad configuration register calculation. + */ + pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + 0x4400 + + (0x400 * (fpad >> 8)) + (8 * (fpad & 0xff))); + + return pad_config_reg; +} + +int get_gpio(int community_base, int pad0_offset) +{ + return (read32((void *)(community_base + pad0_offset))) & PAD_RX_BIT; +} diff --git a/src/soc/intel/braswell/hda.c b/src/soc/intel/braswell/hda.c index dd1ba15..381b3e8 100644 --- a/src/soc/intel/braswell/hda.c +++ b/src/soc/intel/braswell/hda.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,88 +25,16 @@ #include <device/pci_ids.h> #include <reg_script.h> -#include <soc/intel/common/hda_verb.h> +#include <soc/hda.h> #include <soc/iomap.h> -#include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -static const struct reg_script init_ops[] = { - /* Enable no snoop traffic. */ - REG_PCI_OR16(0x78, 1 << 11), - /* Configure HDMI codec connection. */ - REG_PCI_OR32(0xc4, 1 << 1), - REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), - /* Configure internal settings. */ - REG_PCI_OR32(0xc0, 0x7 << 21), - REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), - REG_PCI_WRITE32(0xc8, 0x82a30000), - REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), - /* Disable docking. */ - REG_PCI_RMW8(0x4d, ~(1 << 7), 0), - REG_SCRIPT_END, -}; - -static const uint32_t hdmi_codec_verb_table[] = { - /* coreboot specific header */ - 0x80862882, /* vid did for hdmi codec */ - 0x00000000, /* subsystem id */ - 0x00000003, /* number of jacks */ - - /* pin widget 5 - port B */ - 0x20471c10, - 0x20471d00, - 0x20471e56, - 0x20471f18, - - /* pin widget 6 - port C */ - 0x20571c20, - 0x20571d00, - 0x20571e56, - 0x20571f18, - - /* pin widget 7 - port D */ - 0x20671c30, - 0x20671d00, - 0x20671e56, - 0x20671f58, -}; - -static void hda_init(device_t dev) -{ - struct resource *res; - int codec_mask; - int i; - u8 *base; - - reg_script_run_on_dev(dev, init_ops); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (res == NULL) - return; - - base = res2mmio(res, 0, 0); - codec_mask = hda_codec_detect(base); - - printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); - if (!codec_mask) - return; - - for (i = 3; i >= 0; i--) { - if (!((1 << i) & codec_mask)) - continue; - hda_codec_init(base, i, sizeof(hdmi_codec_verb_table), - hdmi_codec_verb_table); - } -} - static const struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = hda_init, + .init = NULL, .enable = NULL, .scan_bus = NULL, .ops_pci = &soc_pci_ops, diff --git a/src/soc/intel/braswell/include/chipset_fsp_util.h b/src/soc/intel/braswell/include/chipset_fsp_util.h new file mode 100644 index 0000000..7a76102 --- /dev/null +++ b/src/soc/intel/braswell/include/chipset_fsp_util.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef CHIPSET_FSP_UTIL_H + +#define CHIPSET_FSP_UTIL_H + +/* + * Include the FSP binary interface files + * + * These files include the necessary UEFI constants and data structures + * that are used to interface to the FSP binary. + */ + +#include <uefi_types.h> /* UEFI data types */ +#include <IntelFspPkg/Include/FspApi.h> /* FSP API definitions */ +#include <IntelFspPkg/Include/FspInfoHeader.h> /* FSP binary layout */ +#include <MdePkg/Include/Pi/PiBootMode.h> /* UEFI boot mode definitions */ +#include <MdePkg/Include/Pi/PiFirmwareFile.h> /* UEFI file definitions */ +#include <MdePkg/Include/Pi/PiFirmwareVolume.h> /* UEFI file system defs */ +#include <MdePkg/Include/Uefi/UefiMultiPhase.h> /* UEFI memory types */ +#include <MdePkg/Include/Pi/PiHob.h> /* Hand off block definitions */ +#include <MdePkg/Include/Library/HobLib.h> /* HOB routine declarations */ +#include <VpdHeader.h> /* Vital/updatable product data definitions */ + +#endif /* CHIPSET_FSP_UTIL_H */ diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index bdf1cb3..9590e93 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,15 +18,21 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_ACPI_H_ -#define _BAYTRAIL_ACPI_H_ +#ifndef _BRASWELL_ACPI_H_ +#define _BRASWELL_ACPI_H_ #include <arch/acpi.h> #include <soc/nvs.h> -void acpi_create_intel_hpet(acpi_hpet_t * hpet); +#if CONFIG_GOP_SUPPORT +#include <soc/intel/common/gma.h> +int init_igd_opregion(igd_opregion_t *igd_opregion); +#endif + +void acpi_create_intel_hpet(acpi_hpet_t *hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); unsigned long acpi_madt_irq_overrides(unsigned long current); void acpi_init_gnvs(global_nvs_t *gnvs); -#endif /* _BAYTRAIL_ACPI_H_ */ +#endif /* _BRASWELL_ACPI_H_ */ + diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h index 1ed897f..e7bc17d 100644 --- a/src/soc/intel/braswell/include/soc/device_nvs.h +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_DEVICE_NVS_H_ -#define _BAYTRAIL_DEVICE_NVS_H_ +#ifndef _BRASWELL_DEVICE_NVS_H_ +#define _BRASWELL_DEVICE_NVS_H_ #include <stdint.h> @@ -62,7 +63,6 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ - u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ } __attribute__((packed)) device_nvs_t; -#endif +#endif /* _BRASWELL_DEVICE_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/efi_wrapper.h b/src/soc/intel/braswell/include/soc/efi_wrapper.h deleted file mode 100644 index 3304d03..0000000 --- a/src/soc/intel/braswell/include/soc/efi_wrapper.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * PEI EFI entry point - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __EFI_WRAPPER_H__ -#define __EFI_WRAPPER_H__ - -#define EFI_WRAPPER_VER 2 - -/* Provide generic x86 calling conventions. */ -#define ABI_X86 __attribute((regparm(0))) - -/* Errors returned by the EFI wrapper. */ -enum efi_wrapper_error { - INVALID_VER = -1, -}; - -struct efi_wrapper_params { - /* Mainboard Inputs */ - int version; - - void ABI_X86 (*console_out)(unsigned char byte); - - unsigned int tsc_ticks_per_microsecond; -} __attribute__((packed)); - -typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *); -#endif diff --git a/src/soc/intel/braswell/include/soc/ehci.h b/src/soc/intel/braswell/include/soc/ehci.h index a1edd6d..c3abe9c 100644 --- a/src/soc/intel/braswell/include/soc/ehci.h +++ b/src/soc/intel/braswell/include/soc/ehci.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,28 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef BAYTRAIL_EHCI_H -#define BAYTRAIL_EHCI_H +#ifndef _BRASWELL_EHCI_H_ +#define _BRASWELL_EHCI_H_ /* EHCI PCI Registers */ #define EHCI_CMD_STS 0x04 # define INTRDIS (1 << 10) -#define EHCI_SBRN_FLA_PWC 0x60 -# define PORTWKIMP (1 << 16) -# define PORTWKCAPMASK (0x3ff << 17) -#define EHCI_USB2PDO 0x64 -/* EHCI Memory Registers */ -#define USB2CMD 0x20 -# define USB2CMD_ASE (1 << 5) -# define USB2CMD_PSE (1 << 4) -# define USB2CMD_HCRESET (1 << 1) -# define USB2CMD_RS (1 << 0) -#define USB2STS 0x24 -# define USB2STS_HCHALT (1 << 12) - -/* RCBA EHCI Registers */ -#define RCBA_FUNC_DIS 0x220 -# define RCBA_EHCI_DIS (1 << 0) - -#endif /* BAYTRAIL_EHCI_H */ +#endif /* _BRASWELL_EHCI_H_ */ diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h index 7047dd5..4692d23 100644 --- a/src/soc/intel/braswell/include/soc/gfx.h +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,27 +18,48 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_GFX_H_ -#define _BAYTRAIL_GFX_H_ +#ifndef _BRASWELL_GFX_H_ +#define _BRASWELL_GFX_H_ /* * PCI config registers. */ #define GGC 0x50 -# define GGC_VGA_DISABLE (1 << 1) -# define GGC_GTT_SIZE_MASK (3 << 8) +# define GGC_VAMEN (1 << 14) /* Enable acceleration mode */ +# define GGC_GTT_SIZE_MASK (3 << 8) /* GTT graphics memory size */ # define GGC_GTT_SIZE_0MB (0 << 8) -# define GGC_GTT_SIZE_1MB (1 << 8) -# define GGC_GTT_SIZE_2MB (2 << 8) -# define GGC_GSM_SIZE_MASK (0x1f << 3) +# define GGC_GTT_SIZE_2MB (1 << 8) +# define GGC_GTT_SIZE_4MB (2 << 8) +# define GGC_GTT_SIZE_8MB (3 << 8) +# define GGC_GSM_SIZE_MASK (0x1f << 3) /* Main memory use */ # define GGC_GSM_SIZE_0MB (0 << 3) # define GGC_GSM_SIZE_32MB (1 << 3) # define GGC_GSM_SIZE_64MB (2 << 3) +# define GCC_GSM_SIZE_96MB (3 << 3) # define GGC_GSM_SIZE_128MB (4 << 3) +# define GGC_GSM_SIZE_160MB (5 << 3) +# define GGC_GSM_SIZE_192MB (6 << 3) +# define GGC_GSM_SIZE_224MB (7 << 3) +# define GGC_GSM_SIZE_256MB (8 << 3) +# define GGC_GSM_SIZE_288MB (9 << 3) +# define GGC_GSM_SIZE_320MB (0x0a << 3) +# define GGC_GSM_SIZE_352MB (0x0b << 3) +# define GGC_GSM_SIZE_384MB (0x0c << 3) +# define GGC_GSM_SIZE_416MB (0x0d << 3) +# define GGC_GSM_SIZE_448MB (0x0e << 3) +# define GGC_GSM_SIZE_480MB (0x0f << 3) +# define GGC_GSM_SIZE_512MB (0x10 << 3) +# define GGC_VGA_DISABLE (1 << 1) /* VGA Disable */ +# define GGC_GGCLCK (1 << 0) /* Prevent register writes */ #define GSM_BASE 0x5c +# define GSM_BDSM 0xfff00000 /* Base of stolen memory */ +# define GSM_BDSM_LOCK (1 << 0) /* Prevent register writes */ + #define GTT_BASE 0x70 +# define GTT_BGSM 0xfff00000 /* Base of stolen memory */ +# define GTT_BGSM_LOCK (1 << 0) /* Prevent register writes */ #define MSAC 0x62 #define APERTURE_SIZE_MASK (3 << 1) @@ -45,20 +67,32 @@ #define APERTURE_SIZE_256MB (1 << 1) #define APERTURE_SIZE_512MB (3 << 1) -#define VLV_DISPLAY_BASE 0x180000 -#define PIPEA_REG(reg) (VLV_DISPLAY_BASE + (reg)) -#define PIPEB_REG(reg) (VLV_DISPLAY_BASE + 0x100 + (reg)) +#define SWSCI 0xe8 /* SWSCI enable */ +#define ASLS 0xfc /* OpRegion Base */ /* Panel control registers */ #define HOTPLUG_CTRL 0x61110 #define PP_CONTROL 0x61204 -#define PP_CONTROL_UNLOCK 0xabcd0000 -#define PP_CONTROL_EDP_FORCE_VDD (1 << 3) +# define PP_CONTROL_WRITE_PROTECT_KEY 0xffff0000 /* Enable display port VDD */ +# define PP_CONTROL_UNLOCK 0xabcd0000 +# define PP_CONTROL_EDP_FORCE_VDD (1 << 3) /* Enable display port VDD */ +# define PP_CONTROL_BACKLIGHT_ENABLE (1 << 2) +# define PP_CONTROL_POWER_DOWN_ON_RESET (1 << 1) +# define PP_CONTROL_POWER_STATE_TARGET (1 << 0) /* Power up/down (1/0) */ + #define PP_ON_DELAYS 0x61208 #define PP_OFF_DELAYS 0x6120c #define PP_DIVISOR 0x61210 #define BACKLIGHT_CTL2 0x61250 -#define BACKLIGHT_ENABLE (1 << 31) +# define BACKLIGHT_PWM_ENABLE (1 << 31) +# define BACKLIGHT_POLARITY (1 << 28) /* Active low/high (1/0) */ +# define BACKLIGHT_PHASE_IN_INT_STATUS (1 << 26) +# define BACKLIGHT_PHASE_IN_ENABLE (1 << 25) +# define BACKLIGHT_PHASE_IN_INT_ENABLE (1 << 24) +# define BACKLIGHT_PHASE_IN_TIME_BASE 0x00ff0000 +# define BACKLIGHT_PHASE_IN_COUNT 0x0000ff00 +# define BACKLIGHT_PHASE_IN_INCREMENT 0x000000ff + #define BACKLIGHT_CTL 0x61254 -#endif /* _BAYTRAIL_GFX_H_ */ +#endif /* _BRASWELL_GFX_H_ */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index f312cdc..3587f49 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,299 +18,306 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_GPIO_H_ -#define _BAYTRAIL_GPIO_H_ +#ifndef _BRASWELL_GPIO_H_ +#define _BRASWELL_GPIO_H_ #include <stdint.h> #include <arch/io.h> #include <soc/iomap.h> -/* #define GPIO_DEBUG */ +#define COMMUNITY_SIZE 0x20000 -/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ -#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) -#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) -#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) +#define COMMUNITY_GPSOUTHWEST_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHWEST) -/* DIRQ registers start at pad base + 0x980 */ -#define PAD_BASE_DIRQ_OFFSET 0x980 +#define COMMUNITY_GPNORTH_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH) -/* Pad register offset */ -#define PAD_CONF0_REG 0x0 -#define PAD_CONF1_REG 0x4 -#define PAD_VAL_REG 0x8 - -/* Legacy IO register base */ -#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) -#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) -/* Some banks have no legacy GPIO interface */ -#define GP_LEGACY_BASE_NONE 0xFFFF - -#define LEGACY_USE_SEL_REG 0x00 -#define LEGACY_IO_SEL_REG 0x04 -#define LEGACY_GP_LVL_REG 0x08 -#define LEGACY_TPE_REG 0x0C -#define LEGACY_TNE_REG 0x10 -#define LEGACY_TS_REG 0x14 -#define LEGACY_WAKE_EN_REG 0x18 - -/* Number of GPIOs in each bank */ -#define GPNCORE_COUNT 27 -#define GPSCORE_COUNT 102 -#define GPSSUS_COUNT 44 - -/* GPIO legacy IO register settings */ -#define GPIO_USE_MMIO 0 -#define GPIO_USE_LEGACY 1 - -#define GPIO_DIR_OUTPUT 0 -#define GPIO_DIR_INPUT 1 - -#define GPIO_LEVEL_LOW 0 -#define GPIO_LEVEL_HIGH 1 - -#define GPIO_PEDGE_DISABLE 0 -#define GPIO_PEDGE_ENABLE 1 - -#define GPIO_NEDGE_DISABLE 0 -#define GPIO_NEDGE_ENABLE 1 +#define COMMUNITY_GPEAST_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPEAST) -/* config0[29] - Disable second mask */ -#define PAD_MASK2_DISABLE (1 << 29) +#define COMMUNITY_GPSOUTHEAST_BASE \ +(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPSOUTHEAST) -/* config0[27] - Direct Irq En */ -#define PAD_IRQ_EN (1 << 27) +#define GPIO_COMMUNITY_COUNT 4 +#define GPIO_FAMILIES_MAX_PER_COMM 7 +#define GP_SOUTHWEST 0 +#define GP_NORTH 1 +#define GP_EAST 2 +#define GP_SOUTHEAST 3 -/* config0[26] - gd_tne */ -#define PAD_TNE_IRQ (1 << 26) +#define COMMUNITY_BASE(community) \ +(IO_BASE_ADDRESS + community * 0x8000) -/* config0[25] - gd_tpe */ -#define PAD_TPE_IRQ (1 << 25) +#define GP_READ_ACCESS_POLICY_BASE(community) \ +(COMMUNITY_BASE(community) + 0x000) -/* config0[24] - Gd Level */ -#define PAD_LEVEL_IRQ (1 << 24) -#define PAD_EDGE_IRQ (0 << 24) +#define GP_WRITE_ACCESS_POLICY_BASE(community) \ +(COMMUNITY_BASE(community) + 0x100) -/* config0[17] - Slow clkgate / glitch filter */ -#define PAD_SLOWGF_ENABLE (1 << 17) +#define GP_WAKE_STATUS_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x200) -/* config0[16] - Fast clkgate / glitch filter */ -#define PAD_FASTGF_ENABLE (1 << 16) +#define GP_WAKE_MASK_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x280) -/* config0[15] - Hysteresis enable (inverted) */ -#define PAD_HYST_DISABLE (1 << 15) -#define PAD_HYST_ENABLE (0 << 15) +#define GP_INT_STATUS_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x300) -/* config0[14:13] - Hysteresis control */ -#define PAD_HYST_CTRL_DEFAULT (2 << 13) +#define GP_INT_MASK_REG_BASE(community) \ +(COMMUNITY_BASE(community) + 0x380) -/* config0[11] - Bypass Flop */ -#define PAD_FLOP_BYPASS (1 << 11) -#define PAD_FLOP_ENABLE (0 << 11) +#define GP_FAMILY_RCOMP_CTRL(community, family) \ +(COMMUNITY_BASE(community) + 0x1080 + 0x80 * family) -/* config0[10:9] - Pull str */ -#define PAD_PU_2K (0 << 9) -#define PAD_PU_10K (1 << 9) -#define PAD_PU_20K (2 << 9) -#define PAD_PU_40K (3 << 9) +#define GP_FAMILY_RCOMP_OFFSET(community, family) \ +(COMMUNITY_BASE(community) + 0x1084 + 0x80 * family) -/* config0[8:7] - Pull assign */ -#define PAD_PULL_DISABLE (0 << 7) -#define PAD_PULL_UP (1 << 7) -#define PAD_PULL_DOWN (2 << 7) +#define GP_FAMILY_RCOMP_OVERRIDE(community, family) \ +(COMMUNITY_BASE(community) + 0x1088 + 0x80 * family) -/* config0[2:0] - Func. pin mux */ -#define PAD_FUNC0 0x0 -#define PAD_FUNC1 0x1 -#define PAD_FUNC2 0x2 -#define PAD_FUNC3 0x3 -#define PAD_FUNC4 0x4 -#define PAD_FUNC5 0x5 -#define PAD_FUNC6 0x6 +#define GP_FAMILY_RCOMP_VALUE(community, family) \ +(COMMUNITY_BASE(community) + 0x108C + 0x80 * family) -/* pad config0 power-on values - We will not often want to change these */ -#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ - PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ - PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) +#define GP_FAMILY_CONF_COMP(community, family) \ +(COMMUNITY_BASE(community) + 0x1090 + 0x80 * family) -/* pad config1 reg power-on values - Shouldn't need to change this */ -#define PAD_CONFIG1_DEFAULT 0x8000 +#define GP_FAMILY_CONF_REG(community, family) \ +(COMMUNITY_BASE(community) + 0x1094 + 0x80 * family) -/* pad_val[2] - Iinenb - active low */ -#define PAD_VAL_INPUT_DISABLE (1 << 2) -#define PAD_VAL_INPUT_ENABLE (0 << 2) +/* GPIO Security registers offset */ +#define GPIO_READ_ACCESS_POLICY_REG 0x0000 +#define GPIO_WRITE_ACCESS_POLICY_REG 0x0100 +#define GPIO_WAKE_STATUS_REG 0x0200 +#define GPIO_WAKE_MASK_REG0 0x0280 +#define GPIO_WAKE_MASK_REG1 0x0284 +#define GPIO_INTERRUPT_STATUS 0x0300 +#define GPIO_INTERRUPT_MASK 0x0380 +#define GPE0A_STS_REG 0x20 +#define GPE0A_EN_REG 0x28 +#define ALT_GPIO_SMI_REG 0x38 +#define GPIO_ROUT_REG 0x58 -/* pad_val[1] - Ioutenb - active low */ -#define PAD_VAL_OUTPUT_DISABLE (1 << 1) -#define PAD_VAL_OUTPUT_ENABLE (0 << 1) - -/* Input / Output state should usually be mutually exclusive */ -#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) -#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) - -/* pad_val[0] - Value */ -#define PAD_VAL_HIGH (1 << 0) -#define PAD_VAL_LOW (0 << 0) +/* Pad register offset */ +#define PAD_CONF0_REG 0x0 +#define PAD_CONF1_REG 0x4 +#define PAD_VAL_REG 0x8 -/* pad_val reg power-on default varies by pad, and apparently can cause issues - * if not set correctly, even if the pin isn't configured as GPIO. */ -#define PAD_VAL_DEFAULT PAD_VAL_INPUT +/* Some banks have no legacy GPIO interface */ +#define GP_LEGACY_BASE_NONE 0xFFFF -/* Configure GPIOs as MMIO by default */ -#define GPIO_INPUT_PU_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } +/* Number of GPIOs in each bank */ +#define GPNCORE_COUNT 27 +#define GPSCORE_COUNT 102 +#define GPSSUS_COUNT 44 + +#define GP_SOUTHWEST_COUNT 56 +#define GP_NORTH_COUNT 59 +#define GP_EAST_COUNT 24 +#define GP_SOUTHEAST_COUNT 55 + +/* General */ +#define GPIO_REGS_SIZE 8 +#define NA 0 +#define LOW 0 +#define HIGH 1 +#define MASK_WAKE 0 +#define UNMASK_WAKE 1 +#define GPE_CAPABLE 1 +#define GPE_CAPABLE_NONE 0 + +#define MAX_FAMILY_PAD_GPIO_NO 15 +#define FAMILY_PAD_REGS_OFF 0x4400 +#define FAMILY_PAD_REGS_SIZE 0x400 + +/* config0[31:28] - Interrupt Selection Interrupt Select */ +#define PAD_INT_SEL(int_s) (int_s << 28) + +/* config0[27:26] - Glitch Filter Config */ +#define PAD_GFCFG(glitch_cfg) (glitch_cfg << 26) +#define PAD_GFCFG_DISABLE (0 << 26) +#define PAD_ENABLE_EDGE_DETECTION (1 << 26) /* EDGE DETECTION ONLY */ +#define PAD_ENABLE_RX_DETECTION (2 << 26) /* RX DETECTION ONLY */ +#define PAD_ENABLE_EDGE_RX_DETECTION (3 << 26) /* RX & EDGE DETECTION */ + +/* config0[25:24] - RX/TX Enable Config */ +#define PAD_FUNC_CTRL(tx_rx_enable) (tx_rx_enable << 24) +#define PAD_FUNC_CTRL_RX_TX_ENABLE (0 << 24) +#define PAD_FUNC_CTRL_TX_ENABLE_RX_DISABLE (1 << 24) +#define PAD_FUNC_CTRL_TX_ENABLE_RX_ENABLE (2 << 24) +#define PAD_TX_RX_ENABLE (3 << 24) + +/* config0[23:20] - Termination */ +#define PAD_PULL(TERM) (TERM << 20) +#define PAD_PULL_DISABLE (0 << 20) +#define PAD_PULL_DOWN_20K (1 << 20) +#define PAD_PULL_DOWN_5K (2 << 20) +#define PAD_PULL_DOWN_1K (4 << 20) +#define PAD_PULL_UP_20K (9 << 20) +#define PAD_PULL_UP_5K (10 << 20) +#define PAD_PULL_UP_1K (12 << 20) + +/* config0[19:16] - PAD Mode */ +#define PAD_MODE_SELECTION(MODE_SEL) (MODE_SEL<<16) + +#define SET_PAD_MODE_SELECTION(pad_config, mode) \ + ((pad_config & 0xfff0ffff) | PAD_MODE_SELECTION(mode)) + +/* config0[15] - GPIO Enable */ +#define PAD_GPIO_DISABLE (0 << 15) +#define PAD_GPIO_ENABLE (1 << 15) + +/* config0[14:11] - Reserver2 */ + +/* config0[10:8] - GPIO Config */ +#define PAD_GPIO_CFG(gpio_cfg) (gpio_cfg << 8) +#define PAD_GPIOFG_GPIO (0 << 8) +#define PAD_GPIOFG_GPO (1 << 8) +#define PAD_GPIOFG_GPI (2 << 8) +#define PAD_GPIOFG_HI_Z (3 << 8) + +/* config0[7] - Gpio Light Mode Bar */ +/* config0[6:2] - Reserved1 */ +/* config0[1] - GPIO TX State */ +#define PAD_DEFAULT_TX(STATE) (STATE<<1) +/* config0[0] - GPIO RX State */ +#define PAD_RX_BIT 1 + +/* Pad Control Register 1 configuration */ +#define PAD_DISABLE_INT (0 << 0) +#define PAD_TRIG_EDGE_LOW (1 << 0) +#define PAD_TRIG_EDGE_HIGH (2 << 0) +#define PAD_TRIG_EDGE_BOTH (3 << 0) +#define PAD_TRIG_EDGE_LEVEL (4 << 0) + +/* Pad config0 power-on values */ +#define PAD_CONFIG0_DEFAULT 0x00010300 +#define PAD_CONFIG0_DEFAULT0 0x00910300 +#define PAD_CONFIG0_DEFAULT1 0x00110300 +#define PAD_CONFIG0_GPI_DEFAULT 0x00010200 + +/* Pad config1 reg power-on values */ +#define PAD_CONFIG1_DEFAULT0 0x05C00000 +#define PAD_CONFIG1_CSEN 0x0DC00000 +#define PAD_CONFIG1_DEFAULT1 0x05C00020 + +#define GPIO_INPUT_NO_PULL \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } #define GPIO_INPUT_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_10K \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_MMIO, \ - .is_gpio = 1 } - -#define GPIO_INPUT_LEGACY_NOPU \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .is_gpio = 1 } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_LEVELHIGH_NO_PULL \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_LEVELLOW_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGELOW_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGEHIGH_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGELOW_PD_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -/* Direct / dedicated IRQ input - pass signal directly to apic */ -#define GPIO_DIRQ_EDGEBOTH_PU_20K \ - { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, } - -#define GPIO_OUT_LOW \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_LOW, \ - .is_gpio = 1 } - -#define GPIO_OUT_HIGH \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_OUTPUT, \ - .gp_lvl = GPIO_LEVEL_HIGH, \ - .is_gpio = 1 } - -/* Define no-pull / PU / PD configs for each functional config option */ -#define GPIO_FUNC(_func, _pudir, _str) \ - { .use_sel = GPIO_USE_MMIO, \ - .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ - PAD_CONFIG0_DEFAULT, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_DEFAULT } - -/* Default functional configs -- no PU */ -#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) -#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) -#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) -#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) -#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) -#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) -#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) - -/* ACPI GPIO routing. Assume everything is externally pulled and negative edge - * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ -#define GPIO_ACPI_SCI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .sci = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_WAKE \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .wake_en = 1, } -#define GPIO_ACPI_SMI \ - { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = 1, \ - .smi = 1} + { .pad_conf0 = PAD_PULL_UP_20K | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define GPIO_INPUT_PU_5K \ + { .pad_conf0 = PAD_PULL_UP_5K | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define GPI(int_type, int_sel, term, int_msk, glitch_cfg, wake_msk, gpe_val) { \ + .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GFCFG(glitch_cfg) \ + | PAD_PULL(term) | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI, \ + .pad_conf1 = int_type << 0 | PAD_CONFIG1_DEFAULT0, \ + .wake_mask = wake_msk, \ + .int_mask = int_msk, \ + .gpe = gpe_val } + +#define GPO_FUNC(term, tx_state) {\ + .pad_conf0 = PAD_GPIO_ENABLE | PAD_GPIOFG_GPO | PAD_PULL(term) \ + | tx_state << 1, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define NATIVE_FUNC(mode, term, inv_rx_tx) {\ + .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \ + | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 } + +#define NATIVE_FUNC_TX_RX(tx_rx_enable, mode, term, inv_rx_tx) {\ + .pad_conf0 = PAD_FUNC_CTRL(tx_rx_enable) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_GPIO | PAD_MODE_SELECTION(mode) \ + | PAD_PULL(term),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 | inv_rx_tx << 4 } + +#define NATIVE_FUNC_CSEN(mode, term, inv_rx_tx) {\ + .pad_conf0 = PAD_GPIO_DISABLE | PAD_GPIOFG_HI_Z \ + | PAD_MODE_SELECTION(mode) | PAD_PULL(term),\ + .pad_conf1 = PAD_CONFIG1_CSEN | inv_rx_tx << 4 } + +#define NATIVE_INT(mode, int_sel) {\ + .pad_conf0 = PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define SPEAKER \ +{ .pad_conf0 = PAD_CONFIG0_DEFAULT0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define SPARE_PIN\ + { .pad_conf0 = 0x00110300,\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +/* SCI , SMI, Wake */ +#define GPIO_SCI(int_sel) \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ + | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ + | PAD_INT_SEL(int_sel), \ + .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ + .gpe = SCI, \ + .int_mask = 1 } + +#define GPIO_WAKE(int_sel) \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ + | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ + | PAD_INT_SEL(int_sel), \ + .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ + .int_mask = 1 ,\ + .wake_mask = 1 } + +#define GPIO_SMI(int_sel) \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_ENABLE_EDGE_RX_DETECTION\ + | PAD_GPIO_ENABLE | PAD_GPIOFG_GPI \ + | PAD_INT_SEL(int_sel), \ + .pad_conf1 = PAD_TRIG_EDGE_LOW | PAD_CONFIG1_DEFAULT0, \ + .int_mask = 1,\ + .gpe = SMI } + +#define GPIO_SKIP { .skip_config = 1 } + +/* Common GPIO settings */ +#define NATIVE_DEFAULT(mode) NATIVE_FUNC(mode, 0, 0) /* no pull */ +#define NATIVE_PU20K(mode) NATIVE_FUNC(mode, 9, 0) /* PH 20k */ +#define NATIVE_PU5K(mode) NATIVE_FUNC(mode, 10, 0) /* PH 5k */ +#define NATIVE_PU5K_INVTX(mode) NATIVE_FUNC(mode, 10, inv_tx_enable) /* PH 5k */ +#define NATIVE_PU1K(mode) NATIVE_FUNC(mode, 12, 0) /* PH 1k */ +#define NATIVE_PU1K_CSEN_INVTX(mode) \ + NATIVE_FUNC_CSEN(mode, 12, inv_tx_enable) /* PH 1k */ +#define NATIVE_PU1K_INVTX(mode) NATIVE_FUNC(mode, 12, inv_tx_enable) /* PH 1k */ +#define NATIVE_PD20K(mode) NATIVE_FUNC(mode, 1, 0) /* PD 20k */ +#define NATIVE_PD5K(mode) NATIVE_FUNC(mode, 2, 0) /* PD 5k */ +#define NATIVE_PD1K(mode) NATIVE_FUNC(mode, 4, 0) /* PD 1k */ +#define NATIVE_PD1K_CSEN_INVTX(mode) NATIVE_FUNC_CSEN(mode, 4, inv_tx_enable) + /* no pull */ +#define NATIVE_TX_RX_EN NATIVE_FUNC_TX_RX(3, 1, 0, inv_tx_enable) +#define NATIVE_TX_RX_M1 NATIVE_FUNC_TX_RX(0, 1, 0, 0) /* no pull */ +#define NATIVE_TX_RX_M3 NATIVE_FUNC_TX_RX(0, 3, 0, 0) /* no pull */ +#define NATIVE_PU1K_M1 NATIVE_PU1K(1) /* PU1k M1 */ + +/* Default native functions */ +#define Native_M0 NATIVE_DEFAULT(0) +#define Native_M1 NATIVE_DEFAULT(1) +#define Native_M2 NATIVE_DEFAULT(2) +#define Native_M3 NATIVE_DEFAULT(3) +#define Native_M4 NATIVE_DEFAULT(4) +#define Native_M5 NATIVE_DEFAULT(5) +#define Native_M6 NATIVE_DEFAULT(6) +#define Native_M7 NATIVE_DEFAULT(7) +#define Native_M8 NATIVE_DEFAULT(8) + +#define GPIO_OUT_LOW GPO_FUNC(0, 0) /* gpo low */ +#define GPIO_OUT_HIGH GPO_FUNC(0, 1) /* gpo high */ +#define GPIO_NC GPIO_INPUT_PU_20K /* not connect */ /* End marker */ #define GPIO_LIST_END 0xffffffff @@ -317,143 +325,224 @@ #define GPIO_END \ { .pad_conf0 = GPIO_LIST_END } -/* Common default GPIO settings */ -#define GPIO_INPUT GPIO_INPUT_NOPU -#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU -#define GPIO_INPUT_PU GPIO_INPUT_PU_20K -#define GPIO_INPUT_PD GPIO_INPUT_PD_20K -#define GPIO_NC GPIO_OUT_HIGH -#define GPIO_DEFAULT GPIO_FUNC0 - /* 16 DirectIRQs per supported bank */ -#define GPIO_MAX_DIRQS 16 - -/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO - * function 1. Indicate first / last GPIOs with function 1. */ -#define GPIO_NONE 255 -/* All NCORE GPIOs are function 0 */ -#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE -#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE -/* SCORE GPIO [92:93] are function 1 */ -#define GPSCORE_GPIO_F1_RANGE_START 92 -#define GPSCORE_GPIO_F1_RANGE_END 93 -/* SSUS GPIO [11:21] are function 1 */ -#define GPSSUS_GPIO_F1_RANGE_START 11 -#define GPSSUS_GPIO_F1_RANGE_END 21 +#define GPIO_MAX_DIRQS 16 + +#define GPIO_NONE 255 + +/* Functions / defines for changing GPIOs in romstage */ +/* SCORE Pad definitions. */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 +#define PCU_SMB_CLK_PAD 88 +#define PCU_SMB_DATA_PAD 90 +#define SOC_DDI1_VDDEN_PAD 16 +#define UART1_RXD_PAD 9 +#define UART1_TXD_PAD 13 +#define DDI2_DDC_SCL 48 +#define DDI2_DDC_SDA 53 struct soc_gpio_map { u32 pad_conf0; u32 pad_conf1; u32 pad_val; - u32 use_sel : 1; - u32 io_sel : 1; - u32 gp_lvl : 1; - u32 tpe : 1; - u32 tne : 1; - u32 wake_en : 1; - u32 smi : 1; - u32 is_gpio : 1; - u32 sci : 1; + u32 gpe; + u32 int_mask:1; + u32 wake_mask:1; + u32 is_gpio:1; + u32 skip_config:1; } __attribute__ ((packed)); struct soc_gpio_config { - const struct soc_gpio_map *ncore; - const struct soc_gpio_map *score; - const struct soc_gpio_map *ssus; - const u8 (*core_dirq)[GPIO_MAX_DIRQS]; - const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; + const struct soc_gpio_map *north; + const struct soc_gpio_map *southeast; + const struct soc_gpio_map *southwest; + const struct soc_gpio_map *east; }; -/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ +/* Description of a GPIO 'community' */ struct gpio_bank { const int gpio_count; - const u8* gpio_to_pad; + const u8 *gpio_to_pad; const int legacy_base; const unsigned long pad_base; - const u8 has_wake_en :1; - const u8 gpio_f1_range_start; - const u8 gpio_f1_range_end; + const u8 has_gpe_en:1; + const u8 has_wake_en:1; }; -void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); -/* This function is weak and can be overridden by a mainboard function. */ -struct soc_gpio_config* mainboard_get_gpios(void); +typedef enum { + NATIVE = 0xff, + GPIO = 0, /* Native, no need to set PAD_VALUE */ + GPO = 1, /* GPI, input only in PAD_VALUE */ + GPI = 2, /* GPO, output only in PAD_VALUE */ + HI_Z = 3, + NA_GPO = 0, +} gpio_en_t; + +typedef enum { + LO = 0, + HI = 1, +} gpo_d4_t; + +typedef enum { + F0 = 0, + F1 = 1, + F2 = 2, + F3 = 3 +} gpio_func_num_t; + +typedef enum { + _CAP = 1, + _NOT_CAP = 0 +} int_capable_t; + +typedef enum { + P_NONE = 0, /* Pull None */ + P_20K_L = 1, /* Pull Down 20K */ + P_5K_L = 2, /* Pull Down 5K */ + P_1K_L = 4, /* Pull Down 1K */ + P_20K_H = 9, /* Pull Up 20K */ + P_5K_H = 10, /* Pull Up 5K */ + P_1K_H = 12 /* Pull Up 1K */ +} pull_type_t; + +typedef enum { + DISABLE = 0, /* Disable */ + ENABLE = 1, /* Enable */ +} park_mode_enb_t; + +typedef enum { + VOLT_3_3 = 0, /* Working on 3.3 Volts */ + VOLT_1_8 = 1, /* Working on 1.8 Volts */ +} voltage_t; + +typedef enum { + DISABLE_HS = 0, /* Disable high speed mode */ + ENABLE_HS = 1, /* Enable high speed mode */ +} hs_mode_t; + +typedef enum { + PULL_UP = 0, /* On Die Termination Up */ + PULL_DOWN = 1, /* On Die Termination Down */ +} odt_up_dn_t; + +typedef enum { + DISABLE_OD = 0, /* On Die Termination Disable */ + ENABLE_OD = 1, /* On Die Termination Enable */ +} odt_en_t; + +typedef enum { + ONE_BIT = 1, + TWO_BIT = 3, + THREE_BIT = 7, + FOUR_BIT = 15, + FIVE_BIT = 31, + SIX_BIT = 63, + SEVEN_BIT = 127, + EIGHT_BIT = 255 +} bit_t; + +typedef enum { + M0 = 0, + M1, + M2, + M3, + M4, + M5, + M6, + M7, + M8, + M9, + M10, + M11, + M12, + M13, +} mode_list_t; + +typedef enum { + L0 = 0, + L1 = 1, + L2 = 2, + L3 = 3, + L4 = 4, + L5 = 5, + L6 = 6, + L7 = 7, + L8 = 8, + L9 = 9, + L10 = 10, + L11 = 11, + L12 = 12, + L13 = 13, + L14 = 14, + L15 = 15, +} int_select_t; + +typedef enum { + INT_DIS = 0, + trig_edge_low = 1, + trig_edge_high = 2, + trig_edge_both = 3, + trig_level = 4, +} int_type_t; + +typedef enum { + glitch_disable = 0, + en_edge_detect, + en_rx_data, + en_edge_rx_data, +} glitch_cfg; + +typedef enum { + maskable = 0, + non_maskable, +} mask_t; + +typedef enum { + GPE = 0, + SMI, + SCI, +} gpe_config_t; -/* Functions / defines for changing GPIOs in romstage */ -/* SCORE Pad definitions. */ -#define UART_RXD_PAD 82 -#define UART_TXD_PAD 83 -#define PCU_SMB_CLK_PAD 88 -#define PCU_SMB_DATA_PAD 90 -#define SOC_DDI1_VDDEN_PAD 16 +/* + * InvertRxTx 7:4 + * 0 - No Inversion + * 1 - Inversion + * [0] RX Enable + * [1] TX Enable + * [2] RX Data + * [3] TX Data + */ +typedef enum { + no_inversion = 0, + inv_rx_enable = 0x1, + inv_tx_enable = 0x2, + inv_rx_tx_enable = 0x3, + inv_rx_data = 0x4, + inv_tx_data = 0x8, +} invert_rx_tx_t; -static inline u32 *ncore_pconf0(int pad_num) -{ - return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16); -} +void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); +struct soc_gpio_config *mainboard_get_gpios(void); static inline void ncore_select_func(int pad, int func) { - uint32_t reg; - u32 *pconf0_addr = ncore_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} -static inline u32 *score_pconf0(int pad_num) -{ - return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16); -} - -static inline u32 *ssus_pconf0(int pad_num) -{ - return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16); -} - -static inline void score_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = score_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); -} - -static inline void ssus_select_func(int pad, int func) -{ - uint32_t reg; - uint32_t *pconf0_addr = ssus_pconf0(pad); - - reg = read32(pconf0_addr); - reg &= ~0x7; - reg |= func & 0x7; - write32(pconf0_addr, reg); } /* These functions require that the input pad be configured as an input GPIO */ -static inline int score_get_gpio(int pad) -{ - uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; -} static inline int ssus_get_gpio(int pad) { - uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); - - return read32(val_addr) & PAD_VAL_HIGH; + return 0; } static inline void ssus_disable_internal_pull(int pad) { - const uint32_t pull_mask = ~(0xf << 7); - write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); } -#endif /* _BAYTRAIL_GPIO_H_ */ +int get_gpio(int community_base, int pad0_offset); +uint16_t gpio_family_number(uint8_t community, uint8_t pad); +uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad); + +#endif /* _BRASWELL_GPIO_H_ */ diff --git a/src/soc/intel/braswell/include/soc/hda.h b/src/soc/intel/braswell/include/soc/hda.h new file mode 100644 index 0000000..8443ffa --- /dev/null +++ b/src/soc/intel/braswell/include/soc/hda.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BRASWELL_HDA_H_ +#define _BRASWELL_HDA_H_ + +/* + * PCI config registers. + */ + +#define HDA_DCKSTS 0x4d +# define HDA_DCKSTS_DS (1 << 7) +# define HDA_DCKSTS_DM (1 << 0) + +#define HDA_DEVC 0x78 +# define HDA_DEVC_MRRS 0x7000 +# define HDA_DEVC_NSNPEN (1 << 11) +# define HDA_DEVC_AUXPEN (1 << 10) +# define HDA_DEVC_PEEN (1 << 9) +# define HDA_DEVC_ETEN (1 << 8) +# define HDA_DEVC_MAXPAY 0x00e0 +# define HDA_DEVC_ROEN (1 << 4) +# define HDA_DEVC_URREN (1 << 3) +# define HDA_DEVC_FEREN (1 << 2) +# define HDA_DEVC_NFEREN (1 << 1) +# define HDA_DEVC_CEREN (1 << 0) + +#endif /* _BRASWELL_HDA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h index 867484b..d6dde43 100644 --- a/src/soc/intel/braswell/include/soc/iomap.h +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_IOMAP_H_ -#define _BAYTRAIL_IOMAP_H_ +#ifndef _BRASWELL_IOMAP_H_ +#define _BRASWELL_IOMAP_H_ /* @@ -38,11 +39,12 @@ #define PMC_BASE_SIZE 0x400 /* IO Memory */ -#define IO_BASE_ADDRESS 0xfed0c000 -#define IO_BASE_OFFSET_GPSCORE 0x0000 -#define IO_BASE_OFFSET_GPNCORE 0x1000 -#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_ADDRESS 0xfed80000 #define IO_BASE_SIZE 0x4000 +#define COMMUNITY_OFFSET_GPSOUTHWEST 0x00000 +#define COMMUNITY_OFFSET_GPNORTH 0x08000 +#define COMMUNITY_OFFSET_GPEAST 0x10000 +#define COMMUNITY_OFFSET_GPSOUTHEAST 0x18000 /* Intel Legacy Block */ #define ILB_BASE_ADDRESS 0xfed08000 @@ -53,11 +55,11 @@ #define SPI_BASE_SIZE 0x400 /* MODPHY */ -#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_ADDRESS 0xfea00000 #define MPHY_BASE_SIZE 0x100000 /* Power Management Unit */ -#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_ADDRESS 0xfed06000 #define PUNIT_BASE_SIZE 0x800 /* Root Complex Base Address */ @@ -87,4 +89,4 @@ uint32_t nc_read_top_of_low_memory(void); #endif -#endif /* _BAYTRAIL_IOMAP_H_ */ +#endif /* _BRASWELL_IOMAP_H_ */ diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index 6705a73..8cfbc6c 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,29 +18,33 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_IOSF_H_ -#define _BAYTRAIL_IOSF_H_ +#ifndef _BRASWELL_IOSF_H_ +#define _BRASWELL_IOSF_H_ #include <stdint.h> +#if ENV_RAMSTAGE +#include <device/device.h> +#include <reg_script.h> +#endif /* ENV_RAMSTAGE */ #include <soc/pci_devs.h> /* - * The Bay Trail SoC has a message network called IOSF Sideband. The access + * The SoC has a message network called IOSF Sideband. The access * routines are through 3 registers in PCI config space of 00:00.0: * MCR - control register * MDR - data register * MCRX - control register extension - * The extension regist is only used for addresses that don't fit into the - * 8 bit register address. + * The extension register is only used for addresses that don't fit + * into the 8 bit register address. */ #ifndef PCI_DEV #define PCI_DEV(SEGBUS, DEV, FN) ( \ - (((SEGBUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x07) << 12)) + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) #endif -#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) +#define IOSF_PCI_DEV PCI_DEV(0, SOC_DEV, SOC_FUNC) #define MCR_REG 0xd0 #define IOSF_OPCODE(x) ((x) << 24) @@ -55,63 +60,29 @@ #define MDR_REG 0xd4 #define MCRX_REG 0xd8 -uint32_t iosf_aunit_read(int reg); -void iosf_aunit_write(int reg, uint32_t val); -uint32_t iosf_cpu_bus_read(int reg); -void iosf_cpu_bus_write(int reg, uint32_t val); uint32_t iosf_bunit_read(int reg); void iosf_bunit_write(int reg, uint32_t val); -uint32_t iosf_dunit_read(int reg); -void iosf_dunit_write(int reg, uint32_t val); -/* Some registers are per channel while the globals live in dunit 0 */ -uint32_t iosf_dunit_ch0_read(int reg); -uint32_t iosf_dunit_ch1_read(int reg); uint32_t iosf_punit_read(int reg); void iosf_punit_write(int reg, uint32_t val); -uint32_t iosf_usbphy_read(int reg); -void iosf_usbphy_write(int reg, uint32_t val); -uint32_t iosf_ushphy_read(int reg); -void iosf_ushphy_write(int reg, uint32_t val); -uint32_t iosf_sec_read(int reg); -void iosf_sec_write(int reg, uint32_t val); -uint32_t iosf_port45_read(int reg); -void iosf_port45_write(int reg, uint32_t val); -uint32_t iosf_port46_read(int reg); -void iosf_port46_write(int reg, uint32_t val); -uint32_t iosf_port47_read(int reg); -void iosf_port47_write(int reg, uint32_t val); -uint32_t iosf_port55_read(int reg); -void iosf_port55_write(int reg, uint32_t val); -uint32_t iosf_port58_read(int reg); -void iosf_port58_write(int reg, uint32_t val); -uint32_t iosf_port59_read(int reg); -void iosf_port59_write(int reg, uint32_t val); -uint32_t iosf_port5a_read(int reg); -void iosf_port5a_write(int reg, uint32_t val); -uint32_t iosf_lpss_read(int reg); -void iosf_lpss_write(int reg, uint32_t val); -uint32_t iosf_ccu_read(int reg); -void iosf_ccu_write(int reg, uint32_t val); uint32_t iosf_score_read(int reg); void iosf_score_write(int reg, uint32_t val); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); +uint32_t iosf_port58_read(int reg); +void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); -uint32_t iosf_porta2_read(int reg); -void iosf_porta2_write(int reg, uint32_t val); -uint32_t iosf_ssus_read(int reg); -void iosf_ssus_write(int reg, uint32_t val); + +#if ENV_RAMSTAGE +uint64_t reg_script_read_iosf(struct reg_script_context *ctx); +void reg_script_write_iosf(struct reg_script_context *ctx); +#endif /* ENV_RAMSTAGE */ /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ -#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ -#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ #define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ #define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ #define IOSF_PORT_PMC 0x04 /* Power Management Controller */ -#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ -#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ -#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ -#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_SEC 0x44 /* SEC */ #define IOSF_PORT_0x45 0x45 #define IOSF_PORT_0x46 0x46 @@ -125,148 +96,42 @@ void iosf_ssus_write(int reg, uint32_t val); #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 -#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ -#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ #define IOSF_PORT_SSUS 0xa8 /* SUS */ #define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ /* Read and write opcodes differ per port. */ -#define IOSF_OP_READ_AUNIT 0x10 -#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) -#define IOSF_OP_READ_SYSMEMC 0x10 -#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) -#define IOSF_OP_READ_CPU_BUS 0x10 -#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) #define IOSF_OP_READ_BUNIT 0x10 #define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) #define IOSF_OP_READ_PMC 0x06 #define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) -#define IOSF_OP_READ_GFX 0x00 -#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) -#define IOSF_OP_READ_SYSMEMIO 0x06 -#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) -#define IOSF_OP_READ_USBPHY 0x06 -#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) -#define IOSF_OP_READ_SEC 0x04 -#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) -#define IOSF_OP_READ_0x45 0x06 -#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) -#define IOSF_OP_READ_0x46 0x06 -#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) -#define IOSF_OP_READ_0x47 0x06 -#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) #define IOSF_OP_READ_SCORE 0x06 #define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) -#define IOSF_OP_READ_0x55 0x04 -#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) -#define IOSF_OP_READ_0x58 0x06 -#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) -#define IOSF_OP_READ_0x59 0x06 -#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) -#define IOSF_OP_READ_0x5a 0x04 -#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) -#define IOSF_OP_READ_USHPHY 0x06 -#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) -#define IOSF_OP_READ_SCC 0x06 -#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) #define IOSF_OP_READ_LPSS 0x06 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) -#define IOSF_OP_READ_0xa2 0x06 -#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) -#define IOSF_OP_READ_SATAPHY 0x00 -#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) -#define IOSF_OP_READ_PCIEPHY 0x00 -#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) -#define IOSF_OP_READ_SSUS 0x10 -#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) -#define IOSF_OP_READ_CCU 0x06 -#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) +#define IOSF_OP_READ_0x58 0x06 +#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) +#define IOSF_OP_READ_SCC 0x06 +#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) /* * BUNIT Registers. */ -#define BNOCACHE 0x23 /* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ #define BUNIT_BMBOUND 0x25 -/* BMBOUND_HI describes the available ram above 4GiB. It has a +/* + * BMBOUND_HI describes the available ram above 4GiB. It has a * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB * granularity care needs to be taken with the e820 map to account for a hole - * in the ram. */ + * in the ram. + */ #define BUNIT_BMBOUND_HI 0x26 #define BUNIT_MMCONF_REG 0x27 +#define BUNIT_BMISC 0x28 /* The SMMRR registers define the SMM region in MiB granularity. */ -#define BUNIT_SMRCP 0x2b -#define BUNIT_SMRRAC 0x2c -#define BUNIT_SMRWAC 0x2d #define BUNIT_SMRRL 0x2e #define BUNIT_SMRRH 0x2f -# define BUNIT_SMRR_ENABLE (1 << 31) - -/* SA ID bits. */ -#define SAI_IA_UNTRUSTED (1 << 0) -#define SAI_IA_SMM (1 << 2) -#define SAI_IA_BOOT (1 << 4) - -/* - * DUNIT Registers. - */ - -#define DRP 0x00 -# define DRP_DIMM0_RANK0_EN (0x01 << 0) -# define DRP_DIMM0_RANK1_EN (0x01 << 1) -# define DRP_DIMM1_RANK0_EN (0x01 << 2) -# define DRP_DIMM1_RANK1_EN (0x01 << 3) -# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ - DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) -#define DTR0 0x01 -# define DTR0_SPEED_MASK 0x03 -# define DTR0_SPEED_800 0x00 -# define DTR0_SPEED_1066 0x01 -# define DTR0_SPEED_1333 0x02 -# define DTR0_SPEED_1600 0x03 - -/* - * PUNIT Registers - */ -#define SB_BIOS_CONFIG 0x06 -# define SB_BIOS_CONFIG_ECC_EN (1 << 31) -# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) -# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) -# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) -# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) -# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) -# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) -# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) -# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) -# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) -# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) -# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) -#define BIOS_RESET_CPL 0x05 -# define BIOS_RESET_CPL_ALL_DONE (1 << 1) -# define BIOS_RESET_CPL_RESET_DONE (1 << 0) -#define PUNIT_PWRGT_CONTROL 0x60 -#define PUNIT_PWRGT_STATUS 0x61 -#define PUNIT_GPU_EC_VIRUS 0xd2 - -#define PUNIT_SOC_POWER_BUDGET 0x02 -#define PUNIT_SOC_ENERGY_CREDIT 0x03 -#define PUNIT_PTMC 0x80 -#define PUNIT_GFXT 0x88 -#define PUNIT_VEDT 0x89 -#define PUNIT_ISPT 0x8c -#define PUNIT_PTPS 0xb2 -#define PUNIT_TE_AUX0 0xb5 -#define PUNIT_TE_AUX1 0xb6 -#define PUNIT_TE_AUX2 0xb7 -#define PUNIT_TE_AUX3 0xb8 -#define PUNIT_TTE_VRIccMax 0xb9 -#define PUNIT_TTE_VRHot 0xba -#define PUNIT_TTE_XXPROCHOT 0xbb -#define PUNIT_TTE_SLM0 0xbc -#define PUNIT_TTE_SLM1 0xbd -#define PUNIT_TTE_SWT 0xbf /* * LPSS Registers @@ -296,54 +161,37 @@ void iosf_ssus_write(int reg, uint32_t val); */ #define SCC_SD_CTL 0x504 #define SCC_SDIO_CTL 0x508 -#define SCC_MMC_CTL 0x50c +#define SCC_MMC_CTL 0x500 # define SCC_CTL_PCI_CFG_DIS (1 << 0) # define SCC_CTL_ACPI_INT_EN (1 << 1) /* - * CCU Registers - */ - -#define PLT_CLK_CTRL_0 0x3c -#define PLT_CLK_CTRL_1 0x40 -#define PLT_CLK_CTRL_2 0x44 -#define PLT_CLK_CTRL_3 0x48 -#define PLT_CLK_CTRL_4 0x4c -#define PLT_CLK_CTRL_5 0x50 -# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) -# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) -# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) - -/* - * USBPHY Registers - */ -#define USBPHY_COMPBG 0x7f04 -#define USBPHY_PER_PORT_LANE0 0x4100 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 -#define USBPHY_PER_PORT_LANE1 0x4200 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 -#define USBPHY_PER_PORT_LANE2 0x4300 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 -#define USBPHY_PER_PORT_LANE3 0x4400 -#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 - -/* - * USHPHY Registers - */ -#define USHPHY_CDN_PLL_CONTROL 0x03c0 -#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 -#define USHPHY_CCDRLF 0x8040 -#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 -#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 -#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 -#define USHPHY_REE_DAC_CONTROL 0x80b8 -#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 - -/* * LPE Registers */ #define LPE_PCICFGCTR1 0x0500 # define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) # define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) -#endif /* _BAYTRAIL_IOSF_H_ */ +/* + * IO Sideband Function + */ + +#if ENV_RAMSTAGE +#define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_IOSF, \ + REG_SCRIPT_SIZE_32, \ + reg_, mask_, value_, timeout_, unit_) +#define REG_IOSF_READ(unit_, reg_) \ + REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0) +#define REG_IOSF_WRITE(unit_, reg_, value_) \ + REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0) +#define REG_IOSF_RMW(unit_, reg_, mask_, value_) \ + REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0) +#define REG_IOSF_OR(unit_, reg_, value_) \ + REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_) +#define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \ + REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) +#endif /* ENV_RAMSTAGE */ + +#endif /* _BRASWELL_IOSF_H_ */ diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index 34b3f7d..5a781ac 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_IRQ_H_ -#define _BAYTRAIL_IRQ_H_ +#ifndef _BRASWELL_IRQ_H_ +#define _BRASWELL_IRQ_H_ #define PIRQA_APIC_IRQ 16 #define PIRQB_APIC_IRQ 17 @@ -28,6 +29,7 @@ #define PIRQF_APIC_IRQ 21 #define PIRQG_APIC_IRQ 22 #define PIRQH_APIC_IRQ 23 + /* The below IRQs are for when devices are in ACPI mode. Active low. */ #define LPE_DMA0_IRQ 24 #define LPE_DMA1_IRQ 25 @@ -47,50 +49,101 @@ #define LPSS_SPI_IRQ 41 #define LPSS_DMA1_IRQ 42 #define LPSS_DMA2_IRQ 43 -#define SCC_EMMC_IRQ 44 +#define SCC_EMMC_IRQ 45 #define SCC_SDIO_IRQ 46 -#define SCC_SD_IRQ 47 -#define GPIO_NC_IRQ 48 -#define GPIO_SC_IRQ 49 -#define GPIO_SUS_IRQ 50 +#define SCC_SD_IRQ 47 + +#define GPIO_N_IRQ 48 +#define GPIO_SW_IRQ 49 +#define GPIO_E_IRQ 50 + /* GPIO direct / dedicated IRQs. */ -#define GPIO_S0_DED_IRQ_0 51 -#define GPIO_S0_DED_IRQ_1 52 -#define GPIO_S0_DED_IRQ_2 53 -#define GPIO_S0_DED_IRQ_3 54 -#define GPIO_S0_DED_IRQ_4 55 -#define GPIO_S0_DED_IRQ_5 56 -#define GPIO_S0_DED_IRQ_6 57 -#define GPIO_S0_DED_IRQ_7 58 -#define GPIO_S0_DED_IRQ_8 59 -#define GPIO_S0_DED_IRQ_9 60 -#define GPIO_S0_DED_IRQ_10 61 -#define GPIO_S0_DED_IRQ_11 62 -#define GPIO_S0_DED_IRQ_12 63 -#define GPIO_S0_DED_IRQ_13 64 -#define GPIO_S0_DED_IRQ_14 65 -#define GPIO_S0_DED_IRQ_15 66 -#define GPIO_S5_DED_IRQ_0 67 -#define GPIO_S5_DED_IRQ_1 68 -#define GPIO_S5_DED_IRQ_2 69 -#define GPIO_S5_DED_IRQ_3 70 -#define GPIO_S5_DED_IRQ_4 71 -#define GPIO_S5_DED_IRQ_5 72 -#define GPIO_S5_DED_IRQ_6 73 -#define GPIO_S5_DED_IRQ_7 74 -#define GPIO_S5_DED_IRQ_8 75 -#define GPIO_S5_DED_IRQ_9 76 -#define GPIO_S5_DED_IRQ_10 77 -#define GPIO_S5_DED_IRQ_11 78 -#define GPIO_S5_DED_IRQ_12 79 -#define GPIO_S5_DED_IRQ_13 80 -#define GPIO_S5_DED_IRQ_14 81 -#define GPIO_S5_DED_IRQ_15 82 + +/* NORTH COMMUNITY */ +#define GPIO_N_DED_IRQ_0 51 +#define GPIO_N_DED_IRQ_1 52 +#define GPIO_N_DED_IRQ_2 53 +#define GPIO_N_DED_IRQ_3 54 +#define GPIO_N_DED_IRQ_4 55 +#define GPIO_N_DED_IRQ_5 56 +#define GPIO_N_DED_IRQ_6 57 +#define GPIO_N_DED_IRQ_7 58 + +/* SOUTH WEST COMMUNITY */ +#define GPIO_SW_DED_IRQ_0 59 +#define GPIO_SW_DED_IRQ_1 60 +#define GPIO_SW_DED_IRQ_2 61 +#define GPIO_SW_DED_IRQ_3 62 +#define GPIO_SW_DED_IRQ_4 63 +#define GPIO_SW_DED_IRQ_5 64 +#define GPIO_SW_DED_IRQ_6 65 +#define GPIO_SW_DED_IRQ_7 66 + +/* EAST COMMUNITY */ +#define GPIO_E_DED_IRQ_0 67 +#define GPIO_E_DED_IRQ_1 68 +#define GPIO_E_DED_IRQ_2 69 +#define GPIO_E_DED_IRQ_3 70 +#define GPIO_E_DED_IRQ_4 71 +#define GPIO_E_DED_IRQ_5 72 +#define GPIO_E_DED_IRQ_6 73 +#define GPIO_E_DED_IRQ_7 74 +#define GPIO_E_DED_IRQ_8 75 +#define GPIO_E_DED_IRQ_9 76 +#define GPIO_E_DED_IRQ_10 77 +#define GPIO_E_DED_IRQ_11 78 +#define GPIO_E_DED_IRQ_12 79 +#define GPIO_E_DED_IRQ_13 80 +#define GPIO_E_DED_IRQ_14 81 +#define GPIO_E_DED_IRQ_15 82 + +/* More IRQ */ +#define LPSS_SPI2_IRQ 89 +#define LPSS_SPI3_IRQ 90 +#define GPIO_SE_IRQ 91 + +/* GPIO direct / dedicated IRQs. */ +/* SOUTH EAST COMMUNITY */ +#define GPIO_SE_DED_IRQ_0 92 +#define GPIO_SE_DED_IRQ_1 93 +#define GPIO_SE_DED_IRQ_2 94 +#define GPIO_SE_DED_IRQ_3 95 +#define GPIO_SE_DED_IRQ_4 96 +#define GPIO_SE_DED_IRQ_5 97 +#define GPIO_SE_DED_IRQ_6 98 +#define GPIO_SE_DED_IRQ_7 99 +#define GPIO_SE_DED_IRQ_8 100 +#define GPIO_SE_DED_IRQ_9 101 +#define GPIO_SE_DED_IRQ_10 102 +#define GPIO_SE_DED_IRQ_11 103 +#define GPIO_SE_DED_IRQ_12 104 +#define GPIO_SE_DED_IRQ_13 105 +#define GPIO_SE_DED_IRQ_14 106 +#define GPIO_SE_DED_IRQ_15 107 + +/* OTHER IRQs */ +#define GPIO_VIRTUAL 108 +#define LPE_DMA2 109 +#define LPE_SSP3 110 +#define LPE_SSP4 111 +#define LPE_SSP5 112 + /* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ -#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot -#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot -#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) -#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) +#define _GPIO_N_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot +#define _GPIO_SW_DED_IRQ(slot) GPIO_SW_DED_IRQ_##slot +#define _GPIO_E_DED_IRQ(slot) GPIO_E_DED_IRQ_##slot +#define _GPIO_SE_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot +#define GPIO_N_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot) +#define GPIO_SW_DED_IRQ(slot) _GPIO_SW_DED_IRQ(slot) +#define GPIO_E_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot) +#define GPIO_SE_DED_IRQ(slot) _GPIO_SE_DED_IRQ(slot) + +/* TODO NEED TO UPDATE THESE IN onboard.h */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_N_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_SE_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_N_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_E_DED_IRQ(slot) + /* PIC IRQ settings. */ #define PIRQ_PIC_IRQDISABLE 0x0 @@ -127,9 +180,11 @@ # define SCIS_IRQ22 0x06 # define SCIS_IRQ23 0x07 -/* In each mainboard directory there should exist a header file irqroute.h that +/* + * In each mainbaord directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which - * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. + */ #if !defined(__ASSEMBLER__) && !defined(__ACPI__) #include <stdint.h> @@ -137,28 +192,29 @@ #define NUM_IR_DEVS 32 #define NUM_PIRQS 8 -struct baytrail_irq_route { +struct braswell_irq_route { /* Per device configuration. */ uint16_t pcidev[NUM_IR_DEVS]; /* Route path for each internal PIRQx in PIC mode. */ uint8_t pic[NUM_PIRQS]; }; -extern const struct baytrail_irq_route global_baytrail_irq_route; +extern const struct braswell_irq_route global_braswell_irq_route; #define DEFINE_IRQ_ROUTES \ - const struct baytrail_irq_route global_baytrail_irq_route = { \ + const struct braswell_irq_route global_braswell_irq_route = { \ .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ .pic = { PIRQ_PIC_ROUTES, }, \ } +/* The following macros are used for ACPI by the ASL compiler */ #define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ - [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ - ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + [dev_] = (((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0)) #define PIRQ_PIC(pirq_, pic_irq_) \ [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ #endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ -#endif /* _BAYTRAIL_IRQ_H_ */ +#endif /* _BRASWELL_IRQ_H_ */ diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h index 2f6256c..c319804 100644 --- a/src/soc/intel/braswell/include/soc/lpc.h +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_LPC_H_ -#define _BAYTRAIL_LPC_H_ +#ifndef _BRASWELL_LPC_H_ +#define _BRASWELL_LPC_H_ /* PCI config registers in LPC bridge. */ #define REVID 0x08 @@ -37,7 +38,7 @@ #define RID_A_STEPPING_START 1 #define RID_B_STEPPING_START 5 #define RID_C_STEPPING_START 0xe -enum baytrail_stepping { +enum braswell_stepping { STEP_A0, STEP_A1, STEP_B0, @@ -51,4 +52,4 @@ enum baytrail_stepping { #define GCS 0x00 # define BILD (1 << 0) -#endif /* _BAYTRAIL_LPC_H_ */ +#endif /* _BRASWELL_LPC_H_ */ diff --git a/src/soc/intel/braswell/include/soc/mrc_wrapper.h b/src/soc/intel/braswell/include/soc/mrc_wrapper.h deleted file mode 100644 index 355dce0..0000000 --- a/src/soc/intel/braswell/include/soc/mrc_wrapper.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * MRC wrapper definitions - * - * Copyright 2013 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _MRC_WRAPPER_H_ -#define _MRC_WRAPPER_H_ - -#define MRC_PARAMS_VER 5 - -#define NUM_CHANNELS 2 - -/* Provide generic x86 calling conventions. */ -#define ABI_X86 __attribute((regparm(0))) - -enum { - DRAM_INFO_SPD_SMBUS, /* Use the typical SPD smbus access. */ - DRAM_INFO_SPD_MEM, /* SPD info in memory. */ - DRAM_INFO_DETAILED, /* Timing info not in SPD format. */ -}; - -enum dram_type { - DRAM_DDR3, - DRAM_DDR3L, - DRAM_LPDDR3, -}; - -/* Errors returned by the MRC wrapper. */ -enum mrc_wrapper_error { - INVALID_VER = -1, - INVALID_DRAM_TYPE = -2, - INVALID_SLEEP_MODE = -3, - PLATFORM_SETTINGS_FAIL = -4, - DIMM_DETECTION_FAILURE = -5, - MEMORY_CONFIG_FAILURE = -6, - INVALID_CPU_ODT_SETTING = -7, - INVALID_DRAM_ODT_SETTING = -8, -}; - -struct mrc_mainboard_params { - int dram_type; - int dram_info_location; /* DRAM_INFO_* */ - int dram_is_slotted; /* mobo has DRAM slots. */ - /* - * The below ODT settings are only honored when !dram_is_slotted. - * Additionally, weaker_odt_settings being non-zero causes - * cpu_odt_value to not be honored as weaker_odt_settings have a - * special training path. - */ - int weaker_odt_settings; - /* Allowed settings: 60, 80, 100, 120, and 150. */ - int cpu_odt_value; - /* Allowed settings: 60 and 120. */ - int dram_odt_value; - int spd_addrs[NUM_CHANNELS]; - void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */ -} __attribute__((packed)); - -struct mrc_params { - /* Mainboard Inputs */ - int version; - - struct mrc_mainboard_params mainboard; - - void ABI_X86 (*console_out)(unsigned char byte); - - int prev_sleep_state; - - int saved_data_size; - const void *saved_data; - - int txe_size_mb; /* TXE memory size in megabytes. */ - int rmt_enabled; /* Enable RMT training + prints. */ - int io_hole_mb; /* Size of IO hole in MiB. */ - - /* Outputs */ - void *txe_base_address; - int data_to_save_size; - void *data_to_save; -} __attribute__((packed)); - -/* Call into wrapper. */ -typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *); - -#endif /* _MRC_WRAPPER_H_ */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 47b9543..97692fb 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,17 +18,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_MSR_H_ -#define _BAYTRAIL_MSR_H_ +#ifndef _BRASWELL_MSR_H_ +#define _BRASWELL_MSR_H_ #define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -#define SINGLE_PCTL (1 << 11) +#define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 -#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) -#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc @@ -45,7 +47,6 @@ #define MSR_CPU_THERM_CFG2 0x674 #define MSR_CPU_THERM_SENS_CFG 0x675 -/* Read BCLK from MSR */ -unsigned bus_freq_khz(void); +#define BUS_FREQ_KHZ 100000 /* 100 MHz */ -#endif /* _BAYTRAIL_MSR_H_ */ +#endif /* _BRASWELL_MSR_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h index 1ba30d5..861fd53 100644 --- a/src/soc/intel/braswell/include/soc/nvs.h +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 Google Inc + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_NVS_H_ -#define _BAYTRAIL_NVS_H_ +#ifndef _BRASWELL_NVS_H_ +#define _BRASWELL_NVS_H_ #include <vendorcode/google/chromeos/gnvs.h> #include <soc/device_nvs.h> @@ -39,7 +40,7 @@ typedef struct { u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ u8 lids; /* 0x0f - LID state (open = 1) */ u8 pwrs; /* 0x10 - Power state (AC = 1) */ - u8 pcnt; /* 0x11 - Processor Count */ + u8 pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ @@ -58,15 +59,15 @@ typedef struct { u8 rsvd2[8]; /* Base Addresses */ - u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ + u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ u8 rsvd3[196]; - /* ChromeOS specific (0x100-0xfff)*/ + /* ChromeOS specific (0x100-0xfff) */ chromeos_acpi_t chromeos; - /* Baytrail LPSS (0x1000) */ + /* LPSS (0x1000) */ device_nvs_t dev; } __attribute__((packed)) global_nvs_t; @@ -75,4 +76,4 @@ typedef struct { global_nvs_t *smm_get_gnvs(void); #endif -#endif /* _BAYTRAIL_NVS_H_ */ +#endif /* _BRASWELL_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h index 81df73e..64d11a3 100644 --- a/src/soc/intel/braswell/include/soc/pattrs.h +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _PATTRS_H_ -#define _PATTRS_H_ +#ifndef _BRASWELL_PATTRS_H_ +#define _BRASWELL_PATTRS_H_ #include <stdint.h> #include <cpu/x86/msr.h> @@ -31,7 +32,8 @@ enum { IACORE_END }; -/* The pattrs structure is a common place to stash pertinent information +/* + * The pattrs structure is a common place to stash pertinent information * about the processor or platform. Instead of going to the source (msrs, cpuid) * every time an attribute is needed use the pattrs structure. */ @@ -49,16 +51,14 @@ struct pattrs { unsigned bclk_khz; }; -/* This is just to hide the abstraction w/o relying on how the underlying - * storage is allocated. */ -#define PATTRS_GLOB_NAME __global_pattrs -#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME -extern DEFINE_PATTRS; - +/* + * This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. + */ +extern struct pattrs __global_pattrs; static inline const struct pattrs *pattrs_get(void) { - return &PATTRS_GLOB_NAME; + return &__global_pattrs; } - -#endif /* _PATTRS_H_ */ +#endif /* _BRASWELL_PATTRS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h index b3fdce2..ff6582e 100644 --- a/src/soc/intel/braswell/include/soc/pci_devs.h +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,139 +18,137 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_PCI_DEVS_H_ -#define _BAYTRAIL_PCI_DEVS_H_ +#ifndef _BRASWELL_PCI_DEVS_H_ +#define _BRASWELL_PCI_DEVS_H_ /* All these devices live on bus 0 with the associated device and function */ /* SoC transaction router */ #define SOC_DEV 0x0 #define SOC_FUNC 0 -# define SOC_DEVID 0x0f00 +# define SOC_DEVID 0x2280 /* Graphics and Display */ #define GFX_DEV 0x2 #define GFX_FUNC 0 -# define GFX_DEVID 0x0f31 +# define GFX_DEVID 0x22b1 + +/* MMC Port */ +#define MMC_DEV 0x10 +#define MMC_FUNC 0 +# define MMC_DEVID 0x2294 /* SDIO Port */ #define SDIO_DEV 0x11 #define SDIO_FUNC 0 -# define SDIO_DEVID 0x0f15 +# define SDIO_DEVID 0x2295 /* SD Port */ #define SD_DEV 0x12 #define SD_FUNC 0 -# define SD_DEVID 0x0f16 +# define SD_DEVID 0x2296 /* SATA */ #define SATA_DEV 0x13 #define SATA_FUNC 0 -#define IDE1_DEVID 0x0f20 -#define IDE2_DEVID 0x0f21 -#define AHCI1_DEVID 0x0f22 -#define AHCI2_DEVID 0x0f23 +#define AHCI1_DEVID 0x22a3 /* xHCI */ #define XHCI_DEV 0x14 #define XHCI_FUNC 0 -# define XHCI_DEVID 0x0f35 +#define XHCI_DEVID 0x22b5 /* LPE Audio */ #define LPE_DEV 0x15 #define LPE_FUNC 0 -# define LPE_DEVID 0x0f28 - -/* MMC Port */ -#define MMC_DEV 0x17 -#define MMC_FUNC 0 -# define MMC_DEVID 0x0f50 +# define LPE_DEVID 0x22a8 /* Serial IO 1 */ #define SIO1_DEV 0x18 # define SIO_DMA1_DEV SIO1_DEV # define SIO_DMA1_FUNC 0 -# define SIO_DMA1_DEVID 0x0f40 +# define SIO_DMA1_DEVID 0x22c0 # define I2C1_DEV SIO1_DEV # define I2C1_FUNC 1 -# define I2C1_DEVID 0x0f41 +# define I2C1_DEVID 0x22c1 # define I2C2_DEV SIO1_DEV # define I2C2_FUNC 2 -# define I2C2_DEVID 0x0f42 +# define I2C2_DEVID 0x22c2 # define I2C3_DEV SIO1_DEV # define I2C3_FUNC 3 -# define I2C3_DEVID 0x0f43 +# define I2C3_DEVID 0x22c3 # define I2C4_DEV SIO1_DEV # define I2C4_FUNC 4 -# define I2C4_DEVID 0x0f44 +# define I2C4_DEVID 0x22c4 # define I2C5_DEV SIO1_DEV # define I2C5_FUNC 5 -# define I2C5_DEVID 0x0f45 +# define I2C5_DEVID 0x22c5 # define I2C6_DEV SIO1_DEV # define I2C6_FUNC 6 -# define I2C6_DEVID 0x0f46 +# define I2C6_DEVID 0x22c6 # define I2C7_DEV SIO1_DEV # define I2C7_FUNC 7 -# define I2C7_DEVID 0x0f47 +# define I2C7_DEVID 0x22c7 /* Trusted Execution Engine */ #define TXE_DEV 0x1a #define TXE_FUNC 0 -# define TXE_DEVID 0x0f18 +# define TXE_DEVID 0x2298 /* HD Audio */ #define HDA_DEV 0x1b #define HDA_FUNC 0 -# define HDA_DEVID 0x0f04 +# define HDA_DEVID 0x2284 /* PCIe Ports */ #define PCIE_DEV 0x1c # define PCIE_PORT1_DEV PCIE_DEV # define PCIE_PORT1_FUNC 0 -# define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT1_DEVID 0x22c8 # define PCIE_PORT2_DEV PCIE_DEV # define PCIE_PORT2_FUNC 1 -# define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT2_DEVID 0x22ca # define PCIE_PORT3_DEV PCIE_DEV # define PCIE_PORT3_FUNC 2 -# define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT3_DEVID 0x22cc # define PCIE_PORT4_DEV PCIE_DEV # define PCIE_PORT4_FUNC 3 -# define PCIE_PORT4_DEVID 0x0f4e - -/* EHCI */ -#define EHCI_DEV 0x1d -#define EHCI_FUNC 0 -# define EHCI_DEVID 0x0f34 +# define PCIE_PORT4_DEVID 0x22ce +/* Total number of ROOT PORTS */ +#define MAX_ROOT_PORTS_BSW 4 /* Serial IO 2 */ #define SIO2_DEV 0x1e # define SIO_DMA2_DEV SIO2_DEV # define SIO_DMA2_FUNC 0 -# define SIO_DMA2_DEVID 0x0f06 +# define SIO_DMA2_DEVID 0x2286 # define PWM1_DEV SIO2_DEV # define PWM1_FUNC 1 -# define PWM1_DEVID 0x0f08 +# define PWM1_DEVID 0x2288 # define PWM2_DEV SIO2_DEV # define PWM2_FUNC 2 -# define PWM2_DEVID 0x0f09 +# define PWM2_DEVID 0x2289 # define HSUART1_DEV SIO2_DEV # define HSUART1_FUNC 3 -# define HSUART1_DEVID 0x0f0a +# define HSUART1_DEVID 0x228a # define HSUART2_DEV SIO2_DEV # define HSUART2_FUNC 4 -# define HSUART2_DEVID 0x0f0c +# define HSUART2_DEVID 0x228c # define SPI_DEV SIO2_DEV # define SPI_FUNC 5 -# define SPI_DEVID 0xf0e +# define SPI_DEVID 0x228e /* Platform Controller Unit */ #define PCU_DEV 0x1f # define LPC_DEV PCU_DEV # define LPC_FUNC 0 -# define LPC_DEVID 0x0f1c +# define LPC_DEVID 0x229c # define SMBUS_DEV PCU_DEV # define SMBUS_FUNC 3 # define SMBUS_DEVID 0x0f12 -#endif /* _BAYTRAIL_PCI_DEVS_H_ */ +/* PCH SCC Device Modes */ +#define PCH_DISABLED 0 +#define PCH_PCI_MODE 1 +#define PCH_ACPI_MODE 2 +#endif /* _BRASWELL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h index 92ca3c8..b67bc5d 100644 --- a/src/soc/intel/braswell/include/soc/pcie.h +++ b/src/soc/intel/braswell/include/soc/pcie.h @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_PCIE_H_ -#define _BAYTRAIL_PCIE_H_ +#ifndef _BRASWELL_PCIE_H_ +#define _BRASWELL_PCIE_H_ /* PCIe root port config space registers. */ #define XCAP 0x40 @@ -98,5 +99,5 @@ #define PHYCTL4 0x408 # define SQDIS (1 << 27) -#define PCIE_ROOT_PORT_COUNT 4 -#endif /* _BAYTRAIL_PCIE_H_ */ + +#endif /* _BRASWELL_PCIE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pei_data.h b/src/soc/intel/braswell/include/soc/pei_data.h new file mode 100644 index 0000000..ab3f085 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pei_data.h @@ -0,0 +1,68 @@ +/* + * Broadwell UEFI PEI wrapper + * + * Copyright (C) 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PEI_DATA_H_ +#define _PEI_DATA_H_ + +#include <types.h> + +#define PEI_VERSION 22 + +#define ABI_X86 __attribute__((regparm(0))) + +typedef void ABI_X86(*tx_byte_func)(unsigned char byte); + +struct pei_data { + /* Chip settings */ + void *spd_data_ch0; + void *spd_data_ch1; +#if IS_ENABLED(CONFIG_GOP_SUPPORT) + void *vbt_data; +#endif + uint8_t spd_ch0_config; + uint8_t spd_ch1_config; + uint8_t sdcard_mode; + uint8_t emmc_mode; + uint8_t enable_azalia; + + /* System state information */ + int boot_mode; + + /* Fast boot and S3 resume MRC data */ + int saved_data_size; + const void *saved_data; + int disable_saved_data; + + /* New save data from MRC */ + int data_to_save_size; + void *data_to_save; +}; + +typedef struct pei_data PEI_DATA; + +#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pei_wrapper.h b/src/soc/intel/braswell/include/soc/pei_wrapper.h new file mode 100644 index 0000000..1455b95 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pei_wrapper.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BROADWELL_PEI_WRAPPER_H_ +#define _BROADWELL_PEI_WRAPPER_H_ + +#include <soc/pei_data.h> + +typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data); + +void broadwell_fill_pei_data(struct pei_data *pei_data); +void mainboard_fill_pei_data(struct pei_data *pei_data); + +#endif diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h new file mode 100644 index 0000000..744a495 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -0,0 +1,267 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BRASWELL_PM_H_ +#define _BRASWELL_PM_H_ + + +#define IOCOM1 0x3f8 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x00 +# define PMC_WDT_STS (1 << 15) +# define SEC_GBLRST_STS (1 << 7) +# define SEC_WDT_STS (1 << 6) +# define WOL_OVR_WK_STS (1 << 5) +# define PMC_WAKE_STS (1 << 4) +#define PMC_CFG 0x08 +# define SPS (1 << 5) +# define NO_REBOOT (1 << 4) +# define SX_ENT_TO_EN (1 << 3) +# define TIMING_T581_SHIFT (0) +# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) +# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) +# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) +# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) +# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) +#define VLV_PM_STS 0x0c +# define PMC_MSG_FULL_STS (1 << 24) +# define PMC_MSG_4_FULL_STS (1 << 23) +# define PMC_MSG_3_FULL_STS (1 << 22) +# define PMC_MSG_2_FULL_STS (1 << 21) +# define PMC_MSG_1_FULL_STS (1 << 20) +# define CODE_REQ (1 << 8) +# define HPR_ENT_TO (1 << 2) +# define SX_ENT_TO (1 << 1) +#define GEN_PMCON1 0x20 +# define UART_EN (1 << 24) +# define DISB (1 << 23) +# define MEM_SR (1 << 21) +# define SRS (1 << 20) +# define CTS (1 << 19) +# define MS4V (1 << 18) +# define PWR_FLR (1 << 16) +# define PME_B0_S5_DIS (1 << 15) +# define SUS_PWR_FLR (1 << 14) +# define WOL_EN_OVRD (1 << 13) +# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +# define GEN_RST_STS (1 << 9) +# define RPS (1 << 2) +# define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +# define SLPSX_STR_POL_LOCK (1 << 18) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) +#define GPIO_ROUT 0x58 +# define ROUTE_MASK 3 +# define ROUTE_NONE 0 +# define ROUTE_SMI 1 +# define ROUTE_SCI 2 +#define PLT_CLK_CTL_0 0x60 +#define PLT_CLK_CTL_1 0x64 +#define PLT_CLK_CTL_2 0x68 +#define PLT_CLK_CTL_3 0x6c +#define PLT_CLK_CTL_4 0x70 +#define PLT_CLK_CTL_5 0x74 +# define CLK_FREQ_25MHZ (0x0 << 2) +# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_CTL_D3_LPE (0x0 << 0) +# define CLK_CTL_ON (0x1 << 0) +# define CLK_CTL_OFF (0x2 << 0) +#define PME_STS 0xc0 +#define GPE_LEVEL_EDGE 0xc4 +# define GPE_EDGE 0 +# define GPE_LEVEL 1 +#define GPE_POLARITY 0xc8 +# define GPE_ACTIVE_HIGH 1 +# define GPE_ACTIVE_LOW 0 +#define LOCK 0xcc + +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define USB_STS (1 << 13) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define GPE0_EN 0x28 +#define SUS_GPIO_EN7_BIT 23 +#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) +#define SUS_GPIO_EN6_BIT 22 +#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) +#define SUS_GPIO_EN5_BIT 21 +#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) +#define SUS_GPIO_EN4_BIT 20 +#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) +#define SUS_GPIO_EN3_BIT 19 +#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) +#define SUS_GPIO_EN2_BIT 18 +#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) +#define SUS_GPIO_EN1_BIT 17 +#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) +#define SUS_GPIO_EN0_BIT 16 +#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) +#define SUS_GPIO_STS0 (1 << 16) +#define PCIE_WAKE3_STS (1 << 8) +#define PCIE_WAKE2_STS (1 << 7) +#define PCIE_WAKE1_STS (1 << 6) +#define PCIE_WAKE0_STS (1 << 3) +#define PCI_EXP_STS (1 << 9) +#define PME_B0_EN (1 << 13) +#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT +#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */ +#define USB_EN (1 << 17) /* Legacy USB2 SMI logic */ +#define PERIODIC_EN (1 << 14) /* SMI on PERIODIC_STS in SMI_STS */ +#define TCO_EN (1 << 13) /* Enable TCO Logic (BIOSWE et al) */ +#define BIOS_RLS (1 << 7) /* asserts SCI on bit set */ +#define SWSMI_TMR_EN (1 << 6) /* start software smi timer on bit set */ +#define APMC_EN (1 << 5) /* Writes to APM_CNT cause SMI# */ +#define SLP_SMI_EN (1 << 4) /* Write to SLP_EN in PM1_CNT asserts SMI# */ +#define BIOS_EN (1 << 2) /* Assert SMI# on setting GBL_RLS bit */ +#define EOS (1 << 1) /* End of SMI (deassert SMI#) */ +#define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */ +#define SMI_STS 0x34 +#define ALT_GPIO_SMI 0x38 +#define UPRWC 0x3c +# define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ +#define GPE_CTRL 0x40 +#define PM2A_CNT_BLK 0x50 +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +# define SECOND_TO_STS (1 << 17) +# define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +# define TCO_LOCK (1 << 12) +# define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; + int prev_sleep_state; +} __attribute__((packed)); + +/* Power Management Utility Functions. */ +uint16_t get_pmbase(void); +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); + +#if IS_ENABLED(CONFIG_ELOG) +void southcluster_log_state(void); +#else +static inline void southcluster_log_state(void) {} +#endif + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BRASWELL_PM_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pmc.h b/src/soc/intel/braswell/include/soc/pmc.h deleted file mode 100644 index 1af7ab8..0000000 --- a/src/soc/intel/braswell/include/soc/pmc.h +++ /dev/null @@ -1,303 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _BAYTRAIL_PMC_H_ -#define _BAYTRAIL_PMC_H_ - - -#define IOCOM1 0x3f8 - -/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ -#define PRSTS 0x00 -# define PMC_WDT_STS (1 << 15) -# define SEC_GBLRST_STS (1 << 7) -# define SEC_WDT_STS (1 << 6) -# define WOL_OVR_WK_STS (1 << 5) -# define PMC_WAKE_STS (1 << 4) -#define PMC_CFG 0x08 -# define SPS (1 << 5) -# define NO_REBOOT (1 << 4) -# define SX_ENT_TO_EN (1 << 3) -# define TIMING_T581_SHIFT (0) -# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) -# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) -# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) -# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) -# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) -#define VLV_PM_STS 0x0c -# define PMC_MSG_FULL_STS (1 << 24) -# define PMC_MSG_4_FULL_STS (1 << 23) -# define PMC_MSG_3_FULL_STS (1 << 22) -# define PMC_MSG_2_FULL_STS (1 << 21) -# define PMC_MSG_1_FULL_STS (1 << 20) -# define CODE_REQ (1 << 8) -# define HPR_ENT_TO (1 << 2) -# define SX_ENT_TO (1 << 1) -#define GEN_PMCON1 0x20 -# define UART_EN (1 << 24) -# define DISB (1 << 23) -# define MEM_SR (1 << 21) -# define SRS (1 << 20) -# define CTS (1 << 19) -# define MS4V (1 << 18) -# define PWR_FLR (1 << 16) -# define PME_B0_S5_DIS (1 << 15) -# define SUS_PWR_FLR (1 << 14) -# define WOL_EN_OVRD (1 << 13) -# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) -# define GEN_RST_STS (1 << 9) -# define RPS (1 << 2) -# define AFTERG3_EN (1 << 0) -#define GEN_PMCON2 0x24 -# define SLPSX_STR_POL_LOCK (1 << 18) -# define BIOS_PCI_EXP_EN (1 << 10) -# define PWRBTN_LVL (1 << 9) -# define SMI_LOCK (1 << 4) -#define ETR 0x48 -# define CF9LOCK (1 << 31) -# define LTR_DEF (1 << 22) -# define IGNORE_HPET (1 << 21) -# define CF9GR (1 << 20) -# define CWORWRE (1 << 18) -#define FUNC_DIS 0x34 -# define SIO_DMA2_DIS (1 << 0) -# define PWM1_DIS (1 << 1) -# define PWM2_DIS (1 << 2) -# define HSUART1_DIS (1 << 3) -# define HSUART2_DIS (1 << 4) -# define SPI_DIS (1 << 5) -# define SDIO_DIS (1 << 9) -# define SD_DIS (1 << 10) -# define MMC_DIS (1 << 11) -# define HDA_DIS (1 << 12) -# define LPE_DIS (1 << 13) -# define OTG_DIS (1 << 14) -# define XHCI_DIS (1 << 15) -# define SATA_DIS (1 << 17) -# define EHCI_DIS (1 << 18) -# define TXE_DIS (1 << 19) -# define PCIE_PORT1_DIS (1 << 20) -# define PCIE_PORT2_DIS (1 << 21) -# define PCIE_PORT3_DIS (1 << 22) -# define PCIE_PORT4_DIS (1 << 23) -# define SIO_DMA1_DIS (1 << 24) -# define I2C1_DIS (1 << 25) -# define I2C2_DIS (1 << 26) -# define I2C3_DIS (1 << 27) -# define I2C4_DIS (1 << 28) -# define I2C5_DIS (1 << 29) -# define I2C6_DIS (1 << 30) -# define I2C7_DIS (1 << 31) -#define FUNC_DIS2 0x38 -# define USH_SS_PHY_DIS (1 << 2) -# define OTG_SS_PHY_DIS (1 << 1) -# define SMBUS_DIS (1 << 0) -#define GPIO_ROUT 0x58 -# define ROUTE_MASK 3 -# define ROUTE_NONE 0 -# define ROUTE_SMI 1 -# define ROUTE_SCI 2 -#define PLT_CLK_CTL_0 0x60 -#define PLT_CLK_CTL_1 0x64 -#define PLT_CLK_CTL_2 0x68 -#define PLT_CLK_CTL_3 0x6c -#define PLT_CLK_CTL_4 0x70 -#define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) -# define CLK_CTL_D3_LPE (0x0 << 0) -# define CLK_CTL_ON (0x1 << 0) -# define CLK_CTL_OFF (0x2 << 0) -#define PME_STS 0xc0 -#define GPE_LEVEL_EDGE 0xc4 -# define GPE_EDGE 0 -# define GPE_LEVEL 1 -#define GPE_POLARITY 0xc8 -# define GPE_ACTIVE_HIGH 1 -# define GPE_ACTIVE_LOW 0 -#define LOCK 0xcc - -/* IO Mapped registers behind ACPI_BASE_ADDRESS */ -#define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define USB_STS (1 << 13) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define TMROF_STS (1 << 0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define USB_WAKE_EN (1 << 13) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) -#define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP_SHIFT 10 -#define SLP_TYP (7 << SLP_TYP_SHIFT) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) -#define PM1_TMR 0x08 -#define GPE0_STS 0x20 -#define CORE_GPIO_STS7 (1 << 31) -#define CORE_GPIO_STS6 (1 << 30) -#define CORE_GPIO_STS5 (1 << 29) -#define CORE_GPIO_STS4 (1 << 28) -#define CORE_GPIO_STS3 (1 << 27) -#define CORE_GPIO_STS2 (1 << 26) -#define CORE_GPIO_STS1 (1 << 25) -#define CORE_GPIO_STS0 (1 << 24) -#define SUS_GPIO_STS7 (1 << 23) -#define SUS_GPIO_STS6 (1 << 22) -#define SUS_GPIO_STS5 (1 << 21) -#define SUS_GPIO_STS4 (1 << 20) -#define SUS_GPIO_STS3 (1 << 19) -#define SUS_GPIO_STS2 (1 << 18) -#define SUS_GPIO_STS1 (1 << 17) -#define SUS_GPIO_STS0 (1 << 16) -#define PME_B0_STS (1 << 13) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define PCIE_WAKE3_STS (1 << 8) -#define PCIE_WAKE2_STS (1 << 7) -#define PCIE_WAKE1_STS (1 << 6) -#define GUNIT_SCI_STS (1 << 5) -#define PUNIT_SCI_STS (1 << 4) -#define PCIE_WAKE0_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define GPE0_EN 0x28 -#define CORE_GPIO_EN7 (1 << 31) -#define CORE_GPIO_EN6 (1 << 30) -#define CORE_GPIO_EN5 (1 << 29) -#define CORE_GPIO_EN4 (1 << 28) -#define CORE_GPIO_EN3 (1 << 27) -#define CORE_GPIO_EN2 (1 << 26) -#define CORE_GPIO_EN1 (1 << 25) -#define CORE_GPIO_EN0 (1 << 24) -#define SUS_GPIO_EN7_BIT 23 -#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) -#define SUS_GPIO_EN6_BIT 22 -#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) -#define SUS_GPIO_EN5_BIT 21 -#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) -#define SUS_GPIO_EN4_BIT 20 -#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) -#define SUS_GPIO_EN3_BIT 19 -#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) -#define SUS_GPIO_EN2_BIT 18 -#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) -#define SUS_GPIO_EN1_BIT 17 -#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) -#define SUS_GPIO_EN0_BIT 16 -#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) -#define PME_B0_EN (1 << 13) -#define BATLOW_EN (1 << 10) -#define PCI_EXP_EN (1 << 9) -#define PCIE_WAKE3_EN (1 << 8) -#define PCIE_WAKE2_EN (1 << 7) -#define PCIE_WAKE1_EN (1 << 6) -#define PCIE_WAKE0_EN (1 << 3) -#define SWGPE_EN (1 << 2) -#define HOT_PLUG_EN (1 << 1) -#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT -#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) -#define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define USB_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? -#define SMI_STS 0x34 -#define ALT_GPIO_SMI 0x38 -#define UPRWC 0x3c -# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable -#define GPE_CTRL 0x40 -#define PM2A_CNT_BLK 0x50 -#define TCO_RLD 0x60 -#define TCO_STS 0x64 -# define SECOND_TO_STS (1 << 17) -# define TCO_TIMEOUT (1 << 3) -#define TCO1_CNT 0x68 -# define TCO_LOCK (1 << 12) -# define TCO_TMR_HALT (1 << 11) -#define TCO_TMR 0x70 - -/* I/O ports */ -#define RST_CNT 0xcf9 -# define FULL_RST (1 << 3) -# define RST_CPU (1 << 2) -# define SYS_RST (1 << 1) - -#if !defined(__ASSEMBLER__) && !defined(__ACPI__) - -/* Track power state from reset to log events. */ -struct chipset_power_state { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t pm1_cnt; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint32_t tco_sts; - uint32_t prsts; - uint32_t gen_pmcon1; - uint32_t gen_pmcon2; -} __attribute__((packed)); - -/* Power Management Utility Functions. */ -uint16_t get_pmbase(void); -uint32_t clear_smi_status(void); -uint16_t clear_pm1_status(void); -uint32_t clear_tco_status(void); -uint32_t clear_gpe_status(void); -uint32_t clear_alt_status(void); -void clear_pmc_status(void); -void enable_smi(uint32_t mask); -void disable_smi(uint32_t mask); -void enable_pm1(uint16_t events); -void enable_pm1_control(uint32_t mask); -void disable_pm1_control(uint32_t mask); -void enable_gpe(uint32_t mask); -void disable_gpe(uint32_t mask); -void disable_all_gpe(void); - -#if CONFIG_ELOG -void southcluster_log_state(void); -#else -static inline void southcluster_log_state(void) {} -#endif - -#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ - -#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h index 0ed83bd..2926f18 100644 --- a/src/soc/intel/braswell/include/soc/ramstage.h +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,26 +18,22 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_RAMSTAGE_H_ -#define _BAYTRAIL_RAMSTAGE_H_ +#ifndef _BRASWELL_RAMSTAGE_H_ +#define _BRASWELL_RAMSTAGE_H_ #include <device/device.h> -#include <soc/intel/baytrail/chip.h> +#include <chip.h> -/* The baytrail_init_pre_device() function is called prior to device - * initialization, but it's after console and cbmem has been reinitialized. */ -void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); -void baytrail_init_cpus(device_t dev); +/* + * The braswell_init_pre_device() function is called prior to device + * initialization, but it's after console and cbmem has been reinitialized. + */ +void braswell_init_pre_device(struct soc_intel_braswell_config *config); +void braswell_init_cpus(device_t dev); void set_max_freq(void); void southcluster_enable_dev(device_t dev); -#if CONFIG_HAVE_REFCODE_BLOB -void baytrail_run_reference_code(void); -#else -static inline void baytrail_run_reference_code(void) {} -#endif -void baytrail_init_scc(void); void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; -#endif /* _BAYTRAIL_RAMSTAGE_H_ */ +#endif /* _BRASWELL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/reset.h b/src/soc/intel/braswell/include/soc/reset.h deleted file mode 100644 index dbf0fd2..0000000 --- a/src/soc/intel/braswell/include/soc/reset.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _BAYTRAIL_RESET_H_ -#define _BAYTRAIL_RESET_H_ -#include <reset.h> - -/* Bay Trail has the following types of resets: - * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 - * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 - * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 - * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 - * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but - * with ETR[20] set. - */ - -void cold_reset(void); -void warm_reset(void); - -#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index f99a8e2..68c7712 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,38 +18,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_ROMSTAGE_H_ -#define _BAYTRAIL_ROMSTAGE_H_ - -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif +#ifndef _BRASWELL_ROMSTAGE_H_ +#define _BRASWELL_ROMSTAGE_H_ #include <stdint.h> #include <arch/cpu.h> -#include <soc/mrc_wrapper.h> - -struct romstage_params { - unsigned long bist; - struct mrc_params *mrc_params; -}; +#include <fsp_util.h> +#include <soc/pei_data.h> +#include <soc/pm.h> +#include <soc/intel/common/romstage.h> -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); -void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, - uint32_t tsc_high); -void asmlinkage romstage_after_car(void); -void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); void punit_init(void); -void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); +void mainboard_fill_spd_data(struct pei_data *pei_data); -#if CONFIG_ENABLE_BUILTIN_COM1 -void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif +/* romstage_common.c functions */ +void program_base_addresses(void); +void migrate_power_state(void); +struct chipset_power_state *fill_power_state(void); +int chipset_prev_sleep_state(struct chipset_power_state *ps); -#endif /* _BAYTRAIL_ROMSTAGE_H_ */ +#endif /* _BRASWELL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/sata.h b/src/soc/intel/braswell/include/soc/sata.h index 7704c18..96cd42c 100644 --- a/src/soc/intel/braswell/include/soc/sata.h +++ b/src/soc/intel/braswell/include/soc/sata.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,10 +18,138 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef BAYTRAIL_SATA_H -#define BAYTRAIL_SATA_H +#ifndef _BRASWELL_SATA_H_ +#define _BRASWELL_SATA_H_ + +#define SATA_PORT_SUPPORT 0x03 +#define SATA_PORT_MASK 0x3f + +/* PCI Configuration Space */ +#define SATA_PID 0x70 +#define SATA_PID_NEXT 0xff00 +#define SATA_PID_CID 0xff + +#define SATA_MAP 0x90 +#define SATA_MAP_SPD3 (1 << 11) +#define SATA_MAP_SPD2 (1 << 10) +#define SATA_MAP_SPD1 (1 << 9) +#define SATA_MAP_SPD0 (1 << 8) +#define SATA_MAP_SPD_MASK (SATA_MAP_SPD0 | SATA_MAP_SPD1 \ + | SATA_MAP_SPD2 | SATA_MAP_SPD3) +#define SATA_MAP_SMS_RAID 0x40 + +#define SATA_PCS 0x92 +#define SATA_PCS_ORM (1 << 15) +#define SATA_PCS_PORT5 (1 << 5) +#define SATA_PCS_PORT4 (1 << 4) +#define SATA_PCS_PORT3 (1 << 3) +#define SATA_PCS_PORT2 (1 << 2) +#define SATA_PCS_PORT1 (1 << 1) +#define SATA_PCS_PORT0 (1 << 0) +#define SATA_PCS_PORTS (SATA_PCS_PORT0 | SATA_PCS_PORT1 | SATA_PCS_PORT2 \ + | SATA_PCS_PORT3 | SATA_PCS_PORT4 | SATA_PCS_PORT5) + +#define SATA_TM 0x94 +#define SATA_TM_PCD5 (1 << 29) +#define SATA_TM_PCD4 (1 << 28) +#define SATA_TM_PCD3 (1 << 27) +#define SATA_TM_PCD2 (1 << 26) +#define SATA_TM_PCD1 (1 << 25) +#define SATA_TM_PCD0 (1 << 24) +#define SATA_TM_PCD_MASK (SATA_TM_PCD0 | SATA_TM_PCD1 | SATA_TM_PCD2 \ + | SATA_TM_PCD3 | SATA_TM_PCD4 | SATA_TM_PCD5) #define SATA_SIRI 0xa0 #define SATA_SIRD 0xa4 -#endif +/* Memory Mapped I/O Space */ +#define AHCI_GHC_CAP 0 +#define AHCI_GHC_CAP_S64A (1 << 31) +#define AHCI_GHC_CAP_SCQA (1 << 30) +#define AHCI_GHC_CAP_SSNTF (1 << 29) +#define AHCI_GHC_CAP_SMPS (1 << 28) +#define AHCI_GHC_CAP_SSS (1 << 27) +#define AHCI_GHC_CAP_SALP (1 << 26) +#define AHCI_GHC_CAP_SAL (1 << 25) +#define AHCI_GHC_CAP_SCLO (1 << 24) +#define AHCI_GHC_CAP_ISS 0x00f00000 +#define AHCI_GHC_CAP_ISS_GEN1 (1 << 20) +#define AHCI_GHC_CAP_ISS_GEN2 (2 << 20) +#define AHCI_GHC_CAP_ISS_GEN3 (3 << 20) +#define AHCI_GHC_CAP_SNZO (1 << 19) +#define AHCI_GHC_CAP_SAM (1 << 18) +#define AHCI_GHC_CAP_SMP (1 << 17) +#define AHCI_GHC_CAP_FBSS (1 << 16) +#define AHCI_GHC_CAP_PMD (1 << 15) +#define AHCI_GHC_CAP_SSC (1 << 14) +#define AHCI_GHC_CAP_PSC (1 << 13) +#define AHCI_GHC_CAP_NCS 0x00000f00 +#define AHCI_GHC_CAP_CCCS (1 << 7) +#define AHCI_GHC_CAP_EMS (1 << 6) +#define AHCI_GHC_CAP_SXS (1 << 5) +#define AHCI_GHC_CAP_NP 0x0000001f + +#define AHCI_HBA_CTRL 4 +#define AHCI_HBA_CTRL_AE (1 << 31) +#define AHCI_HBA_CTRL_MRSM (1 << 2) +#define AHCI_HBA_CTRL_IE (1 << 1) +#define AHCI_HBA_CTRL_HR (1 << 0) + +#define AHCI_GHC_PI 0x000c +#define AHCI_GHC_CAP2 0x0024 +#define AHCI_GHC_CAP2_DESO (1 << 5) +#define AHCI_GHC_CAP2_SADM (1 << 4) +#define AHCI_GHC_CAP2_SDS (1 << 3) +#define AHCI_GHC_CAP2_APST (1 << 2) +#define AHCI_GHC_CAP2_BOH (1 << 0) + +#define AHCI_VSP 0x00a0 +#define AHCI_VSP_SFMS (1 << 6) +#define AHCI_VSP_PFS (1 << 5) +#define AHCI_VSP_PT (1 << 4) +#define AHCI_VSP_SRPIR (1 << 3) + +#define AHCI_SFM 0xc8 +#define AHCI_SFM_OROM_UI 0x0c00 +#define AHCI_SFM_OROM_UI_2SEC 0 +#define AHCI_SFM_OROM_UI_4SEC (1 << 10) +#define AHCI_SFM_OROM_UI_6SEC (2 << 10) +#define AHCI_SFM_OROM_UI_8SEC (3 << 10) +#define AHCI_SFM_SRT (1 << 9) +#define AHCI_SFM_RRT_ESATA (1 << 8) +#define AHCI_SFM_LED (1 << 7) +#define AHCI_SFM_HDDUNLOCK (1 << 6) +#define AHCI_SFM_OROM_UI_BANNER (1 << 5) +#define AHCI_SFM_RRT (1 << 4) +#define AHCI_SFM_R5 (1 << 3) +#define AHCI_SFM_R10 (1 << 2) +#define AHCI_SFM_R1 (1 << 1) +#define AHCI_SFM_R0 (1 << 0) + +#define AHCI_PXCMD0 0x0118 +#define AHCI_PXCMD1 0x0198 + +#define AHCI_PXCMD_ICC 0xf0000000 +#define AHCI_PXCMD_ASP (1 << 27) +#define AHCI_PXCMD_ALPE (1 << 26) +#define AHCI_PXCMD_DLAE (1 << 25) +#define AHCI_PXCMD_ATAPI (1 << 24) +#define AHCI_PXCMD_APSTE (1 << 23) +#define AHCI_PXCMD_FBSCP (1 << 22) +#define AHCI_PXCMD_ESP (1 << 21) +#define AHCI_PXCMD_CPD (1 << 20) +#define AHCI_PXCMD_MPSP (1 << 19) +#define AHCI_PXCMD_HPCP (1 << 18) +#define AHCI_PXCMD_PMA (1 << 17) +#define AHCI_PXCMD_CR (1 << 15) +#define AHCI_PXCMD_FR (1 << 14) +#define AHCI_PXCMD_MPSS (1 << 13) +#define AHCI_PXCMD_CCS 0x00001f00 +#define AHCI_PXCMD_PSP (1 << 6) +#define AHCI_PXCMD_FRE (1 << 4) +#define AHCI_PXCMD_CLO (1 << 3) +#define AHCI_PXCMD_POD (1 << 2) +#define AHCI_PXCMD_SUD (1 << 1) +#define AHCI_PXCMD_ST (1 << 0) + +#endif /* _BRASWELL_SATA_H_ */ diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h index 0d920fb..f852fc1 100644 --- a/src/soc/intel/braswell/include/soc/smm.h +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,23 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_SMM_H_ -#define _BAYTRAIL_SMM_H_ +#ifndef _BRASWELL_SMM_H_ +#define _BRASWELL_SMM_H_ -/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig - * is included after chipset code. This causes the chipset's Kconfig to be - * clobbered by the arch/x86/Kconfig if they have the same name. */ -static inline int smm_region_size(void) -{ - /* Make it 8MiB by default. */ - if (CONFIG_SMM_TSEG_SIZE == 0) - return (8 << 20); - return CONFIG_SMM_TSEG_SIZE; -} +#include <rules.h> -uintptr_t smm_region_start(void); - -#if !defined(__PRE_RAM__) && !defined(__SMM___) +#if ENV_RAMSTAGE #include <stdint.h> void southcluster_smm_clear_state(void); void southcluster_smm_enable_smi(void); @@ -46,4 +36,4 @@ enum { SMM_SAVE_PARAM_COUNT }; -#endif /* _BAYTRAIL_SMM_H_ */ +#endif /* _BRASWELL_SMM_H_ */ diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h index ef71ad5..a2c126e 100644 --- a/src/soc/intel/braswell/include/soc/spi.h +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _BAYTRAIL_SPI_H_ -#define _BAYTRAIL_SPI_H_ +#ifndef _BRASWELL_SPI_H_ +#define _BRASWELL_SPI_H_ #include <stdint.h> @@ -71,4 +72,5 @@ struct spi_config { /* Return 0 on success < 0 on failure. */ int mainboard_get_spi_config(struct spi_config *cfg); -#endif /* _BAYTRAIL_SPI_H_ */ +#endif /* _BRASWELL_SPI_H_ */ + diff --git a/src/soc/intel/braswell/include/soc/xhci.h b/src/soc/intel/braswell/include/soc/xhci.h index b317361..d5be4b3 100644 --- a/src/soc/intel/braswell/include/soc/xhci.h +++ b/src/soc/intel/braswell/include/soc/xhci.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef BAYTRAIL_XHCI_H -#define BAYTRAIL_XHCI_H +#ifndef _BRASWELL_XHCI_H +#define _BRASWELL_XHCI_H /* XHCI PCI Registers */ #define XHCI_PWR_CTL_STS 0x74 @@ -37,7 +38,7 @@ # define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ # define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ # define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ # define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ # define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ # define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ @@ -45,12 +46,6 @@ # define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ # define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ -/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ -#define BYTM_USB2_PORT_COUNT 4 -#define BYTM_USB2_PORT_MAP 0xf -#define BYTM_USB3_PORT_COUNT 1 -#define BYTM_USB3_PORT_MAP 0x1 - #define XHCI_RESET_TIMEOUT 100000 /* 100ms */ -#endif /* BAYTRAIL_XHCI_H */ +#endif /* _BRASWELL_XHCI_H */ diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 8dba823..7c006f3 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -18,18 +19,19 @@ */ #include <arch/io.h> +#include <console/console.h> #include <soc/iosf.h> -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE #define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12)) static inline void write_iosf_reg(int reg, uint32_t value) { - write32((u32 *)(IOSF_PCI_BASE + reg), value); + write32((void *)(IOSF_PCI_BASE + reg), value); } static inline uint32_t read_iosf_reg(int reg) { - return read32((u32 *)(IOSF_PCI_BASE + reg)); + return read32((void *)(IOSF_PCI_BASE + reg)); } #else static inline void write_iosf_reg(int reg, uint32_t value) @@ -40,7 +42,7 @@ static inline uint32_t read_iosf_reg(int reg) { return pci_read_config32(IOSF_PCI_DEV, reg); } -#endif +#endif /* ENV_RAMSTAGE */ /* Common sequences for all the port accesses. */ static uint32_t iosf_read_port(uint32_t cr, int reg) @@ -60,9 +62,9 @@ static void iosf_write_port(uint32_t cr, int reg, uint32_t val) } #define IOSF_READ(port) \ - IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) + (IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port)) #define IOSF_WRITE(port) \ - IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) + (IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port)) uint32_t iosf_bunit_read(int reg) { @@ -74,28 +76,6 @@ void iosf_bunit_write(int reg, uint32_t val) iosf_write_port(IOSF_WRITE(BUNIT), reg, val); } -uint32_t iosf_dunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(SYSMEMC), reg); -} - -uint32_t iosf_dunit_ch0_read(int reg) -{ - return iosf_dunit_read(reg); -} - -uint32_t iosf_dunit_ch1_read(int reg) -{ - uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | - IOSF_PORT(IOSF_PORT_DUNIT_CH1); - return iosf_read_port(cr, reg); -} - -void iosf_dunit_write(int reg, uint32_t val) -{ - iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); -} - uint32_t iosf_punit_read(int reg) { return iosf_read_port(IOSF_READ(PMC), reg); @@ -106,24 +86,14 @@ void iosf_punit_write(int reg, uint32_t val) iosf_write_port(IOSF_WRITE(PMC), reg, val); } -uint32_t iosf_usbphy_read(int reg) -{ - return iosf_read_port(IOSF_READ(USBPHY), reg); -} - -void iosf_usbphy_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); -} - -uint32_t iosf_ushphy_read(int reg) +uint32_t iosf_score_read(int reg) { - return iosf_read_port(IOSF_READ(USHPHY), reg); + return iosf_read_port(IOSF_READ(SCORE), reg); } -void iosf_ushphy_write(int reg, uint32_t val) +void iosf_score_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); + iosf_write_port(IOSF_WRITE(SCORE), reg, val); } uint32_t iosf_lpss_read(int reg) @@ -133,27 +103,17 @@ uint32_t iosf_lpss_read(int reg) void iosf_lpss_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(LPSS), reg, val); -} - -uint32_t iosf_ccu_read(int reg) -{ - return iosf_read_port(IOSF_READ(CCU), reg); -} - -void iosf_ccu_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CCU), reg, val); + iosf_write_port(IOSF_WRITE(LPSS), reg, val); } -uint32_t iosf_score_read(int reg) +uint32_t iosf_port58_read(int reg) { - return iosf_read_port(IOSF_READ(SCORE), reg); + return iosf_read_port(IOSF_READ(0x58), reg); } -void iosf_score_write(int reg, uint32_t val) +void iosf_port58_write(int reg, uint32_t val) { - return iosf_write_port(IOSF_WRITE(SCORE), reg, val); + iosf_write_port(IOSF_WRITE(0x58), reg, val); } uint32_t iosf_scc_read(int reg) @@ -166,122 +126,71 @@ void iosf_scc_write(int reg, uint32_t val) return iosf_write_port(IOSF_WRITE(SCC), reg, val); } -uint32_t iosf_aunit_read(int reg) -{ - return iosf_read_port(IOSF_READ(AUNIT), reg); -} - -void iosf_aunit_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); -} - -uint32_t iosf_cpu_bus_read(int reg) -{ - return iosf_read_port(IOSF_READ(CPU_BUS), reg); -} - -void iosf_cpu_bus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); -} - -uint32_t iosf_sec_read(int reg) -{ - return iosf_read_port(IOSF_READ(SEC), reg); -} - -void iosf_sec_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SEC), reg, val); -} - -uint32_t iosf_port45_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x45), reg); -} - -void iosf_port45_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x45), reg, val); -} - -uint32_t iosf_port46_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x46), reg); -} - -void iosf_port46_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x46), reg, val); -} -uint32_t iosf_port47_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x47), reg); -} - -void iosf_port47_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x47), reg, val); -} - -uint32_t iosf_port55_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x55), reg); -} - -void iosf_port55_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x55), reg, val); -} - -uint32_t iosf_port58_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x58), reg); -} - -void iosf_port58_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x58), reg, val); -} - -uint32_t iosf_port59_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x59), reg); -} - -void iosf_port59_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x59), reg, val); -} - -uint32_t iosf_port5a_read(int reg) -{ - return iosf_read_port(IOSF_READ(0x5a), reg); -} - -void iosf_port5a_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0x5a), reg, val); -} - -uint32_t iosf_porta2_read(int reg) -{ - return iosf_read_port(IOSF_READ(0xa2), reg); -} - -void iosf_porta2_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(0xa2), reg, val); -} - -uint32_t iosf_ssus_read(int reg) -{ - return iosf_read_port(IOSF_READ(SSUS), reg); -} - -void iosf_ssus_write(int reg, uint32_t val) -{ - return iosf_write_port(IOSF_WRITE(SSUS), reg, val); -} +#if ENV_RAMSTAGE +uint64_t reg_script_read_iosf(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + + /* Process the request */ + switch (step->id) { + case IOSF_PORT_BUNIT: + return iosf_bunit_read(step->reg); + case IOSF_PORT_SCORE: + return iosf_score_read(step->reg); + case IOSF_PORT_LPSS: + return iosf_lpss_read(step->reg); + case IOSF_PORT_0x58: + return iosf_port58_read(step->reg); + case IOSF_PORT_SCC: + return iosf_scc_read(step->reg); + default: + printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", + step->id); + break; + } + return 0; +} + +void reg_script_write_iosf(struct reg_script_context *ctx) +{ + const struct reg_script *step = ctx->step; + + /* Process the request */ + switch (step->id) { + case IOSF_PORT_BUNIT: + iosf_bunit_write(step->reg, step->value); + break; + case IOSF_PORT_SCORE: + iosf_score_write(step->reg, step->value); + break; + case IOSF_PORT_LPSS: + iosf_lpss_write(step->reg, step->value); + break; + case IOSF_PORT_0x58: + iosf_port58_write(step->reg, step->value); + break; + case IOSF_PORT_SCC: + iosf_scc_write(step->reg, step->value); + break; + + default: + printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", + step->id); + break; + } +} + +const struct reg_script_bus_entry reg_script_bus_table[] = { + {REG_SCRIPT_TYPE_IOSF, reg_script_read_iosf, reg_script_write_iosf} +}; + +const struct reg_script_bus_entry *platform_bus_table(size_t *table_entries) +{ + /* Return the table size and address */ + *table_entries = sizeof(reg_script_bus_table) + / sizeof(reg_script_bus_table[0]); + return &reg_script_bus_table[0]; +} + +#endif /* ENV_RAMSTAGE */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index c23fdb2..1f0b51e 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -31,13 +32,15 @@ #include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include "chip.h" -/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB - * address. Just take 1MiB @ 512MiB. */ +/* + * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. + */ #define FIRMWARE_PHYS_BASE (512 << 20) #define FIRMWARE_PHYS_LENGTH (1 << 20) #define FIRMWARE_PCI_REG_BASE 0xa8 @@ -59,7 +62,8 @@ static void lpe_enable_acpi_mode(device_t dev) static const struct reg_script ops[] = { /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER + | PCI_COMMAND_INT_DISABLE), /* Enable ACPI mode */ REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, LPE_PCICFGCTR1_PCI_CFG_DIS | @@ -69,7 +73,7 @@ static void lpe_enable_acpi_mode(device_t dev) global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; @@ -77,7 +81,8 @@ static void lpe_enable_acpi_mode(device_t dev) /* Save BAR0, BAR1, and firmware base to ACPI NVS */ assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); - assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); + /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */ + /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */ assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); /* Device is enabled in ACPI mode */ @@ -91,7 +96,7 @@ static void setup_codec_clock(device_t dev) { uint32_t reg; u32 *clk_reg; - struct soc_intel_baytrail_config *config; + struct soc_intel_braswell_config *config; const char *freq_str; config = dev->chip_info; @@ -119,7 +124,7 @@ static void setup_codec_clock(device_t dev) printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); - clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); @@ -129,34 +134,35 @@ static void lpe_stash_firmware_info(device_t dev) { struct resource *res; struct resource *mmio; - const struct pattrs *pattrs = pattrs_get(); res = find_resource(dev, FIRMWARE_PCI_REG_BASE); if (res == NULL) { printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); return; } + printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base); /* Continue using old way of informing firmware address / size. */ pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); - /* C0 and later steppings use an offset in the MMIO space. */ - if (pattrs->stepping >= STEP_C0) { - mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), - res->base); - write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), - res->size); - } + /* Also put the address in MMIO space like on C0 BTM */ + mmio = find_resource(dev, PCI_BASE_ADDRESS_0); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), \ + res->base); + write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), \ + res->size); } + static void lpe_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; - lpe_stash_firmware_info(dev); + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + lpe_stash_firmware_info(dev); setup_codec_clock(dev); if (config->lpe_acpi_mode) diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index caa945c..2adbf18 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,7 +49,7 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) global_nvs_t *gnvs; /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; @@ -70,26 +71,16 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) reg_script_run_on_dev(dev, ops); } -static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) -{ - struct reg_script ops[] = { - REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, - ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), - LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), - REG_SCRIPT_END, - }; - - reg_script_run_on_dev(dev, ops); -} - static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) { *iosf_reg = -1; *nvs_index = -1; #define SET_IOSF_REG(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - *iosf_reg = LPSS_ ## name_ ## _CTL; \ - *nvs_index = LPSS_NVS_ ## name_ + do { \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_; \ + } while (0) switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); @@ -135,13 +126,13 @@ static void i2c_disable_resets(device_t dev) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) switch (dev->path.pci.devfn) { - CASE_I2C(I2C1): - CASE_I2C(I2C2): - CASE_I2C(I2C3): - CASE_I2C(I2C4): - CASE_I2C(I2C5): - CASE_I2C(I2C6): - CASE_I2C(I2C7): + CASE_I2C(I2C1) : + CASE_I2C(I2C2) : + CASE_I2C(I2C3) : + CASE_I2C(I2C4) : + CASE_I2C(I2C5) : + CASE_I2C(I2C6) : + CASE_I2C(I2C7) : printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); reg_script_run_on_dev(dev, ops); break; @@ -152,9 +143,15 @@ static void i2c_disable_resets(device_t dev) static void lpss_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; int iosf_reg, nvs_index; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + printk(BIOS_SPEW, "%s - %s\n", + get_pci_class_name(dev), + get_pci_subclass_name(dev)); + dev_ctl_reg(dev, &iosf_reg, &nvs_index); if (iosf_reg < 0) { @@ -164,7 +161,7 @@ static void lpss_init(device_t dev) slot, func); return; } - dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); if (config->lpss_acpi_mode) diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c index 9a49e35..902a4d4 100644 --- a/src/soc/intel/braswell/memmap.c +++ b/src/soc/intel/braswell/memmap.c @@ -2,13 +2,14 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * @@ -19,15 +20,66 @@ #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> +#include <soc/intel/common/memmap.h> #include <soc/iosf.h> #include <soc/smm.h> -uintptr_t smm_region_start(void) +static size_t smm_region_size(void) { - return (iosf_bunit_read(BUNIT_SMRRL) << 20); + u32 smm_size; + smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF; + smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF; + smm_size = (smm_size + 1) << 20; + return smm_size; +} + +void smm_region(void **start, size_t *size) +{ + *start = (void *)((iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF) << 20); + *size = smm_region_size(); +} + +size_t mmap_region_granluarity(void) +{ + /* Align to TSEG size when SMM is in use, and 8MiB by default */ + return IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? smm_region_size() + : 8 << 20; } void *cbmem_top(void) { - return (void *) smm_region_start(); + char *smm_base; + size_t smm_size; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + smm_region((void **)&smm_base, &smm_size); + return (void *)(smm_base - CONFIG_CHIPSET_RESERVED_MEM_BYTES); } diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index 09bd454..936dd85 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1 +1,13 @@ -cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c +# Add CPU uCode source to list of files to build. +cpu_microcode-y += microcode_blob.c + +# This section overrides the default build process for the microcode to place +# it at a known location in the CBFS. This only needs to be enabled if FSP is +# being used. +# Define the correct offset for the file in CBFS +fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) + +# Override the location that was supplied by the core code. +add-cpu-microcode-to-cbfs = \ + $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t 0x53 -b $(fsp_ucode_cbfs_base) + diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c index 7c7b6f1..c232ef5 100644 --- a/src/soc/intel/braswell/microcode/microcode_blob.c +++ b/src/soc/intel/braswell/microcode/microcode_blob.c @@ -1,3 +1,3 @@ unsigned microcode[] = { -#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h" +#include "../../../../../3rdparty/soc/intel/braswell/microcode_blob.h" }; diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 97b3bcc..fda58ae 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,19 +18,23 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <vendorcode/google/chromeos/chromeos.h> - +#include <fsp_util.h> +#include <soc/intel/common/memmap.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> +#include <soc/smm.h> +#include <vendorcode/google/chromeos/chromeos.h> -/* Host Memory Map: +/* + * Host Memory Map: * * +--------------------------+ BMBOUND_HI * | Usable DRAM | @@ -46,11 +51,13 @@ * +--------------------------+ SMMRRH, IRM0 * | TSEG | * +--------------------------+ SMMRRL + * | FSP Reserved Mem | + * +--------------------------+ SMMRRL - CONFIG_CHIPSET_RESERVED_MEM_BYTES * | Usable DRAM | * +--------------------------+ 0 * * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resource model: + * coreboot's resrouce model: * * +--------------------------+ BMBOUND_HI * | Cacheable/Usable | @@ -64,7 +71,7 @@ * | Cacheable/Usable | * +--------------------------+ 0 */ -#define RES_IN_KiB(r) ((r) >> 10) +#define RES_IN_KIB(r) ((r) >> 10) uint32_t nc_read_top_of_low_memory(void) { @@ -74,10 +81,13 @@ uint32_t nc_read_top_of_low_memory(void) static void nc_read_resources(device_t dev) { unsigned long mmconf; - unsigned long bmbound; + unsigned long bmbound_k; unsigned long bmbound_hi; - unsigned long smmrrh; - unsigned long smmrrl; + void *smm_base; + size_t smm_size; + unsigned long tseg_base_k; + unsigned long tseg_top_k; + unsigned long fsp_res_base_k; unsigned long base_k, size_k; const unsigned long four_gig_kib = (4 << (30 - 10)); int index = 0; @@ -85,59 +95,62 @@ static void nc_read_resources(device_t dev) /* Read standard PCI resources. */ pci_dev_read_resources(dev); + /* Determine TSEG data */ + smm_region(&smm_base, &smm_size); + tseg_base_k = RES_IN_KIB((unsigned long) smm_base); + tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); + + /* Determine the base of the FSP reserved memory */ + fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top()); + /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); - mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KIB(mmconf), 256 * 1024); /* 0 -> 0xa0000 */ - base_k = RES_IN_KiB(0); - size_k = RES_IN_KiB(0xa0000) - base_k; + base_k = RES_IN_KIB(0); + size_k = RES_IN_KIB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); - /* The SMMRR registers are 1MiB granularity with smmrrh being - * inclusive of the SMM region. */ - smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; - smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; - - /* 0xc0000 -> smrrl - cacheable and usable */ - base_k = RES_IN_KiB(0xc0000); - size_k = smmrrl - base_k; + /* 0xc0000 -> fsp_res_base - cacheable and usable */ + base_k = RES_IN_KIB(0xc0000); + size_k = fsp_res_base_k - base_k; ram_resource(dev, index++, base_k, size_k); - if (smmrrh > smmrrl) - reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); + /* fsp_res_base -> tseg_top - Reserved */ + base_k = fsp_res_base_k; + size_k = tseg_top_k - base_k; + reserved_ram_resource(dev, index++, base_k, size_k); - /* All address space between bmbound and smmrrh is unusable. */ - bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); - mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + /* TSEG TOP -> bmbound is memory backed mmio. */ + bmbound_k = RES_IN_KIB(nc_read_top_of_low_memory()); + mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k); - /* The BMBOUND_HI register matches register bits of 31:24 with address - * bits of 35:28. Therefore, shift register to align properly. */ + /* + * The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. + */ bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); - bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; + bmbound_hi = RES_IN_KIB(bmbound_hi) << 4; if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, - bmbound_hi - four_gig_kib); + bmbound_hi - four_gig_kib); - /* Reserve everything between A segment and 1MB: + /* + * Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + (0x100000 - 0xc0000) >> 10); chromeos_reserve_ram_oops(dev, index++); } static struct device_operations nc_ops = { .read_resources = nc_read_resources, - .set_resources = NULL, - .enable_resources = NULL, - .init = NULL, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index e44ebc6..d437b3b 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,20 +18,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "chip.h" #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> #include <reg_script.h> - #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/smm.h> -#include "chip.h" - static int pll_en_off; static uint32_t strpfusecfg; @@ -47,11 +46,13 @@ static inline int is_first_port(device_t dev) static const struct reg_script init_static_before_exit_latency[] = { /* Disable optimized buffer flush fill and latency tolerant reporting */ REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), - REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), + REG_PCI_RMW32(DSTS2, ~(OBFFEN | LTRME), 0), /* Set maximum payload size. */ REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), - /* Disable transmit datapath flush timer, clear transmit config change - * wait time, clear sideband interface idle counter. */ + /* + * Disable transmit datapath flush timer, clear transmit config change + * wait time, clear sideband interface idle counter. + */ REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), REG_SCRIPT_END, }; @@ -67,8 +68,10 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), /* Set IOSF packet fast transmit mode and link speed training policy. */ REG_PCI_OR16(MPC2, IPF | LSTP), - /* Channel configuration - enable upstream posted split, set non-posted - * and posted request size */ + /* + * Channel configuration - enable upstream posted split, set non-posted + * and posted request size + */ REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), /* Completion status replay enable and set TLP grant count */ REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), @@ -80,7 +83,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_PCI_RMW16(DSTS2, ~CTD, 0x6), /* Enable AER */ REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), - /* Read and write back capability registers. */ + /* Read and write back capabaility registers. */ REG_PCI_OR32(0x34, 0), REG_PCI_OR32(0x80, 0), /* Retrain the link. */ @@ -88,14 +91,16 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_SCRIPT_END, }; -static void byt_pcie_init(device_t dev) +static void pcie_init(device_t dev) { struct reg_script init_script[] = { REG_SCRIPT_NEXT(init_static_before_exit_latency), - /* Exit latency configuration based on - * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ + /* + * Exit latency configuration based on + * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1 + */ REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, - 2 << (L1EXIT_SHIFT + pll_en_off)), + 2 << (L1EXIT_MASK + pll_en_off)), REG_SCRIPT_NEXT(init_static_after_exit_latency), /* Disable hot plug, set power to 10W, set slot number. */ REG_PCI_RMW32(SLCAP, ~(HPC | HPS), @@ -108,10 +113,13 @@ static void byt_pcie_init(device_t dev) REG_SCRIPT_END, }; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; uint32_t reg = pci_read_config32(dev, RPPGEN); reg |= SRDLCGEN | SRDBCGEN; @@ -133,6 +141,9 @@ static void check_port_enabled(device_t dev) { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + switch (root_port_offset(dev)) { case PCIE_PORT1_FUNC: /* Port 1 cannot be disabled from strapping config. */ @@ -155,63 +166,66 @@ static void check_port_enabled(device_t dev) } } -static u8 all_ports_no_dev_present(device_t dev) -{ - u8 func; - u8 temp = dev->path.pci.devfn; - u8 device_not_present = 1; - u8 data; - - for (func = 1; func < PCIE_ROOT_PORT_COUNT; func++) { - dev->path.pci.devfn &= ~0x7; - dev->path.pci.devfn |= func; - - /* is pcie device there */ - if (pci_read_config32(dev, 0) == 0xFFFFFFFF) - continue; - - data = pci_read_config8(dev, XCAP + 3) | (SI >> 24); - pci_write_config8(dev, XCAP + 3, data); - - /* is any device present */ - if ((pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { - device_not_present = 0; - break; - } - } - - dev->path.pci.devfn = temp; - return device_not_present; -} - static void check_device_present(device_t dev) { + /* port1_dev will store the dev struct pointer of the PORT1 */ + static device_t port1_dev; + + /* + * Braswell Soc has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. + * For each port initial assumption is that, each port will have + * devices connected to it. Later we will scan each PORT and if + * the device is not attached to that port we will update + * rootports_in_use. If none of the root port is in use we will + * disable PORT1 otherwise we will keep PORT1 enabled per spec. + * In future if the Soc has more number of PCIe Root ports then + * change MAX_ROOT_PORTS_BSW value accordingly. + */ + + static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { - printk(BIOS_DEBUG, "No PCIe device present.\n"); - if (is_first_port(dev)) { - if (all_ports_no_dev_present(dev)) { - reg_script_run_on_dev(dev, no_dev_behind_port); - dev->enabled = 0; - } - } else { + rootports_in_use--; + printk(BIOS_DEBUG, "No PCIe device present."); + + /* + * Defer PORT1 disabling for now. When we are at Last port + * we will check rootports_in_use and disable PORT1 if none + * of the port has any device connected + */ + if (!is_first_port(dev)) { reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; + } else + port1_dev = dev; + /* + * If none of the ROOT PORT has devices connected then + * disable PORT1 else keep the PORT1 enable + */ + if (!rootports_in_use) { + reg_script_run_on_dev(port1_dev, no_dev_behind_port); + port1_dev->enabled = 0; + southcluster_enable_dev(port1_dev); } - } else if(!dev->enabled) { + } else if (!dev->enabled) { /* Port is disabled, but device present. Disable link. */ pci_write_config32(dev, LCTL, pci_read_config32(dev, LCTL) | LD); } } -static void byt_pcie_enable(device_t dev) +static void pcie_enable(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); if (is_first_port(dev)) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); pll_en_off = !!(reg & PLL_OFF_EN); @@ -230,21 +244,10 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) -{ - static const struct reg_script wait_for_link_active[] = { - REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), - REG_SCRIPT_END, - }; - - /* wait for Link Active with 50ms timeout */ - reg_script_run_on_dev(dev, wait_for_link_active); - - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); -} - static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) { + printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + __FILE__, __func__, dev_name(dev), vid, did); uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); if (!didvid) @@ -260,9 +263,9 @@ static struct device_operations device_ops = { .read_resources = pci_bus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_bus_enable_resources, - .init = byt_pcie_init, - .scan_bus = byt_pciexp_scan_bridge, - .enable = byt_pcie_enable, + .init = pcie_init, + .scan_bus = pciexp_scan_bridge, + .enable = pcie_enable, .ops_pci = &pcie_root_ops, }; diff --git a/src/soc/intel/braswell/perf_power.c b/src/soc/intel/braswell/perf_power.c deleted file mode 100644 index ad5ccfe..0000000 --- a/src/soc/intel/braswell/perf_power.c +++ /dev/null @@ -1,292 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <arch/io.h> -#include <bootstate.h> -#include <console/console.h> -#include <reg_script.h> -#include <soc/iosf.h> - -#define MAKE_MASK_INCLUSIVE(msb) \ - ((1ULL << (1 + (msb))) - 1) -#define MAKE_MASK(msb) \ - ((1ULL << (msb)) - 1) -#define MASK_VAL(msb, lsb, val) \ - ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) - -#define E(arg1, arg2, args) \ - REG_IOSF_RMW(IOSF_PORT_##arg1, arg2, args) - -static const struct reg_script perf_power_settings[] = { -E(AUNIT, 0x18, MASK_VAL(22, 22, 0x1)), // ACKGATE.AMESSAGE_MSGIF -E(AUNIT, 0x18, MASK_VAL(21, 21, 0x1)), // ACKGATE.AREQDOWN_SCL0_ARB -E(AUNIT, 0x18, MASK_VAL(20, 20, 0x1)), // ACKGATE.AREQUP_MIRROR -E(AUNIT, 0x18, MASK_VAL(19, 19, 0x1)), // ACKGATE.AREQTAHACK -E(AUNIT, 0x18, MASK_VAL(18, 18, 0x1)), // ACKGATE.AREQDOWN_TAREQQ -E(AUNIT, 0x18, MASK_VAL(17, 17, 0x1)), // ACKGATE.AREQDOWN_CREDIT -E(AUNIT, 0x18, MASK_VAL(16, 16, 0x1)), // ACKGATE.ASCLUP_FAIR_ARBITER -E(AUNIT, 0x18, MASK_VAL(15, 15, 0x1)), // ACKGATE.AIOSFDOWN_DATA -E(AUNIT, 0x18, MASK_VAL(14, 14, 0x1)), // ACKGATE.ASCLUP_IOSF_ADAPTER -E(AUNIT, 0x18, MASK_VAL(12, 12, 0x1)), // ACKGATE.ASCLUP_CMD_QUEUE -E(AUNIT, 0x18, MASK_VAL(11, 11, 0x1)), // ACKGATE.ASCLUP_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(10, 10, 0x1)), // ACKGATE.AREQUP_CMD_QUEUE -E(AUNIT, 0x18, MASK_VAL(9, 9, 0x1)), // ACKGATE.AREQUP_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(8, 8, 0x1)), // ACKGATE.AREQDOWN_RSP_QUEUE -E(AUNIT, 0x18, MASK_VAL(7, 7, 0x1)), // ACKGATE.AREQDOWN_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(6, 6, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DRVR -E(AUNIT, 0x18, MASK_VAL(5, 5, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF -E(AUNIT, 0x18, MASK_VAL(4, 4, 0x1)), // ACKGATE.AT_REQ_QUEUE -E(AUNIT, 0x18, MASK_VAL(3, 3, 0x1)), // ACKGATE.AT_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(2, 2, 0x1)), // ACKGATE.TA_REQ_QUEUE -E(AUNIT, 0x18, MASK_VAL(1, 1, 0x1)), // ACKGATE.TA_DATA_QUEUE -E(AUNIT, 0x18, MASK_VAL(0, 0, 0x1)), // ACKGATE.CONFIG_REGS -E(AUNIT, 0x20, MASK_VAL(26, 24, 0x2)), // AISOCHCTL.CHANNEL_AB_DEADLINE_EN -E(AUNIT, 0x20, MASK_VAL(8, 0, 0x1)), // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY -E(AUNIT, 0x21, MASK_VAL(31, 31, 0x1)), // AVCCTL.EFFICIENT_PERF_UP_EN -E(AUNIT, 0x21, MASK_VAL(8, 8, 0x0)), // AVCCTL.VC_EN_PRIORITY_DNARB -E(AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)), // AARBCTL0.IOSF0VC2_WGT -E(AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)), // AARBCTL0.IOSF0VC1_WGT -E(AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)), // AARBCTL0.IOSF0VC0_WGT -E(BUNIT, 0x3, MASK_VAL(29, 24, 0x4)), // BARBCTRL0.AGENT3_WEIGHT -E(BUNIT, 0x3, MASK_VAL(21, 16, 0x4)), // BARBCTRL0.AGENT2_WEIGHT -E(BUNIT, 0x3, MASK_VAL(13, 8, 0x4)), // BARBCTRL0.AGENT1_WEIGHT -E(BUNIT, 0x3, MASK_VAL(5, 0, 0x4)), // BARBCTRL0.AGENT0_WEIGHT -E(BUNIT, 0x4, MASK_VAL(29, 24, 0x4)), // BARBCTRL1.AGENT7_WEIGHT -E(BUNIT, 0x4, MASK_VAL(21, 16, 0x4)), // BARBCTRL1.AGENT6_WEIGHT -E(BUNIT, 0x4, MASK_VAL(13, 8, 0x4)), // BARBCTRL1.AGENT5_WEIGHT -E(BUNIT, 0x4, MASK_VAL(5, 0, 0x4)), // BARBCTRL1.AGENT4_WEIGHT -E(BUNIT, 0x5, MASK_VAL(21, 16, 0x4)), // BARBCTRL2.AGENT10_WEIGHT -E(BUNIT, 0x5, MASK_VAL(13, 8, 0x4)), // BARBCTRL2.AGENT9_WEIGHT -E(BUNIT, 0x5, MASK_VAL(5, 0, 0x8)), // BARBCTRL2.AGENT8_WEIGHT -E(BUNIT, 0x7, MASK_VAL(31, 24, 0x20)), // BWFLUSH.FLUSH_THRSHOLD -E(BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)), // BWFLUSH.DIRTY_LWM -E(BUNIT, 0x7, MASK_VAL(7, 0, 0x10)), // BWFLUSH.DIRTY_HWM -E(BUNIT, 0x8, MASK_VAL(23, 0, 0x0)), // BBANKMASK.BANK_MASK -E(BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)), // BROWMASK.ROW_MASK -E(BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)), // BRANKMASK.RANK_MASK -E(BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)), // BALIMIT0.AGENT3_LIMIT -E(BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)), // BALIMIT0.AGENT2_LIMIT -E(BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)), // BALIMIT0.AGENT1_LIMIT -E(BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)), // BALIMIT0.AGENT0_LIMIT -E(BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)), // BALIMIT1.AGENT7_LIMIT -E(BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)), // BALIMIT1.AGENT6_LIMIT -E(BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)), // BALIMIT1.AGENT5_LIMIT -E(BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)), // BALIMIT1.AGENT4_LIMIT -E(BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)), // BALIMIT2.AGENT10_LIMIT -E(BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)), // BALIMIT2.AGENT9_LIMIT -E(BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)), // BALIMIT2.AGENT8_LIMIT -E(BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)), // BARES0.AGENT7_RSVD -E(BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)), // BARES0.AGENT6_RSVD -E(BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)), // BARES0.AGENT5_RSVD -E(BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)), // BARES0.AGENT4_RSVD -E(BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)), // BARES0.AGENT3_RSVD -E(BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)), // BARES0.AGENT2_RSVD -E(BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)), // BARES0.AGENT1_RSVD -E(BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)), // BARES0.AGENT0_RSVD -E(BUNIT, 0x10, MASK_VAL(9, 8, 0x0)), // BARES1.AGENT10_RSVD -E(BUNIT, 0x10, MASK_VAL(5, 4, 0x0)), // BARES1.AGENT9_RSVD -E(BUNIT, 0x10, MASK_VAL(1, 0, 0x0)), // BARES1.AGENT8_RSVD -E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH -E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN -E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY -E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY -E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE -E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 -E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13 -E(BUNIT, 0x12, MASK_VAL(25, 24, 0x0)), // BCOSCAT.COS_CAT_AGENT12 -E(BUNIT, 0x12, MASK_VAL(23, 22, 0x0)), // BCOSCAT.COS_CAT_AGENT11 -E(BUNIT, 0x12, MASK_VAL(21, 20, 0x0)), // BCOSCAT.COS_CAT_AGENT10 -E(BUNIT, 0x12, MASK_VAL(19, 18, 0x0)), // BCOSCAT.COS_CAT_AGENT9 -E(BUNIT, 0x12, MASK_VAL(17, 16, 0x1)), // BCOSCAT.COS_CAT_AGENT8 -E(BUNIT, 0x12, MASK_VAL(15, 14, 0x0)), // BCOSCAT.COS_CAT_AGENT7 -E(BUNIT, 0x12, MASK_VAL(13, 12, 0x0)), // BCOSCAT.COS_CAT_AGENT6 -E(BUNIT, 0x12, MASK_VAL(11, 10, 0x1)), // BCOSCAT.COS_CAT_AGENT5 -E(BUNIT, 0x12, MASK_VAL(9, 8, 0x1)), // BCOSCAT.COS_CAT_AGENT4 -E(BUNIT, 0x12, MASK_VAL(7, 6, 0x0)), // BCOSCAT.COS_CAT_AGENT3 -E(BUNIT, 0x12, MASK_VAL(5, 4, 0x0)), // BCOSCAT.COS_CAT_AGENT2 -E(BUNIT, 0x12, MASK_VAL(3, 2, 0x0)), // BCOSCAT.COS_CAT_AGENT1 -E(BUNIT, 0x12, MASK_VAL(1, 0, 0x0)), // BCOSCAT.COS_CAT_AGENT0 -E(BUNIT, 0x14, MASK_VAL(31, 31, 0x0)), // BFLWT.DISABLE_FLUSH_WEIGHTS -E(BUNIT, 0x14, MASK_VAL(30, 30, 0x0)), // BFLWT.ENABLE_READ_INVALIDATE_TIMER -E(BUNIT, 0x14, MASK_VAL(13, 8, 0x8)), // BFLWT.WRITE_WEIGHTS -E(BUNIT, 0x14, MASK_VAL(5, 0, 0x10)), // BFLWT.READ_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(31, 31, 0x0)), // BISOCWT.ENABLE_ISOC_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)), // BISOCWT.ISOC_REQUEST_WEIGHTS -E(BUNIT, 0x16, MASK_VAL(5, 0, 0x8)), // BISOCWT.NON_ISOC_REQUEST_WEIGHTS -E(BUNIT, 0x18, MASK_VAL(31, 24, 0x20)), // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY -E(BUNIT, 0x18, MASK_VAL(23, 21, 0x6)), // BSCHCTRL0.PAGE_HIT_DELAY -E(BUNIT, 0x18, MASK_VAL(13, 7, 0x0)), // BSCHCTRL0.ISOC_BANK_PREFETCH -E(BUNIT, 0x18, MASK_VAL(6, 0, 0x20)), // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH -E(BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)), // BDEBUG0.CASUAL_TIMER -E(BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)), // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC -E(BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)), // BDEBUG0.CASUAL_WATER_MARK -E(BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)), // BDEBUG1.AGENT_WEIGHT_ENABLE -E(BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)), // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH -E(BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)), // BDEBUG1.ENABLE_DRAM_SELF_RFRSH -E(BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)), // BCTRL.BANK_STATUS_ENABLE -E(BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)), // BCTRL.DISABLE_OWNED -E(BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)), // BCTRL.INORDER_READ_ENABLE -E(BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)), // BCTRL.INORDER_FLUSH_ENABLE -E(BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)), // BCTRL.MISS_VALID_ENTRIES -E(BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)), // BCTRL.DIRTY_STALL -E(BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)), // BCTRL.SINGLE_TAG_ACCESS -E(BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)), // BCTRL.SINGLE_CHUNK_ACCESS -E(BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)), // BCTRL.BECLK_GATE_EN -E(BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)), // BCTRL.MASTERCLK_GATE_EN -E(BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)), // BCTRL.REQUESTCLK_GATE_EN -E(BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)), // BTHCTRL.AGENT_THROTTLING_ENABLE -E(BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)), // BTHCTRL.RANK_SELECTION_MASK -E(BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)), // BTHMASK.ORWRITE_MASK -E(BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)), // BTHMASK.ORREAD_MASK -E(BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)), // BTHMASK.ERWRITE_MASK -E(BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)), // BTHMASK.ERREAD_MASK - //0x02, 0x0, 2, 0, 0x1, //T_INTR_REDIR_CTL.REDIR_MODE_SEL -E(CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)), // T_CTL.SPLIT_GOIWP_MODE -E(CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)), // T_CTL.DISABLE_TRDY_RDGO -E(CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)), // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN -E(CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)), // T_CTL.ENABLE_NPC_COLLECTOR -E(CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)), // T_CTL.ENABLE_IN_ORDER_APIC -E(CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)), // T_CTL.TG_HIGHPRI_WRITE_PULLS - //0x02, 0x3, 12, 12, 0x1, // T_CTL.TG_NDRAMSNP -E(CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)), // T_CTL.TG_DW_POST_PUSH_LOG -E(CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)), // T_CTL.ALWAYS_SNP_IDI -E(CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)), // T_CTL.DIS_LIVE_BRAM_BYP_IDI -E(CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)), // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE -E(CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)), // T_MISC_CTL.DPTE_CNT -E(CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)), // T_MISC_CTL.DPTE_EN -E(CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)), // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)), // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)), // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)), // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)), // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)), // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)), // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)), // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)), // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)), // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)), // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)), // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)), // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)), // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)), // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)), // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)), // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)), // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)), // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)), // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)), // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)), // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)), // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)), // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)), // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN -E(CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)), // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN -E(0x55, 0x54, MASK_VAL(1, 0, 0x0)), // SMB_Config_PMCSR.PS -E(0x55, 0x0FC, MASK_VAL(17, 17, 0x0)), // SMB_Config_CGC.FUNC_CLK_CGD -E(0x55, 0x0FC, MASK_VAL(9, 9, 0x0)), // SMB_Config_CGC.SB_LOCAL_CGD -E(0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x47, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x45, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(0x46, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable -E(PMC, 0x0, MASK_VAL(11, 11, 0x1)), // PUNIT_CONTROL.MODE_DEMOTE_EN -E(PMC, 0x0, MASK_VAL(10, 10, 0x1)), // PUNIT_CONTROL.CORE_DEMOTE_EN - - // - //s0ix_PnP_Settings - // -E(0x58, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en -E(0x58, 0x1e0, MASK_VAL(0, 0, 0x0)), //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en -E(0x58, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en -E(0x58, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en -E(0x58, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en -E(0x58, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en -E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate -E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 -E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en -E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en -E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en -E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en -E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en -E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en -E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en -E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on -E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en -E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en -E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en -E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en -E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en -E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel -E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e -E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc -E(0x5a, 0x40, MASK_VAL(18, 18, 0x1)), //vlv.usb.xhci.controller.xhcc1.xhcil1e -E(0x5a, 0x50, MASK_VAL(3, 3, 0x1)), //vlv.usb.xhci.controller.xhclkgten.hsltcge -E(0x5a, 0x50, MASK_VAL(0, 0, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfblcge -E(0x5a, 0x50, MASK_VAL(1, 1, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfbtcge -E(0x5a, 0x50, MASK_VAL(2, 2, 0x1)), //vlv.usb.xhci.controller.xhclkgten.ssltcge -E(0x5a, 0x50, MASK_VAL(7, 5, 0x2)), //vlv.usb.xhci.controller.xhclkgten.sspllsue -E(0x5a, 0x50, MASK_VAL(13, 13, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso -E(0x5a, 0x50, MASK_VAL(4, 4, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcblcge -E(0x5a, 0x50, MASK_VAL(14, 14, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcftclkse -E(0x5a, 0x50, MASK_VAL(12, 12, 0x0)), //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe -E(0x5a, 0x50, MASK_VAL(11, 10, 0x3)), //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle -E(SCORE, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten -E(SSUS, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten -E(LPSS, 0x180, MASK_VAL(1, 1, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en -E(LPSS, 0x180, MASK_VAL(4, 4, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(0, 0, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable -E(LPSS, 0x180, MASK_VAL(3, 3, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(5, 5, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable -E(LPSS, 0x180, MASK_VAL(2, 2, 0x1)), //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable - //0x54, 0xfc, 31, 0, 0x0, //vlv.pcu.iosfahbep.clock_gating_control - //0x55, 0xfc, 1, 1, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd - //0x55, 0xfc, 0, 0, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd - //0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd -E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 -E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en -E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en -E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en -E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en -E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en -E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en -E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis -E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis -E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis -E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis -E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis -E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis -E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis -E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis -REG_SCRIPT_END, -}; - - -static void perf_power(void *unused) -{ - printk(BIOS_DEBUG, "Applying perf/power settings.\n"); - reg_script_run(perf_power_settings); -} - -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/braswell/placeholders.c b/src/soc/intel/braswell/placeholders.c index 3495c30..92ce00b 100644 --- a/src/soc/intel/braswell/placeholders.c +++ b/src/soc/intel/braswell/placeholders.c @@ -4,8 +4,5 @@ #include <device/pci_rom.h> #include <soc/acpi.h> - -void smm_init(void) {} - /* Rmodules don't like weak symbols. */ u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 0678fb7..044cbda 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,14 +18,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> #include <arch/io.h> #include <console/console.h> - #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> +#include <stdint.h> #if defined(__SMM__) @@ -54,7 +54,7 @@ uint16_t get_pmbase(void) } static void print_num_status_bits(int num_bits, uint32_t status, - const char *bit_names[]) + const char * const bit_names[]) { int i; @@ -71,14 +71,14 @@ static void print_num_status_bits(int num_bits, uint32_t status, } } -static void print_status_bits(uint32_t status, const char *bit_names[]) +static void print_status_bits(uint32_t status, const char * const bit_names[]) { print_num_status_bits(32, status, bit_names); } static uint32_t print_smi_status(uint32_t smi_sts) { - static const char *smi_sts_bits[] = { + static const char * const smi_sts_bits[] = { [2] = "BIOS", [4] = "SLP_SMI", [5] = "APM", @@ -163,7 +163,7 @@ static uint16_t reset_pm1_status(void) static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char *pm1_sts_bits[] = { + static const char * const pm1_sts_bits[] = { [0] = "TMROF", [5] = "GBL", [8] = "PWRBTN", @@ -196,7 +196,7 @@ void enable_pm1(uint16_t events) static uint32_t print_tco_status(uint32_t tco_sts) { - static const char *tco_sts_bits[] = { + static const char * const tco_sts_bits[] = { [3] = "TIMEOUT", [17] = "SECOND_TO", }; @@ -258,7 +258,7 @@ static uint32_t reset_gpe_status(void) static uint32_t print_gpe_sts(uint32_t gpe_sts) { - static const char *gpe_sts_bits[] = { + static const char * const gpe_sts_bits[] = { [1] = "HOTPLUG", [2] = "SWGPE", [3] = "PCIE_WAKE0", @@ -314,7 +314,7 @@ static uint32_t reset_alt_status(void) static uint32_t print_alt_sts(uint32_t alt_gpio_smi) { uint32_t alt_gpio_sts; - static const char *alt_gpio_smi_sts_bits[] = { + static const char * const alt_gpio_smi_sts_bits[] = { [0] = "SUS_GPIO_0", [1] = "SUS_GPIO_1", [2] = "SUS_GPIO_2", @@ -355,10 +355,10 @@ void clear_pmc_status(void) uint32_t prsts; uint32_t gen_pmcon1; - prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); /* Clear the status bits. The RPS field is cleared on a 0 write. */ - write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); - write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((void *)(PMC_BASE_ADDRESS + PRSTS), prsts); } diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 8b6d93c..b129ff5 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,6 +20,7 @@ #include <arch/cpu.h> #include <arch/acpi.h> +#include <bootstate.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/microcode.h> @@ -27,24 +29,23 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <stdlib.h> -#include <string.h> - +#include <fsp_util.h> +#include <romstage_handoff.h> #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> #include <soc/nvs.h> #include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> -#include <soc/iosf.h> - -/* Global PATTRS */ -DEFINE_PATTRS; +#include <soc/intel/common/ramstage.h> +#include <stdlib.h> #define SHOW_PATTRS 1 +struct pattrs __global_pattrs; + static void detect_num_cpus(struct pattrs *attrs) { int ecx = 0; @@ -54,8 +55,10 @@ static void detect_num_cpus(struct pattrs *attrs) leaf_b = cpuid_ext(0xb, ecx); - /* Bay Trail doesn't have hyperthreading so just determine the - * number of cores by from level type (ecx[15:8] == * 2). */ + /* + * The SOC doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2). + */ if ((leaf_b.ecx & 0xff00) == 0x0200) { attrs->num_cpus = leaf_b.ebx & 0xffff; break; @@ -73,7 +76,7 @@ static inline void fill_in_msr(msr_t *msr, int idx) } } -static const char *stepping_str[] = { +static const char * const stepping_str[] = { "A0", "A1", "B0", "B1", "B2", "B3", "C0" }; @@ -103,7 +106,7 @@ static void fill_in_pattrs(void) detect_num_cpus(attrs); if (SHOW_PATTRS) { - printk(BIOS_DEBUG, "BYT: cpuid %08x cpus %d rid %02x step %s\n", + printk(BIOS_DEBUG, "Cpuid %08x cpus %d rid %02x step %s\n", attrs->cpuid, attrs->num_cpus, attrs->revid, (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : stepping_str[attrs->stepping]); @@ -113,22 +116,29 @@ static void fill_in_pattrs(void) fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); /* Set IA core speed ratio and voltages */ - msr = rdmsr(MSR_IACORE_RATIOS); + fill_in_msr(&msr, MSR_IACORE_RATIOS); attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_RATIOS); + fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS); attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ - msr = rdmsr(MSR_IACORE_VIDS); + fill_in_msr(&msr, MSR_IACORE_VIDS); attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; - msr = rdmsr(MSR_IACORE_TURBO_VIDS); + fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS); attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ /* Set bus clock speed */ - attrs->bclk_khz = bus_freq_khz(); + attrs->bclk_khz = BUS_FREQ_KHZ; +} + +static inline void set_acpi_sleep_type(int val) +{ +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + acpi_slp_type = val; +#endif } /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ @@ -160,47 +170,39 @@ static void s3_save_acpi_wake_source(global_nvs_t *gnvs) static void s3_resume_prepare(void) { global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (gnvs == NULL) + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) + memset(gnvs, 0, sizeof(global_nvs_t)); + set_acpi_sleep_type(0); return; + } - if (!acpi_is_wakeup_s3()) - memset(gnvs, 0, sizeof(global_nvs_t)); - else - s3_save_acpi_wake_source(gnvs); -} + set_acpi_sleep_type(3); -static void baytrail_enable_2x_refresh_rate(void) -{ - u32 reg; - reg = iosf_dunit_read(0x8); - reg = reg & ~0x7000; - reg = reg | 0x2000; - iosf_dunit_write(0x8, reg); + s3_save_acpi_wake_source(gnvs); } -void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) +void braswell_init_pre_device(struct soc_intel_braswell_config *config) { struct soc_gpio_config *gpio_config; fill_in_pattrs(); - if (!config->disable_ddr_2x_refresh_rate) - baytrail_enable_2x_refresh_rate(); - /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); /* Indicate S3 resume to rest of ramstage. */ s3_resume_prepare(); - /* Run reference code. */ - baytrail_run_reference_code(); + /* Perform silicon specific init. */ + intel_silicon_init(); /* Get GPIO initial states from mainboard */ gpio_config = mainboard_get_gpios(); setup_soc_gpios(gpio_config, config->enable_xdp_tap); - - baytrail_init_scc(); } diff --git a/src/soc/intel/braswell/refcode.c b/src/soc/intel/braswell/refcode.c deleted file mode 100644 index 558db3c..0000000 --- a/src/soc/intel/braswell/refcode.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <string.h> -#include <arch/acpi.h> -#include <cbmem.h> -#include <console/console.h> -#include <console/streams.h> -#include <cpu/x86/tsc.h> -#include <program_loading.h> -#include <rmodule.h> -#include <stage_cache.h> -#if IS_ENABLED(CONFIG_CHROMEOS) -#include <vendorcode/google/chromeos/vboot_handoff.h> -#endif - -#include <soc/ramstage.h> -#include <soc/efi_wrapper.h> - -static void ABI_X86 send_to_console(unsigned char b) -{ - console_tx_byte(b); -} - -static efi_wrapper_entry_t load_refcode_from_cache(void) -{ - struct prog refcode; - - printk(BIOS_DEBUG, "refcode loading from cache.\n"); - - stage_cache_load_stage(STAGE_REFCODE, &refcode); - - return (efi_wrapper_entry_t)prog_entry(&refcode); -} - -static void cache_refcode(const struct rmod_stage_load *rsl) -{ - stage_cache_add(STAGE_REFCODE, rsl->prog); -} - -#if IS_ENABLED(CONFIG_CHROMEOS) -static int load_refcode_from_vboot(struct rmod_stage_load *refcode) -{ - struct vboot_handoff *vboot_handoff; - const struct firmware_component *fwc; - struct cbfs_stage *stage; - - vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); - fwc = &vboot_handoff->components[CONFIG_VBOOT_REFCODE_INDEX]; - - if (vboot_handoff == NULL || - vboot_handoff->selected_firmware == VB_SELECT_FIRMWARE_READONLY || - CONFIG_VBOOT_REFCODE_INDEX >= MAX_PARSED_FW_COMPONENTS || - fwc->size == 0 || fwc->address == 0) - return -1; - - printk(BIOS_DEBUG, "refcode loading from vboot rw area.\n"); - stage = (void *)(uintptr_t)fwc->address; - - if (rmodule_stage_load(refcode, stage)) { - printk(BIOS_DEBUG, "Error loading reference code.\n"); - return -1; - } - return 0; -} -#else -static int load_refcode_from_vboot(struct rmod_stage_load *refcode) -{ - return -1; -} -#endif - -static int load_refcode_from_cbfs(struct rmod_stage_load *refcode) -{ - printk(BIOS_DEBUG, "refcode loading from cbfs.\n"); - - if (rmodule_stage_load_from_cbfs(refcode)) { - printk(BIOS_DEBUG, "Error loading reference code.\n"); - return -1; - } - - return 0; -} - -static efi_wrapper_entry_t load_reference_code(void) -{ - struct prog prog = { - .name = CONFIG_CBFS_PREFIX "/refcode", - }; - struct rmod_stage_load refcode = { - .cbmem_id = CBMEM_ID_REFCODE, - .prog = &prog, - }; - - if (acpi_is_wakeup_s3()) { - return load_refcode_from_cache(); - } - - if (load_refcode_from_vboot(&refcode) || - load_refcode_from_cbfs(&refcode)) - return NULL; - - /* Cache loaded reference code. */ - cache_refcode(&refcode); - - return prog_entry(&prog); -} - -void baytrail_run_reference_code(void) -{ - int ret; - efi_wrapper_entry_t entry; - struct efi_wrapper_params wrp = { - .version = EFI_WRAPPER_VER, - .console_out = send_to_console, - }; - - entry = load_reference_code(); - - if (entry == NULL) - return; - - wrp.tsc_ticks_per_microsecond = tsc_freq_mhz(); - - /* Call into reference code. */ - ret = entry(&wrp); - - if (ret != 0) { - printk(BIOS_DEBUG, "Reference code returned %d\n", ret); - return; - } -} diff --git a/src/soc/intel/braswell/reset.c b/src/soc/intel/braswell/reset.c deleted file mode 100644 index c4cb2ab..0000000 --- a/src/soc/intel/braswell/reset.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <soc/pmc.h> -#include <soc/reset.h> - -void cold_reset(void) -{ - /* S0->S5->S0 trip. */ - outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); -} - -void warm_reset(void) -{ - /* PMC_PLTRST# asserted. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void soft_reset(void) -{ - /* Sends INIT# to CPU */ - outb(RST_CPU, RST_CNT); -} - -void hard_reset(void) -{ - /* Don't power cycle on hard_reset(). It's not really clear what the - * semantics should be for the meaning of hard_reset(). */ - warm_reset(); -} diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc index 345037d..4149d22 100644 --- a/src/soc/intel/braswell/romstage/Makefile.inc +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -1,7 +1,4 @@ -cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc -romstage-y += romstage.c -romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c -romstage-y += gfx.c +romstage-y += early_spi.c romstage-y += pmc.c -romstage-y += early_spi.c \ No newline at end of file +romstage-y += romstage.c + diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc deleted file mode 100644 index b6fcbf2..0000000 --- a/src/soc/intel/braswell/romstage/cache_as_ram.inc +++ /dev/null @@ -1,285 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cpu/x86/mtrr.h> -#include <cpu/x86/cache.h> -#include <cpu/x86/post_code.h> -#include <cbmem.h> - -/* The full cache-as-ram size includes the cache-as-ram portion from coreboot - * and the space used by the reference code. These 2 values combined should - * be a power of 2 because the MTRR setup assumes that. */ -#define CACHE_AS_RAM_SIZE \ - (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - -/* Cache all of CBFS just below 4GiB as Write-Protect type. */ -#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE) -#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) -#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) -#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) - -#define NoEvictMod_MSR 0x2e0 -#define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* All CPUs need to be in Wait for SIPI state */ -wait_for_sipi: - movl (%esi), %eax - bt $12, %eax - jc wait_for_sipi - - post_code(0x21) - /* Configure the default memory type to uncacheable as well as disable - * fixed and variable range mtrrs. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - post_code(0x22) - /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx - rdmsr - movzx %al, %ebx - /* First variable MTRR. */ - movl $0x200, %ecx - xorl %eax, %eax - xorl %edx, %edx - 1: - wrmsr - inc %ecx - dec %ebx - jnz 1b - - /* Zero out all fixed range and variable range MTRRs. */ - movl $fixed_mtrr_table, %esi - movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx - 1: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz 1b - - post_code(0x23) - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - post_code(0x24) - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x25) - /* Set code caching up for romstage. */ - movl $(MTRRphysBase_MSR(1)), %ecx - movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - - movl $(MTRRphysMask_MSR(1)), %ecx - movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x26) - - /* Enable the L2 cache. */ - movl $BBL_CR_CTL3_MSR, %ecx - rdmsr - orl $0x100, %eax - wrmsr - - post_code(0x27) - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax - invd - movl %eax, %cr0 - - /* enable the 'no eviction' mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $1, %eax - wrmsr - - post_code(0x28) - - /* Clear the cache memory region. This will also fill up the cache */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - xorl %eax, %eax - rep stosl - - /* enable no evict mode */ - movl $NoEvictMod_MSR, %ecx - rdmsr - orl $2, %eax - wrmsr - - post_code(0x29) - - /* Setup the stack. */ - movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax - movl %eax, %esp - - /* Push the initial TSC value from boot block. The low 32 bits are - * in mm0, and the high 32 bits are in mm1. */ - movd %mm1, %eax - pushl %eax - movd %mm0, %eax - pushl %eax - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - -before_romstage: - post_code(0x2a) - /* Call romstage.c main function. */ - call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. It also contains the information - * for setting up MTRRs. */ - movl %eax, %ebx - - post_code(0x2b) - - /* Disable cache. */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - post_code(0x2c) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - invd - - post_code(0x2d) - - /* Disable the no eviction run state */ - movl $NoEvictMod_MSR, %ecx - rdmsr - andl $~2, %eax - wrmsr - - /* Disable the no eviction mode */ - rdmsr - andl $~1, %eax - wrmsr - - post_code(0x2e) - - /* Setup stack as indicated by return value from ramstage_main(). */ - movl %ebx, %esp - - /* Get number of MTRRs. */ - popl %ebx - movl $MTRRphysBase_MSR(0), %ecx -1: - testl %ebx, %ebx - jz 1f - - /* Low 32 bits of MTRR base. */ - popl %eax - /* Upper 32 bits of MTRR base. */ - popl %edx - /* Write MTRR base. */ - wrmsr - inc %ecx - /* Low 32 bits of MTRR mask. */ - popl %eax - /* Upper 32 bits of MTRR mask. */ - popl %edx - /* Write MTRR mask. */ - wrmsr - inc %ecx - - dec %ebx - jmp 1b -1: - post_code(0x2f) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax - movl %eax, %cr0 - - post_code(0x30) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x31) - -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - call romstage_after_car - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -/* Fixed MTRRs */ -fixed_mtrr_table: - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F -fixed_mtrr_table_end: - diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c index 2c48af1..5bff858 100644 --- a/src/soc/intel/braswell/romstage/early_spi.c +++ b/src/soc/intel/braswell/romstage/early_spi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. All rights reserved. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -26,16 +27,18 @@ #include <soc/romstage.h> #include <soc/spi.h> -#define SPI_CYCLE_DELAY 10 /* 10us */ -#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ +#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_TIMEOUT (400000 / SPI_CYCLE_DELAY) /* 400ms */ -#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) -#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) -#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) +#define SPI8(x) (*((volatile u8 *)(SPI_BASE_ADDRESS + (x)))) +#define SPI16(x) (*((volatile u16 *)(SPI_BASE_ADDRESS + (x)))) +#define SPI32(x) (*((volatile u32 *)(SPI_BASE_ADDRESS + (x)))) -/* Minimal set of commands to read wpsr from SPI. Don't use this code outside +/* + * Minimal set of commands to read wpsr from SPI. Don't use this code outside * romstage -- it trashes the opmenu table. - * Returns 0 on success, < 0 on failure. */ + * Returns 0 on success, < 0 on failure. + */ int early_spi_read_wpsr(u8 *sr) { int timeout = SPI_CYCLE_TIMEOUT; @@ -49,7 +52,7 @@ int early_spi_read_wpsr(u8 *sr) SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; /* Wait for error / complete status */ - while(timeout--) { + while (timeout--) { u16 status = SPI16(SSFS); if (status & FLASH_CYCLE_ERROR) { printk(BIOS_ERR, "SPI rdsr failed\n"); diff --git a/src/soc/intel/braswell/romstage/gfx.c b/src/soc/intel/braswell/romstage/gfx.c deleted file mode 100644 index f9bb9c9..0000000 --- a/src/soc/intel/braswell/romstage/gfx.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <soc/gfx.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void gfx_init(void) -{ - uint32_t ggc; - uint8_t msac; - const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); - - /* The GFX device needs to set the aperture, gtt stolen size, and - * graphics stolen memory stolen size before running MRC. For now - * just hard code the defaults. Options can be added to the device - * tree if needed. */ - - ggc = pci_read_config32(gfx_dev, GGC); - msac = pci_read_config8(gfx_dev, MSAC); - - ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); - /* 32MB GSM is not supported with <C0 stepping. */ - ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB; - /* Enable VGA decoding as well. */ - ggc &= ~(GGC_VGA_DISABLE); - - msac &= ~(APERTURE_SIZE_MASK); - msac |= APERTURE_SIZE_256MB; - - pci_write_config32(gfx_dev, GGC, ggc); - pci_write_config8(gfx_dev, MSAC, msac); -} diff --git a/src/soc/intel/braswell/romstage/pmc.c b/src/soc/intel/braswell/romstage/pmc.c index b41359b..7d2ca14 100644 --- a/src/soc/intel/braswell/romstage/pmc.c +++ b/src/soc/intel/braswell/romstage/pmc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,18 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stddef.h> #include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> #include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> #include <soc/romstage.h> -#include "../chip.h" void tco_disable(void) { @@ -38,44 +30,3 @@ void tco_disable(void) reg |= TCO_TMR_HALT; outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); } - -/* This sequence signals the PUNIT to start running. */ -void punit_init(void) -{ - uint32_t reg; - uint8_t rid; - const struct device *dev; - const struct soc_intel_baytrail_config *cfg = NULL; - - rid = pci_read_config8(IOSF_PCI_DEV, REVID); - dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); - - if (dev) - cfg = dev->chip_info; - - reg = iosf_punit_read(SB_BIOS_CONFIG); - /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ - reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; - /* Configure VR low power mode for C0 and above. */ - if (rid >= RID_C_STEPPING_START && cfg != NULL && - (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { - printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); - if (cfg->vnn_ps2_enable) { - reg |= SB_BIOS_CONFIG_PS2_EN_VNN; - printk(BIOS_DEBUG, "VNN "); - } - if (cfg->vcc_ps2_enable) { - reg |= SB_BIOS_CONFIG_PS2_EN_VCC; - printk(BIOS_DEBUG, "VCC "); - } - printk(BIOS_DEBUG, "\n"); - } - iosf_punit_write(SB_BIOS_CONFIG, reg); - - /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ - reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; - pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); - reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | - IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; - pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); -} diff --git a/src/soc/intel/braswell/romstage/raminit.c b/src/soc/intel/braswell/romstage/raminit.c deleted file mode 100644 index 61c122c..0000000 --- a/src/soc/intel/braswell/romstage/raminit.c +++ /dev/null @@ -1,191 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stddef.h> -#include <arch/io.h> -#include <bootmode.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <halt.h> -#include <stage_cache.h> -#include <soc/gpio.h> -#include <soc/intel/common/mrc_cache.h> -#include <soc/iomap.h> -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/reset.h> -#include <soc/romstage.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> - -static void reset_system(void) -{ - warm_reset(); - halt(); -} - -static void enable_smbus(void) -{ - uint32_t reg; - const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); - - /* SMBus I/O BAR */ - reg = SMBUS_BASE_ADDRESS | 2; - pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); - /* Enable decode of I/O space. */ - reg = pci_read_config16(smbus_dev, PCI_COMMAND); - reg |= 0x1; - pci_write_config16(smbus_dev, PCI_COMMAND, reg); - /* Enable Host Controller */ - reg = pci_read_config8(smbus_dev, 0x40); - reg |= 1; - pci_write_config8(smbus_dev, 0x40, reg); - - /* Configure pads to be used for SMBus */ - score_select_func(PCU_SMB_CLK_PAD, 1); - score_select_func(PCU_SMB_DATA_PAD, 1); -} - -static void ABI_X86 send_to_console(unsigned char b) -{ - do_putchar(b); -} - -static void print_dram_info(void) -{ - const int mrc_ver_reg = 0xf0; - const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); - uint32_t reg; - int num_channels; - int speed; - uint32_t ch0; - uint32_t ch1; - - reg = pci_read_config32(soc_dev, mrc_ver_reg); - - printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); - - /* Number of channels enabled and DDR3 type. Determine number of - * channels by keying of the rank enable bits [3:0]. * */ - ch0 = iosf_dunit_ch0_read(DRP); - ch1 = iosf_dunit_ch1_read(DRP); - num_channels = 0; - if (ch0 & DRP_RANK_MASK) - num_channels++; - if (ch1 & DRP_RANK_MASK) - num_channels++; - - printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, - (reg & (1 << 22)) ? "LP" : ""); - - /* DRAM frequency -- all channels run at same frequency. */ - reg = iosf_dunit_read(DTR0); - switch (reg & 0x3) { - case 0: - speed = 800; break; - case 1: - speed = 1066; break; - case 2: - speed = 1333; break; - case 3: - speed = 1600; break; - } - printk(BIOS_INFO, "%dMHz\n", speed); -} - -void raminit(struct mrc_params *mp, int prev_sleep_state) -{ - int ret; - mrc_wrapper_entry_t mrc_entry; - const struct mrc_saved_data *cache; - - /* Fill in default entries. */ - mp->version = MRC_PARAMS_VER; - mp->console_out = &send_to_console; - mp->prev_sleep_state = prev_sleep_state; - mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); - - /* Default to 2GiB IO hole. */ - if (!mp->io_hole_mb) - mp->io_hole_mb = 2048; - - if (recovery_mode_enabled()) { - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current(&cache)) { - mp->saved_data_size = cache->size; - mp->saved_data = &cache->data[0]; - } else if (prev_sleep_state == 3) { - /* If waking from S3 and no cache then. */ - printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - reset_system(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); -#if CONFIG_EC_GOOGLE_CHROMEEC - if (prev_sleep_state == 0) { - /* Ensure EC is running RO firmware. */ - google_chromeec_check_ec_image(EC_IMAGE_RO); - } -#endif - } - - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, - NULL) == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } - - /* - * The entry point is currently the first instruction. Handle the - * case of an ELF file being put in the cbfs by setting the entry - * to the CONFIG_MRC_BIN_ADDRESS. - */ - mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; - - if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) - enable_smbus(); - - ret = mrc_entry(mp); - - print_dram_info(); - - if (prev_sleep_state != 3) { - cbmem_initialize_empty(); - stage_cache_create_empty(); - } else { - stage_cache_recover(); - if (cbmem_initialize()) { - #if CONFIG_HAVE_ACPI_RESUME - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - reset_system(); - #endif - } - } - - printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, - mp->data_to_save_size); - - if (mp->data_to_save != NULL && mp->data_to_save_size > 0) - mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); -} diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 9c8bbc4..568b163 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,44 +18,37 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbmem.h> #include <stddef.h> +#include <arch/early_variables.h> #include <arch/cpu.h> #include <arch/io.h> +#include <arch/cbfs.h> #include <arch/stages.h> -#include <arch/early_variables.h> -#include <console/console.h> -#include <cbfs.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if CONFIG_EC_GOOGLE_CHROMEEC +#include <console/console.h> +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> #endif #include <elog.h> #include <romstage_handoff.h> -#include <stage_cache.h> #include <timestamp.h> +#include <reset.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <fsp_util.h> +#include <soc/intel/common/mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> +#include <soc/iosf.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <soc/smm.h> #include <soc/spi.h> -/* The cache-as-ram assembly file calls romstage_main() after setting up - * cache-as-ram. romstage_main() will then call the mainboards's - * mainboard_romstage_entry() function. That function then calls - * romstage_common() below. The reason for the back and forth is to provide - * common entry point from cache-as-ram while still allowing for code sharing. - * Because we can't use global variables the stack is used for allocations -- - * thus the need to call back and forth. */ - -static void *setup_stack_and_mttrs(void); - -static void program_base_addresses(void) +void program_base_addresses(void) { uint32_t reg; const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); @@ -84,8 +78,8 @@ static void program_base_addresses(void) static void spi_init(void) { - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + void *scs = (void *)(SPI_BASE_ADDRESS + SCS); + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); uint32_t reg; /* Disable generating SMI when setting WPD bit. */ @@ -99,67 +93,9 @@ static void spi_init(void) write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -void * asmlinkage romstage_main(unsigned long bist, - uint32_t tsc_low, uint32_t tsc_hi) -{ - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; - - /* Save initial timestamp from bootblock. */ - timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - -#if CONFIG_EC_GOOGLE_CHROMEEC - /* Ensure the EC is in the right mode for recovery */ - google_chromeec_early_init(); -#endif - - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); - - return setup_stack_and_mttrs(); -} - static struct chipset_power_state power_state CAR_GLOBAL; -static void migrate_power_state(void) -{ - struct chipset_power_state *ps_cbmem; - struct chipset_power_state *ps_car; - - ps_car = car_get_var_ptr(&power_state); - ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); - - if (ps_cbmem == NULL) { - printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); - return; - } - memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); -} -CAR_MIGRATE(migrate_power_state); - -static struct chipset_power_state *fill_power_state(void) +struct chipset_power_state *fill_power_state(void) { struct chipset_power_state *ps = car_get_var_ptr(&power_state); @@ -169,9 +105,11 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); - ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); - ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + ps->prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS)); + ps->gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + ps->gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + + ps->prev_sleep_state = chipset_prev_sleep_state(ps); printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); @@ -179,199 +117,78 @@ static struct chipset_power_state *fill_power_state(void) ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); - + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } /* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int chipset_prev_sleep_state(struct chipset_power_state *ps) +int chipset_prev_sleep_state(struct chipset_power_state *ps) { /* Default to S0. */ - int prev_sleep_state = 0; + int prev_sleep_state = SLEEP_STATE_S0; if (ps->pm1_sts & WAK_STS) { switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { - #if CONFIG_HAVE_ACPI_RESUME + #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) case SLP_TYP_S3: - prev_sleep_state = 3; + prev_sleep_state = SLEEP_STATE_S3; break; #endif case SLP_TYP_S5: - prev_sleep_state = 5; + prev_sleep_state = SLEEP_STATE_S5; break; } + /* Clear SLP_TYP. */ outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } - if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - prev_sleep_state = 5; - } + if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = SLEEP_STATE_S5; return prev_sleep_state; } -static inline void chromeos_init(int prev_sleep_state) +/* SOC initialization before the console is enabled */ +void soc_pre_console_init(struct romstage_params *params) { -#if CONFIG_CHROMEOS - /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ - init_chromeos(prev_sleep_state == 3 ? 2 : 0); -#endif + /* Early chipset initialization */ + program_base_addresses(); + tco_disable(); } -/* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +/* SOC initialization after console is enabled */ +void soc_romstage_init(struct romstage_params *params) { - struct romstage_handoff *handoff; - struct chipset_power_state *ps; - int prev_sleep_state; - - timestamp_add_now(TS_BEFORE_INITRAM); - - ps = fill_power_state(); - prev_sleep_state = chipset_prev_sleep_state(ps); - - printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); + /* Continue chipset initialization */ + spi_init(); -#if CONFIG_ELOG_BOOT_COUNT - if (prev_sleep_state != 3) - boot_count_increment(); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); #endif - - - /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); - - timestamp_add_now(TS_AFTER_INITRAM); - - handoff = romstage_handoff_find_or_add(); - if (handoff != NULL) - handoff->s3_resume = (prev_sleep_state == 3); - else - printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - - chromeos_init(prev_sleep_state); -} - -void asmlinkage romstage_after_car(void) -{ - timestamp_add_now(TS_END_ROMSTAGE); - - /* Load the ramstage. */ - copy_and_run(); - while (1); -} - -static inline uint32_t *stack_push(u32 *stack, u32 value) -{ - stack = &stack[-1]; - *stack = value; - return stack; -} - -/* Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. */ -static unsigned long choose_top_of_stack(void) -{ - unsigned long stack_top; - const unsigned long romstage_ram_stack_size = 0x5000; - - /* cbmem_add() does a find() before add(). */ - stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - romstage_ram_stack_size); - stack_top += romstage_ram_stack_size; - return stack_top; } -/* setup_stack_and_mttrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void *setup_stack_and_mttrs(void) +/* SOC initialization after RAM is enabled */ +void soc_after_ram_init(struct romstage_params *params) { - unsigned long top_of_stack; - int num_mtrrs; - uint32_t *slot; - uint32_t mtrr_mask_upper; - uint32_t top_of_ram; - - /* Top of stack needs to be aligned to a 4-byte boundary. */ - top_of_stack = choose_top_of_stack() & ~3; - slot = (void *)top_of_stack; - num_mtrrs = 0; - - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ - - /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; - - /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; - - top_of_ram = (uint32_t)cbmem_top(); - /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the - * start of the TSEG region. It is required to be 8MiB aligned. Set - * this area as cacheable so it can be used later for ramstage before - * setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Cache 8MiB at the top of ram. Top of ram is where the TSEG - * region resides. However, it is not restricted to SMM mode until - * SMM has been relocated. By setting the region to cacheable it - * provides faster access when relocating the SMM handler as well - * as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; - - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); + struct chipset_power_state *ps_car; + struct chipset_power_state *ps_cbmem; + u32 value; - return slot; -} + /* Migrate the power state from CAR into CBMEM */ + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); -void ramstage_cache_invalid(void) -{ -#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE - /* Perform cold reset on invalid ramstage cache. */ - cold_reset(); -#endif -} + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); -#if CONFIG_CHROMEOS -int vboot_get_sw_write_protect(void) -{ - u8 status; - /* Return unprotected status if status read fails. */ - return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80)); + /* Make sure that E0000 and F0000 are RAM */ + printk(BIOS_DEBUG, "Disable ROM shadow below 1MB.\n"); + value = iosf_bunit_read(BUNIT_BMISC); + value |= 3; + iosf_bunit_write(BUNIT_BMISC, value); } -#endif diff --git a/src/soc/intel/braswell/romstage/uart.c b/src/soc/intel/braswell/romstage/uart.c deleted file mode 100644 index 7705746..0000000 --- a/src/soc/intel/braswell/romstage/uart.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <soc/gpio.h> -#include <soc/iomap.h> -#include <soc/lpc.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> - -void byt_config_com1_and_enable(void) -{ - uint32_t reg; - - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); - - /* Set up the pads to select the UART function */ - score_select_func(UART_RXD_PAD, 1); - score_select_func(UART_TXD_PAD, 1); -} diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index 5294207..98768d1 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,192 +30,17 @@ #include "chip.h" -typedef struct soc_intel_baytrail_config config_t; - -static inline void sir_write(struct device *dev, int idx, u32 value) -{ - pci_write_config32(dev, SATA_SIRI, idx); - pci_write_config32(dev, SATA_SIRD, value); -} +typedef struct soc_intel_braswell_config config_t; static void sata_init(struct device *dev) { - config_t *config = dev->chip_info; - u32 reg32; - u16 reg16; - u8 reg8; - - printk(BIOS_DEBUG, "SATA: Initializing...\n"); - - if (config == NULL) { - printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); - return; - } - - if (!config->sata_ahci) { - /* Set legacy or native decoding mode */ - if (config->ide_legacy_combined) { - reg8 = pci_read_config8(dev, 0x09); - reg8 &= ~0x5; - pci_write_config8(dev, 0x09, reg8); - } else { - reg8 = pci_read_config8(dev, 0x09); - reg8 |= 0x5; - pci_write_config8(dev, 0x09, reg8); - } - - /* Set capabilities pointer */ - pci_write_config8(dev, 0x34, 0x70); - reg16 = pci_read_config16(dev, 0x70); - reg16 &= ~0xFF00; - pci_write_config16(dev, 0x70, reg16); - } - - /* Primary timing - decode enable */ - reg16 = pci_read_config16(dev, 0x40); - reg16 |= 1 << 15; - pci_write_config16(dev, 0x40, reg16); - - /* Secondary timing - decode enable */ - reg16 = pci_read_config16(dev, 0x42); - reg16 |= 1 << 15; - pci_write_config16(dev, 0x42, reg16); - - /* Port mapping enables */ - reg16 = pci_read_config16(dev, 0x90); - reg16 |= (config->sata_port_map ^ 0x3) << 8; - pci_write_config16(dev, 0x90, reg16); - - /* Port control enables */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x003f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - if (config->sata_ahci) { - u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); - - /* Enable CR memory space decoding */ - reg16 = pci_read_config16(dev, 0x04); - reg16 |= 0x2; - pci_write_config16(dev, 0x04, reg16); - - /* Set capability register */ - reg32 = read32(abar + 0x00); - reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM - reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits - reg32 |= (0x3 << 20); // Gen3 SATA - write32(abar + 0x00, reg32); - - /* Ports enabled */ - reg32 = read32(abar + 0x0c); - reg32 &= (u32)(~0x3f); - reg32 |= config->sata_port_map; - write32(abar + 0xc, reg32); - /* Two extra reads to latch */ - read32(abar + 0x0c); - read32(abar + 0x0c); - - /* Set cap2 - Support devslp */ - reg32 = (1 << 5) | (1 << 4) | (1 << 3); - write32(abar + 0x24, reg32); - - /* Set PxCMD registers */ - reg32 = read32(abar + 0x118); - reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); - reg32 |= 2; - write32(abar + 0x118, reg32); - - reg32 = read32(abar + 0x198); - reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | - (1 << 19) | (1 << 18) | (1 << 1)); - reg32 |= 2; - write32(abar + 0x198, reg32); - - /* Clear reset features */ - write32(abar + 0xc8, 0); - - /* Enable interrupts */ - reg8 = read8(abar + 0x04); - reg8 |= 0x02; - write8(abar + 0x04, reg8); - - } else { - /* TODO(shawnn): Configure IDE SATA speed regs */ - } - - /* 1.4 us delay after configuring port / enable bits */ - udelay(2); - - /* Enable clock for ports */ - reg32 = pci_read_config32(dev, 0x94); - reg32 |= 0x3f << 24; - pci_write_config32(dev, 0x94, reg32); - reg32 &= (config->sata_port_map ^ 0x3) << 24; - pci_write_config32(dev, 0x94, reg32); - - /* Lock SataGc register */ - reg32 = (0x1 << 31) | (0x7 << 12); - pci_write_config32(dev, 0x98, reg32); + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); } static void sata_enable(device_t dev) { - config_t *config = dev->chip_info; - u8 reg8; - u16 reg16; - u32 reg32; - southcluster_enable_dev(dev); - if (!config) - return; - - /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ - reg16 = pci_read_config16(dev, 0x90); - reg16 &= ~0x03e0; - reg16 |= (config->sata_port_map ^ 0x3) << 8; - if(config->sata_ahci) - reg16 |= 0x60; - pci_write_config16(dev, 0x90, reg16); - - /* Set reg 0x94 before starting configuration */ - reg32 = pci_read_config32(dev, 0x94); - reg32 &= (u32)(~0x1ff); - reg32 |= 0x183; - pci_write_config32(dev, 0x94, reg32); - - /* Set ORM bit */ - reg16 = pci_read_config16(dev, 0x92); - reg16 |= (1 << 15); - pci_write_config16(dev, 0x92, reg16); - - /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ - reg32 = pci_read_config32(dev, 0x98); - reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); - reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | - (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); - pci_write_config32(dev, 0x98, reg32); - - /* CMD reg - set bus master enable (BME) */ - reg8 = pci_read_config8(dev, 0x04); - reg8 |= (1 << 2); - pci_write_config8(dev, 0x04, reg8); - - /* "Test mode registers" */ - sir_write(dev, 0x70, 0x00288301); - sir_write(dev, 0x54, 0x00000300); - sir_write(dev, 0x58, 0x50000000); - /* "OOB Detection Margin */ - sir_write(dev, 0x6c, 0x130C0603); - /* "Gasket Control" */ - sir_write(dev, 0xf4, 0); - - /* PCS - Enable requested SATA ports */ - reg8 = pci_read_config8(dev, 0x92); - reg8 &= ~0x03; - reg8 |= config->sata_port_map; - pci_write_config8(dev, 0x92, reg8); } static struct device_operations sata_ops = { @@ -223,17 +49,15 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; static const unsigned short pci_device_ids[] = { - IDE1_DEVID, IDE2_DEVID, /* IDE */ - AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ + AHCI1_DEVID, /* AHCI */ 0, }; -static const struct pci_driver baytrail_sata __pci_driver = { +static const struct pci_driver braswell_sata __pci_driver = { .ops = &sata_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 6400996..de4ba7e 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,86 +24,20 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <reg_script.h> - #include <soc/iosf.h> #include <soc/nvs.h> #include <soc/ramstage.h> -static const struct reg_script scc_start_dll[] = { - /* Configure master DLL. */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000), - /* Configure Swing,FSM for Master DLL */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133), - /* Run+Local Reset on Master DLL */ - REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933), - REG_SCRIPT_END, -}; - -static const struct reg_script scc_after_dll[] = { - /* Configure Write Path */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad), - /* Configure Read Path */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad), - /* eMMC 4.5 TX and RX DLL */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0), - /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */ - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0), - REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0), - /* - * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 - * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 - */ - REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), - /* Enable IOSF Snoop */ - REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), - /* SDIO 3V Support. */ - REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30), - REG_SCRIPT_END, -}; - -void baytrail_init_scc(void) -{ - uint32_t dll_values; - - printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n"); - - /* Common Sideband Initialization for SCC */ - reg_script_run(scc_start_dll); - - /* Override Slave Path - populate DLL settings. */ - dll_values = iosf_score_read(0x496c) & 0x7ffff; - dll_values |= iosf_score_read(0x4950) & ~0xfffff; - iosf_score_write(0x4950, dll_values | (1 << 19)); - - reg_script_run(scc_after_dll); -} - void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { - struct reg_script ops[] = { - /* Disable PCI interrupt, enable Memory and Bus Master */ - REG_PCI_OR32(PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), - /* Enable ACPI mode */ - REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, - SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), - REG_SCRIPT_END - }; struct resource *bar; global_nvs_t *gnvs; + printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n", + __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); + /* Find ACPI NVS to update BARs */ - gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); if (!gnvs) { printk(BIOS_ERR, "Unable to locate Global NVS\n"); return; @@ -113,13 +48,6 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) if (bar) gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; - bar = find_resource(dev, PCI_BASE_ADDRESS_1); - if (bar) - gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; - /* Device is enabled in ACPI mode */ gnvs->dev.scc_en[nvs_index] = 1; - - /* Put device in ACPI mode */ - reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 577469d..986823f 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -36,7 +37,10 @@ static void sd_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; + struct soc_intel_braswell_config *config = dev->chip_info; + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); if (config == NULL) return; @@ -44,12 +48,12 @@ static void sd_init(device_t dev) if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); pci_write_config32(dev, CAP_OVERRIDE_LOW, - config->sdcard_cap_low); + config->sdcard_cap_low); pci_write_config32(dev, CAP_OVERRIDE_HIGH, - config->sdcard_cap_high | USE_CAP_OVERRIDES); + config->sdcard_cap_high | USE_CAP_OVERRIDES); } - if (config->scc_acpi_mode) + if (config->sd_acpi_mode) scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); } @@ -58,8 +62,6 @@ static const struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sd_init, - .enable = NULL, - .scan_bus = NULL, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index 3fac525..4a9701f 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,21 +18,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <stdlib.h> +#include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> -#include <halt.h> -#include <spi-generic.h> - -#include <soc/iosf.h> -#include <soc/pci_devs.h> -#include <soc/pmc.h> #include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ static global_nvs_t *gnvs; @@ -42,7 +41,8 @@ int southbridge_io_trap_handler(int smif) switch (smif) { case 0x32: printk(BIOS_DEBUG, "OS Init\n"); - /* gnvs->smif: + /* + * gnvs->smif: * On success, the IO Trap Handler returns 0 * On failure, the IO Trap Handler returns a value != 0 */ @@ -116,14 +116,15 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ-2); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= 5) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); #endif + /* Clear pending GPE events */ + clear_gpe_status(); - /* Next, do the deed. - */ + /* Next, do the deed. */ switch (slp_typ) { case SLP_TYP_S0: @@ -154,8 +155,12 @@ static void southbridge_smi_sleep(void) printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } + /* Clear pending wake status bit to avoid immediate wake */ + write32((void *)(0xfed88000 + 0x0200), + read32((void *)(0xfed88000 + 0x0200))); - /* Write back to the SLP register to cause the originally intended + /* + * Write back to the SLP register to cause the originally intended * event again. We need to set BIT13 (SLP_EN) though to make the * sleep happen. */ @@ -163,9 +168,10 @@ static void southbridge_smi_sleep(void) /* Make sure to stop executing code here for S3/S4/S5 */ if (slp_typ > 1) - halt(); + hlt(); - /* In most sleep states, the code flow of this function ends at + /* + * In most sleep states, the code flow of this function ends at * the line above. However, if we entered sleep state S1 and wake * up again, we will continue to execute code in this function. */ @@ -212,7 +218,7 @@ static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -224,11 +230,11 @@ static void southbridge_smi_gsmi(void) return; /* Command and return value in EAX */ - ret = (u32*)&io_smi->rax; + ret = (u32 *)&io_smi->rax; sub_command = (uint8_t)(*ret >> 8); /* Parameter buffer in EBX */ - param = (u32*)&io_smi->rbx; + param = (u32 *)&io_smi->rbx; /* drivers/elog/gsmi.c */ *ret = gsmi_exec(sub_command, param); @@ -245,66 +251,12 @@ static void finalize(void) } finalize_done = 1; -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif } -/* - * soc_legacy: A payload (Depthcharge) has indicated that the - * legacy payload (SeaBIOS) is being loaded. Switch devices that are - * in ACPI mode to PCI mode so that non-ACPI drivers may work. - * - */ -static void soc_legacy(void) -{ - u32 reg32; - - /* LPE Device */ - if (gnvs->dev.lpe_en) { - reg32 = iosf_port58_read(LPE_PCICFGCTR1); - reg32 &= - ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); - iosf_port58_write(LPE_PCICFGCTR1, reg32); - } - - /* SCC Devices */ -#define SCC_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \ - reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ - reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ - iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ - } } while (0) - - SCC_ACPI_MODE_DISABLE(MMC); - SCC_ACPI_MODE_DISABLE(SD); - SCC_ACPI_MODE_DISABLE(SDIO); - - /* LPSS Devices */ -#define LPSS_ACPI_MODE_DISABLE(name_) \ - do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \ - reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ - reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ - iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ - } } while (0) - - LPSS_ACPI_MODE_DISABLE(SIO_DMA1); - LPSS_ACPI_MODE_DISABLE(I2C1); - LPSS_ACPI_MODE_DISABLE(I2C2); - LPSS_ACPI_MODE_DISABLE(I2C3); - LPSS_ACPI_MODE_DISABLE(I2C4); - LPSS_ACPI_MODE_DISABLE(I2C5); - LPSS_ACPI_MODE_DISABLE(I2C6); - LPSS_ACPI_MODE_DISABLE(I2C7); - LPSS_ACPI_MODE_DISABLE(SIO_DMA2); - LPSS_ACPI_MODE_DISABLE(PWM1); - LPSS_ACPI_MODE_DISABLE(PWM2); - LPSS_ACPI_MODE_DISABLE(HSUART1); - LPSS_ACPI_MODE_DISABLE(HSUART2); - LPSS_ACPI_MODE_DISABLE(SPI); -} - static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -315,14 +267,16 @@ static void southbridge_smi_apmc(void) reg8 = inb(APM_CNT); switch (reg8) { case APM_CNT_CST_CONTROL: - /* Calling this function seems to cause + /* + * Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ printk(BIOS_DEBUG, "C-state control\n"); break; case APM_CNT_PST_CONTROL: - /* Calling this function seems to cause + /* + * Calling this function seems to cause * some kind of race condition in Linux * and causes a kernel oops */ @@ -350,7 +304,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -358,10 +312,6 @@ static void southbridge_smi_apmc(void) case APM_CNT_FINALIZE: finalize(); break; - - case APM_CNT_LEGACY: - soc_legacy(); - break; } mainboard_smi_apmc(reg8); @@ -371,12 +321,13 @@ static void southbridge_smi_pm1(void) { uint16_t pm1_sts = clear_pm1_status(); - /* While OSPM is not active, poweroff immediately + /* + * While OSPM is not active, poweroff immediately * on a power button event. */ if (pm1_sts & PWRBTN_STS) { - // power button pressed -#if CONFIG_ELOG_GSMI + /* power button pressed */ +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); @@ -419,38 +370,38 @@ static void southbridge_smi_periodic(void) typedef void (*smi_handler_t)(void); static const smi_handler_t southbridge_smi[32] = { - NULL, // [0] reserved - NULL, // [1] reserved - NULL, // [2] BIOS_STS - NULL, // [3] LEGACY_USB_STS - southbridge_smi_sleep, // [4] SLP_SMI_STS - southbridge_smi_apmc, // [5] APM_STS - NULL, // [6] SWSMI_TMR_STS - NULL, // [7] reserved - southbridge_smi_pm1, // [8] PM1_STS - southbridge_smi_gpe0, // [9] GPE0_STS - NULL, // [10] reserved - NULL, // [11] reserved - NULL, // [12] reserved - southbridge_smi_tco, // [13] TCO_STS - southbridge_smi_periodic, // [14] PERIODIC_STS - NULL, // [15] SERIRQ_SMI_STS - NULL, // [16] SMBUS_SMI_STS - NULL, // [17] LEGACY_USB2_STS - NULL, // [18] INTEL_USB2_STS - NULL, // [19] reserved - NULL, // [20] PCI_EXP_SMI_STS - NULL, // [21] reserved - NULL, // [22] reserved - NULL, // [23] reserved - NULL, // [24] reserved - NULL, // [25] reserved - NULL, // [26] SPI_STS - NULL, // [27] reserved - NULL, // [28] PUNIT - NULL, // [29] GUNIT - NULL, // [30] reserved - NULL // [31] reserved + NULL, /* [0] reserved */ + NULL, /* [1] reserved */ + NULL, /* [2] BIOS_STS */ + NULL, /* [3] LEGACY_USB_STS */ + southbridge_smi_sleep, /* [4] SLP_SMI_STS */ + southbridge_smi_apmc, /* [5] APM_STS */ + NULL, /* [6] SWSMI_TMR_STS */ + NULL, /* [7] reserved */ + southbridge_smi_pm1, /* [8] PM1_STS */ + southbridge_smi_gpe0, /* [9] GPE0_STS */ + NULL, /* [10] reserved */ + NULL, /* [11] reserved */ + NULL, /* [12] reserved */ + southbridge_smi_tco, /* [13] TCO_STS */ + southbridge_smi_periodic, /* [14] PERIODIC_STS */ + NULL, /* [15] SERIRQ_SMI_STS */ + NULL, /* [16] SMBUS_SMI_STS */ + NULL, /* [17] LEGACY_USB2_STS */ + NULL, /* [18] INTEL_USB2_STS */ + NULL, /* [19] reserved */ + NULL, /* [20] PCI_EXP_SMI_STS */ + NULL, /* [21] reserved */ + NULL, /* [22] reserved */ + NULL, /* [23] reserved */ + NULL, /* [24] reserved */ + NULL, /* [25] reserved */ + NULL, /* [26] SPI_STS */ + NULL, /* [27] reserved */ + NULL, /* [28] PUNIT */ + NULL, /* [29] GUNIT */ + NULL, /* [30] reserved */ + NULL /* [31] reserved */ }; void southbridge_smi_handler(void) @@ -458,7 +409,8 @@ void southbridge_smi_handler(void) int i; uint32_t smi_sts; - /* We need to clear the SMI status registers, or we won't see what's + /* + * We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = clear_smi_status(); @@ -472,12 +424,14 @@ void southbridge_smi_handler(void) southbridge_smi[i](); } else { printk(BIOS_DEBUG, - "SMI_STS[%d] occurred, but no " + "SMI_STS[%d] occured, but no " "handler available.\n", i); } } - /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, - * these events need to be cleared and checked unconditionally. */ + /* + * The GPIO SMI events do not have a status bit in SMI_STS. Therefore, + * these events need to be cleared and checked unconditionally. + */ mainboard_smi_gpi(clear_alt_status()); } diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c index bfddb68..51610b8 100644 --- a/src/soc/intel/braswell/smm.c +++ b/src/soc/intel/braswell/smm.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,21 +20,24 @@ * MA 02110-1301 USA */ -#include <device/device.h> -#include <device/pci.h> -#include <console/console.h> #include <arch/io.h> +#include <console/console.h> #include <cpu/cpu.h> #include <cpu/x86/smm.h> -#include <string.h> - +#include <device/device.h> +#include <device/pci.h> #include <soc/iomap.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/smm.h> +#include <string.h> /* Save settings which will be committed in SMI functions. */ static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; +void smm_init(void) +{ +} + void southcluster_smm_save_param(int param, uint32_t data) { smm_save_params[param] = data; @@ -66,7 +70,7 @@ void southcluster_smm_clear_state(void) static void southcluster_smm_route_gpios(void) { - u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); + void *gpio_rout = (void *)(PMC_BASE_ADDRESS + GPIO_ROUT); const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; uint32_t alt_gpio_reg = 0; uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; @@ -79,9 +83,8 @@ static void southcluster_smm_route_gpios(void) /* Enable SMIs for the gpios that are set to trigger the SMI. */ for (i = 0; i < 16; i++) { - if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) alt_gpio_reg |= (1 << i); - } route_reg >>= 2; } printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); @@ -102,7 +105,8 @@ void southcluster_smm_enable_smi(void) /* Set up the GPIO route. */ southcluster_smm_route_gpios(); - /* Enable SMI generation: + /* + * Enable SMI generation: * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 8df1f1a..58687bb 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,37 +19,40 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> #include <arch/io.h> #include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> +#include "chip.h" #include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/mc146818rtc.h> -#include <drivers/uart/uart8250reg.h> - +#include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/lpc.h> #include <soc/nvs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/spi.h> -#include "chip.h" +#include <stdint.h> static inline void add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) { + printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n", + __FILE__, __func__, dev_name(dev), addr, size); mmio_resource(dev, i, addr >> 10, size >> 10); } static void sc_add_mmio_resources(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); @@ -86,6 +90,9 @@ static void sc_add_io_resource(device_t dev, int base, int size, int index) { struct resource *res; + printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n", + __FILE__, __func__, dev_name(dev), base, size, index); + if (io_range_in_default(base, size)) return; @@ -99,6 +106,9 @@ static void sc_add_io_resources(device_t dev) { struct resource *res; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); res->base = LPC_DEFAULT_IO_RANGE_LOWER; @@ -114,6 +124,9 @@ static void sc_add_io_resources(device_t dev) static void sc_read_resources(device_t dev) { + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); @@ -130,75 +143,43 @@ static void sc_rtc_init(void) int rtc_fail; struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - if (ps != NULL) { + printk(BIOS_SPEW, "%s/%s\n", + __FILE__, __func__); + if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; - } else { - gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); - } + else + gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); rtc_fail = !!(gen_pmcon1 & RPS); - if (rtc_fail) { + if (rtc_fail) printk(BIOS_DEBUG, "RTC failure.\n"); - } cmos_init(rtc_fail); } -/* - * The UART hardware loses power while in suspend. Because of this the kernel - * can hang because it doesn't re-initialize serial ports it is using for - * consoles at resume time. The following function configures the UART - * if the hardware is enabled though it may not be the correct baud rate - * or configuration. This is definitely a hack, but it helps the kernel - * along. - */ -static void com1_configure_resume(device_t dev) -{ - const uint16_t port = 0x3f8; - - /* Is the UART I/O port enabled? */ - if (!(pci_read_config32(dev, UART_CONT) & 1)) - return; - - /* Disable interrupts */ - outb(0x0, port + UART8250_IER); - - /* Enable FIFOs */ - outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); - - /* assert DTR and RTS so the other end is happy */ - outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); - - /* DLAB on */ - outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); - - /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ - outb(1, port + UART8250_DLL); - outb(0, port + UART8250_DLM); - - /* Set to 3 for 8N1 */ - outb(3, port + UART8250_LCR); -} - static void sc_init(device_t dev) { int i; - u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); - u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; - u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); - u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); - const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - struct soc_intel_baytrail_config *config = dev->chip_info; + const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; + const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1); + void *actl = (void *)(ILB_BASE_ADDRESS + ACTL); + const struct braswell_irq_route *ir = &global_braswell_irq_route; + struct soc_intel_braswell_config *config = dev->chip_info; + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); /* Set up the PIRQ PIC routing based on static config. */ - for (i = 0; i < NUM_PIRQS; i++) { - write8(pr_base + i, ir->pic[i]); - } + for (i = 0; i < NUM_PIRQS; i++) + write8((void *)(pr_base + i*sizeof(ir->pic[i])), + ir->pic[i]); + /* Set up the per device PIRQ routing base on static config. */ - for (i = 0; i < NUM_IR_DEVS; i++) { - write16(ir_base + i, ir->pcidev[i]); - } + for (i = 0; i < NUM_IR_DEVS; i++) + write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), + ir->pcidev[i]); /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); @@ -214,108 +195,86 @@ static void sc_init(device_t dev) read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); } - if (acpi_is_wakeup_s3()) - com1_configure_resume(dev); } /* * Common code for the south cluster devices. */ -/* Set bit in function disable register to hide this device. */ +/* Set bit in function disble register to hide this device. */ static void sc_disable_devfn(device_t dev) { - u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); - u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); + void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS); + void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2); uint32_t mask = 0; uint32_t mask2 = 0; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask2 |= name_ ## _DIS + switch (dev->path.pci.devfn) { - case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): - mask |= SDIO_DIS; + SET_DIS_MASK(SDIO); break; - case PCI_DEVFN(SD_DEV, SD_FUNC): - mask |= SD_DIS; + SET_DIS_MASK(SD); break; - case PCI_DEVFN(SATA_DEV, SATA_FUNC): - mask |= SATA_DIS; + SET_DIS_MASK(SATA); break; - case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): - mask |= XHCI_DIS; + SET_DIS_MASK(XHCI); /* Disable super speed PHY when XHCI is not available. */ mask2 |= USH_SS_PHY_DIS; break; - case PCI_DEVFN(LPE_DEV, LPE_FUNC): - mask |= LPE_DIS; + SET_DIS_MASK(LPE); break; - case PCI_DEVFN(MMC_DEV, MMC_FUNC): - mask |= MMC_DIS; + SET_DIS_MASK(MMC); break; - case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): - mask |= SIO_DMA1_DIS; + SET_DIS_MASK(SIO_DMA1); break; - case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(I2C1); break; - case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(I2C2); break; - case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): - mask |= I2C3_DIS; + SET_DIS_MASK(I2C3); break; - case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): - mask |= I2C4_DIS; + SET_DIS_MASK(I2C4); break; - case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): - mask |= I2C5_DIS; + SET_DIS_MASK(I2C5); break; - case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): - mask |= I2C6_DIS; + SET_DIS_MASK(I2C6); break; - case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): - mask |= I2C7_DIS; + SET_DIS_MASK(I2C7); break; - case PCI_DEVFN(TXE_DEV, TXE_FUNC): - mask |= TXE_DIS; + SET_DIS_MASK(TXE); break; - case PCI_DEVFN(HDA_DEV, HDA_FUNC): - mask |= HDA_DIS; + SET_DIS_MASK(HDA); break; - case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): - mask |= PCIE_PORT1_DIS; + SET_DIS_MASK(PCIE_PORT1); break; - case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): - mask |= PCIE_PORT2_DIS; + SET_DIS_MASK(PCIE_PORT2); break; - case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): - mask |= PCIE_PORT3_DIS; + SET_DIS_MASK(PCIE_PORT3); break; - case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): - mask |= PCIE_PORT4_DIS; + SET_DIS_MASK(PCIE_PORT4); break; - case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): - mask |= EHCI_DIS; + SET_DIS_MASK(SIO_DMA2); break; - case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): - mask |= SIO_DMA2_DIS; + SET_DIS_MASK(PWM1); break; - case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): - mask |= PWM1_DIS; + SET_DIS_MASK(PWM2); break; - case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): - mask |= PWM2_DIS; + SET_DIS_MASK(HSUART1); break; - case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): - mask |= HSUART1_DIS; + SET_DIS_MASK(HSUART2); break; - case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): - mask |= HSUART2_DIS; + SET_DIS_MASK(SPI); break; - case PCI_DEVFN(SPI_DEV, SPI_FUNC): - mask |= SPI_DIS; - break; - case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): - mask2 |= SMBUS_DIS; + SET_DIS_MASK2(SMBUS); break; } @@ -335,24 +294,34 @@ static void sc_disable_devfn(device_t dev) static inline void set_d3hot_bits(device_t dev, int offset) { uint32_t reg8; + + printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n", + __FILE__, __func__, dev_name(dev), offset); printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); reg8 |= 0x3; pci_write_config8(dev, offset + 4, reg8); } -/* Parts of the audio subsystem are powered by the HDA device. Therefore, one +/* + * Parts of the audio subsystem are powered by the HDA device. Therefore, one * cannot put HDA into D3Hot. Instead perform this workaround to make some of - * the audio paths work for LPE audio. */ + * the audio paths work for LPE audio. + */ static void hda_work_around(device_t dev) { - u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); + void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); + + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); /* Need to set magic register 0x43 to 0xd7 in config space. */ pci_write_config8(dev, 0x43, 0xd7); - /* Need to set bit 0 of GCTL to take the device out of reset. However, - * that requires setting up the 64-bit BAR. */ + /* + * Need to set bit 0 of GCTL to take the device out of reset. However, + * that requires setting up the 64-bit BAR. + */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); @@ -365,8 +334,13 @@ static int place_device_in_d3hot(device_t dev) { unsigned offset; - /* Parts of the HDA block are used for LPE audio as well. - * Therefore assume the HDA will never be put into D3Hot. */ + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); + + /* + * Parts of the HDA block are used for LPE audio as well. + * Therefore assume the HDA will never be put into D3Hot. + */ if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { hda_work_around(dev); return 0; @@ -379,91 +353,50 @@ static int place_device_in_d3hot(device_t dev) return 0; } - /* For some reason some of the devices don't have the capability - * pointer set correctly. Work around this by hard coding the offset. */ + /* + * For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. + */ +#define DEV_CASE(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + switch (dev->path.pci.devfn) { - case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + DEV_CASE(SDIO) : + DEV_CASE(SD) : + DEV_CASE(MMC) : + DEV_CASE(LPE) : + DEV_CASE(SIO_DMA1) : + DEV_CASE(I2C1) : + DEV_CASE(I2C2) : + DEV_CASE(I2C3) : + DEV_CASE(I2C4) : + DEV_CASE(I2C5) : + DEV_CASE(I2C6) : + DEV_CASE(I2C7) : + DEV_CASE(SIO_DMA2) : + DEV_CASE(PWM1) : + DEV_CASE(PWM2) : + DEV_CASE(HSUART1) : + DEV_CASE(HSUART2) : + DEV_CASE(SPI) : offset = 0x80; break; - case PCI_DEVFN(SD_DEV, SD_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(MMC_DEV, MMC_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(LPE_DEV, LPE_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SPI_DEV, SPI_FUNC): - offset = 0x80; - break; - case PCI_DEVFN(SATA_DEV, SATA_FUNC): - offset = 0x70; - break; - case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + DEV_CASE(SATA) : + DEV_CASE(XHCI) : offset = 0x70; break; - case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): - offset = 0x70; - break; - case PCI_DEVFN(HDA_DEV, HDA_FUNC): + DEV_CASE(HDA) : + DEV_CASE(SMBUS) : offset = 0x50; break; - case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): - offset = 0x50; - break; - case PCI_DEVFN(TXE_DEV, TXE_FUNC): + DEV_CASE(TXE) : /* TXE cannot be placed in D3Hot. */ return 0; - case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): - offset = 0xa0; break; - case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): - offset = 0xa0; - break; - case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): - offset = 0xa0; - break; - case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + DEV_CASE(PCIE_PORT1) : + DEV_CASE(PCIE_PORT2) : + DEV_CASE(PCIE_PORT3) : + DEV_CASE(PCIE_PORT4) : offset = 0xa0; break; } @@ -481,6 +414,8 @@ void southcluster_enable_dev(device_t dev) { uint32_t reg32; + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); int func = PCI_FUNC(dev->path.pci.devfn); @@ -528,18 +463,23 @@ static const struct pci_driver southcluster __pci_driver = { int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) { + printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + __FILE__, __func__, (void *)cfg); return -1; } static void finalize_chipset(void *unused) { - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); - u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); - u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); - u8 *spi = (u8 *)SPI_BASE_ADDRESS; + void *bcr = (void *)(SPI_BASE_ADDRESS + BCR); + void *gcs = (void *)(RCBA_BASE_ADDRESS + GCS); + void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2); + void *etr = (void *)(PMC_BASE_ADDRESS + ETR); + uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct spi_config cfg; + printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + __FILE__, __func__, unused); + /* Set the lock enable on the BIOS control register. */ write32(bcr, read32(bcr) | BCR_LE); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 2795d37..7acce5e 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * See file CREDITS for list of people who contributed to this * project. @@ -21,18 +22,17 @@ */ /* This file is derived from the flashrom project. */ -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <bootstate.h> -#include <delay.h> #include <arch/io.h> +#include <bootstate.h> #include <console/console.h> +#include <delay.h> #include <device/pci_ids.h> -#include <spi_flash.h> - #include <soc/lpc.h> #include <soc/pci_devs.h> +#include <spi_flash.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> #ifdef __SMM__ #define pci_read_config_byte(dev, reg, targ)\ @@ -85,20 +85,6 @@ typedef struct ich9_spi_regs { uint16_t preop; uint16_t optype; uint8_t opmenu[8]; - uint32_t bbar; - uint8_t _reserved3[12]; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; } __attribute__((packed)) ich9_spi_regs; typedef struct ich_spi_controller { @@ -113,7 +99,6 @@ typedef struct ich_spi_controller { unsigned databytes; uint8_t *status; uint16_t *control; - uint32_t *bbar; } ich_spi_controller; static ich_spi_controller cntlr; @@ -168,51 +153,45 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) -static u8 readb_(const void *addr) +static u8 readb_(void *addr) { - u8 v = read8((unsigned long)addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + u8 v = read8(addr); + printk(BIOS_DEBUG, "0x%p --> 0x%2.2x\n", addr, v); return v; } -static u16 readw_(const void *addr) +static u16 readw_(void *addr) { - u16 v = read16((unsigned long)addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + u16 v = read16(addr); + printk(BIOS_DEBUG, "0x%p --> 0x%4.4x\n", addr, v); return v; } -static u32 readl_(const void *addr) +static u32 readl_(void *addr) { - u32 v = read32((unsigned long)addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); + u32 v = read32(addr); + printk(BIOS_DEBUG, "0x%p --> 0x%8.8x\n", addr, v); return v; } -static void writeb_(u8 b, const void *addr) +static void writeb_(u8 b, void *addr) { + printk(BIOS_DEBUG, "0x%p <-- 0x%2.2x\n", addr, b); write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); } -static void writew_(u16 b, const void *addr) +static void writew_(u16 b, void *addr) { + printk(BIOS_DEBUG, "0x%p <-- 0x%4.4x\n", addr, b); write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); } -static void writel_(u32 b, const void *addr) +static void writel_(u32 b, void *addr) { + printk(BIOS_DEBUG, "0x%p <-- 0x%8.8x\n", addr, b); write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); } #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ @@ -241,9 +220,9 @@ static void write_reg(const void *value, void *dest, uint32_t size) } } -static void read_reg(const void *src, void *value, uint32_t size) +static void read_reg(void *src, void *value, uint32_t size) { - const uint8_t *bsrc = src; + uint8_t *bsrc = src; uint8_t *bvalue = value; while (size >= 4) { @@ -256,23 +235,12 @@ static void read_reg(const void *src, void *value, uint32_t size) } } -static void ich_set_bbar(uint32_t minaddr) -{ - const uint32_t bbar_mask = 0x00ffff00; - uint32_t ichspi_bbar; - - minaddr &= bbar_mask; - ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; - ichspi_bbar |= minaddr; - writel_(ichspi_bbar, cntlr.bbar); -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { ich_spi_slave *slave = malloc(sizeof(*slave)); if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + printk(BIOS_ERR, "ICH SPI: Bad allocation\n"); return NULL; } @@ -293,6 +261,11 @@ static ich9_spi_regs *spi_regs(void) #else dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); #endif + if (!dev) { + printk(BIOS_ERR, "%s: PCI device not found", __func__); + return NULL; + } + pci_read_config_dword(dev, SBASE, &sbase); sbase &= ~0x1ff; @@ -301,7 +274,14 @@ static ich9_spi_regs *spi_regs(void) void spi_init(void) { - ich9_spi_regs *ich9_spi = spi_regs(); + ich9_spi_regs *ich9_spi; + + ich9_spi = spi_regs(); + if (!ich9_spi) { + printk(BIOS_ERR, "Not initialising spi as %s returned NULL\n", + __func__); + return; + } ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; cntlr.opmenu = ich9_spi->opmenu; @@ -312,19 +292,19 @@ void spi_init(void) cntlr.databytes = sizeof(ich9_spi->fdata); cntlr.status = &ich9_spi->ssfs; cntlr.control = (uint16_t *)ich9_spi->ssfc; - cntlr.bbar = &ich9_spi->bbar; cntlr.preop = &ich9_spi->preop; - ich_set_bbar(0); } -#ifndef __SMM__ +#if ENV_RAMSTAGE + static void spi_init_cb(void *unused) { spi_init(); } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -#endif + +#endif /* ENV_RAMSTAGE */ int spi_claim_bus(struct spi_slave *slave) { @@ -461,13 +441,14 @@ static int spi_setup_offset(spi_transaction *trans) spi_use_out(trans, 3); return 1; default: - printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", + trans->type); return -1; } } /* - * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * Wait for up to 400ms til status register bit(s) turn 1 (in case wait_til_set * below is True) or 0. In case the wait was for the bit(s) to set - write * those bits back, which would cause resetting them. * @@ -478,6 +459,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) int timeout = 40000; /* This will result in 400 ms */ u16 status = 0; + wait_til_set &= 1; while (timeout--) { status = readw_(cntlr.status); if (wait_til_set ^ ((status & bitmask) == 0)) { @@ -488,7 +470,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) udelay(10); } - printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + printk(BIOS_ERR, "ICH SPI: SCIP timeout, read %x, expected %x\n", status, bitmask); return -1; } @@ -529,9 +511,11 @@ int spi_xfer(struct spi_slave *slave, const void *dout, writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); spi_setup_type(&trans); - if ((opcode_index = spi_setup_opcode(&trans)) < 0) + opcode_index = spi_setup_opcode(&trans); + if (opcode_index < 0) return -1; - if ((with_address = spi_setup_offset(&trans)) < 0) + with_address = spi_setup_offset(&trans); + if (with_address < 0) return -1; if (trans.opcode == SPI_OPCODE_WREN) { @@ -571,7 +555,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return -1; if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + printk(BIOS_ERR, "ICH SPI: Command transaction error\n"); return -1; } @@ -586,8 +570,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * by the SPI chip driver. */ if (trans.bytesout > cntlr.databytes) { - printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " spi_crop_chunk()?\n"); + printk(BIOS_DEBUG, + "ICH SPI: Too much to write. Does your SPI chip driver use" + " CONTROLLER_PAGE_LIMIT?\n"); return -1; } @@ -628,7 +613,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return -1; if (status & SPIS_FCERR) { - printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + printk(BIOS_ERR, "ICH SPI: Data transaction error\n"); return -1; } diff --git a/src/soc/intel/braswell/spi_loading.c b/src/soc/intel/braswell/spi_loading.c new file mode 100644 index 0000000..a166ec6 --- /dev/null +++ b/src/soc/intel/braswell/spi_loading.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/byteorder.h> +#include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define CACHELINE_SIZE 64 +#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) +#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) + +static void *find_mirror_buffer(int len) +{ + int nentries; + int i; + struct lb_memory *mem; + void *buffer; + + len = ALIGN(len, 4096); + + mem = get_lb_mem(); + nentries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); + + /* + * Find the highest RAM entry that accommodates the lenth provide + * while falling below 4GiB. + */ + buffer = NULL; + for (i = 0; i < nentries; i++) { + const uint64_t max_addr = 1ULL << 32; + uint64_t start; + uint64_t size; + struct lb_memory_range *r; + + r = &mem->map[i]; + + if (r->type != LB_MEM_RAM) + continue; + + start = unpack_lb64(r->start); + if (start >= max_addr) + continue; + + size = unpack_lb64(r->size); + if (size < len) + continue; + + /* Adjust size of buffer if range exceeds max address. */ + if (start + size > max_addr) + size = max_addr - start; + + if (size < len) + continue; + + buffer = (void *)(uintptr_t)(start + size - len); + } + + return buffer; +} + +/* + * Mirror the payload file to the default SMM location if it is small enough. + * The default SMM region can be used since no one is using the memory at this + * location at this stage in the boot. + */ +static void *spi_mirror(void *file_start, int file_len) +{ + int alignment_diff; + char *src; + char *dest; + + alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); + + /* + * Adjust file length so that the start and end points are aligned to a + * cacheline. Coupled with the ROM caching in the CPU the SPI hardware + * will read and cache full length cachelines. It will also prefetch + * data as well. Once things are mirrored in memory all accesses should + * hit the CPUs cache. + */ + file_len += alignment_diff; + file_len = ALIGN(file_len, CACHELINE_SIZE); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); + + dest = find_mirror_buffer(file_len); + + /* + * Just pass back the pointer to ROM space if a buffer could not + * be found to mirror into. + */ + if (dest == NULL) + return file_start; + + src = (void *)(CACHELINE_MASK & (long)file_start); + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(dest, src, file_len); + + /* Provide pointer into mirrored space. */ + return &dest[alignment_diff]; +} + +void *cbfs_load_payload(struct cbfs_media *media, const char *name) +{ + int file_len; + void *file_start; + struct cbfs_file *file; + + file_start = vboot_get_payload(&file_len); + + if (file_start != NULL) + return spi_mirror(file_start, file_len); + + file = cbfs_get_file(media, name); + + if (file == NULL) + return NULL; + + if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) + return NULL; + + file_len = ntohl(file->len); + + file_start = CBFS_SUBHEADER(file); + + return spi_mirror(file_start, file_len); +} diff --git a/src/soc/intel/braswell/stage_cache.c b/src/soc/intel/braswell/stage_cache.c deleted file mode 100644 index a4f510d..0000000 --- a/src/soc/intel/braswell/stage_cache.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cbmem.h> -#include <stage_cache.h> -#include <soc/smm.h> - -void stage_cache_external_region(void **base, size_t *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - *base = &smm_base[smm_region_size() - cache_size]; -} diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index 700b098..5a8e886f 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,46 +18,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/msr.h> - -unsigned bus_freq_khz(void) -{ - msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); - switch (clk_info.lo & 0x3) { - case 0: - return 83333; - case 1: - return 100000; - case 2: - return 133333; - case 3: - return 116666; - default: - return 0; - } -} +#include <console/console.h> +#if ENV_RAMSTAGE +#include <soc/ramstage.h> +#else +#include <soc/romstage.h> +#endif +#include <stdint.h> unsigned long tsc_freq_mhz(void) { - msr_t platform_info; - unsigned bclk_khz = bus_freq_khz(); - - if (!bclk_khz) - return 0; + msr_t ia_core_ratios; - platform_info = rdmsr(MSR_PLATFORM_INFO); - return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; + ia_core_ratios = rdmsr(MSR_IACORE_RATIOS); + return (BUS_FREQ_KHZ * ((ia_core_ratios.lo >> 16) & 0x3f)) / 1000; } #if !defined(__SMM__) -#if !defined(__PRE_RAM__) -#include <soc/ramstage.h> -#else -#include <soc/romstage.h> -#endif void set_max_freq(void) { @@ -68,12 +49,17 @@ void set_max_freq(void) msr.lo |= (1 << 16); wrmsr(MSR_IA32_MISC_ENABLES, msr); - /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of - * the PERF_CTL. */ + /* + * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of + * the PERF_CTL. + */ msr = rdmsr(MSR_IACORE_RATIOS); perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; - /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of - * the PERF_CTL. */ + + /* + * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of + * the PERF_CTL. + */ msr = rdmsr(MSR_IACORE_VIDS); perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c index 776e44c..f00f419 100644 --- a/src/soc/intel/braswell/xhci.c +++ b/src/soc/intel/braswell/xhci.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,221 +28,17 @@ #include <soc/iomap.h> #include <soc/iosf.h> -#include <soc/lpc.h> -#include <soc/pattrs.h> #include <soc/pci_devs.h> -#include <soc/pmc.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/xhci.h> #include "chip.h" -struct reg_script usb3_phy_script[] = { - /* USB3PHYInit() */ - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, - ~0x00700000, 0x00500000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, - ~0x001f0000, 0x000A0000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CCDRLF, - ~0x0000000f, 0x0000000b), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, - ~0x000000f0, 0x000000f0), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, - ~0x000001c0, 0x00000000), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, - ~0x00000070, 0x00000020), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, - ~0x00000002, 0x00000002), - REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, - ~0x00000000, 0x00040000), - REG_SCRIPT_END -}; - -const struct reg_script xhci_init_script[] = { - /* CommonXhciHcInit() */ - /* BAR + 0x0c[31:16] = 0x0200 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), - /* BAR + 0x0c[7:0] = 0x0a */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), - /* BAR + 0x8094[23,21,14]=111b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), - /* BAR + 0x8110[20,11,8,2]=1100b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), - /* BAR + 0x8144[8,7,6]=111b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), - /* BAR + 0x8154[21,13,3]=010b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), - /* BAR + 0x816c[19:0]=1110x100000000111100b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), - /* BAR + 0x8188[26,24]=11b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), - /* BAR + 0x8174=0x1000c0a*/ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a), - /* BAR + 0x854c[29]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0), - /* BAR + 0x8178[12:0]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0), - /* BAR + 0x8164[7:0]=0xff */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), - /* BAR + 0x0010[10,9,5]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), - /* BAR + 0x8058[20,16,8]=110b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), - /* BAR + 0x8060[25]=1b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), - /* BAR + 0x80f0[20]=0b */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), - /* BAR + 0x8008[19]=1b (to enable LPM) */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), - /* BAR + 0x80fc[25]=1b */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), - /* 0x40/0x44 are written as bytes to avoid touching bit31 */ - /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ - REG_PCI_RMW8(0x41, ~0x06, 0x01), - /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ - REG_PCI_RMW8(0x42, 0x3c, 0x04), - /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ - REG_PCI_RMW8(0x44, 0x00, 0x8f), - REG_PCI_RMW8(0x45, ~0xcf, 0xc6), - REG_PCI_RMW8(0x46, ~0x0f, 0x0f), - /* BAR + 0x8140 = 0xff00f03c */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), - REG_SCRIPT_END -}; - -const struct reg_script xhci_init_boot_script[] = { - /* Setup USB3 phy */ - REG_SCRIPT_NEXT(usb3_phy_script), - /* Initialize host controller */ - REG_SCRIPT_NEXT(xhci_init_script), - /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), - /* BAR + 0x80e0 toggle bit 24=0 */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), - REG_SCRIPT_END -}; - -const struct reg_script xhci_init_resume_script[] = { - /* Setup USB3 phy */ - REG_SCRIPT_NEXT(usb3_phy_script), - /* Initialize host controller */ - REG_SCRIPT_NEXT(xhci_init_script), - /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), - REG_SCRIPT_END -}; - -const struct reg_script xhci_clock_gating_script[] = { - /* ConfigureXhciClockGating() */ - /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ - REG_PCI_RMW16(0x40, ~0x0600, 0x0100), - REG_PCI_RMW8(0x42, ~0x38, 0x04), - /* D20:F0:44[5:3]=001b */ - REG_PCI_RMW16(0x44, ~0x0030, 0x0008), - /* D20:F0:A0[19:18]=01b */ - REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), - /* D20:F0:A4[15:0]=0x00 */ - REG_PCI_WRITE16(0xa4, 0x0000), - /* D20:F0:B0[21:17,14:13]=0000000b */ - REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), - /* D20:F0:50[31:0]=0x0bce6e5f */ - REG_PCI_WRITE32(0x50, 0x0bce6e5f), - REG_SCRIPT_END -}; - -/* Warm Reset a USB3 port */ -static void xhci_reset_port_usb3(device_t dev, int port) -{ - struct reg_script reset_port_usb3_script[] = { - /* Issue Warm Port Rest to the port */ - REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - XHCI_USB3_PORTSC_WPR), - /* Wait up to 100ms for it to complete */ - REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, - XHCI_RESET_TIMEOUT), - /* Clear change status bits, do not set PED */ - REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), - ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), - REG_SCRIPT_END - }; - reg_script_run_on_dev(dev, reset_port_usb3_script); -} - -/* Prepare ports to be routed to EHCI or XHCI */ -static void xhci_route_all(device_t dev) -{ - static const struct reg_script xhci_route_all_script[] = { - /* USB3 SuperSpeed Enable */ - REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), - /* USB2 Port Route to XHCI */ - REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP), - REG_SCRIPT_END - }; - u32 port_disabled; - int port; - - printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); - - /* Route ports to XHCI controller */ - reg_script_run_on_dev(dev, xhci_route_all_script); - - if (acpi_is_wakeup_s3()) - return; - - /* Reset enabled USB3 ports */ - port_disabled = pci_read_config32(dev, XHCI_USB3PDO); - for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { - if (port_disabled & (1 << port)) - continue; - xhci_reset_port_usb3(dev, port); - } -} - static void xhci_init(device_t dev) { - struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script xhci_hc_init[] = { - /* Initialize clock gating */ - REG_SCRIPT_NEXT(xhci_clock_gating_script), - /* Finalize XHCC1 and XHCC2 */ - REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), - REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), - /* Set USB2 Port Routing Mask */ - REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), - /* Set USB3 Port Routing Mask */ - REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), - /* - * Disable ports if requested - */ - /* Open per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), - REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), - REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), - /* Close per-port disable control override */ - REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), - REG_SCRIPT_END - }; - - /* Initialize XHCI controller for boot or resume path */ - if (acpi_is_wakeup_s3()) - reg_script_run_on_dev(dev, xhci_init_resume_script); - else - reg_script_run_on_dev(dev, xhci_init_boot_script); - - /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ - if (pattrs_get()->stepping == STEP_C0) { - uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); - reg |= 0x00700000; - iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); - } - - /* Finalize Initialization */ - reg_script_run_on_dev(dev, xhci_hc_init); - - /* Route all ports to XHCI if requested */ - if (config->usb_route_to_xhci) - xhci_route_all(dev); + printk(BIOS_SPEW, "%s/%s ( %s )\n", + __FILE__, __func__, dev_name(dev)); } static struct device_operations xhci_device_ops = { @@ -252,7 +49,7 @@ static struct device_operations xhci_device_ops = { .ops_pci = &soc_pci_ops, }; -static const struct pci_driver baytrail_xhci __pci_driver = { +static const struct pci_driver braswell_xhci __pci_driver = { .ops = &xhci_device_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = XHCI_DEVID

1 0

Patch set updated for coreboot: 712f453 Intel Common SOC: Add romstage support
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10050 -gerrit commit 712f4537b84dcd3c52ebabcb1e936cf79fe6e14c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:24:54 2015 -0700 Intel Common SOC: Add romstage support Provide a common romstage implementation for the Intel SOCs. BRANCH=none BUG=None TEST=Build for Braswell Change-Id: I80f5f8f0f36e9023117b07d4af5c806fff8157b6 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/common/Kconfig | 38 ++++ src/soc/intel/common/Makefile.inc | 12 +- src/soc/intel/common/fsp_ramstage.c | 154 +++++++++++++++ src/soc/intel/common/gma.h | 176 +++++++++++++++++ src/soc/intel/common/hda_verb.c | 2 +- src/soc/intel/common/memmap.h | 33 ++++ src/soc/intel/common/mrc_cache.c | 4 +- src/soc/intel/common/raminit.c | 275 +++++++++++++++++++++++++++ src/soc/intel/common/ramstage.h | 36 ++++ src/soc/intel/common/romstage.c | 365 ++++++++++++++++++++++++++++++++++++ src/soc/intel/common/romstage.h | 102 ++++++++++ src/soc/intel/common/spi_loading.c | 152 +++++++++++++++ src/soc/intel/common/stack.c | 168 +++++++++++++++++ src/soc/intel/common/stack.h | 35 ++++ src/soc/intel/common/stage_cache.c | 39 ++++ src/soc/intel/common/vbt.c | 47 +++++ 16 files changed, 1633 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8b5cef3..6dd1f57 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -3,6 +3,8 @@ config SOC_INTEL_COMMON help common code for Intel SOCs +if SOC_INTEL_COMMON + if HAVE_MRC config CACHE_MRC_SETTINGS @@ -27,6 +29,42 @@ endif # CACHE_MRC_SETTINGS endif # HAVE_MRC +config CHIPSET_RESERVED_MEM_BYTES + hex "Size in bytes of chipset reserved memory area" + default 0 + help + If insufficient documentation is available to determine the size of + the chipset reserved memory area by walking the chipset registers, + the CHIPSET_RESERVED_MEM_BYTES may be used as a workaround to account + for the missing pieces of memory. The value specified in bytes is: + + value = TSEG base - top of low usable memory - (any sizes determined + by reading chipset registers) + +config SOC_INTEL_COMMON_FSP_RAM_INIT + bool "FSP: Use the common raminit.c module" + default n + depends on PLATFORM_USES_FSP1_1 + +config SOC_INTEL_COMMON_FSP_ROMSTAGE + bool + default n + config SOC_INTEL_COMMON_RESET bool default n + +config SOC_INTEL_COMMON_STACK + bool + default n + +config SOC_INTEL_COMMON_STAGE_CACHE + bool + default n + +config ROMSTAGE_RAM_STACK_SIZE + hex "Size of the romstage RAM stack in bytes" + default 0x5000 + depends on SOC_INTEL_COMMON_STACK + +endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 6d40aa7..799b085 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,10 +1,18 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_RAM_INIT) += raminit.c +romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOC_INTEL_COMMON_FSP_ROMSTAGE) += romstage.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STACK) += stack.c +romstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c +romstage-$(CONFIG_GOP_SUPPORT) += vbt.c + +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp_ramstage.c ramstage-y += hda_verb.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += nvm.c ramstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c -romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c -romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c endif diff --git a/src/soc/intel/common/fsp_ramstage.c b/src/soc/intel/common/fsp_ramstage.c new file mode 100644 index 0000000..2bab2de --- /dev/null +++ b/src/soc/intel/common/fsp_ramstage.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp_util.h> +#include <romstage_handoff.h> +#include <soc/intel/common/ramstage.h> +#include <stage_cache.h> +#include <timestamp.h> + +/* SOC initialization after FSP silicon init */ +__attribute__((weak)) void soc_after_silicon_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +__attribute__((weak)) void soc_save_support_code(void *start, size_t size, + void *entry) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +__attribute__((weak)) void *soc_restore_support_code(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return NULL; +} + +static void fsp_run_silicon_init(void) +{ + FSP_INFO_HEADER *fsp_info_header; + FSP_SILICON_INIT fsp_silicon_init; + EFI_STATUS status; + + /* Find the FSP image */ + fsp_info_header = fsp_get_fih(); + if (fsp_info_header == NULL) { + printk(BIOS_ERR, "FSP_INFO_HEADER not set!\n"); + return; + } + + /* Perform silicon initialization after RAM is configured */ + printk(BIOS_DEBUG, "Calling FspSiliconInit\n"); + fsp_silicon_init = (FSP_SILICON_INIT)(fsp_info_header->ImageBase + + fsp_info_header->FspSiliconInitEntryOffset); + timestamp_add_now(TS_FSP_SILICON_INIT_START); + status = fsp_silicon_init(NULL); + timestamp_add_now(TS_FSP_SILICON_INIT_END); + printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status); + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + /* Verify the HOBs */ + const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; + void *hob_list_ptr = get_hob_list(); + int missing_hob = 0; + + if (hob_list_ptr == NULL) + die("ERROR - HOB pointer is NULL!\n"); + print_hob_type_structure(0, hob_list_ptr); + + /* + * Verify that FSP is generating the required HOBs: + * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 + * 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified by raminit + * 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified by raminit + * 7.4: FSP_BOOTLOADER_TOLUM_HOB verified by raminit + */ + if (NULL == get_next_guid_hob(&graphics_info_guid, hob_list_ptr)) { + printk(BIOS_ERR, "7.5: EFI_PEI_GRAPHICS_INFO_HOB missing!\n"); + missing_hob = 1; + } + if (missing_hob) + die("ERROR - Missing one or more required FSP HOBs!\n"); +#endif + + soc_after_silicon_init(); +} + +static void fsp_cache_save(void) +{ + const struct cbmem_entry *fsp_entry; + FSP_INFO_HEADER *fih; + + fsp_entry = cbmem_entry_find(CBMEM_ID_REFCODE); + + if (fsp_entry == NULL) { + printk(BIOS_ERR, "ERROR: FSP not found in CBMEM.\n"); + return; + } + + fih = fsp_get_fih(); + + if (fih == NULL) { + printk(BIOS_ERR, "ERROR: No FIH found.\n"); + return; + } + + soc_save_support_code(cbmem_entry_start(fsp_entry), + cbmem_entry_size(fsp_entry), fih); +} + +static int fsp_find_and_relocate(void) +{ + struct cbfs_file *file; + void *fih; + + file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "fsp.bin"); + + if (file == NULL) { + printk(BIOS_ERR, "Couldn't find fsp.bin in CBFS.\n"); + return -1; + } + + fih = fsp_relocate(CBFS_SUBHEADER(file), ntohl(file->len)); + + fsp_update_fih(fih); + + return 0; +} + +void intel_silicon_init(void) +{ + struct romstage_handoff *handoff; + + handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + + if (handoff != NULL && handoff->s3_resume) + fsp_update_fih(soc_restore_support_code()); + else { + fsp_find_and_relocate(); + fsp_cache_save(); + } + + fsp_run_silicon_init(); +} diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..9666147 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ + diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 2523b41..04c5977 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -72,7 +72,7 @@ int hda_codec_detect(u8 *base) /* Clear the "State Change Status Register" STATESTS bits * for each of the "SDIN Stat Change Status Flag" - */ + */ write8(base + HDA_STATESTS_REG, 0xf); /* Turn off the link and poll RESET# bit until it reads back as 0 */ diff --git a/src/soc/intel/common/memmap.h b/src/soc/intel/common/memmap.h new file mode 100644 index 0000000..840b51e --- /dev/null +++ b/src/soc/intel/common/memmap.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_MEMMAP_H_ +#define _COMMON_MEMMAP_H_ + +#include <types.h> + +/* + * mmap_region_granluarity must to return a size which is a positive non-zero + * integer multiple of the SMM size when SMM is in use. When not using SMM, + * this value should be set to 8 MiB. + */ +size_t mmap_region_granluarity(void); +void smm_region(void **start, size_t *size); + +#endif /* _COMMON_MEMMAP_H_ */ diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index f854046..018b757 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -149,7 +149,7 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache) return __mrc_cache_get_current(&region, cache); } -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE /* * romstage code @@ -326,4 +326,4 @@ static void update_mrc_cache(void *unused) BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); -#endif /* defined(__PRE_RAM__) */ +#endif /* ENV_ROMSTAGE */ diff --git a/src/soc/intel/common/raminit.c b/src/soc/intel/common/raminit.c new file mode 100644 index 0000000..16f991b --- /dev/null +++ b/src/soc/intel/common/raminit.c @@ -0,0 +1,275 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> /* hexdump */ +#include <reset.h> +#include <soc/intel/common/memmap.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <string.h> +#include <timestamp.h> + +void raminit(struct romstage_params *params) +{ + const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; + EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root; + FSP_INFO_HEADER *fsp_header; + EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory; + FSP_MEMORY_INIT fsp_memory_init; + FSP_MEMORY_INIT_PARAMS fsp_memory_init_params; + const EFI_GUID fsp_reserved_guid = + FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID; + void *fsp_reserved_memory_area; + FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer; + void *hob_list_ptr; + const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + u32 *mrc_hob; + u32 fsp_reserved_bytes; + EFI_STATUS status; + struct pei_data *pei_ptr; + VPD_DATA_REGION *vpd_ptr; + UPD_DATA_REGION *upd_ptr; + UPD_DATA_REGION upd_data_buffer; + int fsp_verification_failure = 0; +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + unsigned long int data; + EFI_PEI_HOB_POINTERS hob_ptr; +#endif + + /* + * Find and copy the UPD region to the stack so the platform can modify + * the settings if needed. Modifications to the UPD buffer are done in + * the platform callback code. The platform callback code is also + * responsible for assigning the UpdDataRngPtr to this buffer if any + * updates are made. The default state is to leave the UpdDataRngPtr + * set to NULL. This indicates that the FSP code will use the UPD + * region in the FSP binary. + */ + post_code(0x34); + fsp_header = params->chipset_context; + vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset + + fsp_header->ImageBase); + printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr); + upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset + + fsp_header->ImageBase); + printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr); + memcpy(&upd_data_buffer, upd_ptr, sizeof(upd_data_buffer)); + + /* Zero fill RT Buffer data and start populating fields. */ + memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer)); + pei_ptr = params->pei_data; + if (pei_ptr->boot_mode == SLEEP_STATE_S3) { + fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME; + } else if (pei_ptr->saved_data != NULL) { + fsp_rt_common_buffer.BootMode = + BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; + } else { + fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + fsp_rt_common_buffer.UpdDataRgnPtr = &upd_data_buffer; + fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size(); + + /* Get any board specific changes */ + fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data; + fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer; + fsp_memory_init_params.HobListPtr = &hob_list_ptr; + board_fsp_memory_init_params(params, fsp_header, + &fsp_memory_init_params); + post_code(0x36); + + /* Display the UPD data */ +#if IS_ENABLED(CONFIG_DISPLAY_UPD_DATA) + printk(BIOS_SPEW, "Updated Product Data (UPD):\n"); + hexdump32(BIOS_SPEW, (void *)&upd_data_buffer, sizeof(upd_data_buffer)); +#endif + + /* Call FspMemoryInit to initialize RAM */ + fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase + + fsp_header->FspMemoryInitEntryOffset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); + printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n", + fsp_memory_init_params.NvsBufferPtr); + printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n", + fsp_memory_init_params.RtBufferPtr); + printk(BIOS_SPEW, " 0x%p: HobListPtr\n", + fsp_memory_init_params.HobListPtr); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_memory_init(&fsp_memory_init_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + if (status != EFI_SUCCESS) + die("ERROR - FspMemoryInit failed to initialize memory!\n"); + + /* Locate the FSP reserved memory area */ + fsp_reserved_bytes = 0; + fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr); + if (fsp_memory == NULL) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, + "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n"); + } else { + fsp_reserved_bytes = fsp_memory->ResourceLength; + printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n", + (unsigned long int)fsp_reserved_bytes); + } + + /* Display SMM area */ +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + char *smm_base; + size_t smm_size; + + smm_region((void **)&smm_base, &smm_size); + printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size); + printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base); +#endif + + /* Migrate CAR data */ + printk(BIOS_DEBUG, "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", + CONFIG_CHIPSET_RESERVED_MEM_BYTES); + printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top()); + if (pei_ptr->boot_mode != SLEEP_STATE_S3) { + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_reserved_bytes); + } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_reserved_bytes)) { +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + hard_reset(); +#endif + } + + /* Save the FSP runtime parameters. */ + fsp_set_runtime(params->chipset_context, hob_list_ptr); + + /* Lookup the FSP_BOOTLOADER_TOLUM_HOB */ + cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr); + if (cbmem_root == NULL) { + fsp_verification_failure = 1; + printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n"); + printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n", + fsp_rt_common_buffer.BootLoaderTolumSize); + } + +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + if (hob_list_ptr == NULL) + die("ERROR - HOB pointer is NULL!\n"); + + /* + * Verify that FSP is generating the required HOBs: + * 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0 + * 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit + */ + if (NULL != cbmem_root) { + printk(BIOS_DEBUG, + "7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n", + cbmem_root); + data = cbmem_root->PhysicalStart; + printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); + data = cbmem_root->ResourceLength; + printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + } + hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); + if (NULL == hob_ptr.Raw) { + printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); + fsp_verification_failure = + (params->pei_data->saved_data == NULL) ? 1 : 0; + } else { + printk(BIOS_DEBUG, + "7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n", + hob_ptr.Raw); + } + if (fsp_memory != NULL) { + printk(BIOS_DEBUG, + "7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n", + fsp_memory); + data = fsp_memory->PhysicalStart; + printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data); + data = fsp_memory->ResourceLength; + printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data); + } + + /* Verify all the HOBs are present */ + if (fsp_verification_failure) + printk(BIOS_DEBUG, + "ERROR - Missing one or more required FSP HOBs!\n"); + + /* Display the HOBs */ + print_hob_type_structure(0, hob_list_ptr); +#endif + + /* Get the address of the CBMEM region for the FSP reserved memory */ + fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); + printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n", + fsp_reserved_memory_area); + + /* Verify the order of CBMEM root and FSP memory */ + if ((fsp_memory != NULL) && (cbmem_root != NULL) && + (cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, + "ERROR - FSP reserved memory above CBMEM root!\n"); + } + + /* Verify that the FSP memory was properly reserved */ + if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) || + (fsp_memory->PhysicalStart != + (unsigned int)fsp_reserved_memory_area))) { + fsp_verification_failure = 1; + printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n"); +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + if (cbmem_root != NULL) { + size_t delta_bytes = (unsigned int)smm_base + - cbmem_root->PhysicalStart + - cbmem_root->ResourceLength; + printk(BIOS_DEBUG, + "0x%08x: CONFIG_CHIPSET_RESERVED_MEM_BYTES\n", + CONFIG_CHIPSET_RESERVED_MEM_BYTES); + printk(BIOS_DEBUG, + "0x%08x: Chipset reserved bytes reported by FSP\n", + (unsigned int)delta_bytes); + die("Please verify the chipset reserved size\n"); + } +#endif + } + + /* Verify the FSP 1.1 HOB interface */ + if (fsp_verification_failure) + die("ERROR - Coreboot's requirements not met by FSP binary!\n"); + + /* Display the memory configuration */ + report_memory_config(); + + /* Locate the memory configuration data to speed up the next reboot */ + mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); + if (mrc_hob == NULL) + printk(BIOS_DEBUG, + "Memory Configuration Data Hob not present\n"); + else { + pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob); + pei_ptr->data_to_save_size = ALIGN( + ((u32)GET_HOB_LENGTH(mrc_hob)), 16); + } +} diff --git a/src/soc/intel/common/ramstage.h b/src/soc/intel/common/ramstage.h new file mode 100644 index 0000000..e46f108 --- /dev/null +++ b/src/soc/intel/common/ramstage.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_RAMSTAGE_H_ +#define _INTEL_COMMON_RAMSTAGE_H_ + +#include <stdint.h> + +/* Perform Intel silicon init. */ +void intel_silicon_init(void); +/* Called after the silicon init code has run. */ +void soc_after_silicon_init(void); +/* SoC implementation for caching support code. */ +void soc_save_support_code(void *start, size_t size, void *entry); +/* SoC implementation for restoring support code after S3 resume. Returns + * previously passed entry pointer from soc_save_support_code(). */ +void *soc_restore_support_code(void); + +#endif /* _INTEL_COMMON_RAMSTAGE_H_ */ diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c new file mode 100644 index 0000000..0bb5a86 --- /dev/null +++ b/src/soc/intel/common/romstage.c @@ -0,0 +1,365 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/cbfs.h> +#include <arch/stages.h> +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <elog.h> +#include <reset.h> +#include <romstage_handoff.h> +#include <soc/intel/common/mrc_cache.h> +#include <soc/pei_wrapper.h> +#include <soc/pm.h> +#include <soc/romstage.h> +#include <soc/spi.h> +#include <stage_cache.h> +#include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Entry from cache-as-ram.inc. */ +asmlinkage void *romstage_main(unsigned int bist, + uint32_t tsc_low, uint32_t tsc_high, + void *chipset_context) +{ + void *top_of_stack; + struct pei_data pei_data; + struct romstage_params params = { + .bist = bist, + .pei_data = &pei_data, + .chipset_context = chipset_context, + }; + + post_code(0x30); + + /* Save timestamp data */ + timestamp_init((((uint64_t)tsc_high) << 32) | (uint64_t)tsc_low); + timestamp_add_now(TS_START_ROMSTAGE); + + memset(&pei_data, 0, sizeof(pei_data)); + + /* Call into pre-console init code. */ + soc_pre_console_init(&params); + mainboard_pre_console_init(&params); + + /* Start console drivers */ + console_init(); + + /* Display parameters */ + printk(BIOS_SPEW, "bist: 0x%08x\n", bist); + printk(BIOS_SPEW, "tsc_low: 0x%08x\n", tsc_low); + printk(BIOS_SPEW, "tsc_hi: 0x%08x\n", tsc_high); + printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", + CONFIG_MMCONF_BASE_ADDRESS); + printk(BIOS_INFO, "Using: %s\n", + IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) ? "FSP 1.1" : + (IS_ENABLED(CONFIG_HAVE_MRC) ? "MRC" : + "No Memory Support")); + + /* Display FSP banner */ +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + print_fsp_info(params.chipset_context); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + + /* Get power state */ + params.power_state = fill_power_state(); + + /* Print useful platform information */ + report_platform_info(); + + /* Set CPU frequency to maximum */ + set_max_freq(); + + /* Perform SOC specific initialization. */ + soc_romstage_init(&params); + +#if IS_ENABLED(CONFIG_GOP_SUPPORT) + /* Locate VBT and pass to FSP GOP */ + load_vbt(&params); +#endif + /* Call into mainboard. */ + mainboard_romstage_entry(&params); + soc_after_ram_init(&params); + post_code(0x38); + + top_of_stack = setup_stack_and_mtrrs(); + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) + printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + + return top_of_stack; +} + +/* Entry from the mainboard. */ +void romstage_common(struct romstage_params *params) +{ + const struct mrc_saved_data *cache; + struct romstage_handoff *handoff; + struct pei_data *pei_data; + + post_code(0x32); + + timestamp_add_now(TS_BEFORE_INITRAM); + + pei_data = params->pei_data; + pei_data->boot_mode = params->power_state->prev_sleep_state; + +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) + if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) + boot_count_increment(); +#endif + + /* Perform remaining SOC initialization */ + soc_pre_ram_init(params); + post_code(0x33); + + /* Check recovery and MRC cache */ + params->pei_data->saved_data_size = 0; + params->pei_data->saved_data = NULL; + if (!params->pei_data->disable_saved_data) { + if (recovery_mode_enabled()) { + /* Recovery mode does not use MRC cache */ + printk(BIOS_DEBUG, + "Recovery mode: not using MRC cache.\n"); + } else if (!mrc_cache_get_current(&cache)) { + /* MRC cache found */ + params->pei_data->saved_data_size = cache->size; + params->pei_data->saved_data = &cache->data[0]; + } else if (params->pei_data->boot_mode == SLEEP_STATE_S3) { + /* Waking from S3 and no cache. */ + printk(BIOS_DEBUG, + "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + hard_reset(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); + mainboard_check_ec_image(params); + } + } + + /* Initialize RAM */ + raminit(params); + timestamp_add_now(TS_AFTER_INITRAM); + + /* Save MRC output */ + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, + pei_data->data_to_save_size); + if (params->pei_data->boot_mode != SLEEP_STATE_S3) { + if (params->pei_data->data_to_save_size != 0 && + params->pei_data->data_to_save != NULL) { + mrc_cache_stash_data(params->pei_data->data_to_save, + params->pei_data->data_to_save_size); + } + } + + /* Save DIMM information */ + mainboard_save_dimm_info(params); + + /* Create romstage handof information */ + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (params->power_state->prev_sleep_state == + SLEEP_STATE_S3); + else { + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + hard_reset(); + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + /* Normalize the sleep state to what init_chromeos() wants for S3: 2 */ + init_chromeos((params->power_state->prev_sleep_state == SLEEP_STATE_S3) + ? 2 : 0); +#endif +} + +asmlinkage void romstage_after_car(void *chipset_context) +{ + if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); + printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); + soc_after_temp_ram_exit(); + } + + timestamp_add_now(TS_END_ROMSTAGE); + + /* Load the ramstage. */ + copy_and_run(); + die("ERROR - Failed to load ramstage!"); +} + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +__attribute__((weak)) void board_fsp_memory_init_params( + struct romstage_params *params, + FSP_INFO_HEADER *fsp_header, + FSP_MEMORY_INIT_PARAMS * fsp_memory_init_params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ + +/* Initialize the power state */ +__attribute__((weak)) struct chipset_power_state *fill_power_state(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return NULL; +} + +__attribute__((weak)) void mainboard_check_ec_image( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + struct pei_data *pei_data; + + pei_data = params->pei_data; + if (params->pei_data->boot_mode == SLEEP_STATE_S0) { + /* Ensure EC is running RO firmware. */ + google_chromeec_check_ec_image(EC_IMAGE_RO); + } +#endif +} + +/* Board initialization before the console is enabled */ +__attribute__((weak)) void mainboard_pre_console_init( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Board initialization before and after RAM is enabled */ +__attribute__((weak)) void mainboard_romstage_entry( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + + post_code(0x31); + + /* Initliaze memory */ + romstage_common(params); +} + +/* Used by MRC images to save DIMM information */ +__attribute__((weak)) void mainboard_save_dimm_info( + struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Get the memory configuration data */ +__attribute__((weak)) int mrc_cache_get_current( + const struct mrc_saved_data **cache) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +/* Save the memory configuration data */ +__attribute__((weak)) int mrc_cache_stash_data(void *data, size_t size) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + return -1; +} + +/* Transition RAM from off or self-refresh to active */ +__attribute__((weak)) void raminit(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + post_code(0x34); + die("ERROR - No RAM initialization specified!\n"); +} + +void ramstage_cache_invalid(void) +{ +#if IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) + /* Perform cold reset on invalid ramstage cache. */ + hard_reset(); +#endif +} + +/* Display the memory configuration */ +__attribute__((weak)) void report_memory_config(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Display the platform configuration */ +__attribute__((weak)) void report_platform_info(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* Choose top of stack and setup MTRRs */ +__attribute__((weak)) void *setup_stack_and_mtrrs(void) +{ + printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__); + die("ERROR - Must specify top of stack!\n"); + return NULL; +} + +/* Speed up the CPU to the maximum frequency */ +__attribute__((weak)) void set_max_freq(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after RAM is enabled */ +__attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after temporary RAM is disabled */ +__attribute__((weak)) void soc_after_temp_ram_exit(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization before the console is enabled */ +__attribute__((weak)) void soc_pre_console_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization before RAM is enabled */ +__attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} + +/* SOC initialization after console is enabled */ +__attribute__((weak)) void soc_romstage_init(struct romstage_params *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); +#endif +} diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h new file mode 100644 index 0000000..247a1c2 --- /dev/null +++ b/src/soc/intel/common/romstage.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_ROMSTAGE_H_ +#define _COMMON_ROMSTAGE_H_ + +#include <stdint.h> +#include <arch/cpu.h> +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp_util.h> +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +#include <soc/pei_data.h> +#include <soc/pm.h> /* chip_power_state */ + +struct romstage_params { + unsigned long bist; + struct chipset_power_state *power_state; + struct pei_data *pei_data; + void *chipset_context; +}; + +/* + * FSP Boot Flow: + * 1. src/cpu/x86/16bit/reset.inc + * 2. src/cpu/x86/16bit/entry.inc + * 3. other modules + * 4. src/drivers/intel/fsp1_1/cache_as_ram.inc + * 5. src/drivers/intel/fsp1_1/fsp_util.c/find_fsp + * 6. FSP binary/TempRamInit + * 7. src/drivers/intel/fsp1_1/cache_as_ram.inc - return + * 8. src/soc/intel/common/romstage.c/romstage_main + * 9 src/soc/.../romstage/.../soc_pre_console_init + * 10 src/console/console.c/console_init + * 11 src/soc/.../romstage/.../soc_romstage_init + * 12. src/mainboard/.../romstage.c/mainboard_romstage_entry + * 13. src/soc/intel/common/romstage.c/romstage_common + * 14 src/soc/.../romstage/.../soc_pre_raminit + * 15. FSP binary/MemoryInit + * 16. src/soc/intel/common/romstage.c/romstage_common - return + * 17. src/mainboard/.../romstage.c/mainboard_romstage_entry - return + * 18. src/soc/intel/common/romstage.c/romstage_main - return + * 19. src/soc/intel/common/stack.c/setup_stack_and_mttrs + * 20. src/drivers/intel/fsp1_1/cache_as_ram.inc - return, cleanup + * after call to romstage_main + * 21. FSP binary/TempRamExit + * 22. src/soc/intel/common/romstage.c/romstage_after_car + * 23. FSP binary/SiliconInit + * 24. src/soc/intel/common/romstage.c/romstage_after_car - return + * 25. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback + * 26. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify + * 27. FSP binary/FspNotify + * 28. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify_boot_state_callback + * 29. src/drivers/intel/fsp1_1/fsp_util.c/fsp_notify + * 30. FSP binary/FspNotify + */ + +#if IS_ENABLED(CONFIG_GOP_SUPPORT) +void load_vbt(struct romstage_params *params); +#endif +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +void board_fsp_memory_init_params( + struct romstage_params *params, + FSP_INFO_HEADER *fsp_header, + FSP_MEMORY_INIT_PARAMS * fsp_memory_init_params); +#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ +void mainboard_check_ec_image(struct romstage_params *params); +void mainboard_pre_console_init(struct romstage_params *params); +void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_save_dimm_info(struct romstage_params *params); +void raminit(struct romstage_params *params); +void report_memory_config(void); +void report_platform_info(void); +asmlinkage void romstage_after_car(void *chipset_context); +void romstage_common(struct romstage_params *params); +asmlinkage void *romstage_main(unsigned int bist, uint32_t tsc_lo, + uint32_t tsc_high, void *chipset_context); +void *setup_stack_and_mtrrs(void); +void set_max_freq(void); +void soc_after_ram_init(struct romstage_params *params); +void soc_after_temp_ram_exit(void); +void soc_pre_console_init(struct romstage_params *params); +void soc_pre_ram_init(struct romstage_params *params); +void soc_romstage_init(struct romstage_params *params); + +#endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/soc/intel/common/spi_loading.c b/src/soc/intel/common/spi_loading.c new file mode 100644 index 0000000..fe3522b --- /dev/null +++ b/src/soc/intel/common/spi_loading.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/byteorder.h> +#include <boot/coreboot_tables.h> +#include <cbmem.h> +#include <cbfs.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define CACHELINE_SIZE 64 +#define INTRA_CACHELINE_MASK (CACHELINE_SIZE - 1) +#define CACHELINE_MASK (~INTRA_CACHELINE_MASK) + +static void *find_mirror_buffer(int len) +{ + int nentries; + int i; + struct lb_memory *mem; + void *buffer; + + len = ALIGN(len, 4096); + + mem = get_lb_mem(); + nentries = (mem->size - sizeof(*mem)) / sizeof(mem->map[0]); + + /* + * Find the highest RAM entry that accommodates the lenth provide + * while falling below 4GiB. + */ + buffer = NULL; + for (i = 0; i < nentries; i++) { + const uint64_t max_addr = 1ULL << 32; + uint64_t start; + uint64_t size; + struct lb_memory_range *r; + + r = &mem->map[i]; + + if (r->type != LB_MEM_RAM) + continue; + + start = unpack_lb64(r->start); + if (start >= max_addr) + continue; + + size = unpack_lb64(r->size); + if (size < len) + continue; + + /* Adjust size of buffer if range exceeds max address. */ + if (start + size > max_addr) + size = max_addr - start; + + if (size < len) + continue; + + buffer = (void *)(uintptr_t)(start + size - len); + } + + return buffer; +} + +/* + * Mirror the payload file to the default SMM location if it is small enough. + * The default SMM region can be used since no one is using the memory at this + * location at this stage in the boot. + */ +static void *spi_mirror(void *file_start, int file_len) +{ + int alignment_diff; + char *src; + char *dest; + + alignment_diff = (INTRA_CACHELINE_MASK & (long)file_start); + + /* + * Adjust file length so that the start and end points are aligned to a + * cacheline. Coupled with the ROM caching in the CPU the SPI hardware + * will read and cache full length cachelines. It will also prefetch + * data as well. Once things are mirrored in memory all accesses should + * hit the CPUs cache. + */ + file_len += alignment_diff; + file_len = ALIGN(file_len, CACHELINE_SIZE); + + printk(BIOS_DEBUG, "Payload aligned size: 0x%x\n", file_len); + + dest = find_mirror_buffer(file_len); + + /* + * Just pass back the pointer to ROM space if a buffer could not + * be found to mirror into. + */ + if (dest == NULL) + return file_start; + + src = (void *)(CACHELINE_MASK & (long)file_start); + /* + * Note that if mempcy is not using 32-bit moves the performance will + * degrade because the SPI hardware prefetchers look for + * cacheline-aligned 32-bit accesses to kick in. + */ + memcpy(dest, src, file_len); + + /* Provide pointer into mirrored space. */ + return &dest[alignment_diff]; +} + +void *cbfs_load_payload(struct cbfs_media *media, const char *name) +{ + int file_len; + void *file_start; + struct cbfs_file *file; + + file_start = vboot_get_payload(&file_len); + + if (file_start != NULL) + return spi_mirror(file_start, file_len); + + file = cbfs_get_file(media, name); + + if (file == NULL) + return NULL; + + if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) + return NULL; + + file_len = ntohl(file->len); + + file_start = CBFS_SUBHEADER(file); + + return spi_mirror(file_start, file_len); +} diff --git a/src/soc/intel/common/stack.c b/src/soc/intel/common/stack.c new file mode 100644 index 0000000..03cf30c --- /dev/null +++ b/src/soc/intel/common/stack.c @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include "memmap.h" +#include "romstage.h" +#include "stack.h" +#include <stdlib.h> + +const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; + +/* + * Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. + */ +static unsigned long choose_top_of_stack(void) +{ + unsigned long stack_top; + + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + romstage_ram_stack_size); + stack_top += romstage_ram_stack_size; + return stack_top; +} + +/* + * setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. + */ +void *setup_stack_and_mtrrs(void) +{ + size_t alignment; + uint32_t aligned_ram; + uint32_t mtrr_mask_upper; + int num_mtrrs; + uint32_t *slot; + unsigned long top_of_stack; + + /* Top of stack needs to be aligned to a 8-byte boundary. */ + top_of_stack = choose_top_of_stack(); + slot = (void *)top_of_stack; + num_mtrrs = 0; + + /* + * The upper bits of the MTRR mask need to set according to the number + * of physical address bits. + */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + + /* + * The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * +0: Number of MTRRs + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 + */ + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* + * +-------------------------+ Top of RAM (aligned) + * | System Management Mode | + * | code and data | Length: CONFIG_TSEG_SIZE + * | (TSEG) | + * +-------------------------+ SMM base (aligned) + * | | + * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | | + * +-------------------------+ top_of_ram (aligned) + * | | + * | CBMEM Root | + * | | + * +-------------------------+ + * | | + * | FSP Reserved Memory | + * | | + * +-------------------------+ + * | | + * | Various CBMEM Entries | + * | | + * +-------------------------+ top_of_stack (8 byte aligned) + * | | + * | stack (CBMEM Entry) | + * | | + * +-------------------------+ + */ + + /* + * Cache the stack and the other CBMEM entries as well as part or all + * of the FSP reserved memory region. + */ + alignment = mmap_region_granluarity(); + aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size, + alignment); + + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) + void *smm_base; + size_t smm_size; + uint32_t tseg_base; + + /* + * Cache the TSEG region at the top of ram. This region is not + * restricted to SMM mode until SMM has been relocated. By setting + * the region to cacheable it provides faster access when relocating + * the SMM handler as well as using the TSEG region for other purposes. + */ + smm_region(&smm_base, &smm_size); + tseg_base = (uint32_t)smm_base; + slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push32(slot, ~(alignment - 1) | MTRRphysMaskValid); + slot = stack_push32(slot, 0); /* upper base */ + slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK); + num_mtrrs++; +#endif + + /* + * Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + slot = stack_push32(slot, num_mtrrs); + return slot; +} + diff --git a/src/soc/intel/common/stack.h b/src/soc/intel/common/stack.h new file mode 100644 index 0000000..850a070 --- /dev/null +++ b/src/soc/intel/common/stack.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _COMMON_STACK_H_ +#define _COMMON_STACK_H_ + +#include <stdint.h> + +static inline void *stack_push32(void *stack, uint32_t value) +{ + uint32_t *stack32 = stack; + + stack32 = &stack32[-1]; + *stack32 = value; + return stack32; +} + +#endif /* _COMMON_STACK_H_ */ diff --git a/src/soc/intel/common/stage_cache.c b/src/soc/intel/common/stage_cache.c new file mode 100644 index 0000000..2dd4e47 --- /dev/null +++ b/src/soc/intel/common/stage_cache.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <soc/intel/common/memmap.h> +#include <soc/smm.h> +#include <stage_cache.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + size_t smm_size; + const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* + * The ramstage cache lives in the TSEG region. + * The top of ram is defined to be the TSEG base address. + */ + smm_region((void **)&smm_base, &smm_size); + *size = cache_size; + *base = (void *)(&smm_base[smm_size - cache_size]); +} diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c new file mode 100644 index 0000000..8137fb3 --- /dev/null +++ b/src/soc/intel/common/vbt.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include <fsp_util.h> +#include <lib.h> +#include <soc/romstage.h> +#include <string.h> + +/* Locate VBT and pass it to FSP GOP */ +void load_vbt(struct romstage_params *rp) +{ + void *vbt_content; + uint32_t vbt_len; + struct pei_data *ps = rp->pei_data; + + /* Check boot mode - for S3 resume path VBT loading is not needed */ + if (rp->power_state->prev_sleep_state != SLEEP_STATE_S3) { + /* Get VBT data */ + vbt_content = (void *)fsp_get_vbt(&vbt_len); + if (vbt_content != NULL) { + ps->vbt_data = vbt_content; + printk(BIOS_DEBUG, "Find and pass VBT to GOP\n"); + } + } else { + ps->vbt_data = NULL; + printk(BIOS_DEBUG, "S3 resume do not pass VBT to GOP\n"); + } +}

1 0

Patch set updated for coreboot: fd3a77e drivers/intel: Update FSP 1.1 Driver
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10049 -gerrit commit fd3a77ea79b551bf83a9e66f00d78337b86a62bf Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Apr 20 15:29:16 2015 -0700 drivers/intel: Update FSP 1.1 Driver Update the FSP driver files from 1.0 to 1.1. Updates will occur manually to these files only for FSP 1.1 support. An fsp_x_y should be added in the future to support newer versions of the FSP specification. Please note that due to the interface with EDK2, these files make references to data structures and fields that use CamelCase. BRANCH=none BUG=None TEST=Build for Braswell or Skylake boards using FSP 1.1. Change-Id: I2914c047d786a3060075356783ac9758bc41f633 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/fsp1_1/Kconfig | 159 ++++++--- src/drivers/intel/fsp1_1/Makefile.inc | 32 +- src/drivers/intel/fsp1_1/cache_as_ram.inc | 268 +++++++++++--- src/drivers/intel/fsp1_1/fastboot_cache.c | 45 +-- src/drivers/intel/fsp1_1/fsp_gop.c | 101 ++++++ src/drivers/intel/fsp1_1/fsp_gop.h | 34 ++ src/drivers/intel/fsp1_1/fsp_relocate.c | 493 ++++++++++++++++++++++++++ src/drivers/intel/fsp1_1/fsp_util.c | 449 ++++++++++-------------- src/drivers/intel/fsp1_1/fsp_util.h | 110 +++--- src/drivers/intel/fsp1_1/fsp_values.h | 41 --- src/drivers/intel/fsp1_1/hob.c | 560 +++++++++++++++++++++--------- 13 files changed, 1618 insertions(+), 676 deletions(-) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 511cf5c..f405927 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -17,5 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +source src/drivers/intel/fsp1_1/Kconfig source src/drivers/intel/gma/Kconfig source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index dc947ff..3ddb05f 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -1,4 +1,5 @@ subdirs-y += gma subdirs-y += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 +subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 2492298..0707e9f 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -17,18 +17,14 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -if PLATFORM_USES_FSP1_0 - comment "Intel FSP" -config HAVE_FSP_BIN +config PLATFORM_USES_FSP1_1 bool "Use Intel Firmware Support Package" help - Select this option to add an Intel FSP binary to - the resulting coreboot image. + Does the code require the Intel Firmware Support Package? - Note: Without this binary, coreboot builds relying on the FSP - will not boot +if PLATFORM_USES_FSP1_1 config DCACHE_RAM_BASE hex @@ -38,13 +34,61 @@ config DCACHE_RAM_SIZE hex default 0x4000 +config HAVE_FSP_BIN + bool "Should the Intel FSP binary be added to the flash image" + help + Select this option to add an Intel FSP binary to + the resulting coreboot image. + + Note: Without this binary, coreboot builds relying on the FSP + will not boot + if HAVE_FSP_BIN +config CPU_MICROCODE_CBFS_LEN + hex "Microcode update region length in bytes" + default 0 + help + The length in bytes of the microcode update region. + +config CPU_MICROCODE_CBFS_LOC + hex "Microcode update base address in CBFS" + default 0 + help + The location (base address) in CBFS that contains the microcode update + binary. + +config ENABLE_MRC_CACHE + bool + default y if HAVE_ACPI_RESUME + default n + help + Enabling this feature will cause MRC data to be cached in NV storage. + This can either be used for fast boot, or just because the FSP wants + it to be saved. + config FSP_FILE string "Intel FSP binary path and filename" help The path and filename of the Intel FSP binary for this platform. +config FSP_IMAGE_ID_DWORD0 + hex "First 4 bytes of 8 byte platform string" + help + The first four bytes of the eight byte platform specific string + used to identify the FSP binary that should be used. + +config FSP_IMAGE_ID_DWORD1 + hex "Second 4 bytes of 8 byte platform string" + help + The second four bytes of the eight byte platform specific string + used to identify the FSP binary that should be used. + +config FSP_INCLUDE_PATH + string "Path for FSP specific include files" + help + The path and filename of the Intel FSP binary for this platform. + config FSP_LOC hex "Intel FSP Binary location in CBFS" help @@ -52,23 +96,27 @@ config FSP_LOC value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool). -config ENABLE_FSP_FAST_BOOT - bool "Enable Fast Boot" - select ENABLE_MRC_CACHE - default n +config MRC_CACHE_FILE + string "File containing the cached MRC values" help - Enabling this feature will force the MRC data to be cached in NV - storage to be used for speeding up boot time on future reboots - and/or power cycles. + The path and filename of the cached MRC values. -config ENABLE_MRC_CACHE - bool - default y if HAVE_ACPI_RESUME - default n +config MRC_CACHE_LOC + hex "Fast Boot Data Cache location in CBFS" + default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC + default 0xfff50000 + depends on ENABLE_MRC_CACHE help - Enabling this feature will cause MRC data to be cached in NV storage. - This can either be used for fast boot, or just because the FSP wants - it to be saved. + The location in CBFS for the MRC data to be cached. + + WARNING: This should be on a sector boundary of the BIOS ROM chip + and nothing else should be included in that sector, or IT WILL BE + ERASED. + +config MRC_CACHE_LOC_OVERRIDE + hex + help + Sets the override CBFS location of the MRC/fast boot cache. config MRC_CACHE_SIZE hex "Fast Boot Data Cache Size" @@ -88,23 +136,6 @@ config OVERRIDE_CACHE_CACHE_LOC Selected by the platform to set a new default location for the MRC/fast boot cache. -config MRC_CACHE_LOC_OVERRIDE - hex - help - Sets the override CBFS location of the MRC/fast boot cache. - -config MRC_CACHE_LOC - hex "Fast Boot Data Cache location in CBFS" - default MRC_CACHE_LOC_OVERRIDE if OVERRIDE_CACHE_CACHE_LOC - default 0xfff50000 - depends on ENABLE_MRC_CACHE - help - The location in CBFS for the MRC data to be cached. - - WARNING: This should be on a sector boundary of the BIOS ROM chip - and nothing else should be included in that sector, or IT WILL BE - ERASED. - config VIRTUAL_ROM_SIZE hex "Virtual ROM Size" default ROM_SIZE @@ -126,20 +157,54 @@ config CACHE_ROM_SIZE_OVERRIDE default CBFS_SIZE help This is the size of the cachable area that is passed into the FSP in - the early initialization. Typically this should be the size of the CBFS - area, but the size must be a power of 2 whereas the CBFS size does not - have this limitation. + the early initialization. Typically this should be the size of the + CBFS area, but the size must be a power of 2 whereas the CBFS size + does not have this limitation. -config USE_GENERIC_FSP_CAR_INC - bool +config DISPLAY_FAST_BOOT_DATA + bool "Display fast boot data" + default n + +config DISPLAY_HOBS + bool "Display hand-off-blocks (HOBs)" + default n + +config DISPLAY_VBT + bool "Display Video BIOS Table (VBT)" + default n + +config DISPLAY_FSP_ENTRY_POINTS + bool "Display FSP entry points" + default n + +config DISPLAY_UPD_DATA + bool "Display UPD data" default n help - The chipset can select this to use a generic cache_as_ram.inc file - that should be good for all FSP based platforms. + Display the user specified product data prior to memory + initialization. config FSP_USES_UPD bool default n help - If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig. -endif #PLATFORM_USES_FSP1_0 + If this FSP uses UPD/VPD data regions, select this in the chipset + Kconfig. + +config GOP_SUPPORT + bool "Enable GOP support" + default y + +config USE_GENERIC_FSP_CAR_INC + bool + default n + help + The chipset can select this to use a generic cache_as_ram.inc file + that should be good for all FSP based platforms. + +config VBT_FILE + string "GOP Video BIOS table binary path" + depends on GOP_SUPPORT + default "3rdparty/mainboard/$(MAINBOARDDIR)/vbt.bin" + +endif #PLATFORM_USES_FSP1_1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4931cb7..3e03a23 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2015 Intel Corp. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,18 +18,31 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -ramstage-y += fsp_util.c hob.c -romstage-y += fsp_util.c hob.c +romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c +romstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c +romstage-y += fsp_util.c +romstage-y += hob.c ramstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c -romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c +ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c +ramstage-y += fsp_relocate.c +ramstage-y += fsp_util.c +ramstage-y += hob.c -CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 +CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1 ifeq ($(CONFIG_USE_GENERIC_FSP_CAR_INC),y) -cpu_incs += $(src)/drivers/intel/fsp1_0/cache_as_ram.inc +cpu_incs-y += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc endif + +# Add the GOP Video BIOS Table to the cbfs image +cbfs-files-$(CONFIG_GOP_SUPPORT) += vbt.bin +vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE)) +vbt.bin-type := optionrom + + +# Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_BIN),y) cbfs-files-y += fsp.bin fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) @@ -36,14 +50,16 @@ fsp.bin-position := $(CONFIG_FSP_LOC) fsp.bin-type := fsp endif -ifeq ($(CONFIG_ENABLE_MRC_CACHE),y) + +# Create and add the MRC cache to the cbfs image +ifeq ($(CONFIG_ENABLE_MRC_CACHE_FILE),y) $(obj)/mrc.cache: dd if=/dev/zero count=1 \ bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ tr '\000' '\377' > $@ cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache +mrc.cache-file := $(call strip_quotes,$(CONFIG_MRC_CACHE_FILE)) mrc.cache-position := $(CONFIG_MRC_CACHE_LOC) -mrc.cache-type := mrc_cache +mrc.cache-type := 0xac endif diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 8604c3b..30f2fa4 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -4,6 +4,7 @@ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> * Copyright (C) 2007-2008 coresystems GmbH * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,10 +20,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * Replacement for cache_as_ram.inc when using the FSP binary. This code + * locates the FSP binary, initializes the cache as RAM and performs the + * first stage of initialization. Next this code switches the stack from + * the cache to RAM and then disables the cache as RAM. Finally this code + * performs the final stage of initialization. + */ + #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#include <microcode_size.h> #include <cbmem.h> #ifndef CONFIG_FSP_LOC @@ -33,7 +41,7 @@ # error "CONFIG_POST_IO must be set." #endif -#if CONFIG_POST_IO +#if IS_ENABLED(CONFIG_POST_IO) # ifndef CONFIG_POST_IO_PORT # error "CONFIG_POST_IO_PORT must be set." # endif @@ -45,79 +53,216 @@ #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ - cmp $0, %eax - jne bisthalt + /* + * eax: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + mov %eax, %edi cache_as_ram: post_code(0x20) /* + * edi: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + /* * Find the FSP binary in cbfs. * Make a fake stack that has the return value back to this code. */ - lea fake_fsp_stack, %esp - jmp find_fsp + lea fake_fsp_stack, %esp + jmp find_fsp find_fsp_ret: /* Save the FSP location */ - mov %eax, %ebp - cmp $CONFIG_FSP_LOC, %eax - jb halt1 + mov %eax, %ebp + + /* + * Only when a valid FSP binary is found at CONFIG_FSP_LOC is + * the returned FSP_INFO_HEADER structure address above the base + * address of FSP binary specified by the CONFIG_FSP_LOC value. + * All of the error values are in the 0x8xxxxxxx range which are + * below the CONFIG_FSP_LOC value. + */ + cmp $CONFIG_FSP_LOC, %eax + jbe halt1 post_code(0x22) /* Calculate entry into FSP */ - mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ - add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */ + mov 0x30(%ebp), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebp), %eax /* add in the offset for FSP */ /* * Pass early init variables on a fake stack (no memory yet) * as well as the return location */ - lea CAR_init_stack, %esp + lea CAR_init_stack, %esp + + /* + * BIST value is zero + * eax: TempRamInitApi address + * ebp: FSP_INFO_HEADER address + * edi: BIST value + * esi: Not used + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ /* call FSP binary to setup temporary stack */ - jmp *%eax + jmp *%eax CAR_init_done: - addl $4, %esp - cmp $0, %eax - jne halt2 + addl $4, %esp + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + + cmp $0, %eax + jne halt2 + + /* Setup bootloader stack */ + movl %edx, %esp + + /* Save BIST value */ + movd %edi, %mm2 + + /* + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * esp: Top of stack in temp RAM + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + * mm2: BIST value + */ + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + add %edx, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl /* Save FSP_INFO_HEADER location in ebx */ - mov %ebp, %ebx + mov %ebp, %ebx /* - * set up bootloader stack - * ecx: stack base - * edx: stack top + * ebx: FSP_INFO_HEADER address + * esi: Temp RAM base + * esp: Top of stack in temp RAM + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + * mm2: BIST value */ - mov %edx, %esp - movl %esp, %ebp - /* Clear the cbmem CAR memory region. */ - movl %ecx, %edi - movl %edx, %ecx - sub %edi, %ecx - shr $2, %ecx - xorl %eax, %eax - rep stosl + /* Frame for romstage_main(bist, tsc_low, tsc_hi, fih) */ + pushl %ebx + movd %mm1, %eax + pushl %eax + movd %mm0, %eax + pushl %eax + movd %mm2, %eax + pushl %eax before_romstage: post_code(0x23) /* Call romstage.c main function. */ - pushl %ebx /* main takes FSP_INFO_HEADER as its argument */ - call main /* does not return */ - movb $0xB8, %ah - jmp .Lhlt + call romstage_main + + /* + * eax: New stack address + * ebx: FSP_INFO_HEADER address + */ + + /* Switch to the stack in RAM */ + movl %eax, %esp + + /* Calculate TempRamExit entry into FSP */ + movl %ebx, %ebp + mov 0x40(%ebp), %eax + add 0x1c(%ebp), %eax + + /* Build the call frame */ + pushl $0 + + /* Call TempRamExit */ + call *%eax + add $4, %esp + cmp $0, %eax + jne halt3 + + /* Get number of MTRRs. */ + popl %ebx + movl $MTRRphysBase_MSR(0), %ecx +1: + testl %ebx, %ebx + jz 1f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ + wrmsr + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ + wrmsr + inc %ecx + + dec %ebx + jmp 1b +1: + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) -bisthalt: - movb $0xB9, %ah - jmp .Lhlt + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + call romstage_after_car + + + movb $0x69, %ah + jmp .Lhlt halt1: /* - * Failures for postcode 0xBA - failed in find_fsp() + * Failures for postcode 0xBA - failed in fsp_fih_early_find() * * Values are: * 0x01 - FV signature, "_FVH" not present @@ -128,8 +273,8 @@ halt1: * 0x05 - FSP INFO Header signature "FSPH" not found * 0x06 - FSP Image ID is not the expected ID. */ - movb $0xBA, %ah - jmp .Lhlt + movb $0xBA, %ah + jmp .Lhlt halt2: /* @@ -137,25 +282,37 @@ halt2: * * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully. * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. - * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed + * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region. * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked */ - movb $0xBB, %ah + movb $0xBB, %ah + jmp .Lhlt + +halt3: + /* + * Failures for post code BC - failed in TempRamExit + * + * 0x00 - FSP_SUCCESS: Temp RAM Exit completed successfully. + * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid. + * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met. + * 0x07 - FSP_DEVICE_ERROR: Temp RAM Exit failed. + */ + movb $0xBC, %ah .Lhlt: - xchg %al, %ah -#if CONFIG_POST_IO - outb %al, $CONFIG_POST_IO_PORT + xchg %al, %ah +#if IS_ENABLED(CONFIG_POST_IO) + outb %al, $CONFIG_POST_IO_PORT #else post_code(POST_DEAD_CODE) #endif - movl $LHLT_DELAY, %ecx + movl $LHLT_DELAY, %ecx .Lhlt_Delay: - outb %al, $0xED - loop .Lhlt_Delay - jmp .Lhlt + outb %al, $0xED + loop .Lhlt_Delay + jmp .Lhlt /* * esp is set to this location so that the call into and return from the FSP @@ -163,15 +320,14 @@ halt2: */ .align 4 fake_fsp_stack: - .long find_fsp_ret + .long find_fsp_ret CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC - .long MICROCODE_REGION_LENGTH - .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */ - .long CACHE_ROM_SIZE /* Total Firmware Length */ + .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ + .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */ + .long CONFIG_CBFS_SIZE /* Total Firmware Length */ CAR_init_stack: - .long CAR_init_done - .long CAR_init_params - + .long CAR_init_done + .long CAR_init_params diff --git a/src/drivers/intel/fsp1_1/fastboot_cache.c b/src/drivers/intel/fsp1_1/fastboot_cache.c index e8651bb..794b545 100644 --- a/src/drivers/intel/fsp1_1/fastboot_cache.c +++ b/src/drivers/intel/fsp1_1/fastboot_cache.c @@ -3,6 +3,7 @@ * * Copyright (C) 2012 Google Inc. * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,26 +19,23 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <string.h> -#include <bootstate.h> -#include <console/console.h> #include <cbfs.h> -#include <ip_checksum.h> -#include <device/device.h> #include <cbmem.h> -#include <spi-generic.h> -#include <spi_flash.h> -#include <lib.h> // hexdump +#include <console/console.h> #include "fsp_util.h" +#include <ip_checksum.h> +#include <lib.h> // hexdump +#include <spi_flash.h> +#include <string.h> #ifndef CONFIG_VIRTUAL_ROM_SIZE #error "CONFIG_VIRTUAL_ROM_SIZE must be set." #endif /* convert a pointer to flash area into the offset inside the flash */ -static inline u32 to_flash_offset(void *p) { - return ((u32)p + CONFIG_VIRTUAL_ROM_SIZE); +static inline u32 to_flash_offset(void *p) +{ + return (u32)p + CONFIG_VIRTUAL_ROM_SIZE; } static struct mrc_data_container *next_mrc_block( @@ -50,14 +48,15 @@ static struct mrc_data_container *next_mrc_block( mrc_size += MRC_DATA_ALIGN; } - u8 *region_ptr = (u8*)mrc_cache; + u8 *region_ptr = (u8 *)mrc_cache; region_ptr += mrc_size; return (struct mrc_data_container *)region_ptr; } static int is_mrc_cache(struct mrc_data_container *mrc_cache) { - return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); + return (!!mrc_cache) + && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE); } static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) @@ -96,7 +95,8 @@ static struct mrc_data_container *find_current_mrc_cache_local } if (entry_id == 0) { - printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", __func__); + printk(BIOS_ERR, "%s: No valid fast boot cache found.\n", + __func__); return NULL; } @@ -104,7 +104,8 @@ static struct mrc_data_container *find_current_mrc_cache_local if (mrc_cache->mrc_checksum != compute_ip_checksum(mrc_cache->mrc_data, mrc_cache->mrc_data_size)) { - printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", __func__); + printk(BIOS_ERR, "%s: fast boot cache checksum mismatch\n", + __func__); return NULL; } @@ -117,7 +118,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE /* find the first empty block in the MRC cache area. * If there's none, return NULL. * @@ -164,6 +165,7 @@ void update_mrc_cache(void *unused) return; } + cache_base = NULL; cache_size = get_mrc_cache_region(&cache_base); if (cache_base == NULL) { printk(BIOS_ERR, "%s: could not find fast boot cache area\n", @@ -218,19 +220,21 @@ void update_mrc_cache(void *unused) current->mrc_data_size + sizeof(*current), current); } -#endif /* !defined(__PRE_RAM__) */ +#endif /* ENV_RAMSTAGE */ -void * find_and_set_fastboot_cache(void) +void *find_and_set_fastboot_cache(void) { struct mrc_data_container *mrc_cache = NULL; - if (((mrc_cache = find_current_mrc_cache()) == NULL) || + mrc_cache = find_current_mrc_cache(); + if ((mrc_cache == NULL) || (mrc_cache->mrc_data_size == -1UL)) { printk(BIOS_DEBUG, "FSP MRC cache not present.\n"); return NULL; } printk(BIOS_DEBUG, "FSP MRC cache present at %x.\n", (u32)mrc_cache); printk(BIOS_SPEW, "Saved MRC data:\n"); - hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, (mrc_cache->mrc_data_size) / 4); + hexdump32(BIOS_SPEW, (void *)mrc_cache->mrc_data, + mrc_cache->mrc_data_size); return (void *) mrc_cache->mrc_data; } @@ -239,6 +243,7 @@ struct mrc_data_container *find_current_mrc_cache(void) struct mrc_data_container *cache_base; u32 cache_size; + cache_base = NULL; cache_size = get_mrc_cache_region(&cache_base); if (cache_base == NULL) { printk(BIOS_ERR, "%s: could not find fast boot cache area\n", diff --git a/src/drivers/intel/fsp1_1/fsp_gop.c b/src/drivers/intel/fsp1_1/fsp_gop.c new file mode 100644 index 0000000..cf781cd --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp_gop.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbfs.h> +#include <console/console.h> +#include "fsp_util.h" +#include <lib.h> + +/* Reading VBT table from flash */ +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) +{ + struct cbfs_file *vbt_file; + union { + const optionrom_vbt_t *data; + uint32_t *signature; + } vbt; + + /* Locate the vbt file in cbfs */ + vbt_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "vbt.bin"); + if (!vbt_file) { + printk(BIOS_INFO, + "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); + return NULL; + } + + /* Validate the vbt file */ + vbt.data = CBFS_SUBHEADER(vbt_file); + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return NULL; + } + *vbt_len = ntohl(vbt_file->len); + printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n", + vbt.data, *vbt_len); + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + printk(BIOS_DEBUG, "VBT Data:\n"); + hexdump(vbt.data, *vbt_len); + printk(BIOS_DEBUG, "\n"); +#endif + + /* Return the pointer to the vbt file data */ + return vbt.data; +} + +#if ENV_RAMSTAGE +void fsp_gop_framebuffer(struct lb_header *header) +{ + struct lb_framebuffer *framebuffer; + framebuffer = (struct lb_framebuffer *)lb_new_record(header); + + VOID *hob_list_ptr; + hob_list_ptr = get_hob_list(); + const EFI_GUID vbt_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; + u32 *vbt_hob; + EFI_PEI_GRAPHICS_INFO_HOB *vbt_gop; + vbt_hob = get_next_guid_hob(&vbt_guid, hob_list_ptr); + if (vbt_hob == NULL) { + printk(BIOS_ERR, "FSP_ERR: Graphics Data HOB is not present\n"); + return; + } else { + printk(BIOS_DEBUG, "FSP_DEBUG: Graphics Data HOB present\n"); + vbt_gop = GET_GUID_HOB_DATA(vbt_hob); + } + + framebuffer->physical_address = vbt_gop->FrameBufferBase; + framebuffer->x_resolution = vbt_gop->GraphicsMode.HorizontalResolution; + framebuffer->y_resolution = vbt_gop->GraphicsMode.VerticalResolution; + framebuffer->bytes_per_line = vbt_gop->GraphicsMode.PixelsPerScanLine + * 4; + framebuffer->bits_per_pixel = 32; + framebuffer->red_mask_pos = 16; + framebuffer->red_mask_size = 8; + framebuffer->green_mask_pos = 8; + framebuffer->green_mask_size = 8; + framebuffer->blue_mask_pos = 0; + framebuffer->blue_mask_size = 8; + framebuffer->reserved_mask_pos = 24; + framebuffer->reserved_mask_size = 8; + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); +} +#endif /* ENV_RAMSTAGE */ diff --git a/src/drivers/intel/fsp1_1/fsp_gop.h b/src/drivers/intel/fsp1_1/fsp_gop.h new file mode 100644 index 0000000..f0581df --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp_gop.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _FSP_GOP_H_ +#define _FSP_GOP_H_ + +/* GOP support */ +#if IS_ENABLED(CONFIG_GOP_SUPPORT) + +#include <boot/coreboot_tables.h> +#include <soc/intel/common/gma.h> + +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); +#if ENV_RAMSTAGE +void fsp_gop_framebuffer(struct lb_header *header); +#endif /* ENV_RAMSTAGE */ +#endif /* CONFIG_GOP_SUPPORT */ +#endif /* _FSP_GOP_H_ */ diff --git a/src/drivers/intel/fsp1_1/fsp_relocate.c b/src/drivers/intel/fsp1_1/fsp_relocate.c new file mode 100644 index 0000000..d2a76d3 --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp_relocate.c @@ -0,0 +1,493 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/console.h> +#include <cbmem.h> +#include <fsp_util.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <uefi_types.h> + +#define FSP_DBG_LVL BIOS_NEVER + +static const EFI_GUID ffs2_guid = EFI_FIRMWARE_FILE_SYSTEM2_GUID; +static const EFI_GUID fih_guid = FSP_INFO_HEADER_GUID; + +struct fsp_patch_table { + uint32_t signature; + uint16_t header_length; + uint8_t header_revision; + uint8_t reserved; + uint32_t patch_entry_num; + uint32_t patch_entries[0]; +} __attribute__((packed)); + +#define FSPP_SIG 0x50505346 + +static void *relative_offset(void *base, ssize_t offset) +{ + uintptr_t loc; + + loc = (uintptr_t)base; + loc += offset; + + return (void *)loc; +} + +static uint32_t *fspp_reloc(void *fsp, size_t fsp_size, uint32_t e) +{ + size_t offset; + + /* Offsets live in bits 23:0. */ + offset = e & 0xffffff; + + /* If bit 31 is set then the offset is considered a negative value + * relative to the end of the image using 16MiB as the offset's + * reference. */ + if (e & (1 << 31)) + offset = fsp_size - (16 * MiB - offset); + + /* Determine if offset falls within fsp_size for a 32 bit relocation. */ + if (offset > fsp_size - sizeof(uint32_t)) + return NULL; + + return relative_offset(fsp, offset); +} + +static int reloc_type(uint16_t reloc_entry) +{ + /* Reloc type in upper 4 bits */ + return reloc_entry >> 12; +} + +static size_t reloc_offset(uint16_t reloc_entry) +{ + /* Offsets are in low 12 bits. */ + return reloc_entry & ((1 << 12) - 1); +} + +static int te_relocate_in_place(void *te, size_t size) +{ + EFI_TE_IMAGE_HEADER *teih; + EFI_IMAGE_DATA_DIRECTORY *relocd; + EFI_IMAGE_BASE_RELOCATION *relocb; + size_t fixup_offset; + size_t num_relocs; + uint16_t *reloc; + size_t relocd_offset; + uint8_t *te_base; + uint32_t adj; + + teih = te; + + if (teih->Signature != EFI_TE_IMAGE_HEADER_SIGNATURE) { + printk(BIOS_ERR, "TE Signature mismatch: %x vs %x\n", + teih->Signature, EFI_TE_IMAGE_HEADER_SIGNATURE); + return -1; + } + + /* + * A TE image is created by converting a PE file. Because of this + * the offsets within the headers are off. In order to calculate + * the correct releative offets one needs to subtract fixup_offset + * from the encoded offets. Similarly, the linked address of the + * program is found by adding the fixup_offset to the ImageBase. + */ + fixup_offset = teih->StrippedSize - sizeof(EFI_TE_IMAGE_HEADER); + /* Keep track of a base that is correctly adjusted so that offsets + * can be used directly. */ + te_base = te; + te_base -= fixup_offset; + + adj = (uintptr_t)te - (teih->ImageBase + fixup_offset); + + printk(FSP_DBG_LVL, "TE Image %p -> %p adjust value: %x\n", + (void *)(uintptr_t)(teih->ImageBase + fixup_offset), + te, adj); + + /* Adjust ImageBase for consistency. Need to subtract fixup_offset + * so the image could be relocated if needed. */ + teih->ImageBase += adj - fixup_offset; + + relocd = &teih->DataDirectory[EFI_TE_IMAGE_DIRECTORY_ENTRY_BASERELOC]; + + relocd_offset = 0; + /* Though the field name is VirtualAddress it's actually relative to + * the beginning of the image which is linked at ImageBase. */ + relocb = relative_offset(te, relocd->VirtualAddress - fixup_offset); + while (relocd_offset < relocd->Size) { + size_t rva_offset = relocb->VirtualAddress; + + printk(FSP_DBG_LVL, "Relocs for RVA offset %zx\n", rva_offset); + num_relocs = relocb->SizeOfBlock - sizeof(*relocb); + num_relocs /= sizeof(uint16_t); + reloc = relative_offset(relocb, sizeof(*relocb)); + + printk(FSP_DBG_LVL, "Num relocs in block: %zx\n", num_relocs); + + while (num_relocs > 0) { + int type = reloc_type(*reloc); + size_t offset = reloc_offset(*reloc); + + printk(FSP_DBG_LVL, "reloc type %x offset %zx\n", + type, offset); + + if (type == EFI_IMAGE_REL_BASED_HIGHLOW) { + uint32_t *reloc_addr; + + offset += rva_offset; + reloc_addr = (void *)&te_base[offset]; + + printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", + reloc_addr, *reloc_addr, + *reloc_addr + adj); + *reloc_addr += adj; + } else if (type != EFI_IMAGE_REL_BASED_ABSOLUTE) { + printk(BIOS_ERR, "Unknown reloc type: %x\n", + type); + return -1; + } + num_relocs--; + reloc++; + } + + /* Track consumption of relocation directory contents. */ + relocd_offset += relocb->SizeOfBlock; + /* Get next relocation block to process. */ + relocb = relative_offset(relocb, relocb->SizeOfBlock); + } + + return 0; +} + +static size_t csh_size(const EFI_COMMON_SECTION_HEADER *csh) +{ + size_t size; + + /* Unpack the array into a type that can be used. */ + size = 0; + size |= csh->Size[0] << 0; + size |= csh->Size[1] << 8; + size |= csh->Size[2] << 16; + + return size; +} + +static size_t section_data_offset(const EFI_COMMON_SECTION_HEADER *csh) +{ + if (csh_size(csh) == 0x00ffffff) + return sizeof(EFI_COMMON_SECTION_HEADER2); + else + return sizeof(EFI_COMMON_SECTION_HEADER); +} + +static size_t section_data_size(const EFI_COMMON_SECTION_HEADER *csh) +{ + size_t section_size; + + if (csh_size(csh) == 0x00ffffff) + section_size = SECTION2_SIZE(csh); + else + section_size = csh_size(csh); + + return section_size - section_data_offset(csh); +} + +static size_t file_section_offset(const EFI_FFS_FILE_HEADER *ffsfh) +{ + if (IS_FFS_FILE2(ffsfh)) + return sizeof(EFI_FFS_FILE_HEADER2); + else + return sizeof(EFI_FFS_FILE_HEADER); +} + +static size_t ffs_file_size(const EFI_FFS_FILE_HEADER *ffsfh) +{ + size_t size; + + if (IS_FFS_FILE2(ffsfh)) + size = FFS_FILE2_SIZE(ffsfh); + else { + size = ffsfh->Size[0] << 0; + size |= ffsfh->Size[1] << 8; + size |= ffsfh->Size[2] << 16; + } + return size; +} + +static int relocate_patch_table(void *fsp, size_t size, size_t offset, + ssize_t adjustment) +{ + struct fsp_patch_table *table; + uint32_t num; + + table = relative_offset(fsp, offset); + + if ((offset + sizeof(*table) > size) || + (table->header_length + offset) > size) { + printk(BIOS_ERR, "FSPP not entirely contained in region.\n"); + return -1; + } + + printk(FSP_DBG_LVL, "FSPP relocs: %x\n", table->patch_entry_num); + + for (num = 0; num < table->patch_entry_num; num++) { + uint32_t *reloc; + + reloc = fspp_reloc(fsp, size, table->patch_entries[num]); + + if (reloc == NULL) { + printk(BIOS_ERR, "Ignoring FSPP entry: %x\n", + table->patch_entries[num]); + continue; + } + + printk(FSP_DBG_LVL, "Adjusting %p %x -> %x\n", + reloc, *reloc, (unsigned int)(*reloc + adjustment)); + + *reloc += adjustment; + } + + return 0; +} + +static void *relocate_remaining_items(void *fsp, size_t size, size_t fih_offset) +{ + EFI_FFS_FILE_HEADER *ffsfh; + EFI_COMMON_SECTION_HEADER *csh; + FSP_INFO_HEADER *fih; + ssize_t adjustment; + size_t offset; + + printk(FSP_DBG_LVL, "FSP_INFO_HEADER offset is %zx\n", fih_offset); + + if (fih_offset == 0) { + printk(BIOS_ERR, "FSP_INFO_HEADER offset is 0.\n"); + return NULL; + } + + /* FSP_INFO_HEADER at first file in FV within first RAW section. */ + ffsfh = relative_offset(fsp, fih_offset); + fih_offset += file_section_offset(ffsfh); + csh = relative_offset(fsp, fih_offset); + fih_offset += section_data_offset(csh); + fih = relative_offset(fsp, fih_offset); + + if (memcmp(&ffsfh->Name, &fih_guid, sizeof(fih_guid))) { + printk(BIOS_ERR, "Bad FIH GUID.\n"); + return NULL; + } + + if (csh->Type != EFI_SECTION_RAW) { + printk(BIOS_ERR, "FIH file should have raw section: %x\n", + csh->Type); + return NULL; + } + + if (fih->Signature != FSP_SIG) { + printk(BIOS_ERR, "Unexpected FIH signature: %08x\n", + fih->Signature); + return NULL; + } + + adjustment = (intptr_t)fsp - fih->ImageBase; + + /* Update ImageBase to reflect FSP's new home. */ + fih->ImageBase += adjustment; + + /* Need to find patch table and adjust each entry. The tables + * following FSP_INFO_HEADER have a 32-bit signature and header + * length. The patch table is denoted as having a 'FSPP' signature; + * the table format doesn't follow the other tables. */ + offset = fih_offset + fih->HeaderLength; + while (offset + 2 * sizeof(uint32_t) <= size) { + uint32_t *table_headers; + + table_headers = relative_offset(fsp, offset); + + printk(FSP_DBG_LVL, "Checking offset %zx for 'FSPP'\n", + offset); + + if (table_headers[0] != FSPP_SIG) { + offset += table_headers[1]; + continue; + } + + if (relocate_patch_table(fsp, size, offset, adjustment)) { + printk(BIOS_ERR, "FSPP relocation failed.\n"); + return NULL; + } + + return fih; + } + + printk(BIOS_ERR, "Could not find the FSP patch table.\n"); + return NULL; +} + +static ssize_t relocate_fvh(void *fsp, size_t fsp_size, size_t fvh_offset, + size_t *fih_offset) +{ + EFI_FIRMWARE_VOLUME_HEADER *fvh; + EFI_FFS_FILE_HEADER *ffsfh; + EFI_COMMON_SECTION_HEADER *csh; + size_t offset; + size_t file_offset; + size_t size; + + offset = fvh_offset; + fvh = relative_offset(fsp, offset); + + if (fvh->Signature != EFI_FVH_SIGNATURE) + return -1; + + printk(FSP_DBG_LVL, "FVH length: %zx Offset: %zx Mapping length: %zx\n", + (size_t)fvh->FvLength, offset, fsp_size); + + if (fvh->FvLength + offset > fsp_size) + return -1; + + /* Parse only this FV. However, the algorithm uses offsets into the + * entire FSP region so make size include the starting offset. */ + size = fvh->FvLength + offset; + + if (memcmp(&fvh->FileSystemGuid, &ffs2_guid, sizeof(ffs2_guid))) { + printk(BIOS_ERR, "FVH not an FFS2 type.\n"); + return -1; + } + + if (fvh->ExtHeaderOffset != 0) { + EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh; + + offset += fvh->ExtHeaderOffset; + fveh = relative_offset(fsp, offset); + printk(FSP_DBG_LVL, "Extended Header Offset: %zx Size: %zx\n", + (size_t)fvh->ExtHeaderOffset, + (size_t)fveh->ExtHeaderSize); + offset += fveh->ExtHeaderSize; + /* FFS files are 8 byte aligned after extended header. */ + offset = ALIGN_UP(offset, 8); + } else { + offset += fvh->HeaderLength; + } + + file_offset = offset; + while (file_offset + sizeof(*ffsfh) < size) { + offset = file_offset; + printk(FSP_DBG_LVL, "file offset: %zx\n", file_offset); + + /* First file and section should be FSP info header. */ + if (fih_offset != NULL && *fih_offset == 0) + *fih_offset = file_offset; + + ffsfh = relative_offset(fsp, file_offset); + + printk(FSP_DBG_LVL, "file type = %x\n", ffsfh->Type); + printk(FSP_DBG_LVL, "file attribs = %x\n", ffsfh->Attributes); + + /* Next file on 8 byte alignment. */ + file_offset += ffs_file_size(ffsfh); + file_offset = ALIGN_UP(file_offset, 8); + + /* Padding files have no section information. */ + if (ffsfh->Type == EFI_FV_FILETYPE_FFS_PAD) + continue; + + offset += file_section_offset(ffsfh); + + while (offset + sizeof(*csh) < file_offset) { + size_t data_size; + size_t data_offset; + + csh = relative_offset(fsp, offset); + + printk(FSP_DBG_LVL, "section offset: %zx\n", offset); + printk(FSP_DBG_LVL, "section type: %x\n", csh->Type); + + data_size = section_data_size(csh); + data_offset = section_data_offset(csh); + + if (data_size + data_offset + offset > file_offset) { + printk(BIOS_ERR, "Section exceeds FV size.\n"); + return -1; + } + + if (csh->Type == EFI_SECTION_TE) { + void *te; + size_t te_offset = offset + data_offset; + + printk(FSP_DBG_LVL, "TE image at offset %zx\n", + te_offset); + te = relative_offset(fsp, te_offset); + te_relocate_in_place(te, data_size); + } + + offset += data_size + data_offset; + /* Sections are aligned to 4 bytes. */ + offset = ALIGN_UP(offset, 4); + } + } + + /* Return amount of buffer parsed: FV size. */ + return fvh->FvLength; +} + +static FSP_INFO_HEADER *fsp_relocate_in_place(void *fsp, size_t size) +{ + size_t offset; + size_t fih_offset; + + offset = 0; + fih_offset = 0; + while (offset < size) { + ssize_t nparsed; + + /* Relocate each FV within the FSP region. The FSP_INFO_HEADER + * should only be located in the first FV. */ + if (offset == 0) + nparsed = relocate_fvh(fsp, size, offset, &fih_offset); + else + nparsed = relocate_fvh(fsp, size, offset, NULL); + + /* FV should be larger than 0 or failed to parse. */ + if (nparsed <= 0) { + printk(BIOS_ERR, "FV @ offset %zx relocation failed\n", + offset); + return NULL; + } + + offset += nparsed; + } + + return relocate_remaining_items(fsp, size, fih_offset); +} + +FSP_INFO_HEADER *fsp_relocate(void *fsp_src, size_t size) +{ + void *new_loc; + + new_loc = cbmem_add(CBMEM_ID_REFCODE, size); + if (new_loc == NULL) { + printk(BIOS_ERR, "Unable to load FSP into memory.\n"); + return NULL; + } + memcpy(new_loc, fsp_src, size); + return fsp_relocate_in_place(new_loc, size); +} diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 3147b67..e6e2ea1 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,336 +18,234 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> -#include <console/console.h> #include <bootstate.h> #include <cbmem.h> +#include <console/console.h> #include "fsp_util.h" -#include <lib.h> // hexdump -#include <ip_checksum.h> #include <timestamp.h> -#ifndef __PRE_RAM__ -/* Globals pointers for FSP structures */ -void *FspHobListPtr = NULL; -FSP_INFO_HEADER *fsp_header_ptr = NULL; - -void FspNotify (u32 Phase) +/* Locate the FSP binary in the coreboot filesystem */ +FSP_INFO_HEADER *find_fsp(void) { - FSP_NOTFY_PHASE NotifyPhaseProc; - NOTIFY_PHASE_PARAMS NotifyPhaseParams; - EFI_STATUS Status; - - if (fsp_header_ptr == NULL) { - fsp_header_ptr = (void *)find_fsp(); - if ((u32)fsp_header_ptr < 0xff) { - post_code(0x4F); /* output something in case there is no serial */ - die("Can't find the FSP!\n"); - } - } - - /* call FSP PEI to Notify PostPciEnumeration */ - NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_header_ptr->ImageBase + - fsp_header_ptr->NotifyPhaseEntry); - NotifyPhaseParams.Phase = Phase; + union { + EFI_FFS_FILE_HEADER *ffh; + FSP_INFO_HEADER *fih; + EFI_FIRMWARE_VOLUME_EXT_HEADER *fveh; + EFI_FIRMWARE_VOLUME_HEADER *fvh; + EFI_RAW_SECTION *rs; + u8 *u8; + u32 u32; + } fsp_ptr; + u32 *image_id; - timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ? - TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE); +#ifndef CONFIG_FSP_LOC +#error "CONFIG_FSP_LOC must be set." +#endif - Status = NotifyPhaseProc (&NotifyPhaseParams); + for (;;) { + /* Get the FSP binary base address in CBFS */ + fsp_ptr.u8 = (u8 *)CONFIG_FSP_LOC; - timestamp_add_now(Phase == EnumInitPhaseReadyToBoot ? - TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE); + /* Check the FV signature, _FVH */ + if (fsp_ptr.fvh->Signature != 0x4856465F) { + fsp_ptr.u8 = (u8 *)ERROR_NO_FV_SIG; + break; + } - if (Status != 0) - printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); -} -#endif /* #ifndef __PRE_RAM__ */ + /* Locate the file header which follows the FV header. */ + fsp_ptr.u8 += fsp_ptr.fvh->ExtHeaderOffset; + fsp_ptr.u8 += fsp_ptr.fveh->ExtHeaderSize; + fsp_ptr.u8 = (u8 *)((fsp_ptr.u32 + 7) & 0xFFFFFFF8); + + /* Check the FFS GUID */ + if ((((u32 *)&fsp_ptr.ffh->Name)[0] != 0x912740BE) + || (((u32 *)&fsp_ptr.ffh->Name)[1] != 0x47342284) + || (((u32 *)&fsp_ptr.ffh->Name)[2] != 0xB08471B9) + || (((u32 *)&fsp_ptr.ffh->Name)[3] != 0x0C3F3527)) { + fsp_ptr.u8 = (u8 *)ERROR_NO_FFS_GUID; + break; + } -#ifdef __PRE_RAM__ + /* Locate the Raw Section Header */ + fsp_ptr.u8 += sizeof(EFI_FFS_FILE_HEADER); -/* - * Call the FSP to do memory init. The FSP doesn't return to this function. - * The FSP returns to the romstage_main_continue(). - */ -void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) -{ - FSP_FSP_INIT FspInitApi; - FSP_INIT_PARAMS FspInitParams; - FSP_INIT_RT_BUFFER FspRtBuffer; -#if IS_ENABLED(CONFIG_FSP_USES_UPD) - UPD_DATA_REGION fsp_upd_data; -#endif - - memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); - FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; - FspInitParams.NvsBufferPtr = NULL; + if (fsp_ptr.rs->Type != EFI_SECTION_RAW) { + fsp_ptr.u8 = (u8 *)ERROR_NO_INFO_HEADER; + break; + } -#if IS_ENABLED(CONFIG_FSP_USES_UPD) - FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data; -#endif - FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer; - FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ChipsetFspReturnPoint; - FspInitApi = (FSP_FSP_INIT)(fsp_ptr->ImageBase + fsp_ptr->FspInitEntry); + /* Locate the FSP INFO Header which follows the Raw Header. */ + fsp_ptr.u8 += sizeof(EFI_RAW_SECTION); - /* Call the chipset code to fill in the chipset specific structures */ - chipset_fsp_early_init(&FspInitParams, fsp_ptr); + /* Verify that the FSP base address.*/ + if (fsp_ptr.fih->ImageBase != CONFIG_FSP_LOC) { + fsp_ptr.u8 = (u8 *)ERROR_IMAGEBASE_MISMATCH; + break; + } - /* Call back to romstage for board specific changes */ - romstage_fsp_rt_buffer_callback(&FspRtBuffer); + /* Verify the FSP Signature */ + if (fsp_ptr.fih->Signature != FSP_SIG) { + fsp_ptr.u8 = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH; + break; + } - FspInitApi(&FspInitParams); + /* Verify the FSP ID */ + image_id = (u32 *)&fsp_ptr.fih->ImageId[0]; + if ((image_id[0] != CONFIG_FSP_IMAGE_ID_DWORD0) + || (image_id[1] != CONFIG_FSP_IMAGE_ID_DWORD1)) + fsp_ptr.u8 = (u8 *)ERROR_FSP_SIG_MISMATCH; + break; + } - /* Should never return. Control will continue from ContinuationFunc */ - die("Uh Oh! FspInitApi returned"); + return fsp_ptr.fih; } -#endif /* __PRE_RAM__ */ -volatile u8 * find_fsp () +void print_fsp_info(FSP_INFO_HEADER *fsp_header) { - -#ifdef __PRE_RAM__ - volatile register u8 *fsp_ptr asm ("eax"); - - /* Entry point for CAR assembly routine */ - __asm__ __volatile__ ( - ".global find_fsp\n\t" - "find_fsp:\n\t" - ); -#else - volatile u8 *fsp_ptr; -#endif /* __PRE_RAM__ */ - -#ifndef CONFIG_FSP_LOC -#error "CONFIG_FSP_LOC must be set." -#endif - - /* The FSP is stored in CBFS */ - fsp_ptr = (u8 *) CONFIG_FSP_LOC; - - /* Check the FV signature, _FVH */ - if (((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->Signature == 0x4856465F) { - /* Go to the end of the FV header and align the address. */ - fsp_ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)fsp_ptr)->ExtHeaderOffset; - fsp_ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)fsp_ptr)->ExtHeaderSize; - fsp_ptr = (u8 *)(((u32)fsp_ptr + 7) & 0xFFFFFFF8); - } else { - fsp_ptr = (u8*)ERROR_NO_FV_SIG; - } - - /* Check the FFS GUID */ - if (((u32)fsp_ptr > 0xff) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[0] == 0x912740BE) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[1] == 0x47342284) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[2] == 0xB08471B9) && - (((u32 *)&(((EFI_FFS_FILE_HEADER *)fsp_ptr)->Name))[3] == 0x0C3F3527)) { - /* Add the FFS Header size to the base to find the Raw section Header */ - fsp_ptr += sizeof(EFI_FFS_FILE_HEADER); - } else { - fsp_ptr = (u8 *)ERROR_NO_FFS_GUID; + u8 *fsp_base; + + fsp_base = (u8 *)fsp_header->ImageBase; + printk(BIOS_SPEW, "FSP_INFO_HEADER: %p\n", fsp_header); + printk(BIOS_INFO, "FSP Signature: %c%c%c%c%c%c%c%c\n", + fsp_header->ImageId[0], fsp_header->ImageId[1], + fsp_header->ImageId[2], fsp_header->ImageId[3], + fsp_header->ImageId[4], fsp_header->ImageId[5], + fsp_header->ImageId[6], fsp_header->ImageId[7]); + printk(BIOS_INFO, "FSP Header Version: %d\n", + fsp_header->HeaderRevision); + printk(BIOS_INFO, "FSP Revision: %d.%d\n", + (u8)((fsp_header->ImageRevision >> 8) & 0xff), + (u8)(fsp_header->ImageRevision & 0xff)); +#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS) + printk(BIOS_SPEW, "FSP Entry Points:\n"); + printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base); + printk(BIOS_SPEW, " 0x%p: TempRamInit\n", + &fsp_base[fsp_header->TempRamInitEntryOffset]); + printk(BIOS_SPEW, " 0x%p: FspInit\n", + &fsp_base[fsp_header->FspInitEntryOffset]); + if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) { + printk(BIOS_SPEW, " 0x%p: MemoryInit\n", + &fsp_base[fsp_header->FspMemoryInitEntryOffset]); + printk(BIOS_SPEW, " 0x%p: TempRamExit\n", + &fsp_base[fsp_header->TempRamExitEntryOffset]); + printk(BIOS_SPEW, " 0x%p: SiliconInit\n", + &fsp_base[fsp_header->FspSiliconInitEntryOffset]); } + printk(BIOS_SPEW, " 0x%p: NotifyPhase\n", + &fsp_base[fsp_header->NotifyPhaseEntryOffset]); + printk(BIOS_SPEW, " 0x%p: Image End\n", + &fsp_base[fsp_header->ImageSize]); +#endif +} - if (((u32)fsp_ptr > 0xff) && - ((EFI_RAW_SECTION *)fsp_ptr)->Type == EFI_SECTION_RAW) { - /* Add the Raw Header size to the base to find the FSP INFO Header */ - fsp_ptr += sizeof(EFI_RAW_SECTION); - } else { - fsp_ptr = (u8 *)ERROR_NO_INFO_HEADER; - } +#if ENV_RAMSTAGE - /* Verify that the FSP is set to the base address we're expecting.*/ - if (((u32)fsp_ptr > 0xff) && - (*(u32*)(fsp_ptr + FSP_IMAGE_BASE_LOC) != CONFIG_FSP_LOC)) { - fsp_ptr = (u8 *)ERROR_IMAGEBASE_MISMATCH; - } +void fsp_notify(u32 phase) +{ + FSP_NOTIFY_PHASE notify_phase_proc; + NOTIFY_PHASE_PARAMS notify_phase_params; + EFI_STATUS status; + FSP_INFO_HEADER *fsp_header_ptr; - /* Verify the FSP Signature */ - if (((u32)fsp_ptr > 0xff) && - (*(u32*)(fsp_ptr + FSP_IMAGE_SIG_LOC) != FSP_SIG)){ - fsp_ptr = (u8 *)ERROR_INFO_HEAD_SIG_MISMATCH; + fsp_header_ptr = fsp_get_fih(); + if (fsp_header_ptr == NULL) { + fsp_header_ptr = (void *)find_fsp(); + if ((u32)fsp_header_ptr < 0xff) { + /* output something in case there is no serial */ + post_code(0x4F); + die("Can't find the FSP!\n"); + } } - /* Verify the FSP ID */ - if (((u32)fsp_ptr > 0xff) && - ((*(u32 *)(fsp_ptr + FSP_IMAGE_ID_LOC) != FSP_IMAGE_ID_DWORD0) || - (*(u32 *)(fsp_ptr + (FSP_IMAGE_ID_LOC + 4)) != FSP_IMAGE_ID_DWORD1))) { - fsp_ptr = (u8 *)ERROR_FSP_SIG_MISMATCH; - } + /* call FSP PEI to Notify PostPciEnumeration */ + notify_phase_proc = (FSP_NOTIFY_PHASE)(fsp_header_ptr->ImageBase + + fsp_header_ptr->NotifyPhaseEntryOffset); + notify_phase_params.Phase = phase; - return (fsp_ptr); -} + timestamp_add_now(phase == EnumInitPhaseReadyToBoot ? + TS_FSP_BEFORE_FINALIZE : TS_FSP_BEFORE_ENUMERATE); -/** finds the saved temporary memory information in the FSP HOB list - * - * @param hob_list_ptr pointer to the start of the hob list - * @return pointer to saved CAR MEM or NULL if not found. - */ -void * find_saved_temp_mem(void *hob_list_ptr) -{ - EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; - EFI_HOB_GUID_TYPE *saved_mem_hob = - (EFI_HOB_GUID_TYPE *) find_hob_by_guid( - hob_list_ptr, &temp_hob_guid); + status = notify_phase_proc(&notify_phase_params); - if (saved_mem_hob == NULL) - return NULL; + timestamp_add_now(phase == EnumInitPhaseReadyToBoot ? + TS_FSP_AFTER_FINALIZE : TS_FSP_AFTER_ENUMERATE); - return (void *) ((char *) saved_mem_hob + sizeof(EFI_HOB_GUID_TYPE)); + if (status != 0) + printk(BIOS_ERR, "FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", + phase, status); } -#ifndef FSP_RESERVE_MEMORY_SIZE -/** @brief locates the HOB containing the location of the fsp reserved mem area - * - * @param hob_list_ptr pointer to the start of the hob list - * @return pointer to the start of the FSP reserved memory or NULL if not found. - */ -void * find_fsp_reserved_mem(void *hob_list_ptr) +static void fsp_notify_boot_state_callback(void *arg) { - EFI_GUID fsp_reserved_guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; - EFI_HOB_RESOURCE_DESCRIPTOR *fsp_reserved_mem = - (EFI_HOB_RESOURCE_DESCRIPTOR *) find_hob_by_guid( - hob_list_ptr, &fsp_reserved_guid); + u32 phase = (u32)arg; - if (fsp_reserved_mem == NULL) - return NULL; - - return (void *)((uintptr_t)fsp_reserved_mem->PhysicalStart); + printk(BIOS_SPEW, "Calling FspNotify(0x%08x)\n", phase); + fsp_notify(phase); } -#endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, + fsp_notify_boot_state_callback, + (void *)EnumInitPhaseAfterPciEnumeration); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, + fsp_notify_boot_state_callback, + (void *)EnumInitPhaseReadyToBoot); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, + fsp_notify_boot_state_callback, + (void *)EnumInitPhaseReadyToBoot); -void print_fsp_info(void) { +#endif /* ENV_RAMSTAGE */ - if (fsp_header_ptr == NULL) - fsp_header_ptr = (void *)find_fsp(); - if ((u32)fsp_header_ptr < 0xff) { - post_code(0x4F); /* output something in case there is no serial */ - die("Can't find the FSP!\n"); - } +struct fsp_runtime { + uint32_t fih; + uint32_t hob_list; +} __attribute__((packed)); - if (FspHobListPtr == NULL) { - FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); - } - printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr); - printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision); - printk(BIOS_INFO,"FSP Revision: %d.%d\n", - (u8)((fsp_header_ptr->ImageRevision >> 8) & 0xff), - (u8)(fsp_header_ptr->ImageRevision & 0xff)); -} - - -#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) -/** - * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM - */ -int save_mrc_data(void *hob_start) +void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list) { - u32 *mrc_hob; - u32 *mrc_hob_data; - u32 mrc_hob_size; - struct mrc_data_container *mrc_data; - int output_len; - const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - - mrc_hob = GetNextGuidHob(&mrc_guid, hob_start); - if (mrc_hob == NULL){ - printk(BIOS_DEBUG, "Memory Configure Data Hob is not present\n"); - return(0); - } + struct fsp_runtime *fspr; - mrc_hob_data = GET_GUID_HOB_DATA (mrc_hob); - mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob); + fspr = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*fspr)); - printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n", - (void *)mrc_hob_data, mrc_hob_size); + if (fspr == NULL) + die("Can't save FSP runtime information.\n"); - output_len = ALIGN(mrc_hob_size, 16); + fspr->fih = (uintptr_t)fih; + fspr->hob_list = (uintptr_t)hob_list; +} - /* Save the MRC S3/fast boot/ADR restore data to cbmem */ - mrc_data = cbmem_add (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); +FSP_INFO_HEADER *fsp_get_fih(void) +{ + struct fsp_runtime *fspr; - /* Just return if there was a problem with getting CBMEM */ - if (mrc_data == NULL) { - printk(BIOS_WARNING, "CBMEM was not available to save the fast boot cache data.\n"); - return 0; - } + fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME); - printk(BIOS_DEBUG, "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n", - (void *)mrc_hob_data, mrc_data, output_len); + if (fspr == NULL) + return NULL; - mrc_data->mrc_signature = MRC_DATA_SIGNATURE; - mrc_data->mrc_data_size = output_len; - mrc_data->reserved = 0; - memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size); + return (void *)(uintptr_t)fspr->fih; +} - /* Zero the unused space in aligned buffer. */ - if (output_len > mrc_hob_size) - memset((mrc_data->mrc_data + mrc_hob_size), 0, - output_len - mrc_hob_size); +void *fsp_get_hob_list(void) +{ + struct fsp_runtime *fspr; - mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data, - mrc_data->mrc_data_size); + fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME); - printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n"); - hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len / 4); - return (1); -} -#endif /* CONFIG_ENABLE_MRC_CACHE */ + if (fspr == NULL) + return NULL; -static void find_fsp_hob_update_mrc(void *unused) -{ - /* Set the global HOB list pointer */ - FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER)); - - if (!FspHobListPtr){ - printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n"); - } else { - /* 0x0000: Print all types */ - print_hob_type_structure(0x000, FspHobListPtr); - - #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) - if(save_mrc_data(FspHobListPtr)) - update_mrc_cache(NULL); - else - printk(BIOS_DEBUG,"Not updating MRC data in flash.\n"); - #endif - } + return (void *)(uintptr_t)fspr->hob_list; } -/** @brief Notify FSP for PostPciEnumeration - * - * @param unused - */ -static void fsp_after_pci_enum(void *unused) +void fsp_update_fih(FSP_INFO_HEADER *fih) { - /* This call needs to be done before resource allocation. */ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); - FspNotify(EnumInitPhaseAfterPciEnumeration); - printk(BIOS_DEBUG, - "Returned from FspNotify(EnumInitPhaseAfterPciEnumeration)\n"); -} + struct fsp_runtime *fspr; -/** @brief Notify FSP for ReadyToBoot - * - * @param unused - */ -static void fsp_finalize(void *unused) -{ - printk(BIOS_DEBUG, "FspNotify(EnumInitPhaseReadyToBoot)\n"); - print_fsp_info(); - FspNotify(EnumInitPhaseReadyToBoot); - printk(BIOS_DEBUG, "Returned from FspNotify(EnumInitPhaseReadyToBoot)\n"); -} + fspr = cbmem_find(CBMEM_ID_FSP_RUNTIME); -/* Set up for the ramstage FSP calls */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, fsp_after_pci_enum, NULL); -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL); + if (fspr == NULL) + die("Can't update FSP runtime information.\n"); -/* Update the MRC/fast boot cache as part of the late table writing stage */ -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ + fspr->fih = (uintptr_t)fih; +} diff --git a/src/drivers/intel/fsp1_1/fsp_util.h b/src/drivers/intel/fsp1_1/fsp_util.h index d65b842..554fc44 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.h +++ b/src/drivers/intel/fsp1_1/fsp_util.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,35 +21,52 @@ #ifndef FSP_UTIL_H #define FSP_UTIL_H +#include <types.h> +#include <arch/cpu.h> +#include <fsp_gop.h> + +/* + * The following are functions with prototypes defined in the EDK2 headers. The + * EDK2 headers are included with chipset_fsp_util.h. Define the following + * names to reduce the use of CamelCase in the other source files. + */ +#define GetHobList get_hob_list +#define GetNextHob get_next_hob +#define GetFirstHob get_first_hob +#define GetNextGuidHob get_next_guid_hob +#define GetFirstGuidHob get_first_guid_hob + +/* Include the EDK2 headers */ #include <chipset_fsp_util.h> -#include "fsp_values.h" #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) int save_mrc_data(void *hob_start); void * find_and_set_fastboot_cache(void); #endif -volatile u8 * find_fsp (void); +/* find_fsp() should only be called from assembly code. */ +FSP_INFO_HEADER *find_fsp(void); +/* Set FSP's runtime information. */ +void fsp_set_runtime(FSP_INFO_HEADER *fih, void *hob_list); +/* Use a new FSP_INFO_HEADER at runtime. */ +void fsp_update_fih(FSP_INFO_HEADER *fih); +/* fsp_get_fih() is only valid after calling fsp_set_runtime(). */ +FSP_INFO_HEADER *fsp_get_fih(void); +/* fsp_get_hob_list() is only valid after calling fsp_set_runtime(). */ +void *fsp_get_hob_list(void); void fsp_early_init(FSP_INFO_HEADER *fsp_info); -void FspNotify(u32 Phase); -void FspNotifyReturnPoint(EFI_STATUS Status, VOID *HobListPtr); -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer); -void print_fsp_info(void); -void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, - FSP_INFO_HEADER *fsp_ptr); -void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); -void * find_saved_temp_mem(void *hob_list_ptr); -void * find_fsp_reserved_mem(void *hob_list_ptr); - -/* functions in hob.c */ -void print_hob_mem_attributes(void *Hobptr); -void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); -void print_hob_resource_attributes(void *Hobptr); -void print_guid_type_attributes(void *Hobptr); -const char * get_hob_type_string(void *Hobptr); -void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); -uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2); -void printguid(EFI_GUID *guid); +void fsp_notify(u32 phase); +void print_hob_type_structure(u16 hob_type, void *hob_list_ptr); +void print_fsp_info(FSP_INFO_HEADER *fsp_header); +void *get_next_type_guid_hob(UINT16 type, const EFI_GUID *guid, + const void *hob_start); +void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); +void *get_first_resource_hob(const EFI_GUID *guid); +/* + * Relocate FSP entire binary into ram. Returns NULL on error. Otherwise the + * FSP_INFO_HEADER pointer to the relocated FSP. + */ +FSP_INFO_HEADER *fsp_relocate(void *fsp_src, size_t size); /* Additional HOB types not included in the FSP: * #define EFI_HOB_TYPE_HANDOFF 0x0001 @@ -73,63 +91,31 @@ struct mrc_data_container { u32 mrc_signature; // "MRCD" u32 mrc_data_size; // Actual total size of this structure u32 mrc_checksum; // IP style checksum - u32 reserved; // For header alignment + u32 reserved; // For header alignment u8 mrc_data[0]; // Variable size, platform/run time dependent. } __attribute__ ((packed)); struct mrc_data_container *find_current_mrc_cache(void); - -#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif -#endif +#endif /* CONFIG_ENABLE_MRC_CACHE */ /* The offset in bytes from the start of the info structure */ -#define FSP_IMAGE_SIG_LOC 0 -#define FSP_IMAGE_ID_LOC 16 -#define FSP_IMAGE_BASE_LOC 28 +#define FSP_IMAGE_SIG_LOC 0 +#define FSP_IMAGE_ID_LOC 16 +#define FSP_IMAGE_BASE_LOC 28 -#define FSP_SIG 0x48505346 /* 'FSPH' */ +#define FSP_SIG 0x48505346 /* 'FSPH' */ #define ERROR_NO_FV_SIG 1 -#define ERROR_NO_FFS_GUID 2 +#define ERROR_NO_FFS_GUID 2 #define ERROR_NO_INFO_HEADER 3 #define ERROR_IMAGEBASE_MISMATCH 4 -#define ERROR_INFO_HEAD_SIG_MISMATCH 5 +#define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6 -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE extern void *FspHobListPtr; #endif -#define UPD_DEFAULT_CHECK(member) \ - if (config->member != UPD_DEFAULT) { \ - UpdData->member = config->member - 1; \ - } \ - printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \ - config->member ? "(set)" : "(default)"); - -#define UPD_SPD_CHECK(member) \ - if (config->member == UPD_SPD_ADDR_DISABLED) { \ - UpdData->member = 0x00; \ - } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \ - UpdData->member = config->member; \ - } \ - printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \ - config->member ? "(set)" : "(default)"); - -#define UPD_DEVICE_CHECK(devicename, member, statement) \ - case devicename: \ - UpdData->member = dev->enabled; \ - printk(FSP_INFO_LEVEL, statement "%s\n", \ - UpdData->member?"Enabled":"Disabled"); \ - break; - - -#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID -#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ - { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }; -#endif - #endif /* FSP_UTIL_H */ diff --git a/src/drivers/intel/fsp1_1/fsp_values.h b/src/drivers/intel/fsp1_1/fsp_values.h deleted file mode 100644 index e5098bb..0000000 --- a/src/drivers/intel/fsp1_1/fsp_values.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef FSP_VALUES_H -#define FSP_VALUES_H - -#ifndef FSP_DEBUG_LEVEL -# define FSP_DEBUG_LEVEL BIOS_SPEW -#endif - -#ifndef FSP_INFO_LEVEL -# define FSP_INFO_LEVEL BIOS_DEBUG -#endif - -#define INCREMENT_FOR_DEFAULT(x) (x+1) - -#define UPD_DEFAULT 0x00 -#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0) -#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1) -#define UPD_USE_DEVICETREE 0xff - -#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT -#define UPD_SPD_ADDR_DISABLED 0xFF - -#endif diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 99c4ba1..23404f4 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,150 +18,329 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> +#include <arch/early_variables.h> +#include <arch/hlt.h> +#include <bootstate.h> +#include <cbmem.h> #include <console/console.h> -#include <lib.h> // hexdump #include "fsp_util.h" +#include <ip_checksum.h> +#include <lib.h> // hexdump +#include <string.h> + +/* + * Reads a 64-bit value from memory that may be unaligned. + * + * This function returns the 64-bit value pointed to by buffer. The + * function guarantees that the read operation does not produce an + * alignment fault. + * + * If buffer is NULL, then ASSERT(). + * + * buffer: Pointer to a 64-bit value that may be unaligned. + * + * Returns the 64-bit value read from buffer. + * + */ +static +uint64_t +read_unaligned_64( + const uint64_t *buffer + ) +{ + ASSERT(buffer != NULL); + return *buffer; +} -/** Displays a GUID's address and value +/* + * Compares two GUIDs. + * + * This function compares guid1 to guid2. If the GUIDs are identical then + * TRUE is returned. If there are any bit differences in the two GUIDs, + * then FALSE is returned. + * + * If guid1 is NULL, then ASSERT(). + * If guid2 is NULL, then ASSERT(). + * + * guid1: A pointer to a 128 bit GUID. + * guid2: A pointer to a 128 bit GUID. * - * @param guid pointer to the GUID to display + * Returns non-zero if guid1 and guid2 are identical, otherwise returns 0. + * + */ +static +long +compare_guid( + const EFI_GUID * guid1, + const EFI_GUID * guid2 + ) +{ + uint64_t low_part_of_guid1; + uint64_t low_part_of_guid2; + uint64_t high_part_of_guid1; + uint64_t high_part_of_guid2; + + low_part_of_guid1 = read_unaligned_64((const uint64_t *) guid1); + low_part_of_guid2 = read_unaligned_64((const uint64_t *) guid2); + high_part_of_guid1 = read_unaligned_64((const uint64_t *) guid1 + 1); + high_part_of_guid2 = read_unaligned_64((const uint64_t *) guid2 + 1); + + return ((low_part_of_guid1 == low_part_of_guid2) + && (high_part_of_guid1 == high_part_of_guid2)); +} + +/* Returns the pointer to the HOB list. */ +VOID * +EFIAPI +get_hob_list( + VOID + ) +{ + void *hob_list; + + hob_list = fsp_get_hob_list(); + if (hob_list == NULL) + die("Call fsp_set_runtime() before this call!\n"); + return hob_list; +} + +/* Returns the next instance of a HOB type from the starting HOB. */ +VOID * +EFIAPI +get_next_hob( + UINT16 type, + CONST VOID *hob_start + ) +{ + EFI_PEI_HOB_POINTERS hob; + + ASSERT(hob_start != NULL); + + hob.Raw = (UINT8 *)hob_start; + + /* Parse the HOB list until end of list or matching type is found. */ + while (!END_OF_HOB_LIST(hob.Raw)) { + if (hob.Header->HobType == type) + return hob.Raw; + if (GET_HOB_LENGTH(hob.Raw) < sizeof(*hob.Header)) + break; + hob.Raw = GET_NEXT_HOB(hob.Raw); + } + return NULL; +} + +/* Returns the first instance of a HOB type among the whole HOB list. */ +VOID * +EFIAPI +get_first_hob( + UINT16 type + ) +{ + VOID *hob_list; + + hob_list = get_hob_list(); + return get_next_hob(type, hob_list); +} + +/* Returns the next instance of the matched GUID HOB from the starting HOB. */ +VOID * +EFIAPI +get_next_guid_hob( + CONST EFI_GUID * guid, + CONST VOID *hob_start + ) +{ + EFI_PEI_HOB_POINTERS hob; + + hob.Raw = (UINT8 *)hob_start; + while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_GUID_EXTENSION, hob.Raw)) + != NULL) { + if (compare_guid(guid, &hob.Guid->Name)) + break; + hob.Raw = GET_NEXT_HOB(hob.Raw); + } + return hob.Raw; +} + +/* + * Returns the first instance of the matched GUID HOB among the whole HOB list. + */ +VOID * +EFIAPI +get_first_guid_hob( + CONST EFI_GUID * guid + ) +{ + return get_next_guid_hob(guid, get_hob_list()); +} + +/* + * Returns the next instance of the matching resource HOB from the starting HOB. */ -void printguid(EFI_GUID *guid) +void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start) { - printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-", - guid, (unsigned long)guid->Data1, - guid->Data2, guid->Data3); - printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n", - guid->Data4[0], guid->Data4[1], - guid->Data4[2], guid->Data4[3], - guid->Data4[4], guid->Data4[5], - guid->Data4[6], guid->Data4[7] ); + EFI_PEI_HOB_POINTERS hob; + + hob.Raw = (UINT8 *)hob_start; + while ((hob.Raw = get_next_hob(EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, + hob.Raw)) != NULL) { + if (compare_guid(guid, &hob.ResourceDescriptor->Owner)) + break; + hob.Raw = GET_NEXT_HOB(hob.Raw); + } + return hob.Raw; +} + +/* + * Returns the first instance of the matching resource HOB among the whole HOB + * list. + */ +void *get_first_resource_hob(const EFI_GUID *guid) +{ + return get_next_resource_hob(guid, get_hob_list()); } -void print_hob_mem_attributes(void *Hobptr) +static void print_hob_mem_attributes(void *hob_ptr) { - EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr; - EFI_MEMORY_TYPE Hobmemtype = HobMemoryPtr->AllocDescriptor.MemoryType; - u64 Hobmemaddr = HobMemoryPtr->AllocDescriptor.MemoryBaseAddress; - u64 Hobmemlength = HobMemoryPtr->AllocDescriptor.MemoryLength; - const char * Hobmemtypenames[15]; - - Hobmemtypenames[0] = "EfiReservedMemoryType"; - Hobmemtypenames[1] = "EfiLoaderCode"; - Hobmemtypenames[2] = "EfiLoaderData"; - Hobmemtypenames[3] = "EfiBootServicesCode"; - Hobmemtypenames[4] = "EfiBootServicesData"; - Hobmemtypenames[5] = "EfiRuntimeServicesCode"; - Hobmemtypenames[6] = "EfiRuntimeServicesData"; - Hobmemtypenames[7] = "EfiConventionalMemory"; - Hobmemtypenames[8] = "EfiUnusableMemory"; - Hobmemtypenames[9] = "EfiACPIReclaimMemory"; - Hobmemtypenames[10] = "EfiACPIMemoryNVS"; - Hobmemtypenames[11] = "EfiMemoryMappedIO"; - Hobmemtypenames[12] = "EfiMemoryMappedIOPortSpace"; - Hobmemtypenames[13] = "EfiPalCode"; - Hobmemtypenames[14] = "EfiMaxMemoryType"; + EFI_HOB_MEMORY_ALLOCATION *hob_memory_ptr = + (EFI_HOB_MEMORY_ALLOCATION *)hob_ptr; + EFI_MEMORY_TYPE hob_mem_type = + hob_memory_ptr->AllocDescriptor.MemoryType; + u64 hob_mem_addr = hob_memory_ptr->AllocDescriptor.MemoryBaseAddress; + u64 hob_mem_length = hob_memory_ptr->AllocDescriptor.MemoryLength; + const char *hob_mem_type_names[15]; + + hob_mem_type_names[0] = "EfiReservedMemoryType"; + hob_mem_type_names[1] = "EfiLoaderCode"; + hob_mem_type_names[2] = "EfiLoaderData"; + hob_mem_type_names[3] = "EfiBootServicesCode"; + hob_mem_type_names[4] = "EfiBootServicesData"; + hob_mem_type_names[5] = "EfiRuntimeServicesCode"; + hob_mem_type_names[6] = "EfiRuntimeServicesData"; + hob_mem_type_names[7] = "EfiConventionalMemory"; + hob_mem_type_names[8] = "EfiUnusableMemory"; + hob_mem_type_names[9] = "EfiACPIReclaimMemory"; + hob_mem_type_names[10] = "EfiACPIMemoryNVS"; + hob_mem_type_names[11] = "EfiMemoryMappedIO"; + hob_mem_type_names[12] = "EfiMemoryMappedIOPortSpace"; + hob_mem_type_names[13] = "EfiPalCode"; + hob_mem_type_names[14] = "EfiMaxMemoryType"; printk(BIOS_SPEW, " Memory type %s (0x%x)\n", - Hobmemtypenames[(u32)Hobmemtype], (u32) Hobmemtype); + hob_mem_type_names[(u32)hob_mem_type], + (u32)hob_mem_type); printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n", - (unsigned long)Hobmemaddr, (unsigned long)Hobmemlength); + (unsigned long)hob_mem_addr, + (unsigned long)hob_mem_length); } -void print_hob_resource_attributes(void *Hobptr) +static void print_hob_resource_attributes(void *hob_ptr) { - EFI_HOB_RESOURCE_DESCRIPTOR *HobResourcePtr = - (EFI_HOB_RESOURCE_DESCRIPTOR *)Hobptr; - u32 Hobrestype = HobResourcePtr->ResourceType; - u32 Hobresattr = HobResourcePtr->ResourceAttribute; - u64 Hobresaddr = HobResourcePtr->PhysicalStart; - u64 Hobreslength = HobResourcePtr->ResourceLength; - const char *Hobrestypestr = NULL; - - // HOB Resource Types - switch (Hobrestype) { + EFI_HOB_RESOURCE_DESCRIPTOR *hob_resource_ptr = + (EFI_HOB_RESOURCE_DESCRIPTOR *)hob_ptr; + u32 hob_res_type = hob_resource_ptr->ResourceType; + u32 hob_res_attr = hob_resource_ptr->ResourceAttribute; + u64 hob_res_addr = hob_resource_ptr->PhysicalStart; + u64 hob_res_length = hob_resource_ptr->ResourceLength; + const char *hob_res_type_str = NULL; + + /* HOB Resource Types */ + switch (hob_res_type) { case EFI_RESOURCE_SYSTEM_MEMORY: - Hobrestypestr = "EFI_RESOURCE_SYSTEM_MEMORY"; break; + hob_res_type_str = "EFI_RESOURCE_SYSTEM_MEMORY"; + break; case EFI_RESOURCE_MEMORY_MAPPED_IO: - Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO"; break; + hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO"; + break; case EFI_RESOURCE_IO: - Hobrestypestr = "EFI_RESOURCE_IO"; break; + hob_res_type_str = "EFI_RESOURCE_IO"; + break; case EFI_RESOURCE_FIRMWARE_DEVICE: - Hobrestypestr = "EFI_RESOURCE_FIRMWARE_DEVICE"; break; + hob_res_type_str = "EFI_RESOURCE_FIRMWARE_DEVICE"; + break; case EFI_RESOURCE_MEMORY_MAPPED_IO_PORT: - Hobrestypestr = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT"; break; + hob_res_type_str = "EFI_RESOURCE_MEMORY_MAPPED_IO_PORT"; + break; case EFI_RESOURCE_MEMORY_RESERVED: - Hobrestypestr = "EFI_RESOURCE_MEMORY_RESERVED"; break; + hob_res_type_str = "EFI_RESOURCE_MEMORY_RESERVED"; + break; case EFI_RESOURCE_IO_RESERVED: - Hobrestypestr = "EFI_RESOURCE_IO_RESERVED"; break; + hob_res_type_str = "EFI_RESOURCE_IO_RESERVED"; + break; case EFI_RESOURCE_MAX_MEMORY_TYPE: - Hobrestypestr = "EFI_RESOURCE_MAX_MEMORY_TYPE"; break; + hob_res_type_str = "EFI_RESOURCE_MAX_MEMORY_TYPE"; + break; default: - Hobrestypestr = "EFI_RESOURCE_UNKNOWN"; break; + hob_res_type_str = "EFI_RESOURCE_UNKNOWN"; + break; } printk(BIOS_SPEW, " Resource %s (0x%0x) has attributes 0x%0x\n", - Hobrestypestr, Hobrestype, Hobresattr); + hob_res_type_str, hob_res_type, hob_res_attr); printk(BIOS_SPEW, " at location 0x%0lx with length 0x%0lx\n", - (unsigned long)Hobresaddr, (unsigned long)Hobreslength); + (unsigned long)hob_res_addr, + (unsigned long)hob_res_length); } -const char * get_hob_type_string(void *Hobptr) +static const char *get_hob_type_string(void *hob_ptr) { - EFI_HOB_GENERIC_HEADER *HobHeaderPtr = (EFI_HOB_GENERIC_HEADER *)Hobptr; - u16 Hobtype = HobHeaderPtr->HobType; - const char *Hobtypestring = NULL; + EFI_PEI_HOB_POINTERS hob; + const char *hob_type_string = NULL; + const EFI_GUID fsp_reserved_guid = + FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID; + const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + const EFI_GUID bootldr_tmp_mem_guid = + FSP_BOOTLOADER_TEMP_MEMORY_HOB_GUID; + const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID; + const EFI_GUID graphics_info_guid = EFI_PEI_GRAPHICS_INFO_HOB_GUID; - switch (Hobtype) { + hob.Header = (EFI_HOB_GENERIC_HEADER *)hob_ptr; + switch (hob.Header->HobType) { case EFI_HOB_TYPE_HANDOFF: - Hobtypestring = "EFI_HOB_TYPE_HANDOFF"; break; + hob_type_string = "EFI_HOB_TYPE_HANDOFF"; + break; case EFI_HOB_TYPE_MEMORY_ALLOCATION: - Hobtypestring = "EFI_HOB_TYPE_MEMORY_ALLOCATION"; break; + hob_type_string = "EFI_HOB_TYPE_MEMORY_ALLOCATION"; + break; case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: - Hobtypestring = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR"; break; + hob_type_string = "EFI_HOB_TYPE_RESOURCE_DESCRIPTOR"; + break; case EFI_HOB_TYPE_GUID_EXTENSION: - Hobtypestring = "EFI_HOB_TYPE_GUID_EXTENSION"; break; + hob_type_string = "EFI_HOB_TYPE_GUID_EXTENSION"; + if (compare_guid(&bootldr_tmp_mem_guid, &hob.Guid->Name)) + hob_type_string = "FSP_BOOTLOADER_TEMP_MEMORY_HOB"; + else if (compare_guid(&fsp_reserved_guid, &hob.Guid->Name)) + hob_type_string = "FSP_RESERVED_MEMORY_RESOURCE_HOB"; + else if (compare_guid(&mrc_guid, &hob.Guid->Name)) + hob_type_string = "FSP_NON_VOLATILE_STORAGE_HOB"; + else if (compare_guid(&bootldr_tolum_guid, &hob.Guid->Name)) + hob_type_string = "FSP_BOOTLOADER_TOLUM_HOB_GUID"; + else if (compare_guid(&graphics_info_guid, &hob.Guid->Name)) + hob_type_string = "EFI_PEI_GRAPHICS_INFO_HOB_GUID"; + break; case EFI_HOB_TYPE_MEMORY_POOL: - Hobtypestring = "EFI_HOB_TYPE_MEMORY_POOL"; break; + hob_type_string = "EFI_HOB_TYPE_MEMORY_POOL"; + break; case EFI_HOB_TYPE_UNUSED: - Hobtypestring = "EFI_HOB_TYPE_UNUSED"; break; + hob_type_string = "EFI_HOB_TYPE_UNUSED"; + break; case EFI_HOB_TYPE_END_OF_HOB_LIST: - Hobtypestring = "EFI_HOB_TYPE_END_OF_HOB_LIST"; break; + hob_type_string = "EFI_HOB_TYPE_END_OF_HOB_LIST"; + break; default: - Hobtypestring = "EFI_HOB_TYPE_UNRECOGNIZED"; break; + hob_type_string = "EFI_HOB_TYPE_UNRECOGNIZED"; + break; } - return Hobtypestring; + return hob_type_string; } -/** Displays the length, location, and GUID value of a GUID extension - * - * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard - * HOB header containing the HOB type and length, and a GUID for - * identification. The rest of the data is undefined and must be known - * based on the GUID. - * - * This displays the entire HOB length, and the location of the start - * of the HOB, *NOT* the length of or the start of the data inside the HOB. - * - * @param Hobptr - */ -void print_guid_type_attributes(void *Hobptr) -{ - printk(BIOS_SPEW, " at location %p with length0x%0lx\n ", - Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \ - Hobptr)->Guid->Header.HobLength)); - printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name)); - -} - -/* Print out a structure of all the HOBs +/* + * Print out a structure of all the HOBs * that match a certain type: * Print all types (0x0000) - * EFI_HOB_TYPE_HANDOFF (0x0001) + * EFI_HOB_TYPE_HANDOFF (0x0001) * EFI_HOB_TYPE_MEMORY_ALLOCATION (0x0002) * EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (0x0003) * EFI_HOB_TYPE_GUID_EXTENSION (0x0004) @@ -168,102 +348,148 @@ void print_guid_type_attributes(void *Hobptr) * EFI_HOB_TYPE_UNUSED (0xFFFE) * EFI_HOB_TYPE_END_OF_HOB_LIST (0xFFFF) */ -void print_hob_type_structure(u16 Hobtype, void *Hoblistptr) +void print_hob_type_structure(u16 hob_type, void *hob_list_ptr) { - u32 *Currenthob; - u32 *Nexthob = 0; - u8 Lasthob = 0; - u32 Currenttype; - const char *Currenttypestr; + u32 *current_hob; + u32 *next_hob = 0; + u8 last_hob = 0; + u32 current_type; + const char *current_type_str; - Currenthob = Hoblistptr; + current_hob = hob_list_ptr; - /* Print out HOBs of our desired type until + /* + * Print out HOBs of our desired type until * the end of the HOB list */ printk(BIOS_DEBUG, "\n=== FSP HOB Data Structure ===\n"); - printk(BIOS_DEBUG, "FSP Hoblistptr: 0x%0x\n", - (u32) Hoblistptr); + printk(BIOS_DEBUG, "0x%p: hob_list_ptr\n", hob_list_ptr); do { - EFI_HOB_GENERIC_HEADER *CurrentHeaderPtr = - (EFI_HOB_GENERIC_HEADER *)Currenthob; - Currenttype = CurrentHeaderPtr->HobType; /* Get the type of this HOB */ - Currenttypestr = get_hob_type_string(Currenthob); + EFI_HOB_GENERIC_HEADER *current_header_ptr = + (EFI_HOB_GENERIC_HEADER *)current_hob; + + /* Get the type of this HOB */ + current_type = current_header_ptr->HobType; + current_type_str = get_hob_type_string(current_hob); - if (Currenttype == Hobtype || Hobtype == 0x0000) { + if (current_type == hob_type || hob_type == 0x0000) { printk(BIOS_DEBUG, "HOB 0x%0x is an %s (type 0x%0x)\n", - (u32) Currenthob, Currenttypestr, Currenttype); - switch (Currenttype) { + (u32)current_hob, current_type_str, + current_type); + switch (current_type) { case EFI_HOB_TYPE_MEMORY_ALLOCATION: - print_hob_mem_attributes(Currenthob); break; + print_hob_mem_attributes(current_hob); + break; case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: - print_hob_resource_attributes(Currenthob); break; - case EFI_HOB_TYPE_GUID_EXTENSION: - print_guid_type_attributes(Currenthob); break; + print_hob_resource_attributes(current_hob); + break; } } - Lasthob = END_OF_HOB_LIST(Currenthob); /* Check for end of HOB list */ - if (!Lasthob) { - Nexthob = GET_NEXT_HOB(Currenthob); /* Get next HOB pointer */ - Currenthob = Nexthob; // Start on next HOB + /* Check for end of HOB list */ + last_hob = END_OF_HOB_LIST(current_hob); + if (!last_hob) { + /* Get next HOB pointer */ + next_hob = GET_NEXT_HOB(current_hob); + + /* Start on next HOB */ + current_hob = next_hob; } - } while (!Lasthob); + } while (!last_hob); printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n"); } - -/** Finds a HOB entry based on type and guid - * - * @param current_hob pointer to the start of the HOB list - * @param guid the GUID of the HOB entry to find - * @return pointer to the start of the requested HOB or NULL if not found. +#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) +/* + * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM */ -void * find_hob_by_guid(void *current_hob, EFI_GUID *guid) +int save_mrc_data(void *hob_start) { - do { - switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) { + u32 *mrc_hob; + u32 *mrc_hob_data; + u32 mrc_hob_size; + struct mrc_data_container *mrc_data; + int output_len; + const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; - case EFI_HOB_TYPE_MEMORY_ALLOCATION: - if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \ - current_hob)->AllocDescriptor.Name))) - return current_hob; - break; - case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: - if (guids_are_equal(guid, - &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \ - current_hob)->Owner))) - return current_hob; - break; - case EFI_HOB_TYPE_GUID_EXTENSION: - if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \ - current_hob)->Name))) - return current_hob; - break; - } + mrc_hob = get_next_guid_hob(&mrc_guid, hob_start); + if (mrc_hob == NULL) { + printk(BIOS_DEBUG, + "Memory Configure Data Hob is not present\n"); + return 0; + } - if (!END_OF_HOB_LIST(current_hob)) - current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */ - } while (!END_OF_HOB_LIST(current_hob)); + mrc_hob_data = GET_GUID_HOB_DATA(mrc_hob); + mrc_hob_size = (u32) GET_HOB_LENGTH(mrc_hob); - return NULL; -} + printk(BIOS_DEBUG, "Memory Configure Data Hob at %p (size = 0x%x).\n", + (void *)mrc_hob_data, mrc_hob_size); -/** Compares a pair of GUIDs to see if they are equal - * - * GUIDs are 128 bits long, so compare them as pairs of quadwords. - * - * @param guid1 pointer to the first of the GUIDs to compare - * @param guid2 pointer to the second of the GUIDs to compare - * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal - */ -uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2) -{ - uint64_t* guid_1 = (void *) guid1; - uint64_t* guid_2 = (void *) guid2; + output_len = ALIGN(mrc_hob_size, 16); + + /* Save the MRC S3/fast boot/ADR restore data to cbmem */ + mrc_data = cbmem_add(CBMEM_ID_MRCDATA, + output_len + sizeof(struct mrc_data_container)); - if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1))) + /* Just return if there was a problem with getting CBMEM */ + if (mrc_data == NULL) { + printk(BIOS_WARNING, + "CBMEM was not available to save the fast boot cache data.\n"); return 0; + } + + printk(BIOS_DEBUG, + "Copy FSP MRC DATA to HOB (source addr %p, dest addr %p, %u bytes)\n", + (void *)mrc_hob_data, mrc_data, output_len); + + mrc_data->mrc_signature = MRC_DATA_SIGNATURE; + mrc_data->mrc_data_size = output_len; + mrc_data->reserved = 0; + memcpy(mrc_data->mrc_data, (const void *)mrc_hob_data, mrc_hob_size); + /* Zero the unused space in aligned buffer. */ + if (output_len > mrc_hob_size) + memset((mrc_data->mrc_data + mrc_hob_size), 0, + output_len - mrc_hob_size); + + mrc_data->mrc_checksum = compute_ip_checksum(mrc_data->mrc_data, + mrc_data->mrc_data_size); + +#if IS_ENABLED(CONFIG_DISPLAY_FAST_BOOT_DATA) + printk(BIOS_SPEW, "Fast boot data (includes align and checksum):\n"); + hexdump32(BIOS_SPEW, (void *)mrc_data->mrc_data, output_len); +#endif return 1; } + +void __attribute__ ((weak)) update_mrc_cache(void *unused) +{ + printk(BIOS_ERR, "Add routine %s to save the MRC data.\n", __func__); +} +#endif /* CONFIG_ENABLE_MRC_CACHE */ + +#if ENV_RAMSTAGE + +static void find_fsp_hob_update_mrc(void *unused) +{ + void *hob_list_ptr; + + /* 0x0000: Print all types */ + hob_list_ptr = get_hob_list(); +#if IS_ENABLED(CONFIG_DISPLAY_HOBS) + print_hob_type_structure(0x000, hob_list_ptr); +#endif + + #if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) + if (save_mrc_data(hob_list_ptr)) + update_mrc_cache(NULL); + else + printk(BIOS_DEBUG, "Not updating MRC data in flash.\n"); + #endif +} + +/* Update the MRC/fast boot cache as part of the late table writing stage */ +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + find_fsp_hob_update_mrc, NULL); + +#endif /* ENV_RAMSTAGE */

1 0

Patch set updated for coreboot: 5fa64f2 cbmem: Add initial allocation support
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10148 -gerrit commit 5fa64f2365729ae14250a8644e9ddf83714d919d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri May 8 11:33:55 2015 -0700 cbmem: Add initial allocation support Add support to allocate a region just below CBMEM root. This region is reserved for FSP 1.1 to use for its stack and variables. BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: I1d4b36ab366e6f8e036335c56c1756f2dfaab3f5 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/include/cbmem.h | 18 ++++++++++++++++++ src/lib/imd_cbmem.c | 29 ++++++++++++++++++++--------- 2 files changed, 38 insertions(+), 9 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 07e5645..08c1d64 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -146,12 +146,30 @@ struct cbmem_entry; */ #define DYN_CBMEM_ALIGN_SIZE (4096) +#define CBMEM_ROOT_SIZE DYN_CBMEM_ALIGN_SIZE + +/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ +#define CBMEM_ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE +#define CBMEM_LG_ALIGN CBMEM_ROOT_MIN_SIZE + +/* Small allocation parameters. */ +#define CBMEM_SM_ROOT_SIZE 1024 +#define CBMEM_SM_ALIGN 32 + +/* Determine the size for CBMEM root and the small allocations */ +static inline size_t cbmem_overhead_size(void) +{ + return 2 * CBMEM_ROOT_MIN_SIZE; +} /* By default cbmem is attempted to be recovered. Returns 0 if cbmem was * recovered or 1 if cbmem had to be reinitialized. */ int cbmem_initialize(void); +int cbmem_initialize_id_size(u32 id, u64 size); + /* Initialize cbmem to be empty. */ void cbmem_initialize_empty(void); +void cbmem_initialize_empty_id_size(u32 id, u64 size); /* Return the top address for dynamic cbmem. The address returned needs to * be consistent across romstage and ramstage, and it is required to be diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 0649bf3..fc12c25 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -30,13 +30,6 @@ #include <arch/acpi.h> #endif -/* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ -#define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define LG_ALIGN ROOT_MIN_SIZE -/* Small allocation parameters. */ -#define SM_ROOT_SIZE 1024 -#define SM_ALIGN 32 - static inline struct imd *cbmem_get_imd(void) { /* Only supply a backing store for imd in ramstage. */ @@ -116,6 +109,11 @@ static struct imd *imd_init_backing_with_recover(struct imd *backing) void cbmem_initialize_empty(void) { + cbmem_initialize_empty_id_size(0, 0); +} + +void cbmem_initialize_empty_id_size(u32 id, u64 size) +{ struct imd *imd; struct imd imd_backing; @@ -127,12 +125,16 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM:\n"); - if (imd_create_tiered_empty(imd, ROOT_MIN_SIZE, LG_ALIGN, - SM_ROOT_SIZE, SM_ALIGN)) { + if (imd_create_tiered_empty(imd, CBMEM_ROOT_MIN_SIZE, CBMEM_LG_ALIGN, + CBMEM_SM_ROOT_SIZE, CBMEM_SM_ALIGN)) { printk(BIOS_DEBUG, "failed.\n"); return; } + /* Add the specified range first */ + if (size) + cbmem_add(id, size); + /* Complete migration to CBMEM. */ cbmem_run_init_hooks(); } @@ -146,6 +148,11 @@ static inline int cbmem_fail_recovery(void) int cbmem_initialize(void) { + return cbmem_initialize_id_size(0, 0); +} + +int cbmem_initialize_id_size(u32 id, u64 size) +{ struct imd *imd; struct imd imd_backing; @@ -167,6 +174,10 @@ int cbmem_initialize(void) imd_lockdown(imd); #endif + /* Add the specified range first */ + if (size) + cbmem_add(id, size); + /* Complete migration to CBMEM. */ cbmem_run_init_hooks();

1 0

Patch set updated for coreboot: 3035524 Braswell: Use Baytrail as Comparison Base
by Leroy P Leahy 12 May '15

12 May '15

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10117 -gerrit commit 3035524f2e7ad5fd1e49163035b290d672817f37 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 5 15:07:29 2015 -0700 Braswell: Use Baytrail as Comparison Base Add baytrail source for comparison with Braswell. BRANCH=none BUG=None TEST=None Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/braswell/Kconfig | 245 ++++++++ src/soc/intel/braswell/Makefile.inc | 107 ++++ src/soc/intel/braswell/acpi.c | 511 ++++++++++++++++ src/soc/intel/braswell/acpi/cpu.asl | 77 +++ src/soc/intel/braswell/acpi/device_nvs.asl | 87 +++ src/soc/intel/braswell/acpi/dptf/charger.asl | 59 ++ src/soc/intel/braswell/acpi/dptf/cpu.asl | 144 +++++ src/soc/intel/braswell/acpi/dptf/dptf.asl | 78 +++ src/soc/intel/braswell/acpi/dptf/thermal.asl | 203 ++++++ src/soc/intel/braswell/acpi/globalnvs.asl | 108 ++++ src/soc/intel/braswell/acpi/gpio.asl | 110 ++++ src/soc/intel/braswell/acpi/irq_helper.h | 48 ++ src/soc/intel/braswell/acpi/irqlinks.asl | 492 +++++++++++++++ src/soc/intel/braswell/acpi/irqroute.asl | 37 ++ src/soc/intel/braswell/acpi/lpc.asl | 167 +++++ src/soc/intel/braswell/acpi/lpe.asl | 119 ++++ src/soc/intel/braswell/acpi/lpss.asl | 712 ++++++++++++++++++++++ src/soc/intel/braswell/acpi/pcie.asl | 109 ++++ src/soc/intel/braswell/acpi/platform.asl | 78 +++ src/soc/intel/braswell/acpi/scc.asl | 187 ++++++ src/soc/intel/braswell/acpi/sleepstates.asl | 26 + src/soc/intel/braswell/acpi/southcluster.asl | 274 +++++++++ src/soc/intel/braswell/acpi/xhci.asl | 36 ++ src/soc/intel/braswell/bootblock/Makefile.inc | 1 + src/soc/intel/braswell/bootblock/bootblock.c | 79 +++ src/soc/intel/braswell/bootblock/timestamp.inc | 18 + src/soc/intel/braswell/chip.c | 93 +++ src/soc/intel/braswell/chip.h | 95 +++ src/soc/intel/braswell/cpu.c | 309 ++++++++++ src/soc/intel/braswell/dptf.c | 52 ++ src/soc/intel/braswell/ehci.c | 181 ++++++ src/soc/intel/braswell/elog.c | 122 ++++ src/soc/intel/braswell/emmc.c | 77 +++ src/soc/intel/braswell/gfx.c | 398 ++++++++++++ src/soc/intel/braswell/gpio.c | 245 ++++++++ src/soc/intel/braswell/hda.c | 118 ++++ src/soc/intel/braswell/include/soc/acpi.h | 31 + src/soc/intel/braswell/include/soc/device_nvs.h | 68 +++ src/soc/intel/braswell/include/soc/efi_wrapper.h | 52 ++ src/soc/intel/braswell/include/soc/ehci.h | 44 ++ src/soc/intel/braswell/include/soc/gfx.h | 64 ++ src/soc/intel/braswell/include/soc/gpio.h | 459 ++++++++++++++ src/soc/intel/braswell/include/soc/iomap.h | 90 +++ src/soc/intel/braswell/include/soc/iosf.h | 349 +++++++++++ src/soc/intel/braswell/include/soc/irq.h | 164 +++++ src/soc/intel/braswell/include/soc/lpc.h | 54 ++ src/soc/intel/braswell/include/soc/mrc_wrapper.h | 107 ++++ src/soc/intel/braswell/include/soc/msr.h | 51 ++ src/soc/intel/braswell/include/soc/nvs.h | 78 +++ src/soc/intel/braswell/include/soc/pattrs.h | 64 ++ src/soc/intel/braswell/include/soc/pci_devs.h | 155 +++++ src/soc/intel/braswell/include/soc/pcie.h | 102 ++++ src/soc/intel/braswell/include/soc/pmc.h | 303 +++++++++ src/soc/intel/braswell/include/soc/ramstage.h | 42 ++ src/soc/intel/braswell/include/soc/reset.h | 36 ++ src/soc/intel/braswell/include/soc/romstage.h | 54 ++ src/soc/intel/braswell/include/soc/sata.h | 26 + src/soc/intel/braswell/include/soc/smm.h | 49 ++ src/soc/intel/braswell/include/soc/spi.h | 74 +++ src/soc/intel/braswell/include/soc/xhci.h | 56 ++ src/soc/intel/braswell/iosf.c | 287 +++++++++ src/soc/intel/braswell/lpe.c | 189 ++++++ src/soc/intel/braswell/lpss.c | 206 +++++++ src/soc/intel/braswell/memmap.c | 33 + src/soc/intel/braswell/microcode/Makefile.inc | 1 + src/soc/intel/braswell/microcode/microcode_blob.c | 3 + src/soc/intel/braswell/northcluster.c | 148 +++++ src/soc/intel/braswell/pcie.c | 278 +++++++++ src/soc/intel/braswell/perf_power.c | 292 +++++++++ src/soc/intel/braswell/placeholders.c | 11 + src/soc/intel/braswell/pmutil.c | 364 +++++++++++ src/soc/intel/braswell/ramstage.c | 206 +++++++ src/soc/intel/braswell/refcode.c | 148 +++++ src/soc/intel/braswell/reset.c | 47 ++ src/soc/intel/braswell/romstage/Makefile.inc | 7 + src/soc/intel/braswell/romstage/cache_as_ram.inc | 285 +++++++++ src/soc/intel/braswell/romstage/early_spi.c | 65 ++ src/soc/intel/braswell/romstage/gfx.c | 50 ++ src/soc/intel/braswell/romstage/pmc.c | 81 +++ src/soc/intel/braswell/romstage/raminit.c | 191 ++++++ src/soc/intel/braswell/romstage/romstage.c | 377 ++++++++++++ src/soc/intel/braswell/romstage/uart.c | 38 ++ src/soc/intel/braswell/sata.c | 240 ++++++++ src/soc/intel/braswell/scc.c | 125 ++++ src/soc/intel/braswell/sd.c | 70 +++ src/soc/intel/braswell/smihandler.c | 483 +++++++++++++++ src/soc/intel/braswell/smm.c | 133 ++++ src/soc/intel/braswell/southcluster.c | 572 +++++++++++++++++ src/soc/intel/braswell/spi.c | 647 ++++++++++++++++++++ src/soc/intel/braswell/stage_cache.c | 35 ++ src/soc/intel/braswell/tsc_freq.c | 84 +++ src/soc/intel/braswell/xhci.c | 259 ++++++++ 92 files changed, 14329 insertions(+) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig new file mode 100644 index 0000000..3f938c3 --- /dev/null +++ b/src/soc/intel/braswell/Kconfig @@ -0,0 +1,245 @@ +config SOC_INTEL_BRASWELL + bool + help + Bay Trail M/D part support. + +if SOC_INTEL_BRASWELL + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_RAMSTAGE_X86_32 + select BACKUP_DEFAULT_SMM_REGION + select CACHE_MRC_SETTINGS + select CAR_MIGRATION + select COLLECT_TIMESTAMPS + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + select SUPPORT_CPU_UCODE_IN_CBFS + select HAVE_SMI_HANDLER + select HAVE_HARD_RESET + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select RELOCATABLE_MODULES + select RELOCATABLE_RAMSTAGE + select PARALLEL_MP + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select REG_SCRIPT + select SMM_MODULES + select SMM_TSEG + select SMP + select SPI_FLASH + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select TSC_SYNC_MFENCE + select UDELAY_TSC + select SOC_INTEL_COMMON + +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/baytrail/bootblock/bootblock.c" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MAX_CPUS + int + default 4 + +config CPU_ADDR_BITS + int + default 36 + +config SMM_TSEG_SIZE + hex + default 0x800000 + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config HAVE_MRC + bool "Add a Memory Reference Code binary" + default y + help + Select this option to add a blob containing + memory reference code. + Note: Without this binary coreboot will not work + +if HAVE_MRC + +config MRC_FILE + string "Intel memory refeference code path and filename" + default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" + help + The path and filename of the file to use as System Agent + binary. Note that this points to the sandybridge binary file + which is will not work, but it serves its purpose to do builds. + +config MRC_BIN_ADDRESS + hex + default 0xfffa0000 + +config MRC_RMT + bool "Enable MRC RMT training + debug prints" + default n + +endif # HAVE_MRC + +# Cache As RAM region layout: +# +# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE +# | MRC usage | +# | | +# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE +# | Stack |\ +# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE +# | v |/ +# +-------------+ +# | ^ | +# | | | +# | CAR Globals | +# +-------------+ DCACHE_RAM_BASE +# +# Note that the MRC binary is linked to assume the region marked as "MRC usage" +# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then +# a new MRC binary needs to be produced with the updated start and size +# information. + +config DCACHE_RAM_BASE + hex + default 0xfe000000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE + must add up to a power of 2. + +config DCACHE_RAM_MRC_VAR_SIZE + hex + default 0x8000 + help + The amount of cache-as-ram region required by the reference code. + +config DCACHE_RAM_ROMSTAGE_STACK_SIZE + hex + default 0x800 + help + The amount of anticipated stack usage from the data cache + during pre-RAM ROM stage execution. + +config RESET_ON_INVALID_RAMSTAGE_CACHE + bool "Reset the system on S3 wake when ramstage cache invalid." + default n + depends on RELOCATABLE_RAMSTAGE + help + The baytrail romstage code caches the loaded ramstage program + in SMM space. On S3 wake the romstage will copy over a fresh + ramstage that was cached in the SMM space. This option determines + the action to take when the ramstage cache is invalid. If selected + the system will reset otherwise the ramstage will be reloaded from + cbfs. + +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + help + On Bay Trail systems the firmware image has to store a lot more + than just coreboot, including: + - a firmware descriptor + - Intel Management Engine firmware + - MRC cache information + This option allows to limit the size of the CBFS portion in the + firmware image. + +config ENABLE_BUILTIN_COM1 + bool "Enable builtin COM1 Serial Port" + default n + help + The PMC has a legacy COM1 serial port. Choose this option to + configure the pads and enable it. This serial port can be used for + the debug console. + +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + default y + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" + +config HAVE_IFD_BIN + bool + default y + +config BUILD_WITH_FAKE_IFD + bool "Build with a fake IFD" + default y if !HAVE_IFD_BIN + help + If you don't have an Intel Firmware Descriptor (ifd.bin) for your + board, you can select this option and coreboot will build without it. + Though, the resulting coreboot.rom will not contain all parts required + to get coreboot running on your board. You can however write only the + BIOS section to your board's flash ROM and keep the other sections + untouched. Unfortunately the current version of flashrom doesn't + support this yet. But there is a patch pending [1]. + + WARNING: Never write a complete coreboot.rom to your flash ROM if it + was built with a fake IFD. It just won't work. + + [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html + +config IFD_BIOS_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_ME_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_PLATFORM_SECTION + depends on BUILD_WITH_FAKE_IFD + string + default "" + +config IFD_BIN_PATH + string "Path to intel firmware descriptor" + depends on !BUILD_WITH_FAKE_IFD + default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" + +config HAVE_REFCODE_BLOB + depends on ARCH_X86 + bool "An external reference code blob should be put into cbfs." + default n + help + The reference code blob will be placed into cbfs. + +if HAVE_REFCODE_BLOB + +config REFCODE_BLOB_FILE + string "Path and filename to reference code blob." + default "refcode.elf" + help + The path and filename to the file to be added to cbfs. + +endif # HAVE_REFCODE_BLOB + +endif diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc new file mode 100644 index 0000000..0806bbb --- /dev/null +++ b/src/soc/intel/braswell/Makefile.inc @@ -0,0 +1,107 @@ +ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) + +subdirs-y += bootblock +subdirs-y += microcode +subdirs-y += romstage +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo + +ramstage-y += memmap.c +romstage-y += memmap.c +ramstage-y += tsc_freq.c +romstage-y += tsc_freq.c +smm-y += tsc_freq.c +ramstage-y += spi.c +smm-y += spi.c +ramstage-y += chip.c +ramstage-y += gfx.c +ramstage-y += iosf.c +romstage-y += iosf.c +smm-y += iosf.c +ramstage-y += northcluster.c +ramstage-y += ramstage.c +ramstage-y += gpio.c +romstage-y += reset.c +ramstage-y += reset.c +ramstage-y += cpu.c +ramstage-y += pmutil.c +smm-y += pmutil.c +smm-y += smihandler.c +ramstage-y += smm.c +ramstage-y += ehci.c +ramstage-y += xhci.c +ramstage-y += southcluster.c +ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c +ramstage-y += sata.c +ramstage-y += acpi.c +ramstage-y += lpe.c +ramstage-y += scc.c +ramstage-y += emmc.c +ramstage-y += lpss.c +ramstage-y += pcie.c +ramstage-y += sd.c +ramstage-y += dptf.c +ramstage-y += perf_power.c +ramstage-y += stage_cache.c +romstage-y += stage_cache.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += hda.c + +# Remove as ramstage gets fleshed out +ramstage-y += placeholders.c + +CPPFLAGS_common += -Isrc/soc/intel/baytrail/include + +# Run an intermediate step when producing coreboot.rom +# that adds additional components to the final firmware +# image outside of CBFS +INTERMEDIATE:=baytrail_add_me + +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) +IFD_BIN_PATH := $(objgenerated)/ifdfake.bin +IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \ + $(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \ + $(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%)) +else +IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH) +endif + +baytrail_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE) +ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y) + printf "\n** WARNING **\n" + printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n" + printf "Never write a complete coreboot.rom with a fake IFD to your board's\n" + printf "flash ROM! Make sure that you only write valid flash regions.\n\n" + printf " IFDFAKE Building a fake Intel Firmware Descriptor\n" + $(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH) +endif + printf " DD Adding Intel Firmware Descriptor\n" + dd if=$(IFD_BIN_PATH) \ + of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_HAVE_ME_BIN),y) + printf " IFDTOOL me.bin -> coreboot.pre\n" + $(objutil)/ifdtool/ifdtool \ + -i ME:$(CONFIG_ME_BIN_PATH) \ + $(obj)/coreboot.pre + mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre +endif + +# If an MRC file is an ELF file determine the entry address and first loadable +# section offset in the file. Subtract the offset from the entry address to +# determine the final location. +mrcelfoffset = $(shell $(READELF_x86_32) -S -W $(CONFIG_MRC_FILE) | sed -e 's/\[ /[0/' | awk '$$3 ~ /PROGBITS/ { print "0x"$$5; exit }' ) +mrcelfentry = $(shell $(READELF_x86_32) -h -W $(CONFIG_MRC_FILE) | grep 'Entry point address' | awk '{print $$NF }') + +# Add memory reference code blob. +cbfs-files-$(CONFIG_HAVE_MRC) += mrc.bin +mrc.bin-file := $(call strip_quotes,$(CONFIG_MRC_FILE)) +mrc.bin-position := $(if $(findstring elf,$(CONFIG_MRC_FILE)),$(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) )) ),$(CONFIG_MRC_BIN_ADDRESS)) +mrc.bin-type := mrc + +PHONY += baytrail_add_me + +endif diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c new file mode 100644 index 0000000..74e7336 --- /dev/null +++ b/src/soc/intel/braswell/acpi.c @@ -0,0 +1,511 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cpu/intel/turbo.h> + +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/msr.h> +#include <soc/pattrs.h> +#include <soc/pmc.h> + +#include <ec/google/chromeec/ec.h> +#include <vendorcode/google/chromeos/gnvs.h> + +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +/* C-state map without S0ix */ +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + /* C6NS with no L2 shrink */ + /* NOTE: this substate is above CPUID limit */ + .ctype = 2, /* ACPI C2 */ + .latency = 500, + .power = 10, + .resource = MWAIT_RES(5, 1), + }, + { + /* C6FS with full L2 shrink */ + .ctype = 3, /* ACPI C3 */ + .latency = 1500, /* 1.5ms worst case */ + .power = 1, + .resource = MWAIT_RES(5, 2), + } +}; + +void acpi_init_gnvs(global_nvs_t *gnvs) +{ + /* Set unknown wake source */ + gnvs->pm1i = -1; + + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + + /* Top of Low Memory (start of resource allocation) */ + gnvs->tolm = nc_read_top_of_low_memory(); + +#if CONFIG_CONSOLE_CBMEM + /* Update the mem console pointer. */ + gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); +#endif + +#if CONFIG_CHROMEOS + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); +#if CONFIG_EC_GOOGLE_CHROMEEC + gnvs->chromeos.vbt2 = google_ec_running_ro() ? + ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; +#endif +#endif +} + +static int acpi_sci_irq(void) +{ + u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int scis; + static int sci_irq; + + if (sci_irq) + return sci_irq; + + /* Determine how SCI is routed. */ + scis = read32(actl) & SCIS_MASK; + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + +void acpi_create_intel_hpet(acpi_hpet_t * hpet) +{ + acpi_header_t *header = &(hpet->header); + acpi_addr_t *addr = &(hpet->addr); + + memset((void *) hpet, 0, sizeof(acpi_hpet_t)); + + /* fill out header fields */ + memcpy(header->signature, "HPET", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_hpet_t); + header->revision = 1; + + /* fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = (unsigned long long)HPET_BASE_ADDRESS & 0xffffffff; + addr->addrh = (unsigned long long)HPET_BASE_ADDRESS >> 32; + + hpet->id = 0x8086a201; /* Intel */ + hpet->number = 0x00; + hpet->min_tick = 0x0080; + + header->checksum = + acpi_checksum((void *) hpet, sizeof(acpi_hpet_t)); +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + MCFG_BASE_ADDRESS, 0, 0, 255); + return current; +} + +void acpi_fill_in_fadt(acpi_fadt_t *fadt) +{ + const uint16_t pmbase = ACPI_BASE_ADDRESS; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2A_CNT_BLK; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS); + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2A_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + +static acpi_tstate_t baytrail_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +static int generate_T_state_entries(int core, int cores_per_package) +{ + int len; + + /* Indicate SW_ALL coordination for T-states */ + len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + len += acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + len += acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + len += acpigen_write_TSS_package( + ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); + + return len; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static int generate_P_state_entries(int core, int cores_per_package) +{ + int len, len_pss; + int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + int vid, vid_turbo, vid_min, vid_max, vid_range_2; + u32 control_status; + const struct pattrs *pattrs = pattrs_get(); + msr_t msr; + + /* Inputs from CPU attributes */ + ratio_max = pattrs->iacore_ratios[IACORE_MAX]; + ratio_min = pattrs->iacore_ratios[IACORE_LFM]; + vid_max = pattrs->iacore_vids[IACORE_MAX]; + vid_min = pattrs->iacore_vids[IACORE_LFM]; + + /* Set P-states coordination type based on MSR disable bit */ + coord_type = (pattrs->num_cpus > 2) ? SW_ALL : HW_ALL; + + /* Max Non-Turbo Frequency */ + clock_max = (ratio_max * pattrs->bclk_khz) / 1000; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + msr = rdmsr(MSR_PKG_POWER_LIMIT); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + len = acpigen_write_empty_PCT(); + + /* Write _PPC with NVS specified limit on supported P-state */ + len += acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + len += acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + len += acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = 1; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > 15) { /* ACPI max is 15 ratios */ + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + len_pss = acpigen_write_package(num_entries + 2); + + ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; + vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; + control_status = (ratio_turbo << 8) | vid_turbo; + + /* Add entry for Turbo ratio */ + len_pss += acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control*/ + control_status); /*status*/ + } else { + /* _PSS package count without Turbo */ + len_pss = acpigen_write_package(num_entries + 1); + ratio_turbo = ratio_max; + vid_turbo = vid_max; + } + + /* First regular entry is max non-turbo ratio */ + control_status = (ratio_max << 8) | vid_max; + len_pss += acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control */ + control_status); /*status*/ + + /* Set up ratio and vid ranges for VID calculation */ + ratio_range_2 = (ratio_turbo - ratio_min) * 2; + vid_range_2 = (vid_turbo - vid_min) * 2; + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate VID for this ratio */ + vid = ((ratio - ratio_min) * vid_range_2) / + ratio_range_2 + vid_min; + /* Round up if remainder */ + if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) + vid++; + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = (ratio * pattrs->bclk_khz) / 1000; + control_status = (ratio << 8) | (vid & 0xff); + + len_pss += acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control*/ + control_status); /*status*/ + } + + /* Fix package length */ + len_pss--; + acpigen_patch_len(len_pss); + + return len + len_pss; +} + +void generate_cpu_entries(void) +{ + int len_pr, core; + int pcontrol_blk = get_pmbase(), plen = 6; + const struct pattrs *pattrs = pattrs_get(); + + for (core=0; core<pattrs->num_cpus; core++) { + if (core > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + len_pr = acpigen_write_processor( + core, pcontrol_blk, plen); + + /* Generate P-state tables */ + len_pr += generate_P_state_entries( + core, pattrs->num_cpus); + + /* Generate C-state tables */ + len_pr += acpigen_write_CST_package( + cstate_map, ARRAY_SIZE(cstate_map)); + + /* Generate T-state tables */ + len_pr += generate_T_state_entries( + core, pattrs->num_cpus); + + len_pr--; + acpigen_patch_len(len_pr); + } +} + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci_irq = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci_irq >= 20) + sci_flags |= MP_IRQ_POLARITY_LOW; + else + sci_flags |= MP_IRQ_POLARITY_HIGH; + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, + sci_flags); + + return current; +} diff --git a/src/soc/intel/braswell/acpi/cpu.asl b/src/soc/intel/braswell/acpi/cpu.asl new file mode 100644 index 0000000..f7e404d --- /dev/null +++ b/src/soc/intel/braswell/acpi/cpu.asl @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These devices are created at runtime */ +External (\_PR.CP00, DeviceObj) +External (\_PR.CP01, DeviceObj) +External (\_PR.CP02, DeviceObj) +External (\_PR.CP03, DeviceObj) + +/* Notify OS to re-read CPU tables, assuming ^2 CPU count */ +Method (PNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x81) // _CST + Notify (\_PR.CP01, 0x81) // _CST + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x81) // _CST + Notify (\_PR.CP03, 0x81) // _CST + } +} + +/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */ +Method (PPCN) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x80) // _PPC + Notify (\_PR.CP01, 0x80) // _PPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x80) // _PPC + Notify (\_PR.CP03, 0x80) // _PPC + } +} + +/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */ +Method (TNOT) +{ + If (LGreaterEqual (\PCNT, 2)) { + Notify (\_PR.CP00, 0x82) // _TPC + Notify (\_PR.CP01, 0x82) // _TPC + } + If (LGreaterEqual (\PCNT, 4)) { + Notify (\_PR.CP02, 0x82) // _TPC + Notify (\_PR.CP03, 0x82) // _TPC + } +} + +/* Return a package containing enabled processor entries */ +Method (PPKG) +{ + If (LGreaterEqual (\PCNT, 4)) { + Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03}) + } ElseIf (LGreaterEqual (\PCNT, 2)) { + Return (Package() {\_PR.CP00, \_PR.CP01}) + } Else { + Return (Package() {\_PR.CP00}) + } +} diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl new file mode 100644 index 0000000..fce7b53 --- /dev/null +++ b/src/soc/intel/braswell/acpi/device_nvs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Device Enabled in ACPI Mode */ + +S0EN, 8, // SDMA Enable +S1EN, 8, // I2C1 Enable +S2EN, 8, // I2C2 Enable +S3EN, 8, // I2C3 Enable +S4EN, 8, // I2C4 Enable +S5EN, 8, // I2C5 Enable +S6EN, 8, // I2C6 Enable +S7EN, 8, // I2C7 Enable +S8EN, 8, // SDMA2 Enable +S9EN, 8, // SPI Enable +SAEN, 8, // PWM1 Enable +SBEN, 8, // PWM2 Enable +SCEN, 8, // UART2 Enable +SDEN, 8, // UART2 Enable +C0EN, 8, // MMC Enable +C1EN, 8, // SDIO Enable +C2EN, 8, // SD Card Enable +LPEN, 8, // LPE Enable + +/* BAR 0 */ + +S0B0, 32, // SDMA BAR0 +S1B0, 32, // I2C1 BAR0 +S2B0, 32, // I2C2 BAR0 +S3B0, 32, // I2C3 BAR0 +S4B0, 32, // I2C4 BAR0 +S5B0, 32, // I2C5 BAR0 +S6B0, 32, // I2C6 BAR0 +S7B0, 32, // I2C7 BAR0 +S8B0, 32, // SDMA2 BAR0 +S9B0, 32, // SPI BAR0 +SAB0, 32, // PWM1 BAR0 +SBB0, 32, // PWM2 BAR0 +SCB0, 32, // UART1 BAR0 +SDB0, 32, // UART2 BAR0 +C0B0, 32, // MMC BAR0 +C1B0, 32, // SDIO BAR0 +C2B0, 32, // SD Card BAR0 +LPB0, 32, // LPE BAR0 + +/* BAR 1 */ + +S0B1, 32, // SDMA BAR1 +S1B1, 32, // I2C1 BAR1 +S2B1, 32, // I2C2 BAR1 +S3B1, 32, // I2C3 BAR1 +S4B1, 32, // I2C4 BAR1 +S5B1, 32, // I2C5 BAR1 +S6B1, 32, // I2C6 BAR1 +S7B1, 32, // I2C7 BAR1 +S8B1, 32, // SDMA2 BAR1 +S9B1, 32, // SPI BAR1 +SAB1, 32, // PWM1 BAR1 +SBB1, 32, // PWM2 BAR1 +SCB1, 32, // UART1 BAR1 +SDB1, 32, // UART2 BAR1 +C0B1, 32, // MMC BAR1 +C1B1, 32, // SDIO BAR1 +C2B1, 32, // SD Card BAR1 +LPB1, 32, // LPE BAR1 + +/* Extra */ + +LPFW, 32, // LPE BAR2 Firmware diff --git a/src/soc/intel/braswell/acpi/dptf/charger.asl b/src/soc/intel/braswell/acpi/dptf/charger.asl new file mode 100644 index 0000000..7c7f62f --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/charger.asl @@ -0,0 +1,59 @@ +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Return charger performance states defined by mainboard */ + Method (PPSS) + { + Return (\_SB.CHPS) + } + + /* Return maximum charger current limit */ + Method (PPPC) + { + /* Convert size of PPSS table to index */ + Store (SizeOf (\_SB.CHPS), Local0) + Decrement (Local0) + + /* Check if charging is disabled (AC removed) */ + If (LEqual (\PWRS, Zero)) { + /* Return last power state */ + Return (Local0) + } Else { + /* Return highest power state */ + Return (0) + } + + Return (0) + } + + /* Set charger current limit */ + Method (SPPC, 1) + { + /* Retrieve Control (index 4) for specified PPSS level */ + Store (DeRefOf (Index (DeRefOf (Index + (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + + /* Pass Control value to EC to limit charging */ + \_SB.PCI0.LPCB.EC0.CHGS (Local0) + } + + /* Initialize charger participant */ + Method (INIT) + { + /* Disable charge limit */ + \_SB.PCI0.LPCB.EC0.CHGD () + } +} diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl new file mode 100644 index 0000000..58c1c7b --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl @@ -0,0 +1,144 @@ +External (\_PR.CP00._TSS, MethodObj) +External (\_PR.CP00._TPC, MethodObj) +External (\_PR.CP00._PTC, PkgObj) +External (\_PR.CP00._TSD, PkgObj) +External (\_PR.CP00._PSS, MethodObj) + +Device (TCPU) +{ + Name (_HID, EISAID ("INT3401")) + Name (_UID, 0) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Return (\_PR.CP00._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CP00._TPC)) { + Return (\_PR.CP00._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CP00._PTC)) { + Return (\_PR.CP00._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CP00._TSD)) { + Return (\_PR.CP00._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CP00._TSS)) { + Store (SizeOf (\_PR.CP00._TSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + Return (0) + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + Method (_PDL) + { + /* Check for mainboard specific _PDL override */ + If (CondRefOf (\_SB.MPDL)) { + Return (\_SB.MPDL) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* Return PPCC table defined by mainboard */ + Method (PPCC) + { + Return (\_SB.MPPC) + } + +#ifdef DPTF_CPU_CRITICAL + Method (_CRT) + { + Return (^^CTOK (DPTF_CPU_CRITICAL)) + } +#endif + +#ifdef DPTF_CPU_PASSIVE + Method (_PSV) + { + Return (^^CTOK (DPTF_CPU_PASSIVE)) + } +#endif +} diff --git a/src/soc/intel/braswell/acpi/dptf/dptf.asl b/src/soc/intel/braswell/acpi/dptf/dptf.asl new file mode 100644 index 0000000..9ebfb8c --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/dptf.asl @@ -0,0 +1,78 @@ +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Arg0: Buffer containing UUID + * Arg1: Integer containing Revision ID of buffer format + * Arg2: Integer containing count of entries in Arg3 + * Arg3: Buffer containing list of DWORD capabilities + * Return: Buffer containing list of DWORD capabilities + */ + Method (_OSC, 4, Serialized) + { + /* Check for Passive Policy UUID */ + If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + /* Initialize Thermal Devices */ + ^TINI () + +#ifdef DPTF_ENABLE_CHARGER + /* Initialize Charger Device */ + ^TCHG.INIT () +#endif + } + + Return (Arg3) + } + + /* Priority based _TRT */ + Name (TRTR, 1) + + Method (_TRT) + { + Return (\_SB.DTRT) + } + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Include CPU Participant */ + #include "cpu.asl" + + /* Include Thermal Participants */ + #include "thermal.asl" + +#ifdef DPTF_ENABLE_CHARGER + /* Include Charger Participant */ + #include "charger.asl" +#endif +} diff --git a/src/soc/intel/braswell/acpi/dptf/thermal.asl b/src/soc/intel/braswell/acpi/dptf/thermal.asl new file mode 100644 index 0000000..7113215 --- /dev/null +++ b/src/soc/intel/braswell/acpi/dptf/thermal.asl @@ -0,0 +1,203 @@ +/* Thermal Threshold Event Handler */ +Method (TEVT, 1, NotSerialized) +{ + Store (ToInteger (Arg0), Local0) + +#ifdef DPTF_TSR0_SENSOR_ID + If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + Notify (^TSR0, 0x90) + } +#endif +#ifdef DPTF_TSR1_SENSOR_ID + If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + Notify (^TSR1, 0x90) + } +#endif +#ifdef DPTF_TSR2_SENSOR_ID + If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + Notify (^TSR2, 0x90) + } +#endif +} + +/* Thermal device initialization - Disable Aux Trip Points */ +Method (TINI) +{ +#ifdef DPTF_TSR0_SENSOR_ID + ^TSR0.PATD () +#endif +#ifdef DPTF_TSR1_SENSOR_ID + ^TSR1.PATD () +#endif +#ifdef DPTF_TSR2_SENSOR_ID + ^TSR2.PATD () +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (^^CTOK (DPTF_TSR0_PASSIVE)) + } + + Method (_CRT) + { + Return (^^CTOK (DPTF_TSR0_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (^^CTOK (DPTF_TSR1_PASSIVE)) + } + + Method (_CRT) + { + Return (^^CTOK (DPTF_TSR1_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (^^CTOK (DPTF_TSR2_PASSIVE)) + } + + Method (_CRT) + { + Return (^^CTOK (DPTF_TSR2_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl new file mode 100644 index 0000000..a201c03 --- /dev/null +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Global Variables */ + +Name(\PICM, 0) // IOAPIC/8259 + +/* Global ACPI memory region. This region is used for passing information + * between coreboot (aka "the system bios"), ACPI, and the SMI handler. + * Since we don't know where this will end up in memory at ACPI compile time, + * we have to fix it up in coreboot's ACPI creation phase. + */ + + +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Miscellaneous */ + Offset (0x00), + OSYS, 16, // 0x00 - Operating System + SMIF, 8, // 0x02 - SMI function + PRM0, 8, // 0x03 - SMI function parameter + PRM1, 8, // 0x04 - SMI function parameter + SCIF, 8, // 0x05 - SCI function + PRM2, 8, // 0x06 - SCI function parameter + PRM3, 8, // 0x07 - SCI function parameter + LCKF, 8, // 0x08 - Global Lock function for EC + PRM4, 8, // 0x09 - Lock function parameter + PRM5, 8, // 0x0a - Lock function parameter + P80D, 32, // 0x0b - Debug port (IO 0x80) value + LIDS, 8, // 0x0f - LID state (open = 1) + PWRS, 8, // 0x10 - Power State (AC = 1) + PCNT, 8, // 0x11 - Processor count + TPMP, 8, // 0x12 - TPM Present and Enabled + TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS + PM1I, 32, // 0x15 - System Wake Source - PM1 Index + + /* Device Config */ + Offset (0x20), + S5U0, 8, // 0x20 - Enable USB0 in S5 + S5U1, 8, // 0x21 - Enable USB1 in S5 + S3U0, 8, // 0x22 - Enable USB0 in S3 + S3U1, 8, // 0x23 - Enable USB1 in S3 + TACT, 8, // 0x24 - Thermal Active trip point + TPSV, 8, // 0x25 - Thermal Passive trip point + TCRT, 8, // 0x26 - Thermal Critical trip point + DPTE, 8, // 0x27 - Enable DPTF + + /* Base addresses */ + Offset (0x30), + CMEM, 32, // 0x30 - CBMEM TOC + TOLM, 32, // 0x34 - Top of Low Memory + CBMC, 32, // 0x38 - coreboot mem console pointer + + /* ChromeOS specific */ + Offset (0x100), + #include <vendorcode/google/chromeos/acpi/gnvs.asl> + + Offset (0x1000), + #include <soc/intel/baytrail/acpi/device_nvs.asl> +} + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) + Store (One, \S3U1) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) + Store (Zero, \S3U1) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) + Store (One, \S5U1) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) + Store (Zero, \S5U1) +} diff --git a/src/soc/intel/braswell/acpi/gpio.asl b/src/soc/intel/braswell/acpi/gpio.asl new file mode 100644 index 0000000..aa6af71 --- /dev/null +++ b/src/soc/intel/braswell/acpi/gpio.asl @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <soc/iomap.h> +#include <soc/irq.h> + +/* SouthCluster GPIO */ +Device (GPSC) +{ + Name (_HID, "INT33FC") + Name (_CID, "INT33FC") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSCORE, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* NorthCluster GPIO */ +Device (GPNC) +{ + Name (_HID, "INT33FC") + Name (_CID, "INT33FC") + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_NC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPNCORE, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} + +/* SUS GPIO */ +Device (GPSS) +{ + Name (_HID, "INT33FC") + Name (_CID, "INT33FC") + Name (_UID, 3) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,,) + { + GPIO_SUS_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + Add (IO_BASE_ADDRESS, IO_BASE_OFFSET_GPSSUS, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + Return (0xF) + } +} diff --git a/src/soc/intel/braswell/acpi/irq_helper.h b/src/soc/intel/braswell/acpi/irq_helper.h new file mode 100644 index 0000000..b19895b --- /dev/null +++ b/src/soc/intel/braswell/acpi/irq_helper.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef ACPI_DEV_APIC_IRQ +#undef PCI_DEV_PIRQ_ROUTE +#undef PIRQ_PIC_ROUTES +#undef PIRQ_PIC + +#if defined(PIC_MODE) + +#define ACPI_DEV_APIC_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, \_SB.PCI0.LPCB.LNK ## pin_name_, 0 } + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_APIC_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } + +#endif + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + ACPI_DEV_APIC_IRQ(dev_, 0, a_), \ + ACPI_DEV_APIC_IRQ(dev_, 1, b_), \ + ACPI_DEV_APIC_IRQ(dev_, 2, c_), \ + ACPI_DEV_APIC_IRQ(dev_, 3, d_) + +/* Empty PIRQ_PIC definition. */ +#define PIRQ_PIC(pirq_, pic_irq_) + +/* Include the mainboard irq route definition. */ +#include "irqroute.h" diff --git a/src/soc/intel/braswell/acpi/irqlinks.asl b/src/soc/intel/braswell/acpi/irqlinks.asl new file mode 100644 index 0000000..21f1ada --- /dev/null +++ b/src/soc/intel/braswell/acpi/irqlinks.asl @@ -0,0 +1,492 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LNKA) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 1) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTA) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTA + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTA, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKB) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 2) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTB) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTB + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTB, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKC) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 3) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTC) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTC + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTC, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKD) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 4) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTD) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTD + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTD, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKE) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 5) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTE) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTE + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTE, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKF) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 6) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTF) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTF + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTF, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKG) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 7) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTG) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTG + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTG, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} + +Device (LNKH) +{ + Name (_HID, EISAID("PNP0C0F")) + Name (_UID, 8) + + // Disable method + Method (_DIS, 0, Serialized) + { + Store (0x80, PRTH) + } + + // Possible Resource Settings for this Link + Name (_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) + { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + // Current Resource Settings for this link + Method (_CRS, 0, Serialized) + { + Name (RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + // Clear the WordField + Store (Zero, IRQ0) + + // Set the bit from PRTH + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + // Set Resource Setting for this IRQ link + Method (_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + // Which bit is set? + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + // Status + Method (_STA, 0, Serialized) + { + If(And(PRTH, 0x80)) { + Return (0x9) + } Else { + Return (0xb) + } + } +} diff --git a/src/soc/intel/braswell/acpi/irqroute.asl b/src/soc/intel/braswell/acpi/irqroute.asl new file mode 100644 index 0000000..23987d7 --- /dev/null +++ b/src/soc/intel/braswell/acpi/irqroute.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTES + }) + } +} diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl new file mode 100644 index 0000000..408d2b4 --- /dev/null +++ b/src/soc/intel/braswell/acpi/lpc.asl @@ -0,0 +1,167 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +// Intel LPC Bus Device - 0:1f.0 + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + #include "acpi/ec.asl" + + Device (DMAC) // DMA Controller + { + Name(_HID, EISAID("PNP0200")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + Device (FWH) // Firmware Hub + { + Name (_HID, EISAID("INT0800")) + Name (_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + Device (HPET) + { + Name (_HID, EISAID("PNP0103")) + Name (_CID, 0x010CD041) + + Method (_STA, 0) // Device Status + { + Return (0xf) // Enable and show device + } + + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xfed00000, 0x400) + }) + } + + Device(PIC) // 8259 Interrupt Controller + { + Name(_HID,EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate() + { + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + }) + + Method (_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } + + Device (RTC) // Real Time Clock + { + Name (_HID, EISAID("PNP0B00")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x70, 0x70, 1, 8) +// Disable as Windows doesn't like it, and systems don't seem to use it. +// IRQNoFlags() { 8 } + }) + } + + Device (TIMR) // Intel 8254 timer + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() {0} + }) + } + + // Include mainboard's superio.asl file. + #include "acpi/superio.asl" + +#ifdef ENABLE_TPM + Device (TPM) // Trusted Platform Module + { + Name(_HID, EISAID("IFX0102")) + Name(_CID, 0x310cd041) + Name(_UID, 1) + + Method(_STA, 0) + { + If (TPMP) { + Return (0xf) + } + Return (0x0) + } + + Name(_CRS, ResourceTemplate() { + IO (Decode16, 0x2e, 0x2e, 0x01, 0x02) + IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10) + Memory32Fixed (ReadWrite, 0xfed40000, 0x5000) + IRQ (Edge, Activehigh, Exclusive) { 6 } + }) + } +#endif +} diff --git a/src/soc/intel/braswell/acpi/lpe.asl b/src/soc/intel/braswell/acpi/lpe.asl new file mode 100644 index 0000000..dfa555c --- /dev/null +++ b/src/soc/intel/braswell/acpi/lpe.asl @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (LPEA) +{ + Name (_HID, "80860F28") + Name (_CID, "80860F28") + Name (_UID, 1) + Name (_DDN, "Low Power Audio Controller") + Name (_PR0, Package () { PLPE }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x00200000, BAR0) + Memory32Fixed (ReadWrite, 0, 0x00001000, BAR1) + Memory32Fixed (ReadWrite, 0, 0x00100000, BAR2) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_DMA0_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_DMA1_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP0_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP1_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_SSP2_IRQ + } + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPE_IPC2HOST_IRQ + } + }) + + Method (_CRS) + { + /* Update BAR0 from NVS */ + CreateDwordField (^RBUF, ^BAR0._BAS, BAS0) + Store (\LPB0, BAS0) + + /* Update BAR1 from NVS */ + CreateDwordField (^RBUF, ^BAR1._BAS, BAS1) + Store (\LPB1, BAS1) + + /* Update LPE FW from NVS */ + CreateDwordField (^RBUF, ^BAR2._BAS, BAS2) + Store (\LPFW, BAS2) + + /* Append any Mainboard defined GPIOs */ + If (CondRefOf (^GBUF, Local0)) { + ConcatenateResTemplate (^RBUF, ^GBUF, Local1) + Return (Local1) + } + + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\LPEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, LPB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + PowerResource (PLPE, 0, 0) + { + Method (_STA) + { + Return (1) + } + + Method (_OFF) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_ON) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + } +} diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl new file mode 100644 index 0000000..0f8f746 --- /dev/null +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -0,0 +1,712 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (SDM1) +{ + Name (_HID, "INTL9C60") + Name (_UID, 1) + Name (_DDN, "DMA Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA1_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (SDM2) +{ + Name (_HID, "INTL9C60") + Name (_UID, 2) + Name (_DDN, "DMA Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA2_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S8B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S8EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (I2C1) +{ + Name (_HID, "80860F41") + Name (_UID, 1) + Name (_DDN, "I2C Controller #1") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C1_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C2) +{ + Name (_HID, "80860F41") + Name (_UID, 2) + Name (_DDN, "I2C Controller #2") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C2_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C3) +{ + Name (_HID, "80860F41") + Name (_UID, 3) + Name (_DDN, "I2C Controller #3") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C3_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S3B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S3EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S3B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C4) +{ + Name (_HID, "80860F41") + Name (_UID, 4) + Name (_DDN, "I2C Controller #4") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C4_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S4B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S4EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S4B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C5) +{ + Name (_HID, "80860F41") + Name (_UID, 5) + Name (_DDN, "I2C Controller #5") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C5_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S5B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S5B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C6) +{ + Name (_HID, "80860F41") + Name (_UID, 6) + Name (_DDN, "I2C Controller #6") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C6_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S6B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S6B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C7) +{ + Name (_HID, "80860F41") + Name (_UID, 7) + Name (_DDN, "I2C Controller #7") + + /* Standard Mode: HCNT, LCNT, SDA Hold Time */ + Name (SSCN, Package () { 0x200, 0x200, 0x6 }) + + /* Fast Mode: HCNT, LCNT, SDA Hold Time */ + Name (FMCN, Package () { 0x55, 0x99, 0x6 }) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C7_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S7B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S7EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S7B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SPI1) +{ + Name (_HID, "80860F0E") + Name (_UID, 1) + Name (_DDN, "SPI Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_SPI_IRQ + } + FixedDMA (0x0, 0x0, Width32Bit, ) + FixedDMA (0x1, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S9B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S9EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S9B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (PWM1) +{ + Name (_HID, "80860F09") + Name (_UID, 1) + Name (_DDN, "PWM Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SAB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SAEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (PWM2) +{ + Name (_HID, "80860F09") + Name (_UID, 2) + Name (_DDN, "PWM Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SBB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SBEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (UAR1) +{ + Name (_HID, "80860F0A") + Name (_UID, 1) + Name (_DDN, "HS-UART Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART1_IRQ + } + FixedDMA (0x2, 0x2, Width32Bit, ) + FixedDMA (0x3, 0x3, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SCB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SCEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SCB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (UAR2) +{ + Name (_HID, "80860F0A") + Name (_UID, 2) + Name (_DDN, "HS-UART Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART2_IRQ + } + FixedDMA (0x4, 0x4, Width32Bit, ) + FixedDMA (0x5, 0x5, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SDB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SDEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SDB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/braswell/acpi/pcie.asl b/src/soc/intel/braswell/acpi/pcie.asl new file mode 100644 index 0000000..5ad4e78 --- /dev/null +++ b/src/soc/intel/braswell/acpi/pcie.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Intel SOC PCIe support */ + +Device (RP01) +{ + Name (_ADR, 0x001c0000) + + Method (_PRT) + { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) + }) + } Else { + Return (Package() { + #define PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, A, B, C, D) + }) + } + } +} + +Device (RP02) +{ + Name (_ADR, 0x001c0001) + + Method (_PRT) + { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) + }) + } Else { + Return (Package() { + #define PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, B, C, D, A) + }) + } + } +} + +Device (RP03) +{ + Name (_ADR, 0x001c0002) + + Method (_PRT) + { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) + }) + } Else { + Return (Package() { + #define PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, C, D, A, B) + }) + } + } +} + +Device (RP04) +{ + Name (_ADR, 0x001c0003) + + Method (_PRT) + { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) + }) + } Else { + Return (Package() { + #define PIC_MODE + #include <soc/intel/baytrail/acpi/irq_helper.h> + PCI_DEV_PIRQ_ROUTE(0x0, D, A, B, C) + }) + } + } +} diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl new file mode 100644 index 0000000..e32880e --- /dev/null +++ b/src/soc/intel/braswell/acpi/platform.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method (_SWS) +{ + /* Index into PM1 for device that caused wake */ + Return (\PM1I) +} diff --git a/src/soc/intel/braswell/acpi/scc.asl b/src/soc/intel/braswell/acpi/scc.asl new file mode 100644 index 0000000..7181fb1 --- /dev/null +++ b/src/soc/intel/braswell/acpi/scc.asl @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (EMMC) +{ + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_UID, 1) + Name (_DDN, "eMMC Controller 4.5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_EMMC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C0B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Device (EM45) + { + /* Slot 0, Function 8 */ + Name (_ADR, 0x8) + + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device (SDIO) +{ + Name (_HID, "INT33BB") + Name (_CID, "PNP0D40") + Name (_UID, 2) + Name (_DDN, "SDIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SDIO_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SDCD) +{ + Name (_HID, "80860F16") + Name (_CID, "PNP0D40") + Name (_UID, 3) + Name (_DDN, "SD Card Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SD_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/braswell/acpi/sleepstates.asl b/src/soc/intel/braswell/acpi/sleepstates.asl new file mode 100644 index 0000000..8abeb2d --- /dev/null +++ b/src/soc/intel/braswell/acpi/sleepstates.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl new file mode 100644 index 0000000..9092562 --- /dev/null +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <soc/iomap.h> +#include <soc/irq.h> + +Scope(\) +{ + // IO-Trap at 0x800. This is the ACPI->SMI communication interface. + + OperationRegion(IO_T, SystemIO, 0x800, 0x10) + Field(IO_T, ByteAcc, NoLock, Preserve) + { + Offset(0x8), + TRP0, 8 // IO-Trap at 0x808 + } + + // Intel Legacy Block + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field (ILBS, AnyAcc, NoLock, Preserve) + { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) + }) + + // Update PCI resource area + CreateDwordField(MCRS, PMEM._MIN, PMIN) + CreateDwordField(MCRS, PMEM._MAX, PMAX) + CreateDwordField(MCRS, PMEM._LEN, PLEN) + + // TOLM is BMBOUND accessible from IOSF so is saved in NVS + Store (\TOLM, PMIN) + Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) + Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) + Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) + Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +Method (_OSC, 4) +{ + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } +} + +/* IOSF MBI Interface for kernel access */ +Device (IOSF) +{ + Name (_HID, "INT33BD") + Name (_CID, "INT33BD") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + /* MCR / MDR / MCRX */ + Memory32Fixed (ReadWrite, 0, 12, RBAR) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) + Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) + Return (^RBUF) + } +} + +// LPC Bridge 0:1f.0 +#include "lpc.asl" + +// USB XHCI 0:14.0 +#include "xhci.asl" + +// IRQ routing for each PCI device +#include "irqroute.asl" + +// PCI Express Ports 0:1c.x +#include "pcie.asl" + +Scope (\_SB) +{ + // GPIO Devices + #include "gpio.asl" + + // LPSS Devices + #include "lpss.asl" + + // SCC Devices + #include "scc.asl" + + // LPE Device + #include "lpe.asl" +} diff --git a/src/soc/intel/braswell/acpi/xhci.asl b/src/soc/intel/braswell/acpi/xhci.asl new file mode 100644 index 0000000..4d5367a --- /dev/null +++ b/src/soc/intel/braswell/acpi/xhci.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + Name (_PRW, Package () { 0x0d, 3 }) + Name (_S3D, 3) /* Highest D state in S3 state */ + + Device (RHUB) + { + Name (_ADR, 0x00000000) + Device (PRT1) { Name (_ADR, 1) } + Device (PRT2) { Name (_ADR, 2) } + Device (PRT3) { Name (_ADR, 3) } + Device (PRT4) { Name (_ADR, 4) } + } +} diff --git a/src/soc/intel/braswell/bootblock/Makefile.inc b/src/soc/intel/braswell/bootblock/Makefile.inc new file mode 100644 index 0000000..3a40251 --- /dev/null +++ b/src/soc/intel/braswell/bootblock/Makefile.inc @@ -0,0 +1 @@ +chipset_bootblock_inc += $(src)/soc/intel/baytrail/bootblock/timestamp.inc diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c new file mode 100644 index 0000000..9d7f19c --- /dev/null +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <soc/iosf.h> +#include <cpu/intel/microcode/microcode.c> + +static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +{ + msr_t basem, maskm; + basem.lo = base | type; + basem.hi = 0; + wrmsr(MTRRphysBase_MSR(reg), basem); + maskm.lo = ~(size - 1) | MTRRphysMaskValid; + maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; + wrmsr(MTRRphysMask_MSR(reg), maskm); +} + +static void enable_rom_caching(void) +{ + msr_t msr; + + disable_cache(); + /* Why only top 4MiB ? */ + set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + enable_cache(); + + /* Enable Variable MTRRs */ + msr.hi = 0x00000000; + msr.lo = 0x00000800; + wrmsr(MTRRdefType_MSR, msr); +} + +static void setup_mmconfig(void) +{ + uint32_t reg; + + /* Set up the MMCONF range. The register lives in the BUNIT. The + * IO variant of the config access needs to be used initially to + * properly configure as the IOSF access registers live in PCI + * config space. */ + reg = 0; + /* Clear the extended register. */ + pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg); + reg = CONFIG_MMCONF_BASE_ADDRESS | 1; + pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) | + IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN; + pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); +} + +static void bootblock_cpu_init(void) +{ + /* Allow memory-mapped PCI config access. */ + setup_mmconfig(); + + /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + enable_rom_caching(); +} diff --git a/src/soc/intel/braswell/bootblock/timestamp.inc b/src/soc/intel/braswell/bootblock/timestamp.inc new file mode 100644 index 0000000..3db5c35 --- /dev/null +++ b/src/soc/intel/braswell/bootblock/timestamp.inc @@ -0,0 +1,18 @@ +/* Store the initial timestamp for booting in mmx registers. This works + * because the bootblock isn't being compiled with MMX support so mm0 and + * mm1 will be preserved into romstage. */ + .code32 + +.global stash_timestamp +stash_timestamp: + + /* Save the BIST value */ + movl %eax, %ebp + + finit + rdtsc + movd %eax, %mm0 + movd %edx, %mm1 + + /* Restore the BIST value to %eax */ + movl %ebp, %eax diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c new file mode 100644 index 0000000..281019a --- /dev/null +++ b/src/soc/intel/braswell/chip.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/pci_ops.h> + +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include "chip.h" + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = baytrail_init_cpus, + .scan_bus = NULL, +}; + + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle south cluster enablement. */ + if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && + (dev->ops == NULL || dev->ops->enable == NULL)) { + southcluster_enable_dev(dev); + } + } +} + +/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ +static void soc_init(void *chip_info) +{ + baytrail_init_pre_device(chip_info); +} + +struct chip_operations soc_intel_baytrail_ops = { + CHIP_NAME("Intel BayTrail SoC") + .enable_dev = enable_dev, + .init = soc_init, +}; + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = &pci_set_subsystem, +}; diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h new file mode 100644 index 0000000..ecf1ce3 --- /dev/null +++ b/src/soc/intel/braswell/chip.h @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The devicetree parser expects chip.h to reside directly in the path + * specified by the devicetree. */ + +#ifndef _BAYTRAIL_CHIP_H_ +#define _BAYTRAIL_CHIP_H_ + +#include <stdint.h> + +struct soc_intel_baytrail_config { + uint8_t enable_xdp_tap; + uint8_t sata_port_map; + uint8_t sata_ahci; + uint8_t ide_legacy_combined; + uint8_t clkreq_enable; + + /* VR low power settings -- enable PS2 mode for gfx and core */ + int vnn_ps2_enable; + int vcc_ps2_enable; + + /* Disable SLP_X stretching after SUS power well loss. */ + int disable_slp_x_stretch_sus_fail; + + /* USB Port Disable mask */ + uint16_t usb2_port_disable_mask; + uint16_t usb3_port_disable_mask; + + /* USB routing */ + int usb_route_to_xhci; + + /* USB PHY settings specific to the board */ + uint32_t usb2_per_port_lane0; + uint32_t usb2_per_port_rcomp_hs_pullup0; + uint32_t usb2_per_port_lane1; + uint32_t usb2_per_port_rcomp_hs_pullup1; + uint32_t usb2_per_port_lane2; + uint32_t usb2_per_port_rcomp_hs_pullup2; + uint32_t usb2_per_port_lane3; + uint32_t usb2_per_port_rcomp_hs_pullup3; + uint32_t usb2_comp_bg; + + /* LPE Audio Clock configuration. */ + int lpe_codec_clk_freq; /* 19 or 25 are valid. */ + int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + + /* Native SD Card controller - override controller capabilities. */ + uint32_t sdcard_cap_low; + uint32_t sdcard_cap_high; + + /* Enable devices in ACPI mode */ + int lpss_acpi_mode; + int scc_acpi_mode; + int lpe_acpi_mode; + + /* Allow PCIe devices to wake system from suspend. */ + int pcie_wake_enable; + + int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipea_power_on_delay; + uint16_t gpu_pipea_light_on_delay; + uint16_t gpu_pipea_power_off_delay; + uint16_t gpu_pipea_light_off_delay; + uint16_t gpu_pipea_power_cycle_delay; + int gpu_pipea_pwm_freq_hz; + + int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipeb_power_on_delay; + uint16_t gpu_pipeb_light_on_delay; + uint16_t gpu_pipeb_power_off_delay; + uint16_t gpu_pipeb_light_off_delay; + uint16_t gpu_pipeb_power_cycle_delay; + int gpu_pipeb_pwm_freq_hz; + int disable_ddr_2x_refresh_rate; +}; + +extern struct chip_operations soc_intel_baytrail_ops; +#endif /* _BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c new file mode 100644 index 0000000..f4d752e --- /dev/null +++ b/src/soc/intel/braswell/cpu.c @@ -0,0 +1,309 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdlib.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/intel/microcode.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> +#include <reg_script.h> + +#include <soc/iosf.h> +#include <soc/msr.h> +#include <soc/pattrs.h> +#include <soc/ramstage.h> +#include <soc/smm.h> + +static void smm_relocate(void *unused); +static void enable_smis(void *unused); + +static struct mp_flight_record mp_steps[] = { + MP_FR_BLOCK_APS(smm_relocate, NULL, smm_relocate, NULL), + MP_FR_BLOCK_APS(mp_initialize_cpu, NULL, mp_initialize_cpu, NULL), + /* Wait for APs to finish initialization before proceeding. */ + MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL), +}; + +/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */ +static int adjust_apic_id(int index, int apic_id) +{ + return 2 * index; +} + +/* Package level MSRs */ +const struct reg_script package_msr_script[] = { + /* Set Package TDP to ~7W */ + REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), + REG_MSR_RMW(MSR_PP1_POWER_LIMIT, ~(0x7f << 17), 0), + REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), + REG_MSR_WRITE(MSR_CPU_THERM_CFG1, 0x00000305), + REG_MSR_WRITE(MSR_CPU_THERM_CFG2, 0x0405500d), + REG_MSR_WRITE(MSR_CPU_THERM_SENS_CFG, 0x27), + REG_SCRIPT_END +}; + +/* Core level MSRs */ +const struct reg_script core_msr_script[] = { + /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_POWER_MISC, + ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_MSR_OR(MSR_POWER_MISC, 0x44), + REG_SCRIPT_END +}; + +void baytrail_init_cpus(device_t dev) +{ + struct bus *cpu_bus = dev->link_list; + const struct pattrs *pattrs = pattrs_get(); + struct mp_params mp_params; + uint32_t bsmrwac; + void *default_smm_area; + + /* Set up MTRRs based on physical address size. */ + x86_setup_fixed_mtrrs(); + x86_setup_var_mtrrs(pattrs->address_bits, 2); + x86_mtrr_check(); + + mp_params.num_cpus = pattrs->num_cpus, + mp_params.parallel_microcode_load = 1, + mp_params.adjust_apic_id = adjust_apic_id; + mp_params.flight_plan = &mp_steps[0]; + mp_params.num_records = ARRAY_SIZE(mp_steps); + mp_params.microcode_pointer = pattrs->microcode_patch; + + default_smm_area = backup_default_smm_area(); + + /* + * Configure the BUNIT to allow dirty cache line evictions in non-SMM + * mode for the lines that were dirtied while in SMM mode. Otherwise + * the writes would be silently dropped. + */ + bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED; + iosf_bunit_write(BUNIT_SMRWAC, bsmrwac); + + /* Set package MSRs */ + reg_script_run(package_msr_script); + + /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ + enable_turbo(); + + if (mp_init(cpu_bus, &mp_params)) { + printk(BIOS_ERR, "MP initialization failure.\n"); + } + + restore_default_smm_area(default_smm_area); +} + +static void baytrail_core_init(device_t cpu) +{ + printk(BIOS_DEBUG, "Init BayTrail core.\n"); + + /* On bay trail the turbo disable bit is actually scoped at building + * block level -- not package. For non-bsp cores that are within a + * building block enable turbo. The cores within the BSP's building + * block will just see it already enabled and move on. */ + if (lapicid()) + enable_turbo(); + + /* Set core MSRs */ + reg_script_run(core_msr_script); + + /* Set this core to max frequency ratio */ + set_max_freq(); +} + +static struct device_operations cpu_dev_ops = { + .init = baytrail_core_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x30673 }, + { X86_VENDOR_INTEL, 0x30678 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + + +/* + * SMM loading and initialization. + */ + +struct smm_relocation_attrs { + uint32_t smbase; + uint32_t smrr_base; + uint32_t smrr_mask; +}; + +static struct smm_relocation_attrs relo_attrs; + +static void adjust_apic_id_map(struct smm_loader_params *smm_params) +{ + int i; + struct smm_runtime *runtime = smm_params->runtime; + + for (i = 0; i < CONFIG_MAX_CPUS; i++) + runtime->apic_id_to_cpu[i] = mp_get_apic_id(i); +} + +static void asmlinkage cpu_smm_do_relocation(void *arg) +{ + msr_t smrr; + em64t100_smm_state_save_area_t *smm_state; + const struct smm_module_params *p; + const struct smm_runtime *runtime; + int cpu; + + p = arg; + runtime = p->runtime; + cpu = p->cpu; + + if (cpu >= CONFIG_MAX_CPUS) { + printk(BIOS_CRIT, + "Invalid CPU number assigned in SMM stub: %d\n", cpu); + return; + } + + /* Set up SMRR. */ + smrr.lo = relo_attrs.smrr_base; + smrr.hi = 0; + wrmsr(SMRRphysBase_MSR, smrr); + smrr.lo = relo_attrs.smrr_mask; + smrr.hi = 0; + wrmsr(SMRRphysMask_MSR, smrr); + + /* The relocated handler runs with all CPUs concurrently. Therefore + * stagger the entry points adjusting SMBASE downwards by save state + * size * CPU num. */ + smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase); + smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size; + printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase); +} + +static int install_relocation_handler(int num_cpus) +{ + const int save_state_size = sizeof(em64t100_smm_state_save_area_t); + + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = 1, + .handler = (smm_handler_t)&cpu_smm_do_relocation, + }; + + if (smm_setup_relocation_handler(&smm_params)) + return -1; + + adjust_apic_id_map(&smm_params); + + return 0; +} + +static int install_permanent_handler(int num_cpus) +{ + /* There are num_cpus concurrent stacks and num_cpus concurrent save + * state areas. Lastly, set the stack size to the save state size. */ + int save_state_size = sizeof(em64t100_smm_state_save_area_t); + struct smm_loader_params smm_params = { + .per_cpu_stack_size = save_state_size, + .num_concurrent_stacks = num_cpus, + .per_cpu_save_state_size = save_state_size, + .num_concurrent_save_states = num_cpus, + }; + const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE; + + printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", + relo_attrs.smbase); + + if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params)) + return -1; + + adjust_apic_id_map(&smm_params); + + return 0; +} + +static int smm_load_handlers(void) +{ + /* All range registers are aligned to 4KiB */ + const uint32_t rmask = ~((1 << 12) - 1); + const struct pattrs *pattrs = pattrs_get(); + + /* Initialize global tracking state. */ + relo_attrs.smbase = (uint32_t)smm_region_start(); + relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; + relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; + relo_attrs.smrr_mask |= MTRRphysMaskValid; + + /* Install handlers. */ + if (install_relocation_handler(pattrs->num_cpus) < 0) { + printk(BIOS_ERR, "Unable to install SMM relocation handler.\n"); + return -1; + } + + if (install_permanent_handler(pattrs->num_cpus) < 0) { + printk(BIOS_ERR, "Unable to install SMM permanent handler.\n"); + return -1; + } + + /* Ensure the SMM handlers hit DRAM before performing first SMI. */ + wbinvd(); + + return 0; +} + +static void smm_relocate(void *unused) +{ + const struct pattrs *pattrs = pattrs_get(); + + /* Load relocation and permanent handler. */ + if (boot_cpu()) { + if (smm_load_handlers() < 0) { + printk(BIOS_ERR, "Error loading SMM handlers.\n"); + return; + } + southcluster_smm_clear_state(); + } + + /* Relocate SMM space. */ + smm_initiate_relocation(); + + /* Load microcode after SMM relocation. */ + intel_microcode_load_unlocked(pattrs->microcode_patch); +} + +static void enable_smis(void *unused) +{ + southcluster_smm_enable_smi(); +} diff --git a/src/soc/intel/braswell/dptf.c b/src/soc/intel/braswell/dptf.c new file mode 100644 index 0000000..20d3420 --- /dev/null +++ b/src/soc/intel/braswell/dptf.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <reg_script.h> +#include <soc/iosf.h> + +static const struct reg_script dptf_init_settings[] = { + /* SocThermInit */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 0x00000000), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), + /* ratio 11 = 1466mhz for mid and entry celeron */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000B00), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), + REG_SCRIPT_END, +}; + +static void dptf_init(void *unused) +{ + printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n"); + reg_script_run(dptf_init_settings); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL); diff --git a/src/soc/intel/braswell/ehci.c b/src/soc/intel/braswell/ehci.c new file mode 100644 index 0000000..7cf5e2b --- /dev/null +++ b/src/soc/intel/braswell/ehci.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/ramstage.h> +#include <soc/ehci.h> + +#include "chip.h" + +static const struct reg_script ehci_init_script[] = { + /* Enable S0 PLL shutdown + * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ + REG_PCI_OR16(0x7a, 0x14de), + /* Enable SB local clock gating + * D29:F0:7C[14,3,2]=111b (14 set in clock gating step) */ + REG_PCI_OR32(0x7c, 0x0000000c), + REG_PCI_OR32(0x8c, 0x00000001), + /* Enable dynamic clock gating 0x4001=0xCE */ + REG_IOSF_RMW(IOSF_PORT_USBPHY, 0x4001, 0xFFFFFF00, 0xCE), + /* Magic RCBA register set sequence */ + /* RCBA + 0x200=0x1 */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x200, 0x00000001), + /* RCBA + 0x204=0x2 */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x204, 0x00000002), + /* RCBA + 0x208=0x0 */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x208, 0x00000000), + /* RCBA + 0x240[4,3,2,1,0]=00000b */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x240, ~0x0000001f, 0), + /* RCBA + 0x318[9,8,6,5,4,3,2,1,0]=000000111b */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x318, ~0x00000378, 0x00000007), + /* RCBA + 0x31c[3,2,1,0]=0011b */ + REG_MMIO_RMW32(RCBA_BASE_ADDRESS + 0x31c, ~0x0000000c, 0x00000003), + REG_SCRIPT_END +}; + +static const struct reg_script ehci_clock_gating_script[] = { + /* Enable SB local clock gating */ + REG_PCI_OR32(0x7c, 0x00004000), + /* RCBA + 0x284=0xbe (step B0+) */ + REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x284, 0x000000be), + REG_SCRIPT_END +}; + +static const struct reg_script ehci_disable_script[] = { + /* Clear Run/Stop Bit */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), + /* Wait for HC Halted */ + REG_RES_POLL32(PCI_BASE_ADDRESS_0, USB2STS, + USB2STS_HCHALT, USB2STS_HCHALT, 10000), + /* Disable Interrupts */ + REG_PCI_OR32(EHCI_CMD_STS, INTRDIS), + /* Disable Asynchronous and Periodic Scheduler */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, + ~(USB2CMD_ASE | USB2CMD_PSE), 0), + /* Disable port wake */ + REG_PCI_RMW32(EHCI_SBRN_FLA_PWC, ~(PORTWKIMP | PORTWKCAPMASK), 0), + /* Set Function Disable bit in RCBA */ + REG_MMIO_OR32(RCBA_BASE_ADDRESS + RCBA_FUNC_DIS, RCBA_EHCI_DIS), + REG_SCRIPT_END +}; + +static const struct reg_script ehci_hc_reset[] = { + REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), + REG_SCRIPT_END +}; + +static void usb2_phy_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ? + 0x4700 : config->usb2_comp_bg); + struct reg_script usb2_phy_script[] = { + /* USB3PHYInit() */ + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, + usb2_comp_bg), + /* Per port phy settings, set in devicetree.cb */ + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE0, + config->usb2_per_port_lane0), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP0, + config->usb2_per_port_rcomp_hs_pullup0), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE1, + config->usb2_per_port_lane1), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP1, + config->usb2_per_port_rcomp_hs_pullup1), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE2, + config->usb2_per_port_lane2), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP2, + config->usb2_per_port_rcomp_hs_pullup2), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_PER_PORT_LANE3, + config->usb2_per_port_lane3), + REG_IOSF_WRITE(IOSF_PORT_USBPHY, + USBPHY_PER_PORT_RCOMP_HS_PULLUP3, + config->usb2_per_port_rcomp_hs_pullup3), + REG_SCRIPT_END + }; + reg_script_run(usb2_phy_script); +} + +static void ehci_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + struct reg_script ehci_hc_init[] = { + /* Controller init */ + REG_SCRIPT_NEXT(ehci_init_script), + /* Enable clock gating */ + REG_SCRIPT_NEXT(ehci_clock_gating_script), + /* + * Disable ports if requested + */ + /* Open per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), + REG_PCI_WRITE8(EHCI_USB2PDO, config->usb2_port_disable_mask), + /* Close per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), + REG_SCRIPT_END + }; + + /* Don't reset controller in S3 resume path */ + if (!acpi_is_wakeup_s3()) + reg_script_run_on_dev(dev, ehci_hc_reset); + + /* Disable controller if ports are routed to XHCI */ + if (config->usb_route_to_xhci) { + /* Disable controller */ + reg_script_run_on_dev(dev, ehci_disable_script); + + /* Hide device with southcluster function */ + dev->enabled = 0; + southcluster_enable_dev(dev); + } else { + /* Initialize EHCI controller */ + reg_script_run_on_dev(dev, ehci_hc_init); + } + + /* Setup USB2 PHY based on board config */ + usb2_phy_init(dev); +} + +static struct device_operations ehci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = ehci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver baytrail_ehci __pci_driver = { + .ops = &ehci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = EHCI_DEVID +}; diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c new file mode 100644 index 0000000..f20dc97 --- /dev/null +++ b/src/soc/intel/braswell/elog.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/acpi.h> +#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <soc/iomap.h> +#include <soc/pmc.h> + +static void log_power_and_resets(const struct chipset_power_state *ps) +{ + if (ps->gen_pmcon1 & PWR_FLR) { + elog_add_event(ELOG_TYPE_POWER_FAIL); + elog_add_event(ELOG_TYPE_PWROK_FAIL); + } + + if (ps->gen_pmcon1 & SUS_PWR_FLR) { + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + } + + if (ps->gen_pmcon1 & RPS) { + elog_add_event(ELOG_TYPE_RTC_RESET); + } + + if (ps->tco_sts & SECOND_TO_STS) { + elog_add_event(ELOG_TYPE_TCO_RESET); + } + + if (ps->pm1_sts & PRBTNOR_STS) { + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + } + + if (ps->gen_pmcon1 & SRS) { + elog_add_event(ELOG_TYPE_RESET_BUTTON); + } + + if (ps->gen_pmcon1 & GEN_RST_STS) { + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + } +} + +static void log_wake_events(const struct chipset_power_state *ps) +{ + const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | + PCIE_WAKE2_STS | PCIE_WAKE1_STS | + PCIE_WAKE0_STS; + uint32_t gpe0_sts; + uint32_t gpio_mask; + int i; + + /* Mask off disabled events. */ + gpe0_sts = ps->gpe0_sts & ps->gpe0_en; + + if (ps->pm1_sts & WAK_STS) { + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + acpi_is_wakeup_s3() ? 3 : 5); + } + + if (ps->pm1_sts & PWRBTN_STS) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + } + + if (ps->pm1_sts & RTC_STS) { + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + } + + if (gpe0_sts & PME_B0_EN) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + } + + if (gpe0_sts & pcie_wake_mask) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + } + + gpio_mask = SUS_GPIO_STS0; + i = 0; + while (gpio_mask) { + if (gpio_mask & gpe0_sts) { + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + } + gpio_mask <<= 1; + i++; + } +} + +void southcluster_log_state(void) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_DEBUG, "Not logging power state information. " + "Power state not found in cbmem.\n"); + return; + } + + log_power_and_resets(ps); + log_wake_events(ps); +} diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c new file mode 100644 index 0000000..1708428 --- /dev/null +++ b/src/soc/intel/braswell/emmc.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iosf.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include "chip.h" + +static const struct reg_script emmc_ops[] = { + /* Enable 2ms card stable feature. */ + REG_PCI_OR32(0xa8, (1 << 24)), + /* Enable HS200 */ + REG_PCI_WRITE32(0xa0, 0x446cc801), + REG_PCI_WRITE32(0xa4, 0x80000807), + /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ + REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), + /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ + REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), + /* Set slew for HS200 */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), + /* Max timeout */ + REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), + REG_SCRIPT_END, +}; + +static void emmc_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + + printk(BIOS_DEBUG, "eMMC init\n"); + reg_script_run_on_dev(dev, emmc_ops); + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = emmc_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMC_DEVID, +}; diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c new file mode 100644 index 0000000..0601e94 --- /dev/null +++ b/src/soc/intel/braswell/gfx.c @@ -0,0 +1,398 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> +#include <stdlib.h> + +#include <soc/gfx.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#include "chip.h" + +#define GFX_TIMEOUT 100000 /* 100ms */ + +/* + * Lock Power Context Base Register to point to a 24KB block + * of memory in GSM. Power context save data is stored here. + */ +static void gfx_lock_pcbase(device_t dev) +{ + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, + 288,320,352,384,416,448,480,512 }; + u32 pcsize = 24 << 10; /* 24KB */ + u32 wopcmsz = 0x100000; /* PAVP offset */ + u32 gms, gmsize, pcbase; + + gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK; + gms >>= 3; + if (gms > ARRAY_SIZE(gms_size_map)) + return; + gmsize = gms_size_map[gms]; + + /* PcBase = BDSM + GMS Size - WOPCMSZ - PowerContextSize */ + pcbase = pci_read_config32(dev, GSM_BASE) & 0xfff00000; + pcbase += (gmsize-1) * wopcmsz - pcsize; + pcbase |= 1; /* Lock */ + + write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase); +} + +static const struct reg_script gfx_init_script[] = { + /* Allow-Wake render/media wells */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), + /* Render Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, + GFX_TIMEOUT), + /* Media Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, + GFX_TIMEOUT), + /* Workaround - X0:261954/A0:261955 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), + + /* + * PowerMeter Weights + */ + + /* SET1 */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000), + /* SET2 */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), + /* SET3 */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), + /* Enable PowerMeter Counters */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), + + /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ + /* SDP Profile 4 == 0x11940, others 0xcf08 */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), + + /* GfxPause */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), + + /* Dynamic EU Control Settings */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), + + /* Lock ECO Bit Settings */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), + + /* DOP Clock Gating */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), + + /* MBCunit will send the VCR (Fuse) writes as NP-W */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000), + + /* + * RC6 Settings + */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000), + /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019), + /* RC Sleep / RCx Thresholds */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557), + + /* + * Turbo Settings + */ + + /* Render/Video/Blitter Idle Max Count */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A), + /* RP Down Timeout */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240), + + /* + * Turbo Control Settings + */ + + /* RP Up/Down Threshold */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08), + /* RP Up/Down EI */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730), + + /* RP Idle Hysteresis */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), + + /* HW RC6 Control Settings */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000), + + /* RP Control */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592), + + /* Enable PM Interrupts */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e), + + /* Aggressive Clock Gating */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), + + /* Enable Gfx Turbo. */ + REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG, + ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0), + REG_SCRIPT_END +}; + +static const struct reg_script gpu_pre_vbios_script[] = { + /* Make sure GFX is bus master with MMIO access */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), + /* Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, + GFX_TIMEOUT), + /* Tx/Rx Lanes */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, + GFX_TIMEOUT), + /* Common Lane */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, + GFX_TIMEOUT), + /* Ungating Tx only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, + GFX_TIMEOUT), + /* Ungating Common Lane only */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, + GFX_TIMEOUT), + /* Ungating Display */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, + GFX_TIMEOUT), + REG_SCRIPT_END +}; + +static const struct reg_script gfx_post_vbios_script[] = { + /* Deassert Render Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), + /* Deassert Media Force-Wake */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), + /* Set Lock bits */ + REG_PCI_RMW32(GGC, 0xffffffff, 1), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_SCRIPT_END +}; + +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) +{ + reg_script_run_on_dev(dev, ops); +} + +static void gfx_pre_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); + gfx_run_script(dev, gpu_pre_vbios_script); +} + +static void gfx_pm_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Power Management Init\n"); + gfx_run_script(dev, gfx_init_script); + + /* Lock power context base */ + gfx_lock_pcbase(dev); +} + +static void gfx_post_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); + gfx_run_script(dev, gfx_post_vbios_script); +} + +static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz) +{ + int divider; + struct resource *res; + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + + if (res == NULL) + return; + + /* Default to 200 Hz if nothing is set. */ + if (req_hz == 0) + req_hz = 200; + + /* Base clock is 25MHz */ + divider = 25 * 1000 * 1000 / (16 * req_hz); + + /* Do not set duty cycle (lower 16 bits). Just set the divider. */ + write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16); +} + +static void gfx_panel_setup(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + struct reg_script gfx_pipea_init[] = { + /* CONTROL */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + /* POWER ON */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), + (config->gpu_pipea_port_select << 30 | + config->gpu_pipea_power_on_delay << 16 | + config->gpu_pipea_light_on_delay)), + /* POWER OFF */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), + (config->gpu_pipea_power_off_delay << 16 | + config->gpu_pipea_light_off_delay)), + /* DIVISOR */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipea_power_cycle_delay), + REG_SCRIPT_END + }; + struct reg_script gfx_pipeb_init[] = { + /* CONTROL */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + /* POWER ON */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), + (config->gpu_pipeb_port_select << 30 | + config->gpu_pipeb_power_on_delay << 16 | + config->gpu_pipeb_light_on_delay)), + /* POWER OFF */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), + (config->gpu_pipeb_power_off_delay << 16 | + config->gpu_pipeb_light_off_delay)), + /* DIVISOR */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipeb_power_cycle_delay), + REG_SCRIPT_END + }; + + if (config->gpu_pipea_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); + reg_script_run_on_dev(dev, gfx_pipea_init); + set_backlight_pwm(dev, PIPEA_REG(BACKLIGHT_CTL), + config->gpu_pipea_pwm_freq_hz); + } + + if (config->gpu_pipeb_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); + reg_script_run_on_dev(dev, gfx_pipeb_init); + set_backlight_pwm(dev, PIPEB_REG(BACKLIGHT_CTL), + config->gpu_pipeb_pwm_freq_hz); + } +} + +static void gfx_init(device_t dev) +{ + /* Pre VBIOS Init */ + gfx_pre_vbios_init(dev); + + /* Power Management Init */ + gfx_pm_init(dev); + + gfx_panel_setup(dev); + + /* Run VBIOS */ + pci_dev_init(dev); + + /* Post VBIOS Init */ + gfx_post_vbios_init(dev); +} + +static struct device_operations gfx_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gfx_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver gfx_driver __pci_driver = { + .ops = &gfx_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = GFX_DEVID, +}; diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c new file mode 100644 index 0000000..e4cc59a --- /dev/null +++ b/src/soc/intel/braswell/gpio.c @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/pci.h> +#include <console/console.h> +#include <soc/gpio.h> +#include <soc/pmc.h> +#include <soc/smm.h> + +/* GPIO-to-Pad LUTs */ +static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = + { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ + 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ + 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ + 2, 5, 9 }; /* [24:26] */ + +static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = + { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */ + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */ + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */ + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */ + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */ + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */ + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */ + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */ + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */ + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */ + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */ + 106, 87, 91, 104, 97, 100 }; /* [96:101] */ + +static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = + { 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */ + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */ + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */ + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */ + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */ + 52, 53, 59, 40 }; /* [40:43] */ + +/* GPIO bank descriptions */ +static const struct gpio_bank gpncore_bank = { + .gpio_count = GPNCORE_COUNT, + .gpio_to_pad = gpncore_gpio_to_pad, + .legacy_base = GP_LEGACY_BASE_NONE, + .pad_base = GPNCORE_PAD_BASE, + .has_wake_en = 0, + .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END, +}; + +static const struct gpio_bank gpscore_bank = { + .gpio_count = GPSCORE_COUNT, + .gpio_to_pad = gpscore_gpio_to_pad, + .legacy_base = GPSCORE_LEGACY_BASE, + .pad_base = GPSCORE_PAD_BASE, + .has_wake_en = 0, + .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END, +}; + +static const struct gpio_bank gpssus_bank = { + .gpio_count = GPSSUS_COUNT, + .gpio_to_pad = gpssus_gpio_to_pad, + .legacy_base = GPSSUS_LEGACY_BASE, + .pad_base = GPSSUS_PAD_BASE, + .has_wake_en = 1, + .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START, + .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END, +}; + +static void setup_gpios(const struct soc_gpio_map *gpios, + const struct gpio_bank *bank) +{ + const struct soc_gpio_map *config; + int gpio = 0; + u32 reg, pad_conf0; + u8 set, bit; + + u32 use_sel[4] = {0}; + u32 io_sel[4] = {0}; + u32 gp_lvl[4] = {0}; + u32 tpe[4] = {0}; + u32 tne[4] = {0}; + u32 wake_en[4] = {0}; + + if (!gpios) + return; + + for (config = gpios; config->pad_conf0 != GPIO_LIST_END; + config++, gpio++) { + if (gpio > bank->gpio_count) + break; + + set = gpio >> 5; + bit = gpio % 32; + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) { + /* Legacy IO configuration */ + use_sel[set] |= config->use_sel << bit; + io_sel[set] |= config->io_sel << bit; + gp_lvl[set] |= config->gp_lvl << bit; + tpe[set] |= config->tpe << bit; + tne[set] |= config->tne << bit; + + /* Some banks do not have wake_en ability */ + if (bank->has_wake_en) + wake_en[set] |= config->wake_en << bit; + } + + /* Pad configuration registers */ + reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio]; + + /* Add correct func to GPIO pad config */ + pad_conf0 = config->pad_conf0; + if (config->is_gpio) + { + if (gpio >= bank->gpio_f1_range_start && + gpio <= bank->gpio_f1_range_end) + pad_conf0 |= PAD_FUNC1; + else + pad_conf0 |= PAD_FUNC0; + } + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n", + reg, pad_conf0, config->pad_conf1, config->pad_val); +#endif + + write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0); + write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32((u32 *)(reg + PAD_VAL_REG), config->pad_val); + } + + if (bank->legacy_base != GP_LEGACY_BASE_NONE) + for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) { + reg = bank->legacy_base + 0x20 * set; + +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, + "Write GPIO: Reg(%x) - %x %x %x %x %x\n", + reg, use_sel[set], io_sel[set], gp_lvl[set], + tpe[set], tne[set]); +#endif + + outl(use_sel[set], reg + LEGACY_USE_SEL_REG); + outl(io_sel[set], reg + LEGACY_IO_SEL_REG); + outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG); + outl(tpe[set], reg + LEGACY_TPE_REG); + outl(tne[set], reg + LEGACY_TNE_REG); + + /* TS registers are WOC */ + outl(0, reg + LEGACY_TS_REG); + + if (bank->has_wake_en) + outl(wake_en[set], reg + LEGACY_WAKE_EN_REG); + } +} + +static void setup_gpio_route(const struct soc_gpio_map *sus, + const struct soc_gpio_map *core) +{ + uint32_t route_reg = 0; + int i; + + for (i = 0; i < 8; i++) { + /* SMI takes precedence and wake_en implies SCI. */ + if (sus[i].smi) { + route_reg |= ROUTE_SMI << (2 * i); + } else if (sus[i].sci) { + route_reg |= ROUTE_SCI << (2 * i); + } + + if (core[i].smi) { + route_reg |= ROUTE_SMI << (2 * (i + 8)); + } else if (core[i].sci) { + route_reg |= ROUTE_SCI << (2 * (i + 8)); + } + } + southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg); +} + +static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], + const struct gpio_bank *bank) +{ + u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET); + u32 val; + int i; + + /* Write all four DIRQ registers */ + for (i=0; i<4; ++i) { + val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | + dirq[i * 4 + 1] << 8 | dirq[i * 4]; + write32(reg + i, val); +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", + reg + i, val); +#endif + } +} + +void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) +{ + if (config) { + setup_gpios(config->ncore, &gpncore_bank); + setup_gpios(config->score, &gpscore_bank); + setup_gpios(config->ssus, &gpssus_bank); + setup_gpio_route(config->ssus, config->score); + + if (config->core_dirq) + setup_dirqs(*config->core_dirq, &gpscore_bank); + if (config->sus_dirq) + setup_dirqs(*config->sus_dirq, &gpssus_bank); + } + + /* Set on die termination feature with pull up value and + * drive the pad high for TAP_TDO and TAP_TMS + */ + if (!enable_xdp_tap) { + printk(BIOS_DEBUG, "Tri-state TDO and TMS\n"); + write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc); + write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc); + } +} + +struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void) +{ + printk(BIOS_DEBUG, "Default/empty GPIO config\n"); + return NULL; +} diff --git a/src/soc/intel/braswell/hda.c b/src/soc/intel/braswell/hda.c new file mode 100644 index 0000000..dd1ba15 --- /dev/null +++ b/src/soc/intel/braswell/hda.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/intel/common/hda_verb.h> +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +static const struct reg_script init_ops[] = { + /* Enable no snoop traffic. */ + REG_PCI_OR16(0x78, 1 << 11), + /* Configure HDMI codec connection. */ + REG_PCI_OR32(0xc4, 1 << 1), + REG_PCI_OR8(0x43, (1 << 3) | (1 << 6)), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0x00), + /* Configure internal settings. */ + REG_PCI_OR32(0xc0, 0x7 << 21), + REG_PCI_OR32(0xc4, (0x3 << 26) | (1 << 13) | (1 << 10)), + REG_PCI_WRITE32(0xc8, 0x82a30000), + REG_PCI_RMW32(0xd0, ~(1 << 31), 0x0), + /* Disable docking. */ + REG_PCI_RMW8(0x4d, ~(1 << 7), 0), + REG_SCRIPT_END, +}; + +static const uint32_t hdmi_codec_verb_table[] = { + /* coreboot specific header */ + 0x80862882, /* vid did for hdmi codec */ + 0x00000000, /* subsystem id */ + 0x00000003, /* number of jacks */ + + /* pin widget 5 - port B */ + 0x20471c10, + 0x20471d00, + 0x20471e56, + 0x20471f18, + + /* pin widget 6 - port C */ + 0x20571c20, + 0x20571d00, + 0x20571e56, + 0x20571f18, + + /* pin widget 7 - port D */ + 0x20671c30, + 0x20671d00, + 0x20671e56, + 0x20671f58, +}; + +static void hda_init(device_t dev) +{ + struct resource *res; + int codec_mask; + int i; + u8 *base; + + reg_script_run_on_dev(dev, init_ops); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (res == NULL) + return; + + base = res2mmio(res, 0, 0); + codec_mask = hda_codec_detect(base); + + printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); + if (!codec_mask) + return; + + for (i = 3; i >= 0; i--) { + if (!((1 << i) & codec_mask)) + continue; + hda_codec_init(base, i, sizeof(hdmi_codec_verb_table), + hdmi_codec_verb_table); + } +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = hda_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = HDA_DEVID, +}; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h new file mode 100644 index 0000000..bdf1cb3 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_ACPI_H_ +#define _BAYTRAIL_ACPI_H_ + +#include <arch/acpi.h> +#include <soc/nvs.h> + +void acpi_create_intel_hpet(acpi_hpet_t * hpet); +void acpi_fill_in_fadt(acpi_fadt_t *fadt); +unsigned long acpi_madt_irq_overrides(unsigned long current); +void acpi_init_gnvs(global_nvs_t *gnvs); + +#endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h new file mode 100644 index 0000000..1ed897f --- /dev/null +++ b/src/soc/intel/braswell/include/soc/device_nvs.h @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_DEVICE_NVS_H_ +#define _BAYTRAIL_DEVICE_NVS_H_ + +#include <stdint.h> + +/* Offset in Global NVS where this structure lives */ +#define DEVICE_NVS_OFFSET 0x1000 + +#define LPSS_NVS_SIO_DMA1 0 +#define LPSS_NVS_I2C1 1 +#define LPSS_NVS_I2C2 2 +#define LPSS_NVS_I2C3 3 +#define LPSS_NVS_I2C4 4 +#define LPSS_NVS_I2C5 5 +#define LPSS_NVS_I2C6 6 +#define LPSS_NVS_I2C7 7 +#define LPSS_NVS_SIO_DMA2 8 +#define LPSS_NVS_SPI 9 +#define LPSS_NVS_PWM1 10 +#define LPSS_NVS_PWM2 11 +#define LPSS_NVS_HSUART1 12 +#define LPSS_NVS_HSUART2 13 + +#define SCC_NVS_MMC 0 +#define SCC_NVS_SDIO 1 +#define SCC_NVS_SD 2 + +typedef struct { + /* Device Enabled in ACPI Mode */ + u8 lpss_en[14]; + u8 scc_en[3]; + u8 lpe_en; + + /* BAR 0 */ + u32 lpss_bar0[14]; + u32 scc_bar0[3]; + u32 lpe_bar0; + + /* BAR 0 */ + u32 lpss_bar1[14]; + u32 scc_bar1[3]; + u32 lpe_bar1; + + /* Extra */ + u32 lpe_fw; /* LPE Firmware */ + u8 rsvd1[3930]; /* Add padding so sizeof(device_nvs_t) == 0x1000 */ +} __attribute__((packed)) device_nvs_t; + +#endif diff --git a/src/soc/intel/braswell/include/soc/efi_wrapper.h b/src/soc/intel/braswell/include/soc/efi_wrapper.h new file mode 100644 index 0000000..3304d03 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/efi_wrapper.h @@ -0,0 +1,52 @@ +/* + * PEI EFI entry point + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EFI_WRAPPER_H__ +#define __EFI_WRAPPER_H__ + +#define EFI_WRAPPER_VER 2 + +/* Provide generic x86 calling conventions. */ +#define ABI_X86 __attribute((regparm(0))) + +/* Errors returned by the EFI wrapper. */ +enum efi_wrapper_error { + INVALID_VER = -1, +}; + +struct efi_wrapper_params { + /* Mainboard Inputs */ + int version; + + void ABI_X86 (*console_out)(unsigned char byte); + + unsigned int tsc_ticks_per_microsecond; +} __attribute__((packed)); + +typedef int ABI_X86 (*efi_wrapper_entry_t)(struct efi_wrapper_params *); +#endif diff --git a/src/soc/intel/braswell/include/soc/ehci.h b/src/soc/intel/braswell/include/soc/ehci.h new file mode 100644 index 0000000..a1edd6d --- /dev/null +++ b/src/soc/intel/braswell/include/soc/ehci.h @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_EHCI_H +#define BAYTRAIL_EHCI_H + +/* EHCI PCI Registers */ +#define EHCI_CMD_STS 0x04 +# define INTRDIS (1 << 10) +#define EHCI_SBRN_FLA_PWC 0x60 +# define PORTWKIMP (1 << 16) +# define PORTWKCAPMASK (0x3ff << 17) +#define EHCI_USB2PDO 0x64 + +/* EHCI Memory Registers */ +#define USB2CMD 0x20 +# define USB2CMD_ASE (1 << 5) +# define USB2CMD_PSE (1 << 4) +# define USB2CMD_HCRESET (1 << 1) +# define USB2CMD_RS (1 << 0) +#define USB2STS 0x24 +# define USB2STS_HCHALT (1 << 12) + +/* RCBA EHCI Registers */ +#define RCBA_FUNC_DIS 0x220 +# define RCBA_EHCI_DIS (1 << 0) + +#endif /* BAYTRAIL_EHCI_H */ diff --git a/src/soc/intel/braswell/include/soc/gfx.h b/src/soc/intel/braswell/include/soc/gfx.h new file mode 100644 index 0000000..7047dd5 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/gfx.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_GFX_H_ +#define _BAYTRAIL_GFX_H_ + +/* + * PCI config registers. + */ + +#define GGC 0x50 +# define GGC_VGA_DISABLE (1 << 1) +# define GGC_GTT_SIZE_MASK (3 << 8) +# define GGC_GTT_SIZE_0MB (0 << 8) +# define GGC_GTT_SIZE_1MB (1 << 8) +# define GGC_GTT_SIZE_2MB (2 << 8) +# define GGC_GSM_SIZE_MASK (0x1f << 3) +# define GGC_GSM_SIZE_0MB (0 << 3) +# define GGC_GSM_SIZE_32MB (1 << 3) +# define GGC_GSM_SIZE_64MB (2 << 3) +# define GGC_GSM_SIZE_128MB (4 << 3) + +#define GSM_BASE 0x5c +#define GTT_BASE 0x70 + +#define MSAC 0x62 +#define APERTURE_SIZE_MASK (3 << 1) +#define APERTURE_SIZE_128MB (0 << 1) +#define APERTURE_SIZE_256MB (1 << 1) +#define APERTURE_SIZE_512MB (3 << 1) + +#define VLV_DISPLAY_BASE 0x180000 +#define PIPEA_REG(reg) (VLV_DISPLAY_BASE + (reg)) +#define PIPEB_REG(reg) (VLV_DISPLAY_BASE + 0x100 + (reg)) + +/* Panel control registers */ +#define HOTPLUG_CTRL 0x61110 +#define PP_CONTROL 0x61204 +#define PP_CONTROL_UNLOCK 0xabcd0000 +#define PP_CONTROL_EDP_FORCE_VDD (1 << 3) +#define PP_ON_DELAYS 0x61208 +#define PP_OFF_DELAYS 0x6120c +#define PP_DIVISOR 0x61210 +#define BACKLIGHT_CTL2 0x61250 +#define BACKLIGHT_ENABLE (1 << 31) +#define BACKLIGHT_CTL 0x61254 + +#endif /* _BAYTRAIL_GFX_H_ */ diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h new file mode 100644 index 0000000..f312cdc --- /dev/null +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -0,0 +1,459 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_GPIO_H_ +#define _BAYTRAIL_GPIO_H_ + +#include <stdint.h> +#include <arch/io.h> +#include <soc/iomap.h> + +/* #define GPIO_DEBUG */ + +/* Pad base, ex. PAD_CONF0[n]= PAD_BASE+16*n */ +#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) +#define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPNCORE) +#define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSSUS) + +/* DIRQ registers start at pad base + 0x980 */ +#define PAD_BASE_DIRQ_OFFSET 0x980 + +/* Pad register offset */ +#define PAD_CONF0_REG 0x0 +#define PAD_CONF1_REG 0x4 +#define PAD_VAL_REG 0x8 + +/* Legacy IO register base */ +#define GPSCORE_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x00) +#define GPSSUS_LEGACY_BASE (GPIO_BASE_ADDRESS + 0x80) +/* Some banks have no legacy GPIO interface */ +#define GP_LEGACY_BASE_NONE 0xFFFF + +#define LEGACY_USE_SEL_REG 0x00 +#define LEGACY_IO_SEL_REG 0x04 +#define LEGACY_GP_LVL_REG 0x08 +#define LEGACY_TPE_REG 0x0C +#define LEGACY_TNE_REG 0x10 +#define LEGACY_TS_REG 0x14 +#define LEGACY_WAKE_EN_REG 0x18 + +/* Number of GPIOs in each bank */ +#define GPNCORE_COUNT 27 +#define GPSCORE_COUNT 102 +#define GPSSUS_COUNT 44 + +/* GPIO legacy IO register settings */ +#define GPIO_USE_MMIO 0 +#define GPIO_USE_LEGACY 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_PEDGE_DISABLE 0 +#define GPIO_PEDGE_ENABLE 1 + +#define GPIO_NEDGE_DISABLE 0 +#define GPIO_NEDGE_ENABLE 1 + +/* config0[29] - Disable second mask */ +#define PAD_MASK2_DISABLE (1 << 29) + +/* config0[27] - Direct Irq En */ +#define PAD_IRQ_EN (1 << 27) + +/* config0[26] - gd_tne */ +#define PAD_TNE_IRQ (1 << 26) + +/* config0[25] - gd_tpe */ +#define PAD_TPE_IRQ (1 << 25) + +/* config0[24] - Gd Level */ +#define PAD_LEVEL_IRQ (1 << 24) +#define PAD_EDGE_IRQ (0 << 24) + +/* config0[17] - Slow clkgate / glitch filter */ +#define PAD_SLOWGF_ENABLE (1 << 17) + +/* config0[16] - Fast clkgate / glitch filter */ +#define PAD_FASTGF_ENABLE (1 << 16) + +/* config0[15] - Hysteresis enable (inverted) */ +#define PAD_HYST_DISABLE (1 << 15) +#define PAD_HYST_ENABLE (0 << 15) + +/* config0[14:13] - Hysteresis control */ +#define PAD_HYST_CTRL_DEFAULT (2 << 13) + +/* config0[11] - Bypass Flop */ +#define PAD_FLOP_BYPASS (1 << 11) +#define PAD_FLOP_ENABLE (0 << 11) + +/* config0[10:9] - Pull str */ +#define PAD_PU_2K (0 << 9) +#define PAD_PU_10K (1 << 9) +#define PAD_PU_20K (2 << 9) +#define PAD_PU_40K (3 << 9) + +/* config0[8:7] - Pull assign */ +#define PAD_PULL_DISABLE (0 << 7) +#define PAD_PULL_UP (1 << 7) +#define PAD_PULL_DOWN (2 << 7) + +/* config0[2:0] - Func. pin mux */ +#define PAD_FUNC0 0x0 +#define PAD_FUNC1 0x1 +#define PAD_FUNC2 0x2 +#define PAD_FUNC3 0x3 +#define PAD_FUNC4 0x4 +#define PAD_FUNC5 0x5 +#define PAD_FUNC6 0x6 + +/* pad config0 power-on values - We will not often want to change these */ +#define PAD_CONFIG0_DEFAULT (PAD_MASK2_DISABLE | PAD_SLOWGF_ENABLE | \ + PAD_FASTGF_ENABLE | PAD_HYST_DISABLE | \ + PAD_HYST_CTRL_DEFAULT | PAD_FLOP_BYPASS) + +/* pad config1 reg power-on values - Shouldn't need to change this */ +#define PAD_CONFIG1_DEFAULT 0x8000 + +/* pad_val[2] - Iinenb - active low */ +#define PAD_VAL_INPUT_DISABLE (1 << 2) +#define PAD_VAL_INPUT_ENABLE (0 << 2) + +/* pad_val[1] - Ioutenb - active low */ +#define PAD_VAL_OUTPUT_DISABLE (1 << 1) +#define PAD_VAL_OUTPUT_ENABLE (0 << 1) + +/* Input / Output state should usually be mutually exclusive */ +#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) + +/* pad_val[0] - Value */ +#define PAD_VAL_HIGH (1 << 0) +#define PAD_VAL_LOW (0 << 0) + +/* pad_val reg power-on default varies by pad, and apparently can cause issues + * if not set correctly, even if the pin isn't configured as GPIO. */ +#define PAD_VAL_DEFAULT PAD_VAL_INPUT + +/* Configure GPIOs as MMIO by default */ +#define GPIO_INPUT_PU_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PU_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PD_10K \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_PD_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_NOPU \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_MMIO, \ + .is_gpio = 1 } + +#define GPIO_INPUT_LEGACY_NOPU \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .is_gpio = 1 } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ_LEVELHIGH_NO_PULL \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ_LEVELLOW_PU_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ_EDGELOW_PU_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ_EDGEHIGH_PD_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ_EDGELOW_PD_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +/* Direct / dedicated IRQ input - pass signal directly to apic */ +#define GPIO_DIRQ_EDGEBOTH_PU_20K \ + { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, } + +#define GPIO_OUT_LOW \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW, \ + .is_gpio = 1 } + +#define GPIO_OUT_HIGH \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH, \ + .is_gpio = 1 } + +/* Define no-pull / PU / PD configs for each functional config option */ +#define GPIO_FUNC(_func, _pudir, _str) \ + { .use_sel = GPIO_USE_MMIO, \ + .pad_conf0 = PAD_FUNC##_func | PAD_##_pudir | PAD_PU_##_str | \ + PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_DEFAULT } + +/* Default functional configs -- no PU */ +#define GPIO_FUNC0 GPIO_FUNC(0, PULL_DISABLE, 20K) +#define GPIO_FUNC1 GPIO_FUNC(1, PULL_DISABLE, 20K) +#define GPIO_FUNC2 GPIO_FUNC(2, PULL_DISABLE, 20K) +#define GPIO_FUNC3 GPIO_FUNC(3, PULL_DISABLE, 20K) +#define GPIO_FUNC4 GPIO_FUNC(4, PULL_DISABLE, 20K) +#define GPIO_FUNC5 GPIO_FUNC(5, PULL_DISABLE, 20K) +#define GPIO_FUNC6 GPIO_FUNC(6, PULL_DISABLE, 20K) + +/* ACPI GPIO routing. Assume everything is externally pulled and negative edge + * triggered. SCI implies WAKE, but WAKE doesn't imply SCI. */ +#define GPIO_ACPI_SCI \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .sci = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_WAKE \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .wake_en = 1, } +#define GPIO_ACPI_SMI \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = 1, \ + .smi = 1} + +/* End marker */ +#define GPIO_LIST_END 0xffffffff + +#define GPIO_END \ + { .pad_conf0 = GPIO_LIST_END } + +/* Common default GPIO settings */ +#define GPIO_INPUT GPIO_INPUT_NOPU +#define GPIO_INPUT_LEGACY GPIO_INPUT_LEGACY_NOPU +#define GPIO_INPUT_PU GPIO_INPUT_PU_20K +#define GPIO_INPUT_PD GPIO_INPUT_PD_20K +#define GPIO_NC GPIO_OUT_HIGH +#define GPIO_DEFAULT GPIO_FUNC0 + +/* 16 DirectIRQs per supported bank */ +#define GPIO_MAX_DIRQS 16 + +/* Most pins are GPIO function 0. Some banks have a range of pins with GPIO + * function 1. Indicate first / last GPIOs with function 1. */ +#define GPIO_NONE 255 +/* All NCORE GPIOs are function 0 */ +#define GPNCORE_GPIO_F1_RANGE_START GPIO_NONE +#define GPNCORE_GPIO_F1_RANGE_END GPIO_NONE +/* SCORE GPIO [92:93] are function 1 */ +#define GPSCORE_GPIO_F1_RANGE_START 92 +#define GPSCORE_GPIO_F1_RANGE_END 93 +/* SSUS GPIO [11:21] are function 1 */ +#define GPSSUS_GPIO_F1_RANGE_START 11 +#define GPSSUS_GPIO_F1_RANGE_END 21 + +struct soc_gpio_map { + u32 pad_conf0; + u32 pad_conf1; + u32 pad_val; + u32 use_sel : 1; + u32 io_sel : 1; + u32 gp_lvl : 1; + u32 tpe : 1; + u32 tne : 1; + u32 wake_en : 1; + u32 smi : 1; + u32 is_gpio : 1; + u32 sci : 1; +} __attribute__ ((packed)); + +struct soc_gpio_config { + const struct soc_gpio_map *ncore; + const struct soc_gpio_map *score; + const struct soc_gpio_map *ssus; + const u8 (*core_dirq)[GPIO_MAX_DIRQS]; + const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; +}; + +/* Description of GPIO 'bank' ex. {ncore, score. ssus} */ +struct gpio_bank { + const int gpio_count; + const u8* gpio_to_pad; + const int legacy_base; + const unsigned long pad_base; + const u8 has_wake_en :1; + const u8 gpio_f1_range_start; + const u8 gpio_f1_range_end; +}; + +void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap); +/* This function is weak and can be overridden by a mainboard function. */ +struct soc_gpio_config* mainboard_get_gpios(void); + +/* Functions / defines for changing GPIOs in romstage */ +/* SCORE Pad definitions. */ +#define UART_RXD_PAD 82 +#define UART_TXD_PAD 83 +#define PCU_SMB_CLK_PAD 88 +#define PCU_SMB_DATA_PAD 90 +#define SOC_DDI1_VDDEN_PAD 16 + +static inline u32 *ncore_pconf0(int pad_num) +{ + return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16); +} + +static inline void ncore_select_func(int pad, int func) +{ + uint32_t reg; + u32 *pconf0_addr = ncore_pconf0(pad); + + reg = read32(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + write32(pconf0_addr, reg); +} + +static inline u32 *score_pconf0(int pad_num) +{ + return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16); +} + +static inline u32 *ssus_pconf0(int pad_num) +{ + return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16); +} + +static inline void score_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t *pconf0_addr = score_pconf0(pad); + + reg = read32(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + write32(pconf0_addr, reg); +} + +static inline void ssus_select_func(int pad, int func) +{ + uint32_t reg; + uint32_t *pconf0_addr = ssus_pconf0(pad); + + reg = read32(pconf0_addr); + reg &= ~0x7; + reg |= func & 0x7; + write32(pconf0_addr, reg); +} + +/* These functions require that the input pad be configured as an input GPIO */ +static inline int score_get_gpio(int pad) +{ + uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); + + return read32(val_addr) & PAD_VAL_HIGH; +} + +static inline int ssus_get_gpio(int pad) +{ + uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t)); + + return read32(val_addr) & PAD_VAL_HIGH; +} + +static inline void ssus_disable_internal_pull(int pad) +{ + const uint32_t pull_mask = ~(0xf << 7); + write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); +} + +#endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h new file mode 100644 index 0000000..867484b --- /dev/null +++ b/src/soc/intel/braswell/include/soc/iomap.h @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IOMAP_H_ +#define _BAYTRAIL_IOMAP_H_ + + +/* + * Memory Mapped IO bases. + */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MCFG_BASE_SIZE 0x10000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* Temporary Base Address */ +#define TEMP_BASE_ADDRESS 0xfd000000 + +/* + * IO Port bases. + */ +#define ACPI_BASE_ADDRESS 0x0400 +#define ACPI_BASE_SIZE 0x80 + +#define GPIO_BASE_ADDRESS 0x0500 +#define GPIO_BASE_SIZE 0x100 + +#define SMBUS_BASE_ADDRESS 0xefa0 + +#ifndef __ACPI__ +/* Read Top of Low Memory (BMBOUND) */ +uint32_t nc_read_top_of_low_memory(void); +#endif + +#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h new file mode 100644 index 0000000..6705a73 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -0,0 +1,349 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IOSF_H_ +#define _BAYTRAIL_IOSF_H_ + +#include <stdint.h> +#include <soc/pci_devs.h> + +/* + * The Bay Trail SoC has a message network called IOSF Sideband. The access + * routines are through 3 registers in PCI config space of 00:00.0: + * MCR - control register + * MDR - data register + * MCRX - control register extension + * The extension regist is only used for addresses that don't fit into the + * 8 bit register address. + */ + +#ifndef PCI_DEV +#define PCI_DEV(SEGBUS, DEV, FN) ( \ + (((SEGBUS) & 0xFFF) << 20) | \ + (((DEV) & 0x1F) << 15) | \ + (((FN) & 0x07) << 12)) +#endif +#define IOSF_PCI_DEV PCI_DEV(0,SOC_DEV,SOC_FUNC) + +#define MCR_REG 0xd0 +#define IOSF_OPCODE(x) ((x) << 24) +#define IOSF_PORT(x) ((0xff & (x)) << 16) +#define IOSF_REG(x) ((0xff & (x)) << 8) +#define IOSF_REG_UPPER(x) (((~0xff) & (x))) +#define IOSF_BYTE_EN_0 0x10 +#define IOSF_BYTE_EN_1 0x20 +#define IOSF_BYTE_EN_2 0x40 +#define IOSF_BYTE_EN_3 0x80 +#define IOSF_BYTE_EN \ + (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) +#define MDR_REG 0xd4 +#define MCRX_REG 0xd8 + +uint32_t iosf_aunit_read(int reg); +void iosf_aunit_write(int reg, uint32_t val); +uint32_t iosf_cpu_bus_read(int reg); +void iosf_cpu_bus_write(int reg, uint32_t val); +uint32_t iosf_bunit_read(int reg); +void iosf_bunit_write(int reg, uint32_t val); +uint32_t iosf_dunit_read(int reg); +void iosf_dunit_write(int reg, uint32_t val); +/* Some registers are per channel while the globals live in dunit 0 */ +uint32_t iosf_dunit_ch0_read(int reg); +uint32_t iosf_dunit_ch1_read(int reg); +uint32_t iosf_punit_read(int reg); +void iosf_punit_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); +uint32_t iosf_ushphy_read(int reg); +void iosf_ushphy_write(int reg, uint32_t val); +uint32_t iosf_sec_read(int reg); +void iosf_sec_write(int reg, uint32_t val); +uint32_t iosf_port45_read(int reg); +void iosf_port45_write(int reg, uint32_t val); +uint32_t iosf_port46_read(int reg); +void iosf_port46_write(int reg, uint32_t val); +uint32_t iosf_port47_read(int reg); +void iosf_port47_write(int reg, uint32_t val); +uint32_t iosf_port55_read(int reg); +void iosf_port55_write(int reg, uint32_t val); +uint32_t iosf_port58_read(int reg); +void iosf_port58_write(int reg, uint32_t val); +uint32_t iosf_port59_read(int reg); +void iosf_port59_write(int reg, uint32_t val); +uint32_t iosf_port5a_read(int reg); +void iosf_port5a_write(int reg, uint32_t val); +uint32_t iosf_lpss_read(int reg); +void iosf_lpss_write(int reg, uint32_t val); +uint32_t iosf_ccu_read(int reg); +void iosf_ccu_write(int reg, uint32_t val); +uint32_t iosf_score_read(int reg); +void iosf_score_write(int reg, uint32_t val); +uint32_t iosf_scc_read(int reg); +void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_porta2_read(int reg); +void iosf_porta2_write(int reg, uint32_t val); +uint32_t iosf_ssus_read(int reg); +void iosf_ssus_write(int reg, uint32_t val); + +/* IOSF ports. */ +#define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ +#define IOSF_PORT_SYSMEMC 0x01 /* System Memory Controller */ +#define IOSF_PORT_DUNIT_CH0 0x07 /* DUNIT Channel 0 */ +#define IOSF_PORT_CPU_BUS 0x02 /* CPU Bus Interface Controller */ +#define IOSF_PORT_BUNIT 0x03 /* System Memory Arbiter/Bunit */ +#define IOSF_PORT_PMC 0x04 /* Power Management Controller */ +#define IOSF_PORT_GFX 0x06 /* Graphics Adapter */ +#define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ +#define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_SEC 0x44 /* SEC */ +#define IOSF_PORT_0x45 0x45 +#define IOSF_PORT_0x46 0x46 +#define IOSF_PORT_0x47 0x47 +#define IOSF_PORT_SCORE 0x48 /* SCORE */ +#define IOSF_PORT_0x55 0x55 +#define IOSF_PORT_0x58 0x58 +#define IOSF_PORT_0x59 0x59 +#define IOSF_PORT_0x5a 0x5a +#define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ +#define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ +#define IOSF_PORT_0xa2 0xa2 +#define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ +#define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_SSUS 0xa8 /* SUS */ +#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ + +/* Read and write opcodes differ per port. */ +#define IOSF_OP_READ_AUNIT 0x10 +#define IOSF_OP_WRITE_AUNIT (IOSF_OP_READ_AUNIT | 1) +#define IOSF_OP_READ_SYSMEMC 0x10 +#define IOSF_OP_WRITE_SYSMEMC (IOSF_OP_READ_SYSMEMC | 1) +#define IOSF_OP_READ_CPU_BUS 0x10 +#define IOSF_OP_WRITE_CPU_BUS (IOSF_OP_READ_CPU_BUS | 1) +#define IOSF_OP_READ_BUNIT 0x10 +#define IOSF_OP_WRITE_BUNIT (IOSF_OP_READ_BUNIT | 1) +#define IOSF_OP_READ_PMC 0x06 +#define IOSF_OP_WRITE_PMC (IOSF_OP_READ_PMC | 1) +#define IOSF_OP_READ_GFX 0x00 +#define IOSF_OP_WRITE_GFX (IOSF_OP_READ_GFX | 1) +#define IOSF_OP_READ_SYSMEMIO 0x06 +#define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_SEC 0x04 +#define IOSF_OP_WRITE_SEC (IOSF_OP_READ_SEC | 1) +#define IOSF_OP_READ_0x45 0x06 +#define IOSF_OP_WRITE_0x45 (IOSF_OP_READ_0x45 | 1) +#define IOSF_OP_READ_0x46 0x06 +#define IOSF_OP_WRITE_0x46 (IOSF_OP_READ_0x46 | 1) +#define IOSF_OP_READ_0x47 0x06 +#define IOSF_OP_WRITE_0x47 (IOSF_OP_READ_0x47 | 1) +#define IOSF_OP_READ_SCORE 0x06 +#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) +#define IOSF_OP_READ_0x55 0x04 +#define IOSF_OP_WRITE_0x55 (IOSF_OP_READ_0x55 | 1) +#define IOSF_OP_READ_0x58 0x06 +#define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) +#define IOSF_OP_READ_0x59 0x06 +#define IOSF_OP_WRITE_0x59 (IOSF_OP_READ_0x59 | 1) +#define IOSF_OP_READ_0x5a 0x04 +#define IOSF_OP_WRITE_0x5a (IOSF_OP_READ_0x5a | 1) +#define IOSF_OP_READ_USHPHY 0x06 +#define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_SCC 0x06 +#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) +#define IOSF_OP_READ_LPSS 0x06 +#define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) +#define IOSF_OP_READ_0xa2 0x06 +#define IOSF_OP_WRITE_0xa2 (IOSF_OP_READ_0xa2 | 1) +#define IOSF_OP_READ_SATAPHY 0x00 +#define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) +#define IOSF_OP_READ_PCIEPHY 0x00 +#define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) +#define IOSF_OP_READ_SSUS 0x10 +#define IOSF_OP_WRITE_SSUS (IOSF_OP_READ_SSUS | 1) +#define IOSF_OP_READ_CCU 0x06 +#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) + +/* + * BUNIT Registers. + */ + +#define BNOCACHE 0x23 +/* BMBOUND has a 128MiB granularity. Highest address is 0xf8000000. */ +#define BUNIT_BMBOUND 0x25 +/* BMBOUND_HI describes the available ram above 4GiB. It has a + * 256MiB granularity. Physical address bits 35:28 are compared with 31:24 + * bits in the BMBOUND_HI register. Also note that since BMBOUND has 128MiB + * granularity care needs to be taken with the e820 map to account for a hole + * in the ram. */ +#define BUNIT_BMBOUND_HI 0x26 +#define BUNIT_MMCONF_REG 0x27 +/* The SMMRR registers define the SMM region in MiB granularity. */ +#define BUNIT_SMRCP 0x2b +#define BUNIT_SMRRAC 0x2c +#define BUNIT_SMRWAC 0x2d +#define BUNIT_SMRRL 0x2e +#define BUNIT_SMRRH 0x2f +# define BUNIT_SMRR_ENABLE (1 << 31) + +/* SA ID bits. */ +#define SAI_IA_UNTRUSTED (1 << 0) +#define SAI_IA_SMM (1 << 2) +#define SAI_IA_BOOT (1 << 4) + +/* + * DUNIT Registers. + */ + +#define DRP 0x00 +# define DRP_DIMM0_RANK0_EN (0x01 << 0) +# define DRP_DIMM0_RANK1_EN (0x01 << 1) +# define DRP_DIMM1_RANK0_EN (0x01 << 2) +# define DRP_DIMM1_RANK1_EN (0x01 << 3) +# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \ + DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN) +#define DTR0 0x01 +# define DTR0_SPEED_MASK 0x03 +# define DTR0_SPEED_800 0x00 +# define DTR0_SPEED_1066 0x01 +# define DTR0_SPEED_1333 0x02 +# define DTR0_SPEED_1600 0x03 + +/* + * PUNIT Registers + */ +#define SB_BIOS_CONFIG 0x06 +# define SB_BIOS_CONFIG_ECC_EN (1 << 31) +# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) +# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) +# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) +# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) +# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) +# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) +# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) +# define SB_BIOS_CONFIG_PS2_EN_VNN (1 << 3) +# define SB_BIOS_CONFIG_PS2_EN_VCC (1 << 2) +# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) +# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) +#define BIOS_RESET_CPL 0x05 +# define BIOS_RESET_CPL_ALL_DONE (1 << 1) +# define BIOS_RESET_CPL_RESET_DONE (1 << 0) +#define PUNIT_PWRGT_CONTROL 0x60 +#define PUNIT_PWRGT_STATUS 0x61 +#define PUNIT_GPU_EC_VIRUS 0xd2 + +#define PUNIT_SOC_POWER_BUDGET 0x02 +#define PUNIT_SOC_ENERGY_CREDIT 0x03 +#define PUNIT_PTMC 0x80 +#define PUNIT_GFXT 0x88 +#define PUNIT_VEDT 0x89 +#define PUNIT_ISPT 0x8c +#define PUNIT_PTPS 0xb2 +#define PUNIT_TE_AUX0 0xb5 +#define PUNIT_TE_AUX1 0xb6 +#define PUNIT_TE_AUX2 0xb7 +#define PUNIT_TE_AUX3 0xb8 +#define PUNIT_TTE_VRIccMax 0xb9 +#define PUNIT_TTE_VRHot 0xba +#define PUNIT_TTE_XXPROCHOT 0xbb +#define PUNIT_TTE_SLM0 0xbc +#define PUNIT_TTE_SLM1 0xbd +#define PUNIT_TTE_SWT 0xbf + +/* + * LPSS Registers + */ +#define LPSS_SIO_DMA1_CTL 0x280 +#define LPSS_I2C1_CTL 0x288 +#define LPSS_I2C2_CTL 0x290 +#define LPSS_I2C3_CTL 0x298 +#define LPSS_I2C4_CTL 0x2a0 +#define LPSS_I2C5_CTL 0x2a8 +#define LPSS_I2C6_CTL 0x2b0 +#define LPSS_I2C7_CTL 0x2b8 +#define LPSS_SIO_DMA2_CTL 0x240 +#define LPSS_PWM1_CTL 0x248 +#define LPSS_PWM2_CTL 0x250 +#define LPSS_HSUART1_CTL 0x258 +#define LPSS_HSUART2_CTL 0x260 +#define LPSS_SPI_CTL 0x268 +# define LPSS_CTL_ACPI_INT_EN (1 << 21) +# define LPSS_CTL_PCI_CFG_DIS (1 << 20) +# define LPSS_CTL_SNOOP (1 << 18) +# define LPSS_CTL_NOSNOOP (1 << 19) +# define LPSS_CTL_PM_CAP_PRSNT (1 << 1) + +/* + * SCC Registers + */ +#define SCC_SD_CTL 0x504 +#define SCC_SDIO_CTL 0x508 +#define SCC_MMC_CTL 0x50c +# define SCC_CTL_PCI_CFG_DIS (1 << 0) +# define SCC_CTL_ACPI_INT_EN (1 << 1) + +/* + * CCU Registers + */ + +#define PLT_CLK_CTRL_0 0x3c +#define PLT_CLK_CTRL_1 0x40 +#define PLT_CLK_CTRL_2 0x44 +#define PLT_CLK_CTRL_3 0x48 +#define PLT_CLK_CTRL_4 0x4c +#define PLT_CLK_CTRL_5 0x50 +# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) +# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) +# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) + +/* + * USBPHY Registers + */ +#define USBPHY_COMPBG 0x7f04 +#define USBPHY_PER_PORT_LANE0 0x4100 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP0 0x4122 +#define USBPHY_PER_PORT_LANE1 0x4200 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP1 0x4222 +#define USBPHY_PER_PORT_LANE2 0x4300 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP2 0x4322 +#define USBPHY_PER_PORT_LANE3 0x4400 +#define USBPHY_PER_PORT_RCOMP_HS_PULLUP3 0x4422 + +/* + * USHPHY Registers + */ +#define USHPHY_CDN_PLL_CONTROL 0x03c0 +#define USHPHY_CDN_VCO_START_CAL_POINT 0x0054 +#define USHPHY_CCDRLF 0x8040 +#define USHPHY_PEAKING_AMP_CONFIG_DIAG 0x80a8 +#define USHPHY_OFFSET_COR_CONFIG_DIAG 0x80b0 +#define USHPHY_VGA_GAIN_CONFIG_DIAG 0x8080 +#define USHPHY_REE_DAC_CONTROL 0x80b8 +#define USHPHY_CDN_U1_POWER_STATE_DEF 0x0000 + +/* + * LPE Registers + */ +#define LPE_PCICFGCTR1 0x0500 +# define LPE_PCICFGCTR1_PCI_CFG_DIS (1 << 0) +# define LPE_PCICFGCTR1_ACPI_INT_EN (1 << 1) + +#endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h new file mode 100644 index 0000000..34b3f7d --- /dev/null +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_IRQ_H_ +#define _BAYTRAIL_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 +/* The below IRQs are for when devices are in ACPI mode. Active low. */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +#define GPIO_NC_IRQ 48 +#define GPIO_SC_IRQ 49 +#define GPIO_SUS_IRQ 50 +/* GPIO direct / dedicated IRQs. */ +#define GPIO_S0_DED_IRQ_0 51 +#define GPIO_S0_DED_IRQ_1 52 +#define GPIO_S0_DED_IRQ_2 53 +#define GPIO_S0_DED_IRQ_3 54 +#define GPIO_S0_DED_IRQ_4 55 +#define GPIO_S0_DED_IRQ_5 56 +#define GPIO_S0_DED_IRQ_6 57 +#define GPIO_S0_DED_IRQ_7 58 +#define GPIO_S0_DED_IRQ_8 59 +#define GPIO_S0_DED_IRQ_9 60 +#define GPIO_S0_DED_IRQ_10 61 +#define GPIO_S0_DED_IRQ_11 62 +#define GPIO_S0_DED_IRQ_12 63 +#define GPIO_S0_DED_IRQ_13 64 +#define GPIO_S0_DED_IRQ_14 65 +#define GPIO_S0_DED_IRQ_15 66 +#define GPIO_S5_DED_IRQ_0 67 +#define GPIO_S5_DED_IRQ_1 68 +#define GPIO_S5_DED_IRQ_2 69 +#define GPIO_S5_DED_IRQ_3 70 +#define GPIO_S5_DED_IRQ_4 71 +#define GPIO_S5_DED_IRQ_5 72 +#define GPIO_S5_DED_IRQ_6 73 +#define GPIO_S5_DED_IRQ_7 74 +#define GPIO_S5_DED_IRQ_8 75 +#define GPIO_S5_DED_IRQ_9 76 +#define GPIO_S5_DED_IRQ_10 77 +#define GPIO_S5_DED_IRQ_11 78 +#define GPIO_S5_DED_IRQ_12 79 +#define GPIO_S5_DED_IRQ_13 80 +#define GPIO_S5_DED_IRQ_14 81 +#define GPIO_S5_DED_IRQ_15 82 +/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) + +/* PIC IRQ settings. */ +#define PIRQ_PIC_IRQDISABLE 0x0 +#define PIRQ_PIC_IRQ3 0x3 +#define PIRQ_PIC_IRQ4 0x4 +#define PIRQ_PIC_IRQ5 0x5 +#define PIRQ_PIC_IRQ6 0x6 +#define PIRQ_PIC_IRQ7 0x7 +#define PIRQ_PIC_IRQ9 0x9 +#define PIRQ_PIC_IRQ10 0xa +#define PIRQ_PIC_IRQ11 0xb +#define PIRQ_PIC_IRQ12 0xc +#define PIRQ_PIC_IRQ14 0xe +#define PIRQ_PIC_IRQ15 0xf + +/* Overloaded term, but these values determine the per device route. */ +#define PIRQA 0 +#define PIRQB 1 +#define PIRQC 2 +#define PIRQD 3 +#define PIRQE 4 +#define PIRQF 5 +#define PIRQG 6 +#define PIRQH 7 + +/* These registers live behind the ILB_BASE_ADDRESS */ +#define ACTL 0x00 +# define SCIS_MASK 0x07 +# define SCIS_IRQ9 0x00 +# define SCIS_IRQ10 0x01 +# define SCIS_IRQ11 0x02 +# define SCIS_IRQ20 0x04 +# define SCIS_IRQ21 0x05 +# define SCIS_IRQ22 0x06 +# define SCIS_IRQ23 0x07 + +/* In each mainboard directory there should exist a header file irqroute.h that + * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which + * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) +#include <stdint.h> + +#define NUM_IR_DEVS 32 +#define NUM_PIRQS 8 + +struct baytrail_irq_route { + /* Per device configuration. */ + uint16_t pcidev[NUM_IR_DEVS]; + /* Route path for each internal PIRQx in PIC mode. */ + uint8_t pic[NUM_PIRQS]; +}; + +extern const struct baytrail_irq_route global_baytrail_irq_route; + +#define DEFINE_IRQ_ROUTES \ + const struct baytrail_irq_route global_baytrail_irq_route = { \ + .pcidev = { PCI_DEV_PIRQ_ROUTES, }, \ + .pic = { PIRQ_PIC_ROUTES, }, \ + } + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + [dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \ + ((PIRQ ## b_) << 4) | ((PIRQ ## a_) << 0) + +#define PIRQ_PIC(pirq_, pic_irq_) \ + [PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_ + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BAYTRAIL_IRQ_H_ */ diff --git a/src/soc/intel/braswell/include/soc/lpc.h b/src/soc/intel/braswell/include/soc/lpc.h new file mode 100644 index 0000000..2f6256c --- /dev/null +++ b/src/soc/intel/braswell/include/soc/lpc.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_LPC_H_ +#define _BAYTRAIL_LPC_H_ + +/* PCI config registers in LPC bridge. */ +#define REVID 0x08 +#define ABASE 0x40 +#define PBASE 0x44 +#define GBASE 0x48 +#define IOBASE 0x4c +#define IBASE 0x50 +#define SBASE 0x54 +#define MPBASE 0x58 +#define PUBASE 0x5c +#define UART_CONT 0x80 +#define RCBA 0xf0 + + +#define RID_A_STEPPING_START 1 +#define RID_B_STEPPING_START 5 +#define RID_C_STEPPING_START 0xe +enum baytrail_stepping { + STEP_A0, + STEP_A1, + STEP_B0, + STEP_B1, + STEP_B2, + STEP_B3, + STEP_C0, +}; + +/* Registers behind the RCBA_BASE_ADDRESS bar. */ +#define GCS 0x00 +# define BILD (1 << 0) + +#endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/braswell/include/soc/mrc_wrapper.h b/src/soc/intel/braswell/include/soc/mrc_wrapper.h new file mode 100644 index 0000000..355dce0 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/mrc_wrapper.h @@ -0,0 +1,107 @@ +/* + * MRC wrapper definitions + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _MRC_WRAPPER_H_ +#define _MRC_WRAPPER_H_ + +#define MRC_PARAMS_VER 5 + +#define NUM_CHANNELS 2 + +/* Provide generic x86 calling conventions. */ +#define ABI_X86 __attribute((regparm(0))) + +enum { + DRAM_INFO_SPD_SMBUS, /* Use the typical SPD smbus access. */ + DRAM_INFO_SPD_MEM, /* SPD info in memory. */ + DRAM_INFO_DETAILED, /* Timing info not in SPD format. */ +}; + +enum dram_type { + DRAM_DDR3, + DRAM_DDR3L, + DRAM_LPDDR3, +}; + +/* Errors returned by the MRC wrapper. */ +enum mrc_wrapper_error { + INVALID_VER = -1, + INVALID_DRAM_TYPE = -2, + INVALID_SLEEP_MODE = -3, + PLATFORM_SETTINGS_FAIL = -4, + DIMM_DETECTION_FAILURE = -5, + MEMORY_CONFIG_FAILURE = -6, + INVALID_CPU_ODT_SETTING = -7, + INVALID_DRAM_ODT_SETTING = -8, +}; + +struct mrc_mainboard_params { + int dram_type; + int dram_info_location; /* DRAM_INFO_* */ + int dram_is_slotted; /* mobo has DRAM slots. */ + /* + * The below ODT settings are only honored when !dram_is_slotted. + * Additionally, weaker_odt_settings being non-zero causes + * cpu_odt_value to not be honored as weaker_odt_settings have a + * special training path. + */ + int weaker_odt_settings; + /* Allowed settings: 60, 80, 100, 120, and 150. */ + int cpu_odt_value; + /* Allowed settings: 60 and 120. */ + int dram_odt_value; + int spd_addrs[NUM_CHANNELS]; + void *dram_data[NUM_CHANNELS]; /* SPD or Timing specific data. */ +} __attribute__((packed)); + +struct mrc_params { + /* Mainboard Inputs */ + int version; + + struct mrc_mainboard_params mainboard; + + void ABI_X86 (*console_out)(unsigned char byte); + + int prev_sleep_state; + + int saved_data_size; + const void *saved_data; + + int txe_size_mb; /* TXE memory size in megabytes. */ + int rmt_enabled; /* Enable RMT training + prints. */ + int io_hole_mb; /* Size of IO hole in MiB. */ + + /* Outputs */ + void *txe_base_address; + int data_to_save_size; + void *data_to_save; +} __attribute__((packed)); + +/* Call into wrapper. */ +typedef int ABI_X86 (*mrc_wrapper_entry_t)(struct mrc_params *); + +#endif /* _MRC_WRAPPER_H_ */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h new file mode 100644 index 0000000..47b9543 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_MSR_H_ +#define _BAYTRAIL_MSR_H_ + +#define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd +#define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define SINGLE_PCTL (1 << 11) +#define MSR_POWER_MISC 0x120 +#define ENABLE_ULFM_AUTOCM_MASK (1 << 2) +#define ENABLE_INDP_AUTOCM_MASK (1 << 3) +#define MSR_IA32_PERF_CTL 0x199 +#define MSR_IA32_MISC_ENABLES 0x1a0 +#define MSR_POWER_CTL 0x1fc +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610 +#define MSR_PP1_POWER_LIMIT 0x638 +#define MSR_IACORE_RATIOS 0x66a +#define MSR_IACORE_TURBO_RATIOS 0x66c +#define MSR_IACORE_VIDS 0x66b +#define MSR_IACORE_TURBO_VIDS 0x66d +#define MSR_PKG_TURBO_CFG1 0x670 +#define MSR_CPU_TURBO_WKLD_CFG1 0x671 +#define MSR_CPU_TURBO_WKLD_CFG2 0x672 +#define MSR_CPU_THERM_CFG1 0x673 +#define MSR_CPU_THERM_CFG2 0x674 +#define MSR_CPU_THERM_SENS_CFG 0x675 + +/* Read BCLK from MSR */ +unsigned bus_freq_khz(void); + +#endif /* _BAYTRAIL_MSR_H_ */ diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h new file mode 100644 index 0000000..1ba30d5 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/nvs.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_NVS_H_ +#define _BAYTRAIL_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> +#include <soc/device_nvs.h> + +typedef struct { + /* Miscellaneous */ + u16 osys; /* 0x00 - Operating System */ + u8 smif; /* 0x02 - SMI function call ("TRAP") */ + u8 prm0; /* 0x03 - SMI function call parameter */ + u8 prm1; /* 0x04 - SMI function call parameter */ + u8 scif; /* 0x05 - SCI function call (via _L00) */ + u8 prm2; /* 0x06 - SCI function call parameter */ + u8 prm3; /* 0x07 - SCI function call parameter */ + u8 lckf; /* 0x08 - Global Lock function for EC */ + u8 prm4; /* 0x09 - Lock function parameter */ + u8 prm5; /* 0x0a - Lock function parameter */ + u32 p80d; /* 0x0b - Debug port (IO 0x80) value */ + u8 lids; /* 0x0f - LID state (open = 1) */ + u8 pwrs; /* 0x10 - Power state (AC = 1) */ + u8 pcnt; /* 0x11 - Processor Count */ + u8 tpmp; /* 0x12 - TPM Present and Enabled */ + u8 tlvl; /* 0x13 - Throttle Level */ + u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ + u32 pm1i; /* 0x15 - System Wake Source - PM1 Index */ + u8 rsvd1[7]; + + /* Device Config */ + u8 s5u0; /* 0x20 - Enable USB0 in S5 */ + u8 s5u1; /* 0x21 - Enable USB1 in S5 */ + u8 s3u0; /* 0x22 - Enable USB0 in S3 */ + u8 s3u1; /* 0x23 - Enable USB1 in S3 */ + u8 tact; /* 0x24 - Thermal Active trip point */ + u8 tpsv; /* 0x25 - Thermal Passive trip point */ + u8 tcrt; /* 0x26 - Thermal Critical trip point */ + u8 dpte; /* 0x27 - Enable DPTF */ + u8 rsvd2[8]; + + /* Base Addresses */ + u32 obsolete_cmem; /* 0x30 - CBMEM TOC */ + u32 tolm; /* 0x34 - Top of Low Memory */ + u32 cbmc; /* 0x38 - coreboot memconsole */ + u8 rsvd3[196]; + + /* ChromeOS specific (0x100-0xfff)*/ + chromeos_acpi_t chromeos; + + /* Baytrail LPSS (0x1000) */ + device_nvs_t dev; +} __attribute__((packed)) global_nvs_t; + +#ifdef __SMM__ +/* Used in SMM to find the ACPI GNVS address */ +global_nvs_t *smm_get_gnvs(void); +#endif + +#endif /* _BAYTRAIL_NVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pattrs.h b/src/soc/intel/braswell/include/soc/pattrs.h new file mode 100644 index 0000000..81df73e --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pattrs.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PATTRS_H_ +#define _PATTRS_H_ + +#include <stdint.h> +#include <cpu/x86/msr.h> + +enum { + IACORE_MIN, + IACORE_LFM, + IACORE_MAX, + IACORE_TURBO, + IACORE_END +}; + +/* The pattrs structure is a common place to stash pertinent information + * about the processor or platform. Instead of going to the source (msrs, cpuid) + * every time an attribute is needed use the pattrs structure. + */ +struct pattrs { + msr_t platform_id; + msr_t platform_info; + int iacore_ratios[IACORE_END]; + int iacore_vids[IACORE_END]; + uint32_t cpuid; + int revid; + int stepping; + const void *microcode_patch; + int address_bits; + int num_cpus; + unsigned bclk_khz; +}; + +/* This is just to hide the abstraction w/o relying on how the underlying + * storage is allocated. */ +#define PATTRS_GLOB_NAME __global_pattrs +#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME +extern DEFINE_PATTRS; + +static inline const struct pattrs *pattrs_get(void) +{ + return &PATTRS_GLOB_NAME; +} + + +#endif /* _PATTRS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pci_devs.h b/src/soc/intel/braswell/include/soc/pci_devs.h new file mode 100644 index 0000000..b3fdce2 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pci_devs.h @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PCI_DEVS_H_ +#define _BAYTRAIL_PCI_DEVS_H_ + +/* All these devices live on bus 0 with the associated device and function */ + +/* SoC transaction router */ +#define SOC_DEV 0x0 +#define SOC_FUNC 0 +# define SOC_DEVID 0x0f00 + +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +# define GFX_DEVID 0x0f31 + +/* SDIO Port */ +#define SDIO_DEV 0x11 +#define SDIO_FUNC 0 +# define SDIO_DEVID 0x0f15 + +/* SD Port */ +#define SD_DEV 0x12 +#define SD_FUNC 0 +# define SD_DEVID 0x0f16 + +/* SATA */ +#define SATA_DEV 0x13 +#define SATA_FUNC 0 +#define IDE1_DEVID 0x0f20 +#define IDE2_DEVID 0x0f21 +#define AHCI1_DEVID 0x0f22 +#define AHCI2_DEVID 0x0f23 + +/* xHCI */ +#define XHCI_DEV 0x14 +#define XHCI_FUNC 0 +# define XHCI_DEVID 0x0f35 + +/* LPE Audio */ +#define LPE_DEV 0x15 +#define LPE_FUNC 0 +# define LPE_DEVID 0x0f28 + +/* MMC Port */ +#define MMC_DEV 0x17 +#define MMC_FUNC 0 +# define MMC_DEVID 0x0f50 + +/* Serial IO 1 */ +#define SIO1_DEV 0x18 +# define SIO_DMA1_DEV SIO1_DEV +# define SIO_DMA1_FUNC 0 +# define SIO_DMA1_DEVID 0x0f40 +# define I2C1_DEV SIO1_DEV +# define I2C1_FUNC 1 +# define I2C1_DEVID 0x0f41 +# define I2C2_DEV SIO1_DEV +# define I2C2_FUNC 2 +# define I2C2_DEVID 0x0f42 +# define I2C3_DEV SIO1_DEV +# define I2C3_FUNC 3 +# define I2C3_DEVID 0x0f43 +# define I2C4_DEV SIO1_DEV +# define I2C4_FUNC 4 +# define I2C4_DEVID 0x0f44 +# define I2C5_DEV SIO1_DEV +# define I2C5_FUNC 5 +# define I2C5_DEVID 0x0f45 +# define I2C6_DEV SIO1_DEV +# define I2C6_FUNC 6 +# define I2C6_DEVID 0x0f46 +# define I2C7_DEV SIO1_DEV +# define I2C7_FUNC 7 +# define I2C7_DEVID 0x0f47 + +/* Trusted Execution Engine */ +#define TXE_DEV 0x1a +#define TXE_FUNC 0 +# define TXE_DEVID 0x0f18 + +/* HD Audio */ +#define HDA_DEV 0x1b +#define HDA_FUNC 0 +# define HDA_DEVID 0x0f04 + +/* PCIe Ports */ +#define PCIE_DEV 0x1c +# define PCIE_PORT1_DEV PCIE_DEV +# define PCIE_PORT1_FUNC 0 +# define PCIE_PORT1_DEVID 0x0f48 +# define PCIE_PORT2_DEV PCIE_DEV +# define PCIE_PORT2_FUNC 1 +# define PCIE_PORT2_DEVID 0x0f4a +# define PCIE_PORT3_DEV PCIE_DEV +# define PCIE_PORT3_FUNC 2 +# define PCIE_PORT3_DEVID 0x0f4c +# define PCIE_PORT4_DEV PCIE_DEV +# define PCIE_PORT4_FUNC 3 +# define PCIE_PORT4_DEVID 0x0f4e + +/* EHCI */ +#define EHCI_DEV 0x1d +#define EHCI_FUNC 0 +# define EHCI_DEVID 0x0f34 + +/* Serial IO 2 */ +#define SIO2_DEV 0x1e +# define SIO_DMA2_DEV SIO2_DEV +# define SIO_DMA2_FUNC 0 +# define SIO_DMA2_DEVID 0x0f06 +# define PWM1_DEV SIO2_DEV +# define PWM1_FUNC 1 +# define PWM1_DEVID 0x0f08 +# define PWM2_DEV SIO2_DEV +# define PWM2_FUNC 2 +# define PWM2_DEVID 0x0f09 +# define HSUART1_DEV SIO2_DEV +# define HSUART1_FUNC 3 +# define HSUART1_DEVID 0x0f0a +# define HSUART2_DEV SIO2_DEV +# define HSUART2_FUNC 4 +# define HSUART2_DEVID 0x0f0c +# define SPI_DEV SIO2_DEV +# define SPI_FUNC 5 +# define SPI_DEVID 0xf0e + +/* Platform Controller Unit */ +#define PCU_DEV 0x1f +# define LPC_DEV PCU_DEV +# define LPC_FUNC 0 +# define LPC_DEVID 0x0f1c +# define SMBUS_DEV PCU_DEV +# define SMBUS_FUNC 3 +# define SMBUS_DEVID 0x0f12 + +#endif /* _BAYTRAIL_PCI_DEVS_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pcie.h b/src/soc/intel/braswell/include/soc/pcie.h new file mode 100644 index 0000000..92ca3c8 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pcie.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PCIE_H_ +#define _BAYTRAIL_PCIE_H_ + +/* PCIe root port config space registers. */ +#define XCAP 0x40 +# define SI (1 << 24) +#define DCAP 0x44 +# define MPS_MASK 0x7 +#define DCTL_DSTS 0x48 +# define URE (1 << 3) +# define FEE (1 << 2) +# define NFE (1 << 1) +# define CEE (1 << 0) +#define LCAP 0x4c +# define L1EXIT_SHIFT 15 +# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT) +#define LCTL 0x50 +# define CCC (1 << 6) +# define RL (1 << 5) +# define LD (1 << 4) +#define LSTS 0x52 +#define SLCAP 0x54 +# define SLN_SHIFT 19 +# define SLS_SHIFT 15 +# define SLV_SHIFT 7 +# define HPC (1 << 6) +# define HPS (1 << 5) +#define SLCTL_SLSTS 0x58 +# define PDS (1 << 22) +#define DCAP2 0x64 +# define OBFFS (0x3 << 18) +# define LTRMS (1 << 11) +#define DSTS2 0x68 +# define OBFFEN (3 << 13) +# define LTRME (1 << 10) +# define CTD (1 << 4) +#define CHCFG 0xd0 +# define UPSD (1 << 24) +# define UNRS (1 << 15) +# define UPRS (1 << 14) +#define MPC2 0xd4 +# define IPF (1 << 11) +# define LSTP (1 << 6) +# define EOIFD (1 << 1) +#define MPC 0xd8 +# define CCEL_SHIFT 15 +# define CCEL_MASK (0x7 << CCEL_SHIFT) +#define RPPGEN 0xe0 +# define RPSCGEN (1 << 15) +# define LCLKREQEN (1 << 13) +# define BBCLKREQEN (1 << 12) +# define SRDLCGEN (1 << 11) +# define SRDBCGEN (1 << 10) +# define RPDLCGEN (1 << 9) +# define RPDBCGEN (1 << 8) +#define PWRCTL 0xe8 +# define RPL1SQPOL (1 << 1) +# define RPDTSQPOL (1 << 0) +#define PHYCTL2_IOSFBCTL 0xf4 +# define PLL_OFF_EN (1 << 8) +# define TDFT (3 << 14) +# define TXCFGCHWAIT (3 << 12) +# define SIID (3 << 26) +#define STRPFUSECFG 0xfc +# define LANECFG_SHIFT 14 +# define LANECFG_MASK (0x3 << LANECFG_SHIFT) +#define AERCH 0x100 +#define NFTS 0x314 +#define L0SC 0x318 +#define CFG2 0x320 +# define CSREN (1 << 22) +# define LATGC_SHIFT 6 +# define LATGC_MASK (0x7 << LATGC_SHIFT) +#define PCIEDBG 0x324 +# define SPCE (1 << 5) +#define PCIESTS1 0x328 +#define PCIEALC 0x338 +#define RTP 0x33c +#define PHYCTL4 0x408 +# define SQDIS (1 << 27) + +#define PCIE_ROOT_PORT_COUNT 4 +#endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/pmc.h b/src/soc/intel/braswell/include/soc/pmc.h new file mode 100644 index 0000000..1af7ab8 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/pmc.h @@ -0,0 +1,303 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PMC_H_ +#define _BAYTRAIL_PMC_H_ + + +#define IOCOM1 0x3f8 + +/* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x00 +# define PMC_WDT_STS (1 << 15) +# define SEC_GBLRST_STS (1 << 7) +# define SEC_WDT_STS (1 << 6) +# define WOL_OVR_WK_STS (1 << 5) +# define PMC_WAKE_STS (1 << 4) +#define PMC_CFG 0x08 +# define SPS (1 << 5) +# define NO_REBOOT (1 << 4) +# define SX_ENT_TO_EN (1 << 3) +# define TIMING_T581_SHIFT (0) +# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) +# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) +# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) +# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) +# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) +#define VLV_PM_STS 0x0c +# define PMC_MSG_FULL_STS (1 << 24) +# define PMC_MSG_4_FULL_STS (1 << 23) +# define PMC_MSG_3_FULL_STS (1 << 22) +# define PMC_MSG_2_FULL_STS (1 << 21) +# define PMC_MSG_1_FULL_STS (1 << 20) +# define CODE_REQ (1 << 8) +# define HPR_ENT_TO (1 << 2) +# define SX_ENT_TO (1 << 1) +#define GEN_PMCON1 0x20 +# define UART_EN (1 << 24) +# define DISB (1 << 23) +# define MEM_SR (1 << 21) +# define SRS (1 << 20) +# define CTS (1 << 19) +# define MS4V (1 << 18) +# define PWR_FLR (1 << 16) +# define PME_B0_S5_DIS (1 << 15) +# define SUS_PWR_FLR (1 << 14) +# define WOL_EN_OVRD (1 << 13) +# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +# define GEN_RST_STS (1 << 9) +# define RPS (1 << 2) +# define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +# define SLPSX_STR_POL_LOCK (1 << 18) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) +#define ETR 0x48 +# define CF9LOCK (1 << 31) +# define LTR_DEF (1 << 22) +# define IGNORE_HPET (1 << 21) +# define CF9GR (1 << 20) +# define CWORWRE (1 << 18) +#define FUNC_DIS 0x34 +# define SIO_DMA2_DIS (1 << 0) +# define PWM1_DIS (1 << 1) +# define PWM2_DIS (1 << 2) +# define HSUART1_DIS (1 << 3) +# define HSUART2_DIS (1 << 4) +# define SPI_DIS (1 << 5) +# define SDIO_DIS (1 << 9) +# define SD_DIS (1 << 10) +# define MMC_DIS (1 << 11) +# define HDA_DIS (1 << 12) +# define LPE_DIS (1 << 13) +# define OTG_DIS (1 << 14) +# define XHCI_DIS (1 << 15) +# define SATA_DIS (1 << 17) +# define EHCI_DIS (1 << 18) +# define TXE_DIS (1 << 19) +# define PCIE_PORT1_DIS (1 << 20) +# define PCIE_PORT2_DIS (1 << 21) +# define PCIE_PORT3_DIS (1 << 22) +# define PCIE_PORT4_DIS (1 << 23) +# define SIO_DMA1_DIS (1 << 24) +# define I2C1_DIS (1 << 25) +# define I2C2_DIS (1 << 26) +# define I2C3_DIS (1 << 27) +# define I2C4_DIS (1 << 28) +# define I2C5_DIS (1 << 29) +# define I2C6_DIS (1 << 30) +# define I2C7_DIS (1 << 31) +#define FUNC_DIS2 0x38 +# define USH_SS_PHY_DIS (1 << 2) +# define OTG_SS_PHY_DIS (1 << 1) +# define SMBUS_DIS (1 << 0) +#define GPIO_ROUT 0x58 +# define ROUTE_MASK 3 +# define ROUTE_NONE 0 +# define ROUTE_SMI 1 +# define ROUTE_SCI 2 +#define PLT_CLK_CTL_0 0x60 +#define PLT_CLK_CTL_1 0x64 +#define PLT_CLK_CTL_2 0x68 +#define PLT_CLK_CTL_3 0x6c +#define PLT_CLK_CTL_4 0x70 +#define PLT_CLK_CTL_5 0x74 +# define CLK_FREQ_25MHZ (0x0 << 2) +# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_CTL_D3_LPE (0x0 << 0) +# define CLK_CTL_ON (0x1 << 0) +# define CLK_CTL_OFF (0x2 << 0) +#define PME_STS 0xc0 +#define GPE_LEVEL_EDGE 0xc4 +# define GPE_EDGE 0 +# define GPE_LEVEL 1 +#define GPE_POLARITY 0xc8 +# define GPE_ACTIVE_HIGH 1 +# define GPE_ACTIVE_LOW 0 +#define LOCK 0xcc + +/* IO Mapped registers behind ACPI_BASE_ADDRESS */ +#define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define USB_STS (1 << 13) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define TMROF_STS (1 << 0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define USB_WAKE_EN (1 << 13) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) +#define PM1_CNT 0x04 +#define SLP_EN (1 << 13) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) +#define PM1_TMR 0x08 +#define GPE0_STS 0x20 +#define CORE_GPIO_STS7 (1 << 31) +#define CORE_GPIO_STS6 (1 << 30) +#define CORE_GPIO_STS5 (1 << 29) +#define CORE_GPIO_STS4 (1 << 28) +#define CORE_GPIO_STS3 (1 << 27) +#define CORE_GPIO_STS2 (1 << 26) +#define CORE_GPIO_STS1 (1 << 25) +#define CORE_GPIO_STS0 (1 << 24) +#define SUS_GPIO_STS7 (1 << 23) +#define SUS_GPIO_STS6 (1 << 22) +#define SUS_GPIO_STS5 (1 << 21) +#define SUS_GPIO_STS4 (1 << 20) +#define SUS_GPIO_STS3 (1 << 19) +#define SUS_GPIO_STS2 (1 << 18) +#define SUS_GPIO_STS1 (1 << 17) +#define SUS_GPIO_STS0 (1 << 16) +#define PME_B0_STS (1 << 13) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define PCIE_WAKE3_STS (1 << 8) +#define PCIE_WAKE2_STS (1 << 7) +#define PCIE_WAKE1_STS (1 << 6) +#define GUNIT_SCI_STS (1 << 5) +#define PUNIT_SCI_STS (1 << 4) +#define PCIE_WAKE0_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define GPE0_EN 0x28 +#define CORE_GPIO_EN7 (1 << 31) +#define CORE_GPIO_EN6 (1 << 30) +#define CORE_GPIO_EN5 (1 << 29) +#define CORE_GPIO_EN4 (1 << 28) +#define CORE_GPIO_EN3 (1 << 27) +#define CORE_GPIO_EN2 (1 << 26) +#define CORE_GPIO_EN1 (1 << 25) +#define CORE_GPIO_EN0 (1 << 24) +#define SUS_GPIO_EN7_BIT 23 +#define SUS_GPIO_EN7 (1 << SUS_GPIO_EN7_BIT) +#define SUS_GPIO_EN6_BIT 22 +#define SUS_GPIO_EN6 (1 << SUS_GPIO_EN6_BIT) +#define SUS_GPIO_EN5_BIT 21 +#define SUS_GPIO_EN5 (1 << SUS_GPIO_EN5_BIT) +#define SUS_GPIO_EN4_BIT 20 +#define SUS_GPIO_EN4 (1 << SUS_GPIO_EN4_BIT) +#define SUS_GPIO_EN3_BIT 19 +#define SUS_GPIO_EN3 (1 << SUS_GPIO_EN3_BIT) +#define SUS_GPIO_EN2_BIT 18 +#define SUS_GPIO_EN2 (1 << SUS_GPIO_EN2_BIT) +#define SUS_GPIO_EN1_BIT 17 +#define SUS_GPIO_EN1 (1 << SUS_GPIO_EN1_BIT) +#define SUS_GPIO_EN0_BIT 16 +#define SUS_GPIO_EN0 (1 << SUS_GPIO_EN0_BIT) +#define PME_B0_EN (1 << 13) +#define BATLOW_EN (1 << 10) +#define PCI_EXP_EN (1 << 9) +#define PCIE_WAKE3_EN (1 << 8) +#define PCIE_WAKE2_EN (1 << 7) +#define PCIE_WAKE1_EN (1 << 6) +#define PCIE_WAKE0_EN (1 << 3) +#define SWGPE_EN (1 << 2) +#define HOT_PLUG_EN (1 << 1) +#define _ACPI_ENABLE_WAKE_SUS_GPIO(x) SUS_GPIO_EN##x##_BIT +#define ACPI_ENABLE_WAKE_SUS_GPIO(x) _ACPI_ENABLE_WAKE_SUS_GPIO(x) +#define SMI_EN 0x30 +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define USB_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define SMI_STS 0x34 +#define ALT_GPIO_SMI 0x38 +#define UPRWC 0x3c +# define UPRWC_WR_EN (1 << 1) // USB Per-Port Registers Write Enable +#define GPE_CTRL 0x40 +#define PM2A_CNT_BLK 0x50 +#define TCO_RLD 0x60 +#define TCO_STS 0x64 +# define SECOND_TO_STS (1 << 17) +# define TCO_TIMEOUT (1 << 3) +#define TCO1_CNT 0x68 +# define TCO_LOCK (1 << 12) +# define TCO_TMR_HALT (1 << 11) +#define TCO_TMR 0x70 + +/* I/O ports */ +#define RST_CNT 0xcf9 +# define FULL_RST (1 << 3) +# define RST_CPU (1 << 2) +# define SYS_RST (1 << 1) + +#if !defined(__ASSEMBLER__) && !defined(__ACPI__) + +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; +} __attribute__((packed)); + +/* Power Management Utility Functions. */ +uint16_t get_pmbase(void); +uint32_t clear_smi_status(void); +uint16_t clear_pm1_status(void); +uint32_t clear_tco_status(void); +uint32_t clear_gpe_status(void); +uint32_t clear_alt_status(void); +void clear_pmc_status(void); +void enable_smi(uint32_t mask); +void disable_smi(uint32_t mask); +void enable_pm1(uint16_t events); +void enable_pm1_control(uint32_t mask); +void disable_pm1_control(uint32_t mask); +void enable_gpe(uint32_t mask); +void disable_gpe(uint32_t mask); +void disable_all_gpe(void); + +#if CONFIG_ELOG +void southcluster_log_state(void); +#else +static inline void southcluster_log_state(void) {} +#endif + +#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */ + +#endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h new file mode 100644 index 0000000..0ed83bd --- /dev/null +++ b/src/soc/intel/braswell/include/soc/ramstage.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RAMSTAGE_H_ +#define _BAYTRAIL_RAMSTAGE_H_ + +#include <device/device.h> +#include <soc/intel/baytrail/chip.h> + +/* The baytrail_init_pre_device() function is called prior to device + * initialization, but it's after console and cbmem has been reinitialized. */ +void baytrail_init_pre_device(struct soc_intel_baytrail_config *config); +void baytrail_init_cpus(device_t dev); +void set_max_freq(void); +void southcluster_enable_dev(device_t dev); +#if CONFIG_HAVE_REFCODE_BLOB +void baytrail_run_reference_code(void); +#else +static inline void baytrail_run_reference_code(void) {} +#endif +void baytrail_init_scc(void); +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); + +extern struct pci_operations soc_pci_ops; + +#endif /* _BAYTRAIL_RAMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/reset.h b/src/soc/intel/braswell/include/soc/reset.h new file mode 100644 index 0000000..dbf0fd2 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/reset.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_RESET_H_ +#define _BAYTRAIL_RESET_H_ +#include <reset.h> + +/* Bay Trail has the following types of resets: + * - Soft reset (INIT# to cpu) - write 0x1 to I/O 0x92 + * - Soft reset (INIT# to cpu)- write 0x4 to I/0 0xcf9 + * - Cold reset (S0->S5->S0) - write 0xe to I/0 0xcf9 + * - Warm reset (PMC_PLTRST# assertion) - write 0x6 to I/O 0xcf9 + * - Global reset (S0->S5->S0 with TXE reset) - write 0x6 or 0xe to 0xcf9 but + * with ETR[20] set. + */ + +void cold_reset(void); +void warm_reset(void); + +#endif /* _BAYTRAIL_RESET_H_ */ diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h new file mode 100644 index 0000000..f99a8e2 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_ROMSTAGE_H_ +#define _BAYTRAIL_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <stdint.h> +#include <arch/cpu.h> +#include <soc/mrc_wrapper.h> + +struct romstage_params { + unsigned long bist; + struct mrc_params *mrc_params; +}; + +void mainboard_romstage_entry(struct romstage_params *params); +void romstage_common(struct romstage_params *params); +void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_lo, + uint32_t tsc_high); +void asmlinkage romstage_after_car(void); +void raminit(struct mrc_params *mp, int prev_sleep_state); +void gfx_init(void); +void tco_disable(void); +void punit_init(void); +void set_max_freq(void); +int early_spi_read_wpsr(u8 *sr); + +#if CONFIG_ENABLE_BUILTIN_COM1 +void byt_config_com1_and_enable(void); +#else +static inline void byt_config_com1_and_enable(void) { } +#endif + +#endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/braswell/include/soc/sata.h b/src/soc/intel/braswell/include/soc/sata.h new file mode 100644 index 0000000..7704c18 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/sata.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_SATA_H +#define BAYTRAIL_SATA_H + +#define SATA_SIRI 0xa0 +#define SATA_SIRD 0xa4 + +#endif diff --git a/src/soc/intel/braswell/include/soc/smm.h b/src/soc/intel/braswell/include/soc/smm.h new file mode 100644 index 0000000..0d920fb --- /dev/null +++ b/src/soc/intel/braswell/include/soc/smm.h @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_SMM_H_ +#define _BAYTRAIL_SMM_H_ + +/* There is a bug in the order of Kconfig includes in that arch/x86/Kconfig + * is included after chipset code. This causes the chipset's Kconfig to be + * clobbered by the arch/x86/Kconfig if they have the same name. */ +static inline int smm_region_size(void) +{ + /* Make it 8MiB by default. */ + if (CONFIG_SMM_TSEG_SIZE == 0) + return (8 << 20); + return CONFIG_SMM_TSEG_SIZE; +} + +uintptr_t smm_region_start(void); + +#if !defined(__PRE_RAM__) && !defined(__SMM___) +#include <stdint.h> +void southcluster_smm_clear_state(void); +void southcluster_smm_enable_smi(void); +void southcluster_smm_save_param(int param, uint32_t data); +#endif + +enum { + SMM_SAVE_PARAM_GPIO_ROUTE = 0, + SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, + SMM_SAVE_PARAM_COUNT +}; + +#endif /* _BAYTRAIL_SMM_H_ */ diff --git a/src/soc/intel/braswell/include/soc/spi.h b/src/soc/intel/braswell/include/soc/spi.h new file mode 100644 index 0000000..ef71ad5 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/spi.h @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_SPI_H_ +#define _BAYTRAIL_SPI_H_ + +#include <stdint.h> + +/* These registers live behind SPI_BASE_ADDRESS. */ +#define HSFSTS 0x04 +#define FDATA0 0x10 +# define FLOCKDN (0x1 << 15) +#define SSFS 0x90 +# define CYCLE_DONE_STATUS (0x1 << 2) +# define FLASH_CYCLE_ERROR (0x1 << 3) +#define SSFC 0x91 +# define SPI_CYCLE_GO (0x1 << 1) +# define DATA_CYCLE (0x1 << 14) +#define PREOP 0x94 +#define OPTYPE 0x96 +#define OPMENU0 0x98 +#define OPMENU1 0x9c +#define LVSCC 0xc4 +# define VCL (0x1 << 23) +# define EO(x) (((x) & 0xff) << 8) +# define WG_1_BYTE (0x0 << 2) +# define WG_64_BYTE (0x1 << 2) +# define BES_256_BYTE (0x0 << 0) +# define BES_4_KB (0x1 << 0) +# define BES_8_KB (0x2 << 0) +# define BES_64_KB (0x3 << 0) +#define UVSCC 0xc8 +#define SCS 0xf8 +# define SMIWPEN (0x1 << 7) +#define BCR 0xfc +# define EISS (0x1 << 5) +# define SRC_MASK (0x3 << 2) +# define SRC_CACHE_NO_PREFETCH (0x0 << 2) +# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) +# define SRC_CACHE_PREFETCH (0x2 << 2) +# define BCR_LE (0x1 << 1) +# define BCR_WPD (0x1 << 0) + +/* + * SPI lockdown configuration. + */ +struct spi_config { + uint16_t preop; + uint16_t optype; + uint32_t opmenu[2]; + uint32_t lvscc; + uint32_t uvscc; +}; + +/* Return 0 on success < 0 on failure. */ +int mainboard_get_spi_config(struct spi_config *cfg); + +#endif /* _BAYTRAIL_SPI_H_ */ diff --git a/src/soc/intel/braswell/include/soc/xhci.h b/src/soc/intel/braswell/include/soc/xhci.h new file mode 100644 index 0000000..b317361 --- /dev/null +++ b/src/soc/intel/braswell/include/soc/xhci.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef BAYTRAIL_XHCI_H +#define BAYTRAIL_XHCI_H + +/* XHCI PCI Registers */ +#define XHCI_PWR_CTL_STS 0x74 +#define XHCI_USB2PR 0xd0 +#define XHCI_USB2PRM 0xd4 +#define XHCI_USB3PR 0xd8 +#define XHCI_USB3PRM 0xdc +#define XHCI_USB2PDO 0xe4 +#define XHCI_USB3PDO 0xe8 + +/* XHCI Memory Registers */ +#define XHCI_USB3_PORTSC(port) (0x4e0 + (port * 0x10)) +# define XHCI_USB3_PORTSC_CHST (0x7f << 17) +# define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ +# define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ +# define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ +# define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ +# define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +# define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +# define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +# define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ +# define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ +# define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ +# define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ +# define XHCI_PLSW_ENABLE (5 << 5) /* Enable port */ + +/* The Fuse register is incorrect for Baytrail-M so use hardcoded values */ +#define BYTM_USB2_PORT_COUNT 4 +#define BYTM_USB2_PORT_MAP 0xf +#define BYTM_USB3_PORT_COUNT 1 +#define BYTM_USB3_PORT_MAP 0x1 + +#define XHCI_RESET_TIMEOUT 100000 /* 100ms */ + +#endif /* BAYTRAIL_XHCI_H */ diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c new file mode 100644 index 0000000..8dba823 --- /dev/null +++ b/src/soc/intel/braswell/iosf.c @@ -0,0 +1,287 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/iosf.h> + +#if !defined(__PRE_RAM__) +#define IOSF_PCI_BASE (CONFIG_MMCONF_BASE_ADDRESS + (IOSF_PCI_DEV << 12)) + +static inline void write_iosf_reg(int reg, uint32_t value) +{ + write32((u32 *)(IOSF_PCI_BASE + reg), value); +} +static inline uint32_t read_iosf_reg(int reg) +{ + return read32((u32 *)(IOSF_PCI_BASE + reg)); +} +#else +static inline void write_iosf_reg(int reg, uint32_t value) +{ + pci_write_config32(IOSF_PCI_DEV, reg, value); +} +static inline uint32_t read_iosf_reg(int reg) +{ + return pci_read_config32(IOSF_PCI_DEV, reg); +} +#endif + +/* Common sequences for all the port accesses. */ +static uint32_t iosf_read_port(uint32_t cr, int reg) +{ + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); + return read_iosf_reg(MDR_REG); +} + +static void iosf_write_port(uint32_t cr, int reg, uint32_t val) +{ + cr |= IOSF_REG(reg) | IOSF_BYTE_EN; + write_iosf_reg(MDR_REG, val); + write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg)); + write_iosf_reg(MCR_REG, cr); +} + +#define IOSF_READ(port) \ + IOSF_OPCODE(IOSF_OP_READ_##port) | IOSF_PORT(IOSF_PORT_##port) +#define IOSF_WRITE(port) \ + IOSF_OPCODE(IOSF_OP_WRITE_##port) | IOSF_PORT(IOSF_PORT_##port) + +uint32_t iosf_bunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(BUNIT), reg); +} + +void iosf_bunit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(BUNIT), reg, val); +} + +uint32_t iosf_dunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(SYSMEMC), reg); +} + +uint32_t iosf_dunit_ch0_read(int reg) +{ + return iosf_dunit_read(reg); +} + +uint32_t iosf_dunit_ch1_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) | + IOSF_PORT(IOSF_PORT_DUNIT_CH1); + return iosf_read_port(cr, reg); +} + +void iosf_dunit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(SYSMEMC), reg, val); +} + +uint32_t iosf_punit_read(int reg) +{ + return iosf_read_port(IOSF_READ(PMC), reg); +} + +void iosf_punit_write(int reg, uint32_t val) +{ + iosf_write_port(IOSF_WRITE(PMC), reg, val); +} + +uint32_t iosf_usbphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USBPHY), reg); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); +} + +uint32_t iosf_ushphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USHPHY), reg); +} + +void iosf_ushphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USHPHY), reg, val); +} + +uint32_t iosf_lpss_read(int reg) +{ + return iosf_read_port(IOSF_READ(LPSS), reg); +} + +void iosf_lpss_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(LPSS), reg, val); +} + +uint32_t iosf_ccu_read(int reg) +{ + return iosf_read_port(IOSF_READ(CCU), reg); +} + +void iosf_ccu_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(CCU), reg, val); +} + +uint32_t iosf_score_read(int reg) +{ + return iosf_read_port(IOSF_READ(SCORE), reg); +} + +void iosf_score_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SCORE), reg, val); +} + +uint32_t iosf_scc_read(int reg) +{ + return iosf_read_port(IOSF_READ(SCC), reg); +} + +void iosf_scc_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SCC), reg, val); +} + +uint32_t iosf_aunit_read(int reg) +{ + return iosf_read_port(IOSF_READ(AUNIT), reg); +} + +void iosf_aunit_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(AUNIT), reg, val); +} + +uint32_t iosf_cpu_bus_read(int reg) +{ + return iosf_read_port(IOSF_READ(CPU_BUS), reg); +} + +void iosf_cpu_bus_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(CPU_BUS), reg, val); +} + +uint32_t iosf_sec_read(int reg) +{ + return iosf_read_port(IOSF_READ(SEC), reg); +} + +void iosf_sec_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SEC), reg, val); +} + +uint32_t iosf_port45_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x45), reg); +} + +void iosf_port45_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x45), reg, val); +} + +uint32_t iosf_port46_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x46), reg); +} + +void iosf_port46_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x46), reg, val); +} + +uint32_t iosf_port47_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x47), reg); +} + +void iosf_port47_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x47), reg, val); +} + +uint32_t iosf_port55_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x55), reg); +} + +void iosf_port55_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x55), reg, val); +} + +uint32_t iosf_port58_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x58), reg); +} + +void iosf_port58_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x58), reg, val); +} + +uint32_t iosf_port59_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x59), reg); +} + +void iosf_port59_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x59), reg, val); +} + +uint32_t iosf_port5a_read(int reg) +{ + return iosf_read_port(IOSF_READ(0x5a), reg); +} + +void iosf_port5a_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0x5a), reg, val); +} + +uint32_t iosf_porta2_read(int reg) +{ + return iosf_read_port(IOSF_READ(0xa2), reg); +} + +void iosf_porta2_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(0xa2), reg, val); +} + +uint32_t iosf_ssus_read(int reg) +{ + return iosf_read_port(IOSF_READ(SSUS), reg); +} + +void iosf_ssus_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(SSUS), reg, val); +} diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c new file mode 100644 index 0000000..c23fdb2 --- /dev/null +++ b/src/soc/intel/braswell/lpe.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/lpc.h> +#include <soc/nvs.h> +#include <soc/pattrs.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/ramstage.h> +#include "chip.h" + + +/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. */ +#define FIRMWARE_PHYS_BASE (512 << 20) +#define FIRMWARE_PHYS_LENGTH (1 << 20) +#define FIRMWARE_PCI_REG_BASE 0xa8 +#define FIRMWARE_PCI_REG_LENGTH 0xac +#define FIRMWARE_REG_BASE_C0 0x144000 +#define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) + +static void assign_device_nvs(device_t dev, u32 *field, unsigned index) +{ + struct resource *res; + + res = find_resource(dev, index); + if (res) + *field = res->base; +} + +static void lpe_enable_acpi_mode(device_t dev) +{ + static const struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, + LPE_PCICFGCTR1_PCI_CFG_DIS | + LPE_PCICFGCTR1_ACPI_INT_EN), + REG_SCRIPT_END + }; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0, BAR1, and firmware base to ACPI NVS */ + assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); + assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); + assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpe_en = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} + +static void setup_codec_clock(device_t dev) +{ + uint32_t reg; + u32 *clk_reg; + struct soc_intel_baytrail_config *config; + const char *freq_str; + + config = dev->chip_info; + switch (config->lpe_codec_clk_freq) { + case 19: + freq_str = "19.2"; + reg = CLK_FREQ_19P2MHZ; + break; + case 25: + freq_str = "25"; + reg = CLK_FREQ_25MHZ; + break; + default: + printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + return; + } + + /* Default to always running. */ + reg |= CLK_CTL_ON; + + if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { + printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); + return; + } + + printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); + + clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); + clk_reg += config->lpe_codec_clk_num; + + write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); +} + +static void lpe_stash_firmware_info(device_t dev) +{ + struct resource *res; + struct resource *mmio; + const struct pattrs *pattrs = pattrs_get(); + + res = find_resource(dev, FIRMWARE_PCI_REG_BASE); + if (res == NULL) { + printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); + return; + } + + /* Continue using old way of informing firmware address / size. */ + pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); + + /* C0 and later steppings use an offset in the MMIO space. */ + if (pattrs->stepping >= STEP_C0) { + mmio = find_resource(dev, PCI_BASE_ADDRESS_0); + write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), + res->base); + write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), + res->size); + } +} + +static void lpe_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + + lpe_stash_firmware_info(dev); + + setup_codec_clock(dev); + + if (config->lpe_acpi_mode) + lpe_enable_acpi_mode(dev); +} + +static void lpe_read_resources(device_t dev) +{ + pci_dev_read_resources(dev); + + reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, + FIRMWARE_PHYS_BASE >> 10, + FIRMWARE_PHYS_LENGTH >> 10); +} + +static const struct device_operations device_ops = { + .read_resources = lpe_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpe_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPE_DEVID, +}; diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c new file mode 100644 index 0000000..caa945c --- /dev/null +++ b/src/soc/intel/braswell/lpss.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iosf.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +#include "chip.h" + +static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, + LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpss_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} + +static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +{ + struct reg_script ops[] = { + REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, + ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), + LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), + REG_SCRIPT_END, + }; + + reg_script_run_on_dev(dev, ops); +} + +static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) +{ + *iosf_reg = -1; + *nvs_index = -1; +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_ + + switch (dev->path.pci.devfn) { + SET_IOSF_REG(SIO_DMA1); + break; + SET_IOSF_REG(I2C1); + break; + SET_IOSF_REG(I2C2); + break; + SET_IOSF_REG(I2C3); + break; + SET_IOSF_REG(I2C4); + break; + SET_IOSF_REG(I2C5); + break; + SET_IOSF_REG(I2C6); + break; + SET_IOSF_REG(I2C7); + break; + SET_IOSF_REG(SIO_DMA2); + break; + SET_IOSF_REG(PWM1); + break; + SET_IOSF_REG(PWM2); + break; + SET_IOSF_REG(HSUART1); + break; + SET_IOSF_REG(HSUART2); + break; + SET_IOSF_REG(SPI); + break; + } +} + +static void i2c_disable_resets(device_t dev) +{ + /* Release the I2C devices from reset. */ + static const struct reg_script ops[] = { + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), + REG_SCRIPT_END, + }; + +#define CASE_I2C(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1): + CASE_I2C(I2C2): + CASE_I2C(I2C3): + CASE_I2C(I2C4): + CASE_I2C(I2C5): + CASE_I2C(I2C6): + CASE_I2C(I2C7): + printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); + reg_script_run_on_dev(dev, ops); + break; + default: + return; + } +} + +static void lpss_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + int iosf_reg, nvs_index; + + dev_ctl_reg(dev, &iosf_reg, &nvs_index); + + if (iosf_reg < 0) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", + slot, func); + return; + } + dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); + + if (config->lpss_acpi_mode) + dev_enable_acpi_mode(dev, iosf_reg, nvs_index); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpss_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + SIO_DMA1_DEVID, + I2C1_DEVID, + I2C2_DEVID, + I2C3_DEVID, + I2C4_DEVID, + I2C5_DEVID, + I2C6_DEVID, + I2C7_DEVID, + SIO_DMA2_DEVID, + PWM1_DEVID, + PWM2_DEVID, + HSUART1_DEVID, + HSUART2_DEVID, + SPI_DEVID, + 0, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c new file mode 100644 index 0000000..9a49e35 --- /dev/null +++ b/src/soc/intel/braswell/memmap.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <soc/iosf.h> +#include <soc/smm.h> + +uintptr_t smm_region_start(void) +{ + return (iosf_bunit_read(BUNIT_SMRRL) << 20); +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc new file mode 100644 index 0000000..09bd454 --- /dev/null +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -0,0 +1 @@ +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c diff --git a/src/soc/intel/braswell/microcode/microcode_blob.c b/src/soc/intel/braswell/microcode/microcode_blob.c new file mode 100644 index 0000000..7c7b6f1 --- /dev/null +++ b/src/soc/intel/braswell/microcode/microcode_blob.c @@ -0,0 +1,3 @@ +unsigned microcode[] = { +#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h" +}; diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c new file mode 100644 index 0000000..97b3bcc --- /dev/null +++ b/src/soc/intel/braswell/northcluster.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> + +/* Host Memory Map: + * + * +--------------------------+ BMBOUND_HI + * | Usable DRAM | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ BMBOUND + * | TPM | + * +--------------------------+ IMR2 + * | TXE | + * +--------------------------+ IMR1 + * | iGD | + * +--------------------------+ + * | GTT | + * +--------------------------+ SMMRRH, IRM0 + * | TSEG | + * +--------------------------+ SMMRRL + * | Usable DRAM | + * +--------------------------+ 0 + * + * Note that there are really only a few regions that need to enumerated w.r.t. + * coreboot's resource model: + * + * +--------------------------+ BMBOUND_HI + * | Cacheable/Usable | + * +--------------------------+ 4GiB + * + * +--------------------------+ BMBOUND + * | Uncacheable/Reserved | + * +--------------------------+ SMMRRH + * | Cacheable/Reserved | + * +--------------------------+ SMMRRL + * | Cacheable/Usable | + * +--------------------------+ 0 + */ +#define RES_IN_KiB(r) ((r) >> 10) + +uint32_t nc_read_top_of_low_memory(void) +{ + return iosf_bunit_read(BUNIT_BMBOUND) & ~((1 << 27) - 1); +} + +static void nc_read_resources(device_t dev) +{ + unsigned long mmconf; + unsigned long bmbound; + unsigned long bmbound_hi; + unsigned long smmrrh; + unsigned long smmrrl; + unsigned long base_k, size_k; + const unsigned long four_gig_kib = (4 << (30 - 10)); + int index = 0; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* PCIe memory-mapped config space access - 256 MiB. */ + mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); + mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024); + + /* 0 -> 0xa0000 */ + base_k = RES_IN_KiB(0); + size_k = RES_IN_KiB(0xa0000) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* The SMMRR registers are 1MiB granularity with smmrrh being + * inclusive of the SMM region. */ + smmrrl = (iosf_bunit_read(BUNIT_SMRRL) & 0xffff) << 10; + smmrrh = ((iosf_bunit_read(BUNIT_SMRRH) & 0xffff) + 1) << 10; + + /* 0xc0000 -> smrrl - cacheable and usable */ + base_k = RES_IN_KiB(0xc0000); + size_k = smmrrl - base_k; + ram_resource(dev, index++, base_k, size_k); + + if (smmrrh > smmrrl) + reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl); + + /* All address space between bmbound and smmrrh is unusable. */ + bmbound = RES_IN_KiB(nc_read_top_of_low_memory()); + mmio_resource(dev, index++, smmrrh, bmbound - smmrrh); + + /* The BMBOUND_HI register matches register bits of 31:24 with address + * bits of 35:28. Therefore, shift register to align properly. */ + bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1); + bmbound_hi = RES_IN_KiB(bmbound_hi) << 4; + if (bmbound_hi > four_gig_kib) + ram_resource(dev, index++, four_gig_kib, + bmbound_hi - four_gig_kib); + + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), + (0x100000 - 0xc0000) >> 10); + + chromeos_reserve_ram_oops(dev, index++); +} + +static struct device_operations nc_ops = { + .read_resources = nc_read_resources, + .set_resources = NULL, + .enable_resources = NULL, + .init = NULL, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver nc_driver __pci_driver = { + .ops = &nc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SOC_DEVID, +}; diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c new file mode 100644 index 0000000..e44ebc6 --- /dev/null +++ b/src/soc/intel/braswell/pcie.c @@ -0,0 +1,278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/pci_devs.h> +#include <soc/pcie.h> +#include <soc/ramstage.h> +#include <soc/smm.h> + +#include "chip.h" + +static int pll_en_off; +static uint32_t strpfusecfg; + +static inline int root_port_offset(device_t dev) +{ + return PCI_FUNC(dev->path.pci.devfn); +} + +static inline int is_first_port(device_t dev) +{ + return root_port_offset(dev) == PCIE_PORT1_FUNC; +} + +static const struct reg_script init_static_before_exit_latency[] = { + /* Disable optimized buffer flush fill and latency tolerant reporting */ + REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), + REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), + /* Set maximum payload size. */ + REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), + /* Disable transmit datapath flush timer, clear transmit config change + * wait time, clear sideband interface idle counter. */ + REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), + REG_SCRIPT_END, +}; + +static const struct reg_script init_static_after_exit_latency[] = { + /* Set common clock configuration. */ + REG_PCI_OR16(LCTL, CCC), + /* Set NFTS to 0x743a361b */ + REG_PCI_WRITE32(NFTS, 0x743a361b), + /* Set common clock latency to 0x3 */ + REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)), + /* Set relay timer policy. */ + REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), + /* Set IOSF packet fast transmit mode and link speed training policy. */ + REG_PCI_OR16(MPC2, IPF | LSTP), + /* Channel configuration - enable upstream posted split, set non-posted + * and posted request size */ + REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), + /* Completion status replay enable and set TLP grant count */ + REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), + /* Assume no IOAPIC behind root port -- disable EOI forwarding. */ + REG_PCI_OR16(MPC2, EOIFD), + /* Expose AER */ + REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)), + /* set completion timeout to 160ms to 170ms */ + REG_PCI_RMW16(DSTS2, ~CTD, 0x6), + /* Enable AER */ + REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), + /* Read and write back capability registers. */ + REG_PCI_OR32(0x34, 0), + REG_PCI_OR32(0x80, 0), + /* Retrain the link. */ + REG_PCI_OR16(LCTL, RL), + REG_SCRIPT_END, +}; + +static void byt_pcie_init(device_t dev) +{ + struct reg_script init_script[] = { + REG_SCRIPT_NEXT(init_static_before_exit_latency), + /* Exit latency configuration based on + * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ + REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, + 2 << (L1EXIT_SHIFT + pll_en_off)), + REG_SCRIPT_NEXT(init_static_after_exit_latency), + /* Disable hot plug, set power to 10W, set slot number. */ + REG_PCI_RMW32(SLCAP, ~(HPC | HPS), + (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | + (root_port_offset(dev) << SLN_SHIFT)), + /* Dynamic clock gating. */ + REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), + REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), + REG_PCI_OR32(PCIEDBG, SPCE), + REG_SCRIPT_END, + }; + + reg_script_run_on_dev(dev, init_script); + + if (is_first_port(dev)) { + struct soc_intel_baytrail_config *config = dev->chip_info; + uint32_t reg = pci_read_config32(dev, RPPGEN); + reg |= SRDLCGEN | SRDBCGEN; + + if (config && config->clkreq_enable) + reg |= LCLKREQEN | BBCLKREQEN; + + pci_write_config32(dev, RPPGEN, reg); + } +} + +static const struct reg_script no_dev_behind_port[] = { + REG_PCI_OR32(PCIEALC, (1 << 26)), + REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), + REG_PCI_OR32(PHYCTL4, SQDIS), + REG_SCRIPT_END, +}; + +static void check_port_enabled(device_t dev) +{ + int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; + + switch (root_port_offset(dev)) { + case PCIE_PORT1_FUNC: + /* Port 1 cannot be disabled from strapping config. */ + break; + case PCIE_PORT2_FUNC: + /* Port 2 disabled in all configs but 4x1. */ + if (rp_config != 0x0) + dev->enabled = 0; + break; + case PCIE_PORT3_FUNC: + /* Port 3 disabled only in 1x4 config. */ + if (rp_config == 0x3) + dev->enabled = 0; + break; + case PCIE_PORT4_FUNC: + /* Port 4 disabled in 1x4 and 2x2 config. */ + if (rp_config >= 0x2) + dev->enabled = 0; + break; + } +} + +static u8 all_ports_no_dev_present(device_t dev) +{ + u8 func; + u8 temp = dev->path.pci.devfn; + u8 device_not_present = 1; + u8 data; + + for (func = 1; func < PCIE_ROOT_PORT_COUNT; func++) { + dev->path.pci.devfn &= ~0x7; + dev->path.pci.devfn |= func; + + /* is pcie device there */ + if (pci_read_config32(dev, 0) == 0xFFFFFFFF) + continue; + + data = pci_read_config8(dev, XCAP + 3) | (SI >> 24); + pci_write_config8(dev, XCAP + 3, data); + + /* is any device present */ + if ((pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { + device_not_present = 0; + break; + } + } + + dev->path.pci.devfn = temp; + return device_not_present; +} + +static void check_device_present(device_t dev) +{ + /* Set slot implemented. */ + pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); + + /* No device present. */ + if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { + printk(BIOS_DEBUG, "No PCIe device present.\n"); + if (is_first_port(dev)) { + if (all_ports_no_dev_present(dev)) { + reg_script_run_on_dev(dev, no_dev_behind_port); + dev->enabled = 0; + } + } else { + reg_script_run_on_dev(dev, no_dev_behind_port); + dev->enabled = 0; + } + } else if(!dev->enabled) { + /* Port is disabled, but device present. Disable link. */ + pci_write_config32(dev, LCTL, + pci_read_config32(dev, LCTL) | LD); + } +} + +static void byt_pcie_enable(device_t dev) +{ + if (is_first_port(dev)) { + struct soc_intel_baytrail_config *config = dev->chip_info; + uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); + pll_en_off = !!(reg & PLL_OFF_EN); + + strpfusecfg = pci_read_config32(dev, STRPFUSECFG); + + if (config && config->pcie_wake_enable) + southcluster_smm_save_param( + SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1); + } + + /* Check if device is enabled in strapping. */ + check_port_enabled(dev); + /* Determine if device is behind port. */ + check_device_present(dev); + + southcluster_enable_dev(dev); +} + +static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) +{ + static const struct reg_script wait_for_link_active[] = { + REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), + REG_SCRIPT_END, + }; + + /* wait for Link Active with 50ms timeout */ + reg_script_run_on_dev(dev, wait_for_link_active); + + return do_pci_scan_bridge(dev, max, pciexp_scan_bus); +} + +static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +{ + uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); + + if (!didvid) + didvid = pci_read_config32(dev, PCI_VENDOR_ID); + pci_write_config32(dev, 0x94, didvid); +} + +static struct pci_operations pcie_root_ops = { + .set_subsystem = &pcie_root_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = byt_pcie_init, + .scan_bus = byt_pciexp_scan_bridge, + .enable = byt_pcie_enable, + .ops_pci = &pcie_root_ops, +}; + +static const unsigned short pci_device_ids[] = { + PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID, + 0 +}; + +static const struct pci_driver pcie_root_ports __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/braswell/perf_power.c b/src/soc/intel/braswell/perf_power.c new file mode 100644 index 0000000..ad5ccfe --- /dev/null +++ b/src/soc/intel/braswell/perf_power.c @@ -0,0 +1,292 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <reg_script.h> +#include <soc/iosf.h> + +#define MAKE_MASK_INCLUSIVE(msb) \ + ((1ULL << (1 + (msb))) - 1) +#define MAKE_MASK(msb) \ + ((1ULL << (msb)) - 1) +#define MASK_VAL(msb, lsb, val) \ + ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) + +#define E(arg1, arg2, args) \ + REG_IOSF_RMW(IOSF_PORT_##arg1, arg2, args) + +static const struct reg_script perf_power_settings[] = { +E(AUNIT, 0x18, MASK_VAL(22, 22, 0x1)), // ACKGATE.AMESSAGE_MSGIF +E(AUNIT, 0x18, MASK_VAL(21, 21, 0x1)), // ACKGATE.AREQDOWN_SCL0_ARB +E(AUNIT, 0x18, MASK_VAL(20, 20, 0x1)), // ACKGATE.AREQUP_MIRROR +E(AUNIT, 0x18, MASK_VAL(19, 19, 0x1)), // ACKGATE.AREQTAHACK +E(AUNIT, 0x18, MASK_VAL(18, 18, 0x1)), // ACKGATE.AREQDOWN_TAREQQ +E(AUNIT, 0x18, MASK_VAL(17, 17, 0x1)), // ACKGATE.AREQDOWN_CREDIT +E(AUNIT, 0x18, MASK_VAL(16, 16, 0x1)), // ACKGATE.ASCLUP_FAIR_ARBITER +E(AUNIT, 0x18, MASK_VAL(15, 15, 0x1)), // ACKGATE.AIOSFDOWN_DATA +E(AUNIT, 0x18, MASK_VAL(14, 14, 0x1)), // ACKGATE.ASCLUP_IOSF_ADAPTER +E(AUNIT, 0x18, MASK_VAL(12, 12, 0x1)), // ACKGATE.ASCLUP_CMD_QUEUE +E(AUNIT, 0x18, MASK_VAL(11, 11, 0x1)), // ACKGATE.ASCLUP_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(10, 10, 0x1)), // ACKGATE.AREQUP_CMD_QUEUE +E(AUNIT, 0x18, MASK_VAL(9, 9, 0x1)), // ACKGATE.AREQUP_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(8, 8, 0x1)), // ACKGATE.AREQDOWN_RSP_QUEUE +E(AUNIT, 0x18, MASK_VAL(7, 7, 0x1)), // ACKGATE.AREQDOWN_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(6, 6, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DRVR +E(AUNIT, 0x18, MASK_VAL(5, 5, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF +E(AUNIT, 0x18, MASK_VAL(4, 4, 0x1)), // ACKGATE.AT_REQ_QUEUE +E(AUNIT, 0x18, MASK_VAL(3, 3, 0x1)), // ACKGATE.AT_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(2, 2, 0x1)), // ACKGATE.TA_REQ_QUEUE +E(AUNIT, 0x18, MASK_VAL(1, 1, 0x1)), // ACKGATE.TA_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(0, 0, 0x1)), // ACKGATE.CONFIG_REGS +E(AUNIT, 0x20, MASK_VAL(26, 24, 0x2)), // AISOCHCTL.CHANNEL_AB_DEADLINE_EN +E(AUNIT, 0x20, MASK_VAL(8, 0, 0x1)), // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY +E(AUNIT, 0x21, MASK_VAL(31, 31, 0x1)), // AVCCTL.EFFICIENT_PERF_UP_EN +E(AUNIT, 0x21, MASK_VAL(8, 8, 0x0)), // AVCCTL.VC_EN_PRIORITY_DNARB +E(AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)), // AARBCTL0.IOSF0VC2_WGT +E(AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)), // AARBCTL0.IOSF0VC1_WGT +E(AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)), // AARBCTL0.IOSF0VC0_WGT +E(BUNIT, 0x3, MASK_VAL(29, 24, 0x4)), // BARBCTRL0.AGENT3_WEIGHT +E(BUNIT, 0x3, MASK_VAL(21, 16, 0x4)), // BARBCTRL0.AGENT2_WEIGHT +E(BUNIT, 0x3, MASK_VAL(13, 8, 0x4)), // BARBCTRL0.AGENT1_WEIGHT +E(BUNIT, 0x3, MASK_VAL(5, 0, 0x4)), // BARBCTRL0.AGENT0_WEIGHT +E(BUNIT, 0x4, MASK_VAL(29, 24, 0x4)), // BARBCTRL1.AGENT7_WEIGHT +E(BUNIT, 0x4, MASK_VAL(21, 16, 0x4)), // BARBCTRL1.AGENT6_WEIGHT +E(BUNIT, 0x4, MASK_VAL(13, 8, 0x4)), // BARBCTRL1.AGENT5_WEIGHT +E(BUNIT, 0x4, MASK_VAL(5, 0, 0x4)), // BARBCTRL1.AGENT4_WEIGHT +E(BUNIT, 0x5, MASK_VAL(21, 16, 0x4)), // BARBCTRL2.AGENT10_WEIGHT +E(BUNIT, 0x5, MASK_VAL(13, 8, 0x4)), // BARBCTRL2.AGENT9_WEIGHT +E(BUNIT, 0x5, MASK_VAL(5, 0, 0x8)), // BARBCTRL2.AGENT8_WEIGHT +E(BUNIT, 0x7, MASK_VAL(31, 24, 0x20)), // BWFLUSH.FLUSH_THRSHOLD +E(BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)), // BWFLUSH.DIRTY_LWM +E(BUNIT, 0x7, MASK_VAL(7, 0, 0x10)), // BWFLUSH.DIRTY_HWM +E(BUNIT, 0x8, MASK_VAL(23, 0, 0x0)), // BBANKMASK.BANK_MASK +E(BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)), // BROWMASK.ROW_MASK +E(BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)), // BRANKMASK.RANK_MASK +E(BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)), // BALIMIT0.AGENT3_LIMIT +E(BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)), // BALIMIT0.AGENT2_LIMIT +E(BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)), // BALIMIT0.AGENT1_LIMIT +E(BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)), // BALIMIT0.AGENT0_LIMIT +E(BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)), // BALIMIT1.AGENT7_LIMIT +E(BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)), // BALIMIT1.AGENT6_LIMIT +E(BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)), // BALIMIT1.AGENT5_LIMIT +E(BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)), // BALIMIT1.AGENT4_LIMIT +E(BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)), // BALIMIT2.AGENT10_LIMIT +E(BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)), // BALIMIT2.AGENT9_LIMIT +E(BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)), // BALIMIT2.AGENT8_LIMIT +E(BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)), // BARES0.AGENT7_RSVD +E(BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)), // BARES0.AGENT6_RSVD +E(BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)), // BARES0.AGENT5_RSVD +E(BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)), // BARES0.AGENT4_RSVD +E(BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)), // BARES0.AGENT3_RSVD +E(BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)), // BARES0.AGENT2_RSVD +E(BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)), // BARES0.AGENT1_RSVD +E(BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)), // BARES0.AGENT0_RSVD +E(BUNIT, 0x10, MASK_VAL(9, 8, 0x0)), // BARES1.AGENT10_RSVD +E(BUNIT, 0x10, MASK_VAL(5, 4, 0x0)), // BARES1.AGENT9_RSVD +E(BUNIT, 0x10, MASK_VAL(1, 0, 0x0)), // BARES1.AGENT8_RSVD +E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH +E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN +E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY +E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY +E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE +E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 +E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13 +E(BUNIT, 0x12, MASK_VAL(25, 24, 0x0)), // BCOSCAT.COS_CAT_AGENT12 +E(BUNIT, 0x12, MASK_VAL(23, 22, 0x0)), // BCOSCAT.COS_CAT_AGENT11 +E(BUNIT, 0x12, MASK_VAL(21, 20, 0x0)), // BCOSCAT.COS_CAT_AGENT10 +E(BUNIT, 0x12, MASK_VAL(19, 18, 0x0)), // BCOSCAT.COS_CAT_AGENT9 +E(BUNIT, 0x12, MASK_VAL(17, 16, 0x1)), // BCOSCAT.COS_CAT_AGENT8 +E(BUNIT, 0x12, MASK_VAL(15, 14, 0x0)), // BCOSCAT.COS_CAT_AGENT7 +E(BUNIT, 0x12, MASK_VAL(13, 12, 0x0)), // BCOSCAT.COS_CAT_AGENT6 +E(BUNIT, 0x12, MASK_VAL(11, 10, 0x1)), // BCOSCAT.COS_CAT_AGENT5 +E(BUNIT, 0x12, MASK_VAL(9, 8, 0x1)), // BCOSCAT.COS_CAT_AGENT4 +E(BUNIT, 0x12, MASK_VAL(7, 6, 0x0)), // BCOSCAT.COS_CAT_AGENT3 +E(BUNIT, 0x12, MASK_VAL(5, 4, 0x0)), // BCOSCAT.COS_CAT_AGENT2 +E(BUNIT, 0x12, MASK_VAL(3, 2, 0x0)), // BCOSCAT.COS_CAT_AGENT1 +E(BUNIT, 0x12, MASK_VAL(1, 0, 0x0)), // BCOSCAT.COS_CAT_AGENT0 +E(BUNIT, 0x14, MASK_VAL(31, 31, 0x0)), // BFLWT.DISABLE_FLUSH_WEIGHTS +E(BUNIT, 0x14, MASK_VAL(30, 30, 0x0)), // BFLWT.ENABLE_READ_INVALIDATE_TIMER +E(BUNIT, 0x14, MASK_VAL(13, 8, 0x8)), // BFLWT.WRITE_WEIGHTS +E(BUNIT, 0x14, MASK_VAL(5, 0, 0x10)), // BFLWT.READ_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(31, 31, 0x0)), // BISOCWT.ENABLE_ISOC_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)), // BISOCWT.ISOC_REQUEST_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(5, 0, 0x8)), // BISOCWT.NON_ISOC_REQUEST_WEIGHTS +E(BUNIT, 0x18, MASK_VAL(31, 24, 0x20)), // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY +E(BUNIT, 0x18, MASK_VAL(23, 21, 0x6)), // BSCHCTRL0.PAGE_HIT_DELAY +E(BUNIT, 0x18, MASK_VAL(13, 7, 0x0)), // BSCHCTRL0.ISOC_BANK_PREFETCH +E(BUNIT, 0x18, MASK_VAL(6, 0, 0x20)), // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH +E(BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)), // BDEBUG0.CASUAL_TIMER +E(BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)), // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC +E(BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)), // BDEBUG0.CASUAL_WATER_MARK +E(BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)), // BDEBUG1.AGENT_WEIGHT_ENABLE +E(BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)), // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH +E(BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)), // BDEBUG1.ENABLE_DRAM_SELF_RFRSH +E(BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)), // BCTRL.BANK_STATUS_ENABLE +E(BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)), // BCTRL.DISABLE_OWNED +E(BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)), // BCTRL.INORDER_READ_ENABLE +E(BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)), // BCTRL.INORDER_FLUSH_ENABLE +E(BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)), // BCTRL.MISS_VALID_ENTRIES +E(BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)), // BCTRL.DIRTY_STALL +E(BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)), // BCTRL.SINGLE_TAG_ACCESS +E(BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)), // BCTRL.SINGLE_CHUNK_ACCESS +E(BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)), // BCTRL.BECLK_GATE_EN +E(BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)), // BCTRL.MASTERCLK_GATE_EN +E(BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)), // BCTRL.REQUESTCLK_GATE_EN +E(BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)), // BTHCTRL.AGENT_THROTTLING_ENABLE +E(BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)), // BTHCTRL.RANK_SELECTION_MASK +E(BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)), // BTHMASK.ORWRITE_MASK +E(BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)), // BTHMASK.ORREAD_MASK +E(BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)), // BTHMASK.ERWRITE_MASK +E(BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)), // BTHMASK.ERREAD_MASK + //0x02, 0x0, 2, 0, 0x1, //T_INTR_REDIR_CTL.REDIR_MODE_SEL +E(CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)), // T_CTL.SPLIT_GOIWP_MODE +E(CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)), // T_CTL.DISABLE_TRDY_RDGO +E(CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)), // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN +E(CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)), // T_CTL.ENABLE_NPC_COLLECTOR +E(CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)), // T_CTL.ENABLE_IN_ORDER_APIC +E(CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)), // T_CTL.TG_HIGHPRI_WRITE_PULLS + //0x02, 0x3, 12, 12, 0x1, // T_CTL.TG_NDRAMSNP +E(CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)), // T_CTL.TG_DW_POST_PUSH_LOG +E(CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)), // T_CTL.ALWAYS_SNP_IDI +E(CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)), // T_CTL.DIS_LIVE_BRAM_BYP_IDI +E(CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)), // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE +E(CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)), // T_MISC_CTL.DPTE_CNT +E(CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)), // T_MISC_CTL.DPTE_EN +E(CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)), // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)), // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)), // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)), // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)), // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)), // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)), // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)), // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)), // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)), // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)), // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)), // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)), // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)), // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)), // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)), // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)), // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)), // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)), // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)), // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)), // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)), // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)), // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)), // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)), // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)), // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x55, 0x54, MASK_VAL(1, 0, 0x0)), // SMB_Config_PMCSR.PS +E(0x55, 0x0FC, MASK_VAL(17, 17, 0x0)), // SMB_Config_CGC.FUNC_CLK_CGD +E(0x55, 0x0FC, MASK_VAL(9, 9, 0x0)), // SMB_Config_CGC.SB_LOCAL_CGD +E(0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x47, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x45, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x46, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(PMC, 0x0, MASK_VAL(11, 11, 0x1)), // PUNIT_CONTROL.MODE_DEMOTE_EN +E(PMC, 0x0, MASK_VAL(10, 10, 0x1)), // PUNIT_CONTROL.CORE_DEMOTE_EN + + // + //s0ix_PnP_Settings + // +E(0x58, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en +E(0x58, 0x1e0, MASK_VAL(0, 0, 0x0)), //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en +E(0x58, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en +E(0x58, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en +E(0x58, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en +E(0x58, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en +E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate +E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 +E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en +E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en +E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en +E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en +E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en +E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en +E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on +E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en +E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en +E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en +E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en +E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en +E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en +E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel +E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e +E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc +E(0x5a, 0x40, MASK_VAL(18, 18, 0x1)), //vlv.usb.xhci.controller.xhcc1.xhcil1e +E(0x5a, 0x50, MASK_VAL(3, 3, 0x1)), //vlv.usb.xhci.controller.xhclkgten.hsltcge +E(0x5a, 0x50, MASK_VAL(0, 0, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfblcge +E(0x5a, 0x50, MASK_VAL(1, 1, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfbtcge +E(0x5a, 0x50, MASK_VAL(2, 2, 0x1)), //vlv.usb.xhci.controller.xhclkgten.ssltcge +E(0x5a, 0x50, MASK_VAL(7, 5, 0x2)), //vlv.usb.xhci.controller.xhclkgten.sspllsue +E(0x5a, 0x50, MASK_VAL(13, 13, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso +E(0x5a, 0x50, MASK_VAL(4, 4, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcblcge +E(0x5a, 0x50, MASK_VAL(14, 14, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcftclkse +E(0x5a, 0x50, MASK_VAL(12, 12, 0x0)), //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe +E(0x5a, 0x50, MASK_VAL(11, 10, 0x3)), //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle +E(SCORE, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten +E(SSUS, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten +E(LPSS, 0x180, MASK_VAL(1, 1, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en +E(LPSS, 0x180, MASK_VAL(4, 4, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(0, 0, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable +E(LPSS, 0x180, MASK_VAL(3, 3, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(5, 5, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(2, 2, 0x1)), //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable + //0x54, 0xfc, 31, 0, 0x0, //vlv.pcu.iosfahbep.clock_gating_control + //0x55, 0xfc, 1, 1, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd + //0x55, 0xfc, 0, 0, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd + //0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd +E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 +E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en +E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en +E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en +E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en +E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en +E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en +E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis +E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis +E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis +E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis +E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis +E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis +E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis +E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis +REG_SCRIPT_END, +}; + + +static void perf_power(void *unused) +{ + printk(BIOS_DEBUG, "Applying perf/power settings.\n"); + reg_script_run(perf_power_settings); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL); diff --git a/src/soc/intel/braswell/placeholders.c b/src/soc/intel/braswell/placeholders.c new file mode 100644 index 0000000..3495c30 --- /dev/null +++ b/src/soc/intel/braswell/placeholders.c @@ -0,0 +1,11 @@ + +#include <arch/acpi.h> +#include <cpu/cpu.h> +#include <device/pci_rom.h> +#include <soc/acpi.h> + + +void smm_init(void) {} + +/* Rmodules don't like weak symbols. */ +u32 map_oprom_vendev(u32 vendev) { return vendev; } diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c new file mode 100644 index 0000000..0678fb7 --- /dev/null +++ b/src/soc/intel/braswell/pmutil.c @@ -0,0 +1,364 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> + +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> + +#if defined(__SMM__) + +static const device_t pcu_dev = PCI_DEV(0, PCU_DEV, 0); + +static inline device_t get_pcu_dev(void) +{ + return pcu_dev; +} + +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> + +static device_t pcu_dev; +static device_t get_pcu_dev(void) +{ + if (pcu_dev == NULL) + pcu_dev = dev_find_slot(0, PCI_DEVFN(PCU_DEV, 0)); + return pcu_dev; +} +#endif + +uint16_t get_pmbase(void) +{ + return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8; +} + +static void print_num_status_bits(int num_bits, uint32_t status, + const char *bit_names[]) +{ + int i; + + if (!status) + return; + + for (i = num_bits - 1; i >= 0; i--) { + if (status & (1 << i)) { + if (bit_names[i]) + printk(BIOS_DEBUG, "%s ", bit_names[i]); + else + printk(BIOS_DEBUG, "BIT%d ", i); + } + } +} + +static void print_status_bits(uint32_t status, const char *bit_names[]) +{ + print_num_status_bits(32, status, bit_names); +} + +static uint32_t print_smi_status(uint32_t smi_sts) +{ + static const char *smi_sts_bits[] = { + [2] = "BIOS", + [4] = "SLP_SMI", + [5] = "APM", + [6] = "SWSMI_TMR", + [8] = "PM1", + [9] = "GPE0", + [12] = "DEVMON", + [13] = "TCO", + [14] = "PERIODIC", + [15] = "ILB", + [16] = "SMBUS_SMI", + [17] = "LEGACY_USB2", + [18] = "INTEL_USB2", + [20] = "PCI_EXP_SMI", + [26] = "SPI", + [28] = "PUNIT", + [29] = "GUNIT", + }; + + if (!smi_sts) + return 0; + + printk(BIOS_DEBUG, "SMI_STS: "); + print_status_bits(smi_sts, smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return smi_sts; +} + +static uint32_t reset_smi_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_sts = inl(pmbase + SMI_STS); + outl(smi_sts, pmbase + SMI_STS); + return smi_sts; +} + +uint32_t clear_smi_status(void) +{ + return print_smi_status(reset_smi_status()); +} + +void enable_smi(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_en = inl(pmbase + SMI_EN); + smi_en |= mask; + outl(smi_en, pmbase + SMI_EN); +} + +void disable_smi(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t smi_en = inl(pmbase + SMI_EN); + smi_en &= ~mask; + outl(smi_en, pmbase + SMI_EN); +} + +void enable_pm1_control(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= mask; + outl(pm1_cnt, pmbase + PM1_CNT); +} + +void disable_pm1_control(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt &= ~mask; + outl(pm1_cnt, pmbase + PM1_CNT); +} + +static uint16_t reset_pm1_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint16_t pm1_sts = inw(pmbase + PM1_STS); + outw(pm1_sts, pmbase + PM1_STS); + return pm1_sts; +} + +static uint16_t print_pm1_status(uint16_t pm1_sts) +{ + static const char *pm1_sts_bits[] = { + [0] = "TMROF", + [5] = "GBL", + [8] = "PWRBTN", + [10] = "RTC", + [11] = "PRBTNOR", + [13] = "USB", + [14] = "PCIEXPWAK", + [15] = "WAK", + }; + + if (!pm1_sts) + return 0; + + printk(BIOS_SPEW, "PM1_STS: "); + print_status_bits(pm1_sts, pm1_sts_bits); + printk(BIOS_SPEW, "\n"); + + return pm1_sts; +} + +uint16_t clear_pm1_status(void) +{ + return print_pm1_status(reset_pm1_status()); +} + +void enable_pm1(uint16_t events) +{ + outw(events, get_pmbase() + PM1_EN); +} + +static uint32_t print_tco_status(uint32_t tco_sts) +{ + static const char *tco_sts_bits[] = { + [3] = "TIMEOUT", + [17] = "SECOND_TO", + }; + + if (!tco_sts) + return 0; + + printk(BIOS_DEBUG, "TCO_STS: "); + print_status_bits(tco_sts, tco_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return tco_sts; +} + +static uint32_t reset_tco_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t tco_sts = inl(pmbase + TCO_STS); + uint32_t tco_en = inl(pmbase + TCO1_CNT); + + outl(tco_sts, pmbase + TCO_STS); + return tco_sts & tco_en; +} + +uint32_t clear_tco_status(void) +{ + return print_tco_status(reset_tco_status()); +} + +void enable_gpe(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe0_en = inl(pmbase + GPE0_EN); + gpe0_en |= mask; + outl(gpe0_en, pmbase + GPE0_EN); +} + +void disable_gpe(uint32_t mask) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe0_en = inl(pmbase + GPE0_EN); + gpe0_en &= ~mask; + outl(gpe0_en, pmbase + GPE0_EN); +} + +void disable_all_gpe(void) +{ + disable_gpe(~0); +} + + +static uint32_t reset_gpe_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t gpe_sts = inl(pmbase + GPE0_STS); + outl(gpe_sts, pmbase + GPE0_STS); + return gpe_sts; +} + +static uint32_t print_gpe_sts(uint32_t gpe_sts) +{ + static const char *gpe_sts_bits[] = { + [1] = "HOTPLUG", + [2] = "SWGPE", + [3] = "PCIE_WAKE0", + [4] = "PUNIT", + [5] = "GUNIT", + [6] = "PCIE_WAKE1", + [7] = "PCIE_WAKE2", + [8] = "PCIE_WAKE3", + [9] = "PCI_EXP", + [10] = "BATLOW", + [13] = "PME_B0", + [16] = "SUS_GPIO_0", + [17] = "SUS_GPIO_1", + [18] = "SUS_GPIO_2", + [19] = "SUS_GPIO_3", + [20] = "SUS_GPIO_4", + [21] = "SUS_GPIO_5", + [22] = "SUS_GPIO_6", + [23] = "SUS_GPIO_7", + [24] = "CORE_GPIO_0", + [25] = "CORE_GPIO_1", + [26] = "CORE_GPIO_2", + [27] = "CORE_GPIO_3", + [28] = "CORE_GPIO_4", + [29] = "CORE_GPIO_5", + [30] = "CORE_GPIO_6", + [31] = "CORE_GPIO_7", + }; + + if (!gpe_sts) + return gpe_sts; + + printk(BIOS_DEBUG, "GPE0a_STS: "); + print_status_bits(gpe_sts, gpe_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return gpe_sts; +} + +uint32_t clear_gpe_status(void) +{ + return print_gpe_sts(reset_gpe_status()); +} + +static uint32_t reset_alt_status(void) +{ + uint16_t pmbase = get_pmbase(); + uint32_t alt_gpio_smi = inl(pmbase + ALT_GPIO_SMI); + outl(alt_gpio_smi, pmbase + ALT_GPIO_SMI); + return alt_gpio_smi; +} + +static uint32_t print_alt_sts(uint32_t alt_gpio_smi) +{ + uint32_t alt_gpio_sts; + static const char *alt_gpio_smi_sts_bits[] = { + [0] = "SUS_GPIO_0", + [1] = "SUS_GPIO_1", + [2] = "SUS_GPIO_2", + [3] = "SUS_GPIO_3", + [4] = "SUS_GPIO_4", + [5] = "SUS_GPIO_5", + [6] = "SUS_GPIO_6", + [7] = "SUS_GPIO_7", + [8] = "CORE_GPIO_0", + [9] = "CORE_GPIO_1", + [10] = "CORE_GPIO_2", + [11] = "CORE_GPIO_3", + [12] = "CORE_GPIO_4", + [13] = "CORE_GPIO_5", + [14] = "CORE_GPIO_6", + [15] = "CORE_GPIO_7", + }; + + /* Status bits are in the upper 16 bits. */ + alt_gpio_sts = alt_gpio_smi >> 16; + if (!alt_gpio_sts) + return alt_gpio_smi; + + printk(BIOS_DEBUG, "ALT_GPIO_SMI: "); + print_num_status_bits(16, alt_gpio_sts, alt_gpio_smi_sts_bits); + printk(BIOS_DEBUG, "\n"); + + return alt_gpio_smi; +} + +uint32_t clear_alt_status(void) +{ + return print_alt_sts(reset_alt_status()); +} + +void clear_pmc_status(void) +{ + uint32_t prsts; + uint32_t gen_pmcon1; + + prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + + /* Clear the status bits. The RPS field is cleared on a 0 write. */ + write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS); + write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts); +} diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c new file mode 100644 index 0000000..8b6d93c --- /dev/null +++ b/src/soc/intel/braswell/ramstage.c @@ -0,0 +1,206 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/cpu.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <stdlib.h> +#include <string.h> + +#include <soc/gpio.h> +#include <soc/lpc.h> +#include <soc/msr.h> +#include <soc/nvs.h> +#include <soc/pattrs.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/ramstage.h> +#include <soc/iosf.h> + +/* Global PATTRS */ +DEFINE_PATTRS; + +#define SHOW_PATTRS 1 + +static void detect_num_cpus(struct pattrs *attrs) +{ + int ecx = 0; + + while (1) { + struct cpuid_result leaf_b; + + leaf_b = cpuid_ext(0xb, ecx); + + /* Bay Trail doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2). */ + if ((leaf_b.ecx & 0xff00) == 0x0200) { + attrs->num_cpus = leaf_b.ebx & 0xffff; + break; + } + ecx++; + } +} + +static inline void fill_in_msr(msr_t *msr, int idx) +{ + *msr = rdmsr(idx); + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "msr(%x) = %08x%08x\n", + idx, msr->hi, msr->lo); + } +} + +static const char *stepping_str[] = { + "A0", "A1", "B0", "B1", "B2", "B3", "C0" +}; + +static void fill_in_pattrs(void) +{ + device_t dev; + msr_t msr; + struct pattrs *attrs = (struct pattrs *)pattrs_get(); + + attrs->cpuid = cpuid_eax(1); + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + attrs->revid = pci_read_config8(dev, REVID); + /* The revision to stepping IDs have two values per metal stepping. */ + if (attrs->revid >= RID_C_STEPPING_START) { + attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2; + attrs->stepping += STEP_C0; + } else if (attrs->revid >= RID_B_STEPPING_START) { + attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2; + attrs->stepping += STEP_B0; + } else { + attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2; + attrs->stepping += STEP_A0; + } + + attrs->microcode_patch = intel_microcode_find(); + attrs->address_bits = cpuid_eax(0x80000008) & 0xff; + detect_num_cpus(attrs); + + if (SHOW_PATTRS) { + printk(BIOS_DEBUG, "BYT: cpuid %08x cpus %d rid %02x step %s\n", + attrs->cpuid, attrs->num_cpus, attrs->revid, + (attrs->stepping >= ARRAY_SIZE(stepping_str)) ? "??" : + stepping_str[attrs->stepping]); + } + + fill_in_msr(&attrs->platform_id, MSR_IA32_PLATFORM_ID); + fill_in_msr(&attrs->platform_info, MSR_PLATFORM_INFO); + + /* Set IA core speed ratio and voltages */ + msr = rdmsr(MSR_IACORE_RATIOS); + attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f; + attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f; + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); + attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ + + msr = rdmsr(MSR_IACORE_VIDS); + attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f; + attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f; + attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f; + msr = rdmsr(MSR_IACORE_TURBO_VIDS); + attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */ + + /* Set bus clock speed */ + attrs->bclk_khz = bus_freq_khz(); +} + +/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */ +static void s3_save_acpi_wake_source(global_nvs_t *gnvs) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + uint16_t pm1; + + if (!ps) + return; + + pm1 = ps->pm1_sts & ps->pm1_en; + + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + printk(BIOS_DEBUG, "ACPI System Wake Source is PM1 Index %d\n", + gnvs->pm1i); +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + if (gnvs == NULL) + return; + + if (!acpi_is_wakeup_s3()) + memset(gnvs, 0, sizeof(global_nvs_t)); + else + s3_save_acpi_wake_source(gnvs); +} + +static void baytrail_enable_2x_refresh_rate(void) +{ + u32 reg; + reg = iosf_dunit_read(0x8); + reg = reg & ~0x7000; + reg = reg | 0x2000; + iosf_dunit_write(0x8, reg); +} + +void baytrail_init_pre_device(struct soc_intel_baytrail_config *config) +{ + struct soc_gpio_config *gpio_config; + + fill_in_pattrs(); + + if (!config->disable_ddr_2x_refresh_rate) + baytrail_enable_2x_refresh_rate(); + + /* Allow for SSE instructions to be executed. */ + write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + + /* Run reference code. */ + baytrail_run_reference_code(); + + /* Get GPIO initial states from mainboard */ + gpio_config = mainboard_get_gpios(); + setup_soc_gpios(gpio_config, config->enable_xdp_tap); + + baytrail_init_scc(); +} diff --git a/src/soc/intel/braswell/refcode.c b/src/soc/intel/braswell/refcode.c new file mode 100644 index 0000000..558db3c --- /dev/null +++ b/src/soc/intel/braswell/refcode.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <console/console.h> +#include <console/streams.h> +#include <cpu/x86/tsc.h> +#include <program_loading.h> +#include <rmodule.h> +#include <stage_cache.h> +#if IS_ENABLED(CONFIG_CHROMEOS) +#include <vendorcode/google/chromeos/vboot_handoff.h> +#endif + +#include <soc/ramstage.h> +#include <soc/efi_wrapper.h> + +static void ABI_X86 send_to_console(unsigned char b) +{ + console_tx_byte(b); +} + +static efi_wrapper_entry_t load_refcode_from_cache(void) +{ + struct prog refcode; + + printk(BIOS_DEBUG, "refcode loading from cache.\n"); + + stage_cache_load_stage(STAGE_REFCODE, &refcode); + + return (efi_wrapper_entry_t)prog_entry(&refcode); +} + +static void cache_refcode(const struct rmod_stage_load *rsl) +{ + stage_cache_add(STAGE_REFCODE, rsl->prog); +} + +#if IS_ENABLED(CONFIG_CHROMEOS) +static int load_refcode_from_vboot(struct rmod_stage_load *refcode) +{ + struct vboot_handoff *vboot_handoff; + const struct firmware_component *fwc; + struct cbfs_stage *stage; + + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + fwc = &vboot_handoff->components[CONFIG_VBOOT_REFCODE_INDEX]; + + if (vboot_handoff == NULL || + vboot_handoff->selected_firmware == VB_SELECT_FIRMWARE_READONLY || + CONFIG_VBOOT_REFCODE_INDEX >= MAX_PARSED_FW_COMPONENTS || + fwc->size == 0 || fwc->address == 0) + return -1; + + printk(BIOS_DEBUG, "refcode loading from vboot rw area.\n"); + stage = (void *)(uintptr_t)fwc->address; + + if (rmodule_stage_load(refcode, stage)) { + printk(BIOS_DEBUG, "Error loading reference code.\n"); + return -1; + } + return 0; +} +#else +static int load_refcode_from_vboot(struct rmod_stage_load *refcode) +{ + return -1; +} +#endif + +static int load_refcode_from_cbfs(struct rmod_stage_load *refcode) +{ + printk(BIOS_DEBUG, "refcode loading from cbfs.\n"); + + if (rmodule_stage_load_from_cbfs(refcode)) { + printk(BIOS_DEBUG, "Error loading reference code.\n"); + return -1; + } + + return 0; +} + +static efi_wrapper_entry_t load_reference_code(void) +{ + struct prog prog = { + .name = CONFIG_CBFS_PREFIX "/refcode", + }; + struct rmod_stage_load refcode = { + .cbmem_id = CBMEM_ID_REFCODE, + .prog = &prog, + }; + + if (acpi_is_wakeup_s3()) { + return load_refcode_from_cache(); + } + + if (load_refcode_from_vboot(&refcode) || + load_refcode_from_cbfs(&refcode)) + return NULL; + + /* Cache loaded reference code. */ + cache_refcode(&refcode); + + return prog_entry(&prog); +} + +void baytrail_run_reference_code(void) +{ + int ret; + efi_wrapper_entry_t entry; + struct efi_wrapper_params wrp = { + .version = EFI_WRAPPER_VER, + .console_out = send_to_console, + }; + + entry = load_reference_code(); + + if (entry == NULL) + return; + + wrp.tsc_ticks_per_microsecond = tsc_freq_mhz(); + + /* Call into reference code. */ + ret = entry(&wrp); + + if (ret != 0) { + printk(BIOS_DEBUG, "Reference code returned %d\n", ret); + return; + } +} diff --git a/src/soc/intel/braswell/reset.c b/src/soc/intel/braswell/reset.c new file mode 100644 index 0000000..c4cb2ab --- /dev/null +++ b/src/soc/intel/braswell/reset.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/pmc.h> +#include <soc/reset.h> + +void cold_reset(void) +{ + /* S0->S5->S0 trip. */ + outb(RST_CPU | SYS_RST | FULL_RST, RST_CNT); +} + +void warm_reset(void) +{ + /* PMC_PLTRST# asserted. */ + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void soft_reset(void) +{ + /* Sends INIT# to CPU */ + outb(RST_CPU, RST_CNT); +} + +void hard_reset(void) +{ + /* Don't power cycle on hard_reset(). It's not really clear what the + * semantics should be for the meaning of hard_reset(). */ + warm_reset(); +} diff --git a/src/soc/intel/braswell/romstage/Makefile.inc b/src/soc/intel/braswell/romstage/Makefile.inc new file mode 100644 index 0000000..345037d --- /dev/null +++ b/src/soc/intel/braswell/romstage/Makefile.inc @@ -0,0 +1,7 @@ +cpu_incs += $(src)/soc/intel/baytrail/romstage/cache_as_ram.inc +romstage-y += romstage.c +romstage-y += raminit.c +romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c +romstage-y += gfx.c +romstage-y += pmc.c +romstage-y += early_spi.c \ No newline at end of file diff --git a/src/soc/intel/braswell/romstage/cache_as_ram.inc b/src/soc/intel/braswell/romstage/cache_as_ram.inc new file mode 100644 index 0000000..b6fcbf2 --- /dev/null +++ b/src/soc/intel/braswell/romstage/cache_as_ram.inc @@ -0,0 +1,285 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> +#include <cbmem.h> + +/* The full cache-as-ram size includes the cache-as-ram portion from coreboot + * and the space used by the reference code. These 2 values combined should + * be a power of 2 because the MTRR setup assumes that. */ +#define CACHE_AS_RAM_SIZE \ + (CONFIG_DCACHE_RAM_SIZE + CONFIG_DCACHE_RAM_MRC_VAR_SIZE) +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + +/* Cache all of CBFS just below 4GiB as Write-Protect type. */ +#define CODE_CACHE_SIZE (CONFIG_CBFS_SIZE) +#define CODE_CACHE_BASE (-CODE_CACHE_SIZE) +#define CODE_CACHE_MASK (~(CODE_CACHE_SIZE - 1)) +#define CPU_PHYSMASK_HI ((1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1) + +#define NoEvictMod_MSR 0x2e0 +#define BBL_CR_CTL3_MSR 0x11e +#define MCG_CAP_MSR 0x179 + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* All CPUs need to be in Wait for SIPI state */ +wait_for_sipi: + movl (%esi), %eax + bt $12, %eax + jc wait_for_sipi + + post_code(0x21) + /* Configure the default memory type to uncacheable as well as disable + * fixed and variable range mtrrs. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + post_code(0x22) + /* Zero the variable MTRRs. */ + movl $MCG_CAP_MSR, %ecx + rdmsr + movzx %al, %ebx + /* First variable MTRR. */ + movl $0x200, %ecx + xorl %eax, %eax + xorl %edx, %edx + 1: + wrmsr + inc %ecx + dec %ebx + jnz 1b + + /* Zero out all fixed range and variable range MTRRs. */ + movl $fixed_mtrr_table, %esi + movl $((fixed_mtrr_table_end - fixed_mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx + 1: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz 1b + + post_code(0x23) + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + post_code(0x24) + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x25) + /* Set code caching up for romstage. */ + movl $(MTRRphysBase_MSR(1)), %ecx + movl $(CODE_CACHE_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + + movl $(MTRRphysMask_MSR(1)), %ecx + movl $(CODE_CACHE_MASK | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x26) + + /* Enable the L2 cache. */ + movl $BBL_CR_CTL3_MSR, %ecx + rdmsr + orl $0x100, %eax + wrmsr + + post_code(0x27) + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax + invd + movl %eax, %cr0 + + /* enable the 'no eviction' mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $1, %eax + wrmsr + + post_code(0x28) + + /* Clear the cache memory region. This will also fill up the cache */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + xorl %eax, %eax + rep stosl + + /* enable no evict mode */ + movl $NoEvictMod_MSR, %ecx + rdmsr + orl $2, %eax + wrmsr + + post_code(0x29) + + /* Setup the stack. */ + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax + movl %eax, %esp + + /* Push the initial TSC value from boot block. The low 32 bits are + * in mm0, and the high 32 bits are in mm1. */ + movd %mm1, %eax + pushl %eax + movd %mm0, %eax + pushl %eax + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + +before_romstage: + post_code(0x2a) + /* Call romstage.c main function. */ + call romstage_main + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ + movl %eax, %ebx + + post_code(0x2b) + + /* Disable cache. */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + post_code(0x2c) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + invd + + post_code(0x2d) + + /* Disable the no eviction run state */ + movl $NoEvictMod_MSR, %ecx + rdmsr + andl $~2, %eax + wrmsr + + /* Disable the no eviction mode */ + rdmsr + andl $~1, %eax + wrmsr + + post_code(0x2e) + + /* Setup stack as indicated by return value from ramstage_main(). */ + movl %ebx, %esp + + /* Get number of MTRRs. */ + popl %ebx + movl $MTRRphysBase_MSR(0), %ecx +1: + testl %ebx, %ebx + jz 1f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ + wrmsr + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ + wrmsr + inc %ecx + + dec %ebx + jmp 1b +1: + post_code(0x2f) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax + movl %eax, %cr0 + + post_code(0x30) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x31) + +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + call romstage_after_car + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +/* Fixed MTRRs */ +fixed_mtrr_table: + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F +fixed_mtrr_table_end: + diff --git a/src/soc/intel/braswell/romstage/early_spi.c b/src/soc/intel/braswell/romstage/early_spi.c new file mode 100644 index 0000000..2c48af1 --- /dev/null +++ b/src/soc/intel/braswell/romstage/early_spi.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <delay.h> +#include <console/console.h> + +#include <soc/iomap.h> +#include <soc/romstage.h> +#include <soc/spi.h> + +#define SPI_CYCLE_DELAY 10 /* 10us */ +#define SPI_CYCLE_TIMEOUT 400000 / SPI_CYCLE_DELAY /* 400ms */ + +#define SPI8(x) *((volatile u8 *)(SPI_BASE_ADDRESS + x)) +#define SPI16(x) *((volatile u16 *)(SPI_BASE_ADDRESS + x)) +#define SPI32(x) *((volatile u32 *)(SPI_BASE_ADDRESS + x)) + +/* Minimal set of commands to read wpsr from SPI. Don't use this code outside + * romstage -- it trashes the opmenu table. + * Returns 0 on success, < 0 on failure. */ +int early_spi_read_wpsr(u8 *sr) +{ + int timeout = SPI_CYCLE_TIMEOUT; + + /* No address associated with rdsr */ + SPI8(OPTYPE) = 0x0; + /* Setup opcode[0] = read wpsr */ + SPI8(OPMENU0) = 0x5; + + /* Start transaction */ + SPI16(SSFC) = DATA_CYCLE | SPI_CYCLE_GO; + + /* Wait for error / complete status */ + while(timeout--) { + u16 status = SPI16(SSFS); + if (status & FLASH_CYCLE_ERROR) { + printk(BIOS_ERR, "SPI rdsr failed\n"); + return -1; + } else if (status & CYCLE_DONE_STATUS) + break; + + udelay(SPI_CYCLE_DELAY); + } + + *sr = SPI32(FDATA0) & 0xff; + return 0; +} diff --git a/src/soc/intel/braswell/romstage/gfx.c b/src/soc/intel/braswell/romstage/gfx.c new file mode 100644 index 0000000..f9bb9c9 --- /dev/null +++ b/src/soc/intel/braswell/romstage/gfx.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gfx.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void gfx_init(void) +{ + uint32_t ggc; + uint8_t msac; + const unsigned int gfx_dev = PCI_DEV(0, GFX_DEV, GFX_FUNC); + + /* The GFX device needs to set the aperture, gtt stolen size, and + * graphics stolen memory stolen size before running MRC. For now + * just hard code the defaults. Options can be added to the device + * tree if needed. */ + + ggc = pci_read_config32(gfx_dev, GGC); + msac = pci_read_config8(gfx_dev, MSAC); + + ggc &= ~(GGC_GTT_SIZE_MASK | GGC_GSM_SIZE_MASK); + /* 32MB GSM is not supported with <C0 stepping. */ + ggc |= GGC_GTT_SIZE_2MB | GGC_GSM_SIZE_64MB; + /* Enable VGA decoding as well. */ + ggc &= ~(GGC_VGA_DISABLE); + + msac &= ~(APERTURE_SIZE_MASK); + msac |= APERTURE_SIZE_256MB; + + pci_write_config32(gfx_dev, GGC, ggc); + pci_write_config8(gfx_dev, MSAC, msac); +} diff --git a/src/soc/intel/braswell/romstage/pmc.c b/src/soc/intel/braswell/romstage/pmc.c new file mode 100644 index 0000000..b41359b --- /dev/null +++ b/src/soc/intel/braswell/romstage/pmc.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/romstage.h> +#include "../chip.h" + +void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +/* This sequence signals the PUNIT to start running. */ +void punit_init(void) +{ + uint32_t reg; + uint8_t rid; + const struct device *dev; + const struct soc_intel_baytrail_config *cfg = NULL; + + rid = pci_read_config8(IOSF_PCI_DEV, REVID); + dev = dev_find_slot(0, PCI_DEVFN(SOC_DEV, SOC_FUNC)); + + if (dev) + cfg = dev->chip_info; + + reg = iosf_punit_read(SB_BIOS_CONFIG); + /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ + reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; + /* Configure VR low power mode for C0 and above. */ + if (rid >= RID_C_STEPPING_START && cfg != NULL && + (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { + printk(BIOS_DEBUG, "Enabling VR PS2 mode: "); + if (cfg->vnn_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VNN; + printk(BIOS_DEBUG, "VNN "); + } + if (cfg->vcc_ps2_enable) { + reg |= SB_BIOS_CONFIG_PS2_EN_VCC; + printk(BIOS_DEBUG, "VCC "); + } + printk(BIOS_DEBUG, "\n"); + } + iosf_punit_write(SB_BIOS_CONFIG, reg); + + /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ + reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; + pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); + reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | + IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; + pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); +} diff --git a/src/soc/intel/braswell/romstage/raminit.c b/src/soc/intel/braswell/romstage/raminit.c new file mode 100644 index 0000000..61c122c --- /dev/null +++ b/src/soc/intel/braswell/romstage/raminit.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/io.h> +#include <bootmode.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <halt.h> +#include <stage_cache.h> +#include <soc/gpio.h> +#include <soc/intel/common/mrc_cache.h> +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/reset.h> +#include <soc/romstage.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> + +static void reset_system(void) +{ + warm_reset(); + halt(); +} + +static void enable_smbus(void) +{ + uint32_t reg; + const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); + + /* SMBus I/O BAR */ + reg = SMBUS_BASE_ADDRESS | 2; + pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); + /* Enable decode of I/O space. */ + reg = pci_read_config16(smbus_dev, PCI_COMMAND); + reg |= 0x1; + pci_write_config16(smbus_dev, PCI_COMMAND, reg); + /* Enable Host Controller */ + reg = pci_read_config8(smbus_dev, 0x40); + reg |= 1; + pci_write_config8(smbus_dev, 0x40, reg); + + /* Configure pads to be used for SMBus */ + score_select_func(PCU_SMB_CLK_PAD, 1); + score_select_func(PCU_SMB_DATA_PAD, 1); +} + +static void ABI_X86 send_to_console(unsigned char b) +{ + do_putchar(b); +} + +static void print_dram_info(void) +{ + const int mrc_ver_reg = 0xf0; + const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC); + uint32_t reg; + int num_channels; + int speed; + uint32_t ch0; + uint32_t ch1; + + reg = pci_read_config32(soc_dev, mrc_ver_reg); + + printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff); + + /* Number of channels enabled and DDR3 type. Determine number of + * channels by keying of the rank enable bits [3:0]. * */ + ch0 = iosf_dunit_ch0_read(DRP); + ch1 = iosf_dunit_ch1_read(DRP); + num_channels = 0; + if (ch0 & DRP_RANK_MASK) + num_channels++; + if (ch1 & DRP_RANK_MASK) + num_channels++; + + printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels, + (reg & (1 << 22)) ? "LP" : ""); + + /* DRAM frequency -- all channels run at same frequency. */ + reg = iosf_dunit_read(DTR0); + switch (reg & 0x3) { + case 0: + speed = 800; break; + case 1: + speed = 1066; break; + case 2: + speed = 1333; break; + case 3: + speed = 1600; break; + } + printk(BIOS_INFO, "%dMHz\n", speed); +} + +void raminit(struct mrc_params *mp, int prev_sleep_state) +{ + int ret; + mrc_wrapper_entry_t mrc_entry; + const struct mrc_saved_data *cache; + + /* Fill in default entries. */ + mp->version = MRC_PARAMS_VER; + mp->console_out = &send_to_console; + mp->prev_sleep_state = prev_sleep_state; + mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); + + /* Default to 2GiB IO hole. */ + if (!mp->io_hole_mb) + mp->io_hole_mb = 2048; + + if (recovery_mode_enabled()) { + printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); + } else if (!mrc_cache_get_current(&cache)) { + mp->saved_data_size = cache->size; + mp->saved_data = &cache->data[0]; + } else if (prev_sleep_state == 3) { + /* If waking from S3 and no cache then. */ + printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + reset_system(); + } else { + printk(BIOS_DEBUG, "No MRC cache found.\n"); +#if CONFIG_EC_GOOGLE_CHROMEEC + if (prev_sleep_state == 0) { + /* Ensure EC is running RO firmware. */ + google_chromeec_check_ec_image(EC_IMAGE_RO); + } +#endif + } + + /* Determine if mrc.bin is in the cbfs. */ + if (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, + NULL) == NULL) { + printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); + return; + } + + /* + * The entry point is currently the first instruction. Handle the + * case of an ELF file being put in the cbfs by setting the entry + * to the CONFIG_MRC_BIN_ADDRESS. + */ + mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS; + + if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) + enable_smbus(); + + ret = mrc_entry(mp); + + print_dram_info(); + + if (prev_sleep_state != 3) { + cbmem_initialize_empty(); + stage_cache_create_empty(); + } else { + stage_cache_recover(); + if (cbmem_initialize()) { + #if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + reset_system(); + #endif + } + } + + printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, + mp->data_to_save_size); + + if (mp->data_to_save != NULL && mp->data_to_save_size > 0) + mrc_cache_stash_data(mp->data_to_save, mp->data_to_save_size); +} diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c new file mode 100644 index 0000000..9c8bbc4 --- /dev/null +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -0,0 +1,377 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <arch/early_variables.h> +#include <console/console.h> +#include <cbfs.h> +#include <cbmem.h> +#include <cpu/x86/mtrr.h> +#if CONFIG_EC_GOOGLE_CHROMEEC +#include <ec/google/chromeec/ec.h> +#endif +#include <elog.h> +#include <romstage_handoff.h> +#include <stage_cache.h> +#include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/reset.h> +#include <soc/romstage.h> +#include <soc/smm.h> +#include <soc/spi.h> + +/* The cache-as-ram assembly file calls romstage_main() after setting up + * cache-as-ram. romstage_main() will then call the mainboards's + * mainboard_romstage_entry() function. That function then calls + * romstage_common() below. The reason for the back and forth is to provide + * common entry point from cache-as-ram while still allowing for code sharing. + * Because we can't use global variables the stack is used for allocations -- + * thus the need to call back and forth. */ + +static void *setup_stack_and_mttrs(void); + +static void program_base_addresses(void) +{ + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); +} + +static void spi_init(void) +{ + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; + + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); +} + +/* Entry from cache-as-ram.inc. */ +void * asmlinkage romstage_main(unsigned long bist, + uint32_t tsc_low, uint32_t tsc_hi) +{ + struct romstage_params rp = { + .bist = bist, + .mrc_params = NULL, + }; + + /* Save initial timestamp from bootblock. */ + timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + + /* Save romstage begin */ + timestamp_add_now(TS_START_ROMSTAGE); + + program_base_addresses(); + + tco_disable(); + + byt_config_com1_and_enable(); + + console_init(); + + spi_init(); + + set_max_freq(); + + punit_init(); + + gfx_init(); + +#if CONFIG_EC_GOOGLE_CHROMEEC + /* Ensure the EC is in the right mode for recovery */ + google_chromeec_early_init(); +#endif + + /* Call into mainboard. */ + mainboard_romstage_entry(&rp); + + return setup_stack_and_mttrs(); +} + +static struct chipset_power_state power_state CAR_GLOBAL; + +static void migrate_power_state(void) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +CAR_MIGRATE(migrate_power_state); + +static struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); + ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); + ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS)); + ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2)); + + printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", + ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", + ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); + + return ps; +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +static int chipset_prev_sleep_state(struct chipset_power_state *ps) +{ + /* Default to S0. */ + int prev_sleep_state = 0; + + if (ps->pm1_sts & WAK_STS) { + switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if CONFIG_HAVE_ACPI_RESUME + case SLP_TYP_S3: + prev_sleep_state = 3; + break; + #endif + case SLP_TYP_S5: + prev_sleep_state = 5; + break; + } + /* Clear SLP_TYP. */ + outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + } + + if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { + prev_sleep_state = 5; + } + + return prev_sleep_state; +} + +static inline void chromeos_init(int prev_sleep_state) +{ +#if CONFIG_CHROMEOS + /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ + init_chromeos(prev_sleep_state == 3 ? 2 : 0); +#endif +} + +/* Entry from the mainboard. */ +void romstage_common(struct romstage_params *params) +{ + struct romstage_handoff *handoff; + struct chipset_power_state *ps; + int prev_sleep_state; + + timestamp_add_now(TS_BEFORE_INITRAM); + + ps = fill_power_state(); + prev_sleep_state = chipset_prev_sleep_state(ps); + + printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); + +#if CONFIG_ELOG_BOOT_COUNT + if (prev_sleep_state != 3) + boot_count_increment(); +#endif + + + /* Initialize RAM */ + raminit(params->mrc_params, prev_sleep_state); + + timestamp_add_now(TS_AFTER_INITRAM); + + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == 3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + chromeos_init(prev_sleep_state); +} + +void asmlinkage romstage_after_car(void) +{ + timestamp_add_now(TS_END_ROMSTAGE); + + /* Load the ramstage. */ + copy_and_run(); + while (1); +} + +static inline uint32_t *stack_push(u32 *stack, u32 value) +{ + stack = &stack[-1]; + *stack = value; + return stack; +} + +/* Romstage needs quite a bit of stack for decompressing images since the lzma + * lib keeps its state on the stack during romstage. */ +static unsigned long choose_top_of_stack(void) +{ + unsigned long stack_top; + const unsigned long romstage_ram_stack_size = 0x5000; + + /* cbmem_add() does a find() before add(). */ + stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + romstage_ram_stack_size); + stack_top += romstage_ram_stack_size; + return stack_top; +} + +/* setup_stack_and_mttrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +static void *setup_stack_and_mttrs(void) +{ + unsigned long top_of_stack; + int num_mtrrs; + uint32_t *slot; + uint32_t mtrr_mask_upper; + uint32_t top_of_ram; + + /* Top of stack needs to be aligned to a 4-byte boundary. */ + top_of_stack = choose_top_of_stack() & ~3; + slot = (void *)top_of_stack; + num_mtrrs = 0; + + /* The upper bits of the MTRR mask need to set according to the number + * of physical address bits. */ + mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; + + /* The order for each MTRR is value then base with upper 32-bits of + * each value coming before the lower 32-bits. The reasoning for + * this ordering is to create a stack layout like the following: + * +0: Number of MTRRs + * +4: MTRR base 0 31:0 + * +8: MTRR base 0 63:32 + * +12: MTRR mask 0 31:0 + * +16: MTRR mask 0 63:32 + * +20: MTRR base 1 31:0 + * +24: MTRR base 1 63:32 + * +28: MTRR mask 1 31:0 + * +32: MTRR mask 1 63:32 + */ + + /* Cache the ROM as WP just below 4GiB. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); + num_mtrrs++; + + /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); + num_mtrrs++; + + top_of_ram = (uint32_t)cbmem_top(); + /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the + * start of the TSEG region. It is required to be 8MiB aligned. Set + * this area as cacheable so it can be used later for ramstage before + * setting up the entire RAM as cacheable. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* Cache 8MiB at the top of ram. Top of ram is where the TSEG + * region resides. However, it is not restricted to SMM mode until + * SMM has been relocated. By setting the region to cacheable it + * provides faster access when relocating the SMM handler as well + * as using the TSEG region for other purposes. */ + slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ + slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); + slot = stack_push(slot, 0); /* upper base */ + slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); + num_mtrrs++; + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. */ + slot = stack_push(slot, num_mtrrs); + + return slot; +} + +void ramstage_cache_invalid(void) +{ +#if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE + /* Perform cold reset on invalid ramstage cache. */ + cold_reset(); +#endif +} + +#if CONFIG_CHROMEOS +int vboot_get_sw_write_protect(void) +{ + u8 status; + /* Return unprotected status if status read fails. */ + return (early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80)); +} +#endif diff --git a/src/soc/intel/braswell/romstage/uart.c b/src/soc/intel/braswell/romstage/uart.c new file mode 100644 index 0000000..7705746 --- /dev/null +++ b/src/soc/intel/braswell/romstage/uart.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void byt_config_com1_and_enable(void) +{ + uint32_t reg; + + /* Enable the UART hardware for COM1. */ + reg = 1; + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + + /* Set up the pads to select the UART function */ + score_select_func(UART_RXD_PAD, 1); + score_select_func(UART_TXD_PAD, 1); +} diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c new file mode 100644 index 0000000..5294207 --- /dev/null +++ b/src/soc/intel/braswell/sata.c @@ -0,0 +1,240 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <soc/sata.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include "chip.h" + +typedef struct soc_intel_baytrail_config config_t; + +static inline void sir_write(struct device *dev, int idx, u32 value) +{ + pci_write_config32(dev, SATA_SIRI, idx); + pci_write_config32(dev, SATA_SIRD, value); +} + +static void sata_init(struct device *dev) +{ + config_t *config = dev->chip_info; + u32 reg32; + u16 reg16; + u8 reg8; + + printk(BIOS_DEBUG, "SATA: Initializing...\n"); + + if (config == NULL) { + printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n"); + return; + } + + if (!config->sata_ahci) { + /* Set legacy or native decoding mode */ + if (config->ide_legacy_combined) { + reg8 = pci_read_config8(dev, 0x09); + reg8 &= ~0x5; + pci_write_config8(dev, 0x09, reg8); + } else { + reg8 = pci_read_config8(dev, 0x09); + reg8 |= 0x5; + pci_write_config8(dev, 0x09, reg8); + } + + /* Set capabilities pointer */ + pci_write_config8(dev, 0x34, 0x70); + reg16 = pci_read_config16(dev, 0x70); + reg16 &= ~0xFF00; + pci_write_config16(dev, 0x70, reg16); + } + + /* Primary timing - decode enable */ + reg16 = pci_read_config16(dev, 0x40); + reg16 |= 1 << 15; + pci_write_config16(dev, 0x40, reg16); + + /* Secondary timing - decode enable */ + reg16 = pci_read_config16(dev, 0x42); + reg16 |= 1 << 15; + pci_write_config16(dev, 0x42, reg16); + + /* Port mapping enables */ + reg16 = pci_read_config16(dev, 0x90); + reg16 |= (config->sata_port_map ^ 0x3) << 8; + pci_write_config16(dev, 0x90, reg16); + + /* Port control enables */ + reg16 = pci_read_config16(dev, 0x92); + reg16 &= ~0x003f; + reg16 |= config->sata_port_map; + pci_write_config16(dev, 0x92, reg16); + + if (config->sata_ahci) { + u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + /* Enable CR memory space decoding */ + reg16 = pci_read_config16(dev, 0x04); + reg16 |= 0x2; + pci_write_config16(dev, 0x04, reg16); + + /* Set capability register */ + reg32 = read32(abar + 0x00); + reg32 |= 0x0c046000; // set PSC+SSC+SALP+SSS+SAM + reg32 &= ~0x00f20060; // clear SXS+EMS+PMS+gen bits + reg32 |= (0x3 << 20); // Gen3 SATA + write32(abar + 0x00, reg32); + + /* Ports enabled */ + reg32 = read32(abar + 0x0c); + reg32 &= (u32)(~0x3f); + reg32 |= config->sata_port_map; + write32(abar + 0xc, reg32); + /* Two extra reads to latch */ + read32(abar + 0x0c); + read32(abar + 0x0c); + + /* Set cap2 - Support devslp */ + reg32 = (1 << 5) | (1 << 4) | (1 << 3); + write32(abar + 0x24, reg32); + + /* Set PxCMD registers */ + reg32 = read32(abar + 0x118); + reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | + (1 << 19) | (1 << 18) | (1 << 1)); + reg32 |= 2; + write32(abar + 0x118, reg32); + + reg32 = read32(abar + 0x198); + reg32 &= ~((1 << 27) | (1 << 26) | (1 << 22) | (1 << 21) | + (1 << 19) | (1 << 18) | (1 << 1)); + reg32 |= 2; + write32(abar + 0x198, reg32); + + /* Clear reset features */ + write32(abar + 0xc8, 0); + + /* Enable interrupts */ + reg8 = read8(abar + 0x04); + reg8 |= 0x02; + write8(abar + 0x04, reg8); + + } else { + /* TODO(shawnn): Configure IDE SATA speed regs */ + } + + /* 1.4 us delay after configuring port / enable bits */ + udelay(2); + + /* Enable clock for ports */ + reg32 = pci_read_config32(dev, 0x94); + reg32 |= 0x3f << 24; + pci_write_config32(dev, 0x94, reg32); + reg32 &= (config->sata_port_map ^ 0x3) << 24; + pci_write_config32(dev, 0x94, reg32); + + /* Lock SataGc register */ + reg32 = (0x1 << 31) | (0x7 << 12); + pci_write_config32(dev, 0x98, reg32); +} + +static void sata_enable(device_t dev) +{ + config_t *config = dev->chip_info; + u8 reg8; + u16 reg16; + u32 reg32; + + southcluster_enable_dev(dev); + if (!config) + return; + + /* Port mapping -- mask off SPD + SMS + SC bits, then re-set */ + reg16 = pci_read_config16(dev, 0x90); + reg16 &= ~0x03e0; + reg16 |= (config->sata_port_map ^ 0x3) << 8; + if(config->sata_ahci) + reg16 |= 0x60; + pci_write_config16(dev, 0x90, reg16); + + /* Set reg 0x94 before starting configuration */ + reg32 = pci_read_config32(dev, 0x94); + reg32 &= (u32)(~0x1ff); + reg32 |= 0x183; + pci_write_config32(dev, 0x94, reg32); + + /* Set ORM bit */ + reg16 = pci_read_config16(dev, 0x92); + reg16 |= (1 << 15); + pci_write_config16(dev, 0x92, reg16); + + /* R_PCH_SATA_TM2 - Undocumented in EDS, set according to ref. code */ + reg32 = pci_read_config32(dev, 0x98); + reg32 &= (u32)~(0x1f80 | (1 << 6) | (1 << 5)); + reg32 |= (1 << 29) | (1 << 25) | (1 << 23) | (1 << 22) | + (1 << 20) | (1 << 19) | (1 << 18) | (1 << 9) | (1 << 5); + pci_write_config32(dev, 0x98, reg32); + + /* CMD reg - set bus master enable (BME) */ + reg8 = pci_read_config8(dev, 0x04); + reg8 |= (1 << 2); + pci_write_config8(dev, 0x04, reg8); + + /* "Test mode registers" */ + sir_write(dev, 0x70, 0x00288301); + sir_write(dev, 0x54, 0x00000300); + sir_write(dev, 0x58, 0x50000000); + /* "OOB Detection Margin */ + sir_write(dev, 0x6c, 0x130C0603); + /* "Gasket Control" */ + sir_write(dev, 0xf4, 0); + + /* PCS - Enable requested SATA ports */ + reg8 = pci_read_config8(dev, 0x92); + reg8 &= ~0x03; + reg8 |= config->sata_port_map; + pci_write_config8(dev, 0x92, reg8); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sata_init, + .enable = sata_enable, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + IDE1_DEVID, IDE2_DEVID, /* IDE */ + AHCI1_DEVID, AHCI2_DEVID, /* AHCI */ + 0, +}; + +static const struct pci_driver baytrail_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c new file mode 100644 index 0000000..6400996 --- /dev/null +++ b/src/soc/intel/braswell/scc.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iosf.h> +#include <soc/nvs.h> +#include <soc/ramstage.h> + +static const struct reg_script scc_start_dll[] = { + /* Configure master DLL. */ + REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000), + /* Configure Swing,FSM for Master DLL */ + REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133), + /* Run+Local Reset on Master DLL */ + REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933), + REG_SCRIPT_END, +}; + +static const struct reg_script scc_after_dll[] = { + /* Configure Write Path */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad), + /* Configure Read Path */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad), + /* eMMC 4.5 TX and RX DLL */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0), + /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0), + /* + * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 + * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 + */ + REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), + /* Enable IOSF Snoop */ + REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), + /* SDIO 3V Support. */ + REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30), + REG_SCRIPT_END, +}; + +void baytrail_init_scc(void) +{ + uint32_t dll_values; + + printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n"); + + /* Common Sideband Initialization for SCC */ + reg_script_run(scc_start_dll); + + /* Override Slave Path - populate DLL settings. */ + dll_values = iosf_score_read(0x496c) & 0x7ffff; + dll_values |= iosf_score_read(0x4950) & ~0xfffff; + iosf_score_write(0x4950, dll_values | (1 << 19)); + + reg_script_run(scc_after_dll); +} + +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, + SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.scc_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run_on_dev(dev, ops); +} diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c new file mode 100644 index 0000000..577469d --- /dev/null +++ b/src/soc/intel/braswell/sd.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <soc/iosf.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include "chip.h" + +#define CAP_OVERRIDE_LOW 0xa0 +#define CAP_OVERRIDE_HIGH 0xa4 +# define USE_CAP_OVERRIDES (1 << 31) + +static void sd_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + + if (config == NULL) + return; + + if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { + printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); + pci_write_config32(dev, CAP_OVERRIDE_LOW, + config->sdcard_cap_low); + pci_write_config32(dev, CAP_OVERRIDE_HIGH, + config->sdcard_cap_high | USE_CAP_OVERRIDES); + } + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sd_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SD_DEVID, +}; diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c new file mode 100644 index 0000000..3fac525 --- /dev/null +++ b/src/soc/intel/braswell/smihandler.c @@ -0,0 +1,483 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <stdlib.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/smm.h> +#include <device/pci_def.h> +#include <elog.h> +#include <halt.h> +#include <spi-generic.h> + +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/nvs.h> + +/* GNVS needs to be set by coreboot initiating a software SMI. */ +static global_nvs_t *gnvs; +static int smm_initialized; + +int southbridge_io_trap_handler(int smif) +{ + switch (smif) { + case 0x32: + printk(BIOS_DEBUG, "OS Init\n"); + /* gnvs->smif: + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + */ + gnvs->smif = 0; + return 1; /* IO trap handled */ + } + + /* Not handled */ + return 0; +} + +void southbridge_smi_set_eos(void) +{ + enable_smi(EOS); +} + +global_nvs_t *smm_get_gnvs(void) +{ + return gnvs; +} + +static void busmaster_disable_on_bus(int bus) +{ + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } +} + +static void southbridge_smi_sleep(void) +{ + uint32_t reg32; + uint8_t slp_typ; + uint16_t pmbase = get_pmbase(); + + /* First, disable further SMIs */ + disable_smi(SLP_SMI_EN); + + /* Figure out SLP_TYP */ + reg32 = inl(pmbase + PM1_CNT); + printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); + slp_typ = (reg32 >> 10) & 7; + + /* Do any mainboard sleep handling */ + mainboard_smi_sleep(slp_typ-2); + +#if CONFIG_ELOG_GSMI + /* Log S3, S4, and S5 entry */ + if (slp_typ >= 5) + elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2); +#endif + + /* Next, do the deed. + */ + + switch (slp_typ) { + case SLP_TYP_S0: + printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); + break; + case SLP_TYP_S1: + printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); + break; + case SLP_TYP_S3: + printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); + + /* Invalidate the cache before going to S3 */ + wbinvd(); + break; + case SLP_TYP_S4: + printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); + break; + case SLP_TYP_S5: + printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); + + /* Disable all GPE */ + disable_all_gpe(); + + /* also iterates over all bridges on bus 0 */ + busmaster_disable_on_bus(0); + break; + default: + printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); + break; + } + + /* Write back to the SLP register to cause the originally intended + * event again. We need to set BIT13 (SLP_EN) though to make the + * sleep happen. + */ + enable_pm1_control(SLP_EN); + + /* Make sure to stop executing code here for S3/S4/S5 */ + if (slp_typ > 1) + halt(); + + /* In most sleep states, the code flow of this function ends at + * the line above. However, if we entered sleep state S1 and wake + * up again, we will continue to execute code in this function. + */ + reg32 = inl(pmbase + PM1_CNT); + if (reg32 & SCI_EN) { + /* The OS is not an ACPI OS, so we set the state to S0 */ + disable_pm1_control(SLP_EN | SLP_TYP); + } +} + +/* + * Look for Synchronous IO SMI and use save state from that + * core in case we are not running on the same core that + * initiated the IO transaction. + */ +static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd) +{ + em64t100_smm_state_save_area_t *state; + int node; + + /* Check all nodes looking for the one that issued the IO */ + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0==1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4==0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return state; + } + + return NULL; +} + +#if CONFIG_ELOG_GSMI +static void southbridge_smi_gsmi(void) +{ + u32 *ret, *param; + uint8_t sub_command; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(ELOG_GSMI_APM_CNT); + + if (!io_smi) + return; + + /* Command and return value in EAX */ + ret = (u32*)&io_smi->rax; + sub_command = (uint8_t)(*ret >> 8); + + /* Parameter buffer in EBX */ + param = (u32*)&io_smi->rbx; + + /* drivers/elog/gsmi.c */ + *ret = gsmi_exec(sub_command, param); +} +#endif + +static void finalize(void) +{ + static int finalize_done; + + if (finalize_done) { + printk(BIOS_DEBUG, "SMM already finalized.\n"); + return; + } + finalize_done = 1; + +#if CONFIG_SPI_FLASH_SMM + /* Re-init SPI driver to handle locked BAR */ + spi_init(); +#endif +} + +/* + * soc_legacy: A payload (Depthcharge) has indicated that the + * legacy payload (SeaBIOS) is being loaded. Switch devices that are + * in ACPI mode to PCI mode so that non-ACPI drivers may work. + * + */ +static void soc_legacy(void) +{ + u32 reg32; + + /* LPE Device */ + if (gnvs->dev.lpe_en) { + reg32 = iosf_port58_read(LPE_PCICFGCTR1); + reg32 &= + ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN); + iosf_port58_write(LPE_PCICFGCTR1, reg32); + } + + /* SCC Devices */ +#define SCC_ACPI_MODE_DISABLE(name_) \ + do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \ + reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \ + reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \ + iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \ + } } while (0) + + SCC_ACPI_MODE_DISABLE(MMC); + SCC_ACPI_MODE_DISABLE(SD); + SCC_ACPI_MODE_DISABLE(SDIO); + + /* LPSS Devices */ +#define LPSS_ACPI_MODE_DISABLE(name_) \ + do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \ + reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \ + reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \ + iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \ + } } while (0) + + LPSS_ACPI_MODE_DISABLE(SIO_DMA1); + LPSS_ACPI_MODE_DISABLE(I2C1); + LPSS_ACPI_MODE_DISABLE(I2C2); + LPSS_ACPI_MODE_DISABLE(I2C3); + LPSS_ACPI_MODE_DISABLE(I2C4); + LPSS_ACPI_MODE_DISABLE(I2C5); + LPSS_ACPI_MODE_DISABLE(I2C6); + LPSS_ACPI_MODE_DISABLE(I2C7); + LPSS_ACPI_MODE_DISABLE(SIO_DMA2); + LPSS_ACPI_MODE_DISABLE(PWM1); + LPSS_ACPI_MODE_DISABLE(PWM2); + LPSS_ACPI_MODE_DISABLE(HSUART1); + LPSS_ACPI_MODE_DISABLE(HSUART2); + LPSS_ACPI_MODE_DISABLE(SPI); +} + +static void southbridge_smi_apmc(void) +{ + uint8_t reg8; + em64t100_smm_state_save_area_t *state; + + /* Emulate B2 register as the FADT / Linux expects it */ + + reg8 = inb(APM_CNT); + switch (reg8) { + case APM_CNT_CST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "C-state control\n"); + break; + case APM_CNT_PST_CONTROL: + /* Calling this function seems to cause + * some kind of race condition in Linux + * and causes a kernel oops + */ + printk(BIOS_DEBUG, "P-state control\n"); + break; + case APM_CNT_ACPI_DISABLE: + disable_pm1_control(SCI_EN); + printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n"); + break; + case APM_CNT_ACPI_ENABLE: + enable_pm1_control(SCI_EN); + printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n"); + break; + case APM_CNT_GNVS_UPDATE: + if (smm_initialized) { + printk(BIOS_DEBUG, + "SMI#: SMM structures already initialized!\n"); + return; + } + state = smi_apmc_find_state_save(reg8); + if (state) { + /* EBX in the state save contains the GNVS pointer */ + gnvs = (global_nvs_t *)((uint32_t)state->rbx); + smm_initialized = 1; + printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); + } + break; +#if CONFIG_ELOG_GSMI + case ELOG_GSMI_APM_CNT: + southbridge_smi_gsmi(); + break; +#endif + case APM_CNT_FINALIZE: + finalize(); + break; + + case APM_CNT_LEGACY: + soc_legacy(); + break; + } + + mainboard_smi_apmc(reg8); +} + +static void southbridge_smi_pm1(void) +{ + uint16_t pm1_sts = clear_pm1_status(); + + /* While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + // power button pressed +#if CONFIG_ELOG_GSMI + elog_add_event(ELOG_TYPE_POWER_BUTTON); +#endif + disable_pm1_control(-1UL); + enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT)); + } +} + +static void southbridge_smi_gpe0(void) +{ + clear_gpe_status(); +} + +static void southbridge_smi_tco(void) +{ + uint32_t tco_sts = clear_tco_status(); + + /* Any TCO event? */ + if (!tco_sts) + return; + + if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ + /* Handle TCO timeout */ + printk(BIOS_DEBUG, "TCO Timeout.\n"); + } +} + +static void southbridge_smi_periodic(void) +{ + uint32_t reg32; + + reg32 = inl(get_pmbase() + SMI_EN); + + /* Are periodic SMIs enabled? */ + if ((reg32 & PERIODIC_EN) == 0) + return; + + printk(BIOS_DEBUG, "Periodic SMI.\n"); +} + +typedef void (*smi_handler_t)(void); + +static const smi_handler_t southbridge_smi[32] = { + NULL, // [0] reserved + NULL, // [1] reserved + NULL, // [2] BIOS_STS + NULL, // [3] LEGACY_USB_STS + southbridge_smi_sleep, // [4] SLP_SMI_STS + southbridge_smi_apmc, // [5] APM_STS + NULL, // [6] SWSMI_TMR_STS + NULL, // [7] reserved + southbridge_smi_pm1, // [8] PM1_STS + southbridge_smi_gpe0, // [9] GPE0_STS + NULL, // [10] reserved + NULL, // [11] reserved + NULL, // [12] reserved + southbridge_smi_tco, // [13] TCO_STS + southbridge_smi_periodic, // [14] PERIODIC_STS + NULL, // [15] SERIRQ_SMI_STS + NULL, // [16] SMBUS_SMI_STS + NULL, // [17] LEGACY_USB2_STS + NULL, // [18] INTEL_USB2_STS + NULL, // [19] reserved + NULL, // [20] PCI_EXP_SMI_STS + NULL, // [21] reserved + NULL, // [22] reserved + NULL, // [23] reserved + NULL, // [24] reserved + NULL, // [25] reserved + NULL, // [26] SPI_STS + NULL, // [27] reserved + NULL, // [28] PUNIT + NULL, // [29] GUNIT + NULL, // [30] reserved + NULL // [31] reserved +}; + +void southbridge_smi_handler(void) +{ + int i; + uint32_t smi_sts; + + /* We need to clear the SMI status registers, or we won't see what's + * happening in the following calls. + */ + smi_sts = clear_smi_status(); + + /* Call SMI sub handler for each of the status bits */ + for (i = 0; i < ARRAY_SIZE(southbridge_smi); i++) { + if (!(smi_sts & (1 << i))) + continue; + + if (southbridge_smi[i] != NULL) { + southbridge_smi[i](); + } else { + printk(BIOS_DEBUG, + "SMI_STS[%d] occurred, but no " + "handler available.\n", i); + } + } + + /* The GPIO SMI events do not have a status bit in SMI_STS. Therefore, + * these events need to be cleared and checked unconditionally. */ + mainboard_smi_gpi(clear_alt_status()); +} diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c new file mode 100644 index 0000000..bfddb68 --- /dev/null +++ b/src/soc/intel/braswell/smm.c @@ -0,0 +1,133 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <arch/io.h> +#include <cpu/cpu.h> +#include <cpu/x86/smm.h> +#include <string.h> + +#include <soc/iomap.h> +#include <soc/pmc.h> +#include <soc/smm.h> + +/* Save settings which will be committed in SMI functions. */ +static uint32_t smm_save_params[SMM_SAVE_PARAM_COUNT]; + +void southcluster_smm_save_param(int param, uint32_t data) +{ + smm_save_params[param] = data; +} + +void southcluster_smm_clear_state(void) +{ + uint32_t smi_en; + + /* Log events from chipset before clearing */ + southcluster_log_state(); + + printk(BIOS_DEBUG, "Initializing Southbridge SMI..."); + printk(BIOS_SPEW, " pmbase = 0x%04x\n", get_pmbase()); + + smi_en = inl(get_pmbase() + SMI_EN); + if (smi_en & APMC_EN) { + printk(BIOS_INFO, "SMI# handler already enabled?\n"); + return; + } + + /* Dump and clear status registers */ + clear_smi_status(); + clear_pm1_status(); + clear_tco_status(); + clear_gpe_status(); + clear_alt_status(); + clear_pmc_status(); +} + +static void southcluster_smm_route_gpios(void) +{ + u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT); + const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI; + uint32_t alt_gpio_reg = 0; + uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE]; + int i; + + printk(BIOS_DEBUG, "GPIO_ROUT = %08x\n", route_reg); + + /* Start the routing for the specific gpios. */ + write32(gpio_rout, route_reg); + + /* Enable SMIs for the gpios that are set to trigger the SMI. */ + for (i = 0; i < 16; i++) { + if ((route_reg & ROUTE_MASK) == ROUTE_SMI) { + alt_gpio_reg |= (1 << i); + } + route_reg >>= 2; + } + printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg); + + outl(alt_gpio_reg, alt_gpio_smi); +} + +void southcluster_smm_enable_smi(void) +{ + uint16_t pm1_events = PWRBTN_EN | GBL_EN; + + printk(BIOS_DEBUG, "Enabling SMIs.\n"); + if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE]) + pm1_events |= PCIEXPWAK_DIS; + enable_pm1(pm1_events); + disable_gpe(PME_B0_EN); + + /* Set up the GPIO route. */ + southcluster_smm_route_gpios(); + + /* Enable SMI generation: + * - on APMC writes (io 0xb2) + * - on writes to SLP_EN (sleep states) + * - on writes to GBL_RLS (bios commands) + * No SMIs: + * - on TCO events + * - on microcontroller writes (io 0x62/0x66) + */ + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); +} + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + /* + * Issue SMI to set the gnvs pointer in SMM. + * tcg and smi1 are unused. + * + * EAX = APM_CNT_GNVS_UPDATE + * EBX = gnvs pointer + * EDX = APM_CNT + */ + asm volatile ( + "outb %%al, %%dx\n\t" + : /* ignore result */ + : "a" (APM_CNT_GNVS_UPDATE), + "b" ((uint32_t)gnvs), + "d" (APM_CNT) + ); +} diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c new file mode 100644 index 0000000..8df1f1a --- /dev/null +++ b/src/soc/intel/braswell/southcluster.c @@ -0,0 +1,572 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/mc146818rtc.h> +#include <drivers/uart/uart8250reg.h> + +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/lpc.h> +#include <soc/nvs.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/ramstage.h> +#include <soc/spi.h> +#include "chip.h" + +static inline void +add_mmio_resource(device_t dev, int i, unsigned long addr, unsigned long size) +{ + mmio_resource(dev, i, addr >> 10, size >> 10); +} + +static void sc_add_mmio_resources(device_t dev) +{ + add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); + add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); + add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE); + add_mmio_resource(dev, IBASE, ILB_BASE_ADDRESS, ILB_BASE_SIZE); + add_mmio_resource(dev, SBASE, SPI_BASE_ADDRESS, SPI_BASE_SIZE); + add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE); + add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE); + add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE); +} + +/* Default IO range claimed by the LPC device. The upper bound is exclusive. */ +#define LPC_DEFAULT_IO_RANGE_LOWER 0 +#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000 + +static inline int io_range_in_default(int base, int size) +{ + /* Does it start above the range? */ + if (base >= LPC_DEFAULT_IO_RANGE_UPPER) + return 0; + + /* Is it entirely contained? */ + if (base >= LPC_DEFAULT_IO_RANGE_LOWER && + (base + size) < LPC_DEFAULT_IO_RANGE_UPPER) + return 1; + + /* This will return not in range for partial overlaps. */ + return 0; +} + +/* + * Note: this function assumes there is no overlap with the default LPC device's + * claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER. + */ +static void sc_add_io_resource(device_t dev, int base, int size, int index) +{ + struct resource *res; + + if (io_range_in_default(base, size)) + return; + + res = new_resource(dev, index); + res->base = base; + res->size = size; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void sc_add_io_resources(device_t dev) +{ + struct resource *res; + + /* Add the default claimed IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = LPC_DEFAULT_IO_RANGE_LOWER; + res->size = LPC_DEFAULT_IO_RANGE_UPPER - LPC_DEFAULT_IO_RANGE_LOWER; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* GPIO */ + sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); + + /* ACPI */ + sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); +} + +static void sc_read_resources(device_t dev) +{ + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add non-standard MMIO resources. */ + sc_add_mmio_resources(dev); + + /* Add IO resources. */ + sc_add_io_resources(dev); +} + +static void sc_rtc_init(void) +{ + uint32_t gen_pmcon1; + int rtc_fail; + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps != NULL) { + gen_pmcon1 = ps->gen_pmcon1; + } else { + gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + } + + rtc_fail = !!(gen_pmcon1 & RPS); + + if (rtc_fail) { + printk(BIOS_DEBUG, "RTC failure.\n"); + } + + cmos_init(rtc_fail); +} + +/* + * The UART hardware loses power while in suspend. Because of this the kernel + * can hang because it doesn't re-initialize serial ports it is using for + * consoles at resume time. The following function configures the UART + * if the hardware is enabled though it may not be the correct baud rate + * or configuration. This is definitely a hack, but it helps the kernel + * along. + */ +static void com1_configure_resume(device_t dev) +{ + const uint16_t port = 0x3f8; + + /* Is the UART I/O port enabled? */ + if (!(pci_read_config32(dev, UART_CONT) & 1)) + return; + + /* Disable interrupts */ + outb(0x0, port + UART8250_IER); + + /* Enable FIFOs */ + outb(UART8250_FCR_FIFO_EN, port + UART8250_FCR); + + /* assert DTR and RTS so the other end is happy */ + outb(UART8250_MCR_DTR | UART8250_MCR_RTS, port + UART8250_MCR); + + /* DLAB on */ + outb(UART8250_LCR_DLAB | 3, port + UART8250_LCR); + + /* Set Baud Rate Divisor. 1 ==> 115200 Baud */ + outb(1, port + UART8250_DLL); + outb(0, port + UART8250_DLM); + + /* Set to 3 for 8N1 */ + outb(3, port + UART8250_LCR); +} + +static void sc_init(device_t dev) +{ + int i; + u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); + u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20; + u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); + u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + struct soc_intel_baytrail_config *config = dev->chip_info; + + /* Set up the PIRQ PIC routing based on static config. */ + for (i = 0; i < NUM_PIRQS; i++) { + write8(pr_base + i, ir->pic[i]); + } + /* Set up the per device PIRQ routing base on static config. */ + for (i = 0; i < NUM_IR_DEVS; i++) { + write16(ir_base + i, ir->pcidev[i]); + } + + /* Route SCI to IRQ9 */ + write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); + + sc_rtc_init(); + + if (config->disable_slp_x_stretch_sus_fail) { + printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); + write32(gen_pmcon1, + read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); + } else { + write32(gen_pmcon1, + read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP); + } + + if (acpi_is_wakeup_s3()) + com1_configure_resume(dev); +} + +/* + * Common code for the south cluster devices. + */ + +/* Set bit in function disable register to hide this device. */ +static void sc_disable_devfn(device_t dev) +{ + u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS); + u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2); + uint32_t mask = 0; + uint32_t mask2 = 0; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + mask |= SDIO_DIS; + break; + case PCI_DEVFN(SD_DEV, SD_FUNC): + mask |= SD_DIS; + break; + case PCI_DEVFN(SATA_DEV, SATA_FUNC): + mask |= SATA_DIS; + break; + case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + mask |= XHCI_DIS; + /* Disable super speed PHY when XHCI is not available. */ + mask2 |= USH_SS_PHY_DIS; + break; + case PCI_DEVFN(LPE_DEV, LPE_FUNC): + mask |= LPE_DIS; + break; + case PCI_DEVFN(MMC_DEV, MMC_FUNC): + mask |= MMC_DIS; + break; + case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): + mask |= SIO_DMA1_DIS; + break; + case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): + mask |= I2C1_DIS; + break; + case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): + mask |= I2C1_DIS; + break; + case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): + mask |= I2C3_DIS; + break; + case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): + mask |= I2C4_DIS; + break; + case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): + mask |= I2C5_DIS; + break; + case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): + mask |= I2C6_DIS; + break; + case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): + mask |= I2C7_DIS; + break; + case PCI_DEVFN(TXE_DEV, TXE_FUNC): + mask |= TXE_DIS; + break; + case PCI_DEVFN(HDA_DEV, HDA_FUNC): + mask |= HDA_DIS; + break; + case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): + mask |= PCIE_PORT1_DIS; + break; + case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): + mask |= PCIE_PORT2_DIS; + break; + case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): + mask |= PCIE_PORT3_DIS; + break; + case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + mask |= PCIE_PORT4_DIS; + break; + case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): + mask |= EHCI_DIS; + break; + case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): + mask |= SIO_DMA2_DIS; + break; + case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): + mask |= PWM1_DIS; + break; + case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): + mask |= PWM2_DIS; + break; + case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): + mask |= HSUART1_DIS; + break; + case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): + mask |= HSUART2_DIS; + break; + case PCI_DEVFN(SPI_DEV, SPI_FUNC): + mask |= SPI_DIS; + break; + case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): + mask2 |= SMBUS_DIS; + break; + } + + if (mask != 0) { + write32(func_dis, read32(func_dis) | mask); + /* Ensure posted write hits. */ + read32(func_dis); + } + + if (mask2 != 0) { + write32(func_dis2, read32(func_dis2) | mask2); + /* Ensure posted write hits. */ + read32(func_dis2); + } +} + +static inline void set_d3hot_bits(device_t dev, int offset) +{ + uint32_t reg8; + printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); + reg8 = pci_read_config8(dev, offset + 4); + reg8 |= 0x3; + pci_write_config8(dev, offset + 4, reg8); +} + +/* Parts of the audio subsystem are powered by the HDA device. Therefore, one + * cannot put HDA into D3Hot. Instead perform this workaround to make some of + * the audio paths work for LPE audio. */ +static void hda_work_around(device_t dev) +{ + u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8); + + /* Need to set magic register 0x43 to 0xd7 in config space. */ + pci_write_config8(dev, 0x43, 0xd7); + + /* Need to set bit 0 of GCTL to take the device out of reset. However, + * that requires setting up the 64-bit BAR. */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + write32(gctl, read32(gctl) | 0x1); + pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); +} + +static int place_device_in_d3hot(device_t dev) +{ + unsigned offset; + + /* Parts of the HDA block are used for LPE audio as well. + * Therefore assume the HDA will never be put into D3Hot. */ + if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { + hda_work_around(dev); + return 0; + } + + offset = pci_find_capability(dev, PCI_CAP_ID_PM); + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + /* For some reason some of the devices don't have the capability + * pointer set correctly. Work around this by hard coding the offset. */ + switch (dev->path.pci.devfn) { + case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SD_DEV, SD_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(MMC_DEV, MMC_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(LPE_DEV, LPE_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SPI_DEV, SPI_FUNC): + offset = 0x80; + break; + case PCI_DEVFN(SATA_DEV, SATA_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): + offset = 0x70; + break; + case PCI_DEVFN(HDA_DEV, HDA_FUNC): + offset = 0x50; + break; + case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): + offset = 0x50; + break; + case PCI_DEVFN(TXE_DEV, TXE_FUNC): + /* TXE cannot be placed in D3Hot. */ + return 0; + case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): + offset = 0xa0; + break; + case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): + offset = 0xa0; + break; + } + + if (offset != 0) { + set_d3hot_bits(dev, offset); + return 0; + } + + return -1; +} + +/* Common PCI device function disable. */ +void southcluster_enable_dev(device_t dev) +{ + uint32_t reg32; + + if (!dev->enabled) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", + dev_path(dev), slot, func); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Place device in D3Hot */ + if (place_device_in_d3hot(dev) < 0) { + printk(BIOS_WARNING, + "Could not place %02x.%01x into D3Hot. " + "Keeping device visible.\n", slot, func); + return; + } + /* Disable this device if possible */ + sc_disable_devfn(dev); + } else { + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); + } +} + +static struct device_operations device_ops = { + .read_resources = sc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = NULL, + .init = sc_init, + .enable = southcluster_enable_dev, + .scan_bus = scan_static_bus, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPC_DEVID, +}; + +int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg) +{ + return -1; +} + +static void finalize_chipset(void *unused) +{ + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS); + u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2); + u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR); + u8 *spi = (u8 *)SPI_BASE_ADDRESS; + struct spi_config cfg; + + /* Set the lock enable on the BIOS control register. */ + write32(bcr, read32(bcr) | BCR_LE); + + /* Set BIOS lock down bit controlling boot block size and swapping. */ + write32(gcs, read32(gcs) | BILD); + + /* Lock sleep stretching policy and set SMI lock. */ + write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK); + + /* Set the CF9 lock. */ + write32(etr, read32(etr) | CF9LOCK); + + if (mainboard_get_spi_config(&cfg) < 0) { + printk(BIOS_DEBUG, "No SPI lockdown configuration.\n"); + } else { + write16(spi + PREOP, cfg.preop); + write16(spi + OPTYPE, cfg.optype); + write32(spi + OPMENU0, cfg.opmenu[0]); + write32(spi + OPMENU1, cfg.opmenu[1]); + write16(spi + HSFSTS, read16(spi + HSFSTS) | FLOCKDN); + write32(spi + UVSCC, cfg.uvscc); + write32(spi + LVSCC, cfg.lvscc | VCL); + } + + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + outb(APM_CNT_FINALIZE, APM_CNT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c new file mode 100644 index 0000000..2795d37 --- /dev/null +++ b/src/soc/intel/braswell/spi.c @@ -0,0 +1,647 @@ +/* + * Copyright (c) 2013 Google Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is derived from the flashrom project. */ +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <bootstate.h> +#include <delay.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <spi_flash.h> + +#include <soc/lpc.h> +#include <soc/pci_devs.h> + +#ifdef __SMM__ +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#else /* !__SMM__ */ +#include <device/device.h> +#include <device/pci.h> +#define pci_read_config_byte(dev, reg, targ)\ + *(targ) = pci_read_config8(dev, reg) +#define pci_read_config_word(dev, reg, targ)\ + *(targ) = pci_read_config16(dev, reg) +#define pci_read_config_dword(dev, reg, targ)\ + *(targ) = pci_read_config32(dev, reg) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* !__SMM__ */ + +typedef struct spi_slave ich_spi_slave; + +static int ichspi_lock = 0; + +typedef struct ich9_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; + uint32_t _reserved2[2]; + uint8_t ssfs; + uint8_t ssfc[3]; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) ich9_spi_regs; + +typedef struct ich_spi_controller { + int locked; + + uint8_t *opmenu; + int menubytes; + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; +} ich_spi_controller; + +static ich_spi_controller cntlr; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000 +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +#if CONFIG_DEBUG_SPI_FLASH + +static u8 readb_(const void *addr) +{ + u8 v = read8((unsigned long)addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = read16((unsigned long)addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = read32((unsigned long)addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, const void *addr) +{ + write8(addr, b); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, const void *addr) +{ + write16(addr, b); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, const void *addr) +{ + write32(addr, b); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ + +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) + +#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + const uint8_t *bvalue = value; + uint8_t *bdest = dest; + + while (size >= 4) { + writel_(*(const uint32_t *)bvalue, bdest); + bdest += 4; bvalue += 4; size -= 4; + } + while (size) { + writeb_(*bvalue, bdest); + bdest++; bvalue++; size--; + } +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + const uint8_t *bsrc = src; + uint8_t *bvalue = value; + + while (size >= 4) { + *(uint32_t *)bvalue = readl_(bsrc); + bsrc += 4; bvalue += 4; size -= 4; + } + while (size) { + *bvalue = readb_(bsrc); + bsrc++; bvalue++; size--; + } +} + +static void ich_set_bbar(uint32_t minaddr) +{ + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + writel_(ichspi_bbar, cntlr.bbar); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + ich_spi_slave *slave = malloc(sizeof(*slave)); + + if (!slave) { + printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + return NULL; + } + + memset(slave, 0, sizeof(*slave)); + + slave->bus = bus; + slave->cs = cs; + return slave; +} + +static ich9_spi_regs *spi_regs(void) +{ + device_t dev; + uint32_t sbase; + +#ifdef __SMM__ + dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); +#else + dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); +#endif + pci_read_config_dword(dev, SBASE, &sbase); + sbase &= ~0x1ff; + + return (void *)sbase; +} + +void spi_init(void) +{ + ich9_spi_regs *ich9_spi = spi_regs(); + + ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; + cntlr.opmenu = ich9_spi->opmenu; + cntlr.menubytes = sizeof(ich9_spi->opmenu); + cntlr.optype = &ich9_spi->optype; + cntlr.addr = &ich9_spi->faddr; + cntlr.data = (uint8_t *)ich9_spi->fdata; + cntlr.databytes = sizeof(ich9_spi->fdata); + cntlr.status = &ich9_spi->ssfs; + cntlr.control = (uint16_t *)ich9_spi->ssfc; + cntlr.bbar = &ich9_spi->bbar; + cntlr.preop = &ich9_spi->preop; + ich_set_bbar(0); +} + +#ifndef __SMM__ +static void spi_init_cb(void *unused) +{ + spi_init(); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); +#endif + +int spi_claim_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +typedef struct spi_transaction { + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +} spi_transaction; + +static inline void spi_use_out(spi_transaction *trans, unsigned bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(spi_transaction *trans, unsigned bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(spi_transaction *trans) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + } + + /* Fast read command is called with 5 bytes instead of 4 */ + if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + --trans->bytesout; + } +} + +static int spi_setup_opcode(spi_transaction *trans) +{ + uint16_t optypes; + uint8_t opmenu[cntlr.menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!ichspi_lock) { + /* The lock is off, so just use index 0. */ + writeb_(trans->opcode, cntlr.opmenu); + optypes = readw_(cntlr.optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + writew_(optypes, cntlr.optype); + return 0; + } else { + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < cntlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == cntlr.menubytes) { + printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = readw_(cntlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; + } +} + +static int spi_setup_offset(spi_transaction *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); + return -1; + } +} + +/* + * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set + * below is True) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(u16 bitmask, int wait_til_set) +{ + int timeout = 40000; /* This will result in 400 ms */ + u16 status = 0; + + while (timeout--) { + status = readw_(cntlr.status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + writew_((status & bitmask), cntlr.status); + return status; + } + udelay(10); + } + + printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(cntlr.databytes, buf_len); +} + +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bytesout, void *din, unsigned int bytesin) +{ + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + + spi_transaction trans = { + dout, bytesout, + din, bytesin, + 0xff, 0xff, 0 + }; + + /* There has to always at least be an opcode. */ + if (!bytesout || !dout) { + printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); + return -1; + } + /* Make sure if we read something we have a place to put it. */ + if (bytesin != 0 && !din) { + printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); + + spi_setup_type(&trans); + if ((opcode_index = spi_setup_opcode(&trans)) < 0) + return -1; + if ((with_address = spi_setup_offset(&trans)) < 0) + return -1; + + if (trans.opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + if (!ichspi_lock) + writew_(trans.opcode, cntlr.preop); + return 0; + } + + /* Preset control fields */ + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (readw_(cntlr.preop)) + control |= SPIC_ACS; + + if (!trans.bytesout && !trans.bytesin) { + /* SPI addresses are 24 bit only */ + if (with_address) + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + /* + * This is a 'no data' command (like Write Enable), its + * bytesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + writew_(control, cntlr.control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); + return -1; + } + + return 0; + } + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans.bytesout > cntlr.databytes) { + printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans.bytesout || trans.bytesin) { + uint32_t data_length; + + /* SPI addresses are 24 bit only */ + writel_(trans.offset & 0x00FFFFFF, cntlr.addr); + + if (trans.bytesout) + data_length = min(trans.bytesout, cntlr.databytes); + else + data_length = min(trans.bytesin, cntlr.databytes); + + /* Program data into FDATA0 to N */ + if (trans.bytesout) { + write_reg(trans.out, cntlr.data, data_length); + spi_use_out(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((cntlr.databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + writew_(control, cntlr.control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans.bytesin) { + read_reg(cntlr.data, trans.in, data_length); + spi_use_in(&trans, data_length); + if (with_address) + trans.offset += data_length; + } + } + + /* Clear atomic preop now that xfer is done */ + writew_(0, cntlr.preop); + + return 0; +} diff --git a/src/soc/intel/braswell/stage_cache.c b/src/soc/intel/braswell/stage_cache.c new file mode 100644 index 0000000..a4f510d --- /dev/null +++ b/src/soc/intel/braswell/stage_cache.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <stage_cache.h> +#include <soc/smm.h> + +void stage_cache_external_region(void **base, size_t *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + *base = &smm_base[smm_region_size() - cache_size]; +} diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c new file mode 100644 index 0000000..700b098 --- /dev/null +++ b/src/soc/intel/braswell/tsc_freq.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/msr.h> + +unsigned bus_freq_khz(void) +{ + msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); + switch (clk_info.lo & 0x3) { + case 0: + return 83333; + case 1: + return 100000; + case 2: + return 133333; + case 3: + return 116666; + default: + return 0; + } +} + +unsigned long tsc_freq_mhz(void) +{ + msr_t platform_info; + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + platform_info = rdmsr(MSR_PLATFORM_INFO); + return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; +} + +#if !defined(__SMM__) +#if !defined(__PRE_RAM__) +#include <soc/ramstage.h> +#else +#include <soc/romstage.h> +#endif + +void set_max_freq(void) +{ + msr_t perf_ctl; + msr_t msr; + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of + * the PERF_CTL. */ + msr = rdmsr(MSR_IACORE_RATIOS); + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; + /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of + * the PERF_CTL. */ + msr = rdmsr(MSR_IACORE_VIDS); + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; + perf_ctl.hi = 0; + + wrmsr(MSR_IA32_PERF_CTL, perf_ctl); +} + +#endif /* __SMM__ */ diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c new file mode 100644 index 0000000..776e44c --- /dev/null +++ b/src/soc/intel/braswell/xhci.c @@ -0,0 +1,259 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/lpc.h> +#include <soc/pattrs.h> +#include <soc/pci_devs.h> +#include <soc/pmc.h> +#include <soc/ramstage.h> +#include <soc/xhci.h> + +#include "chip.h" + +struct reg_script usb3_phy_script[] = { + /* USB3PHYInit() */ + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_PLL_CONTROL, + ~0x00700000, 0x00500000), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_VCO_START_CAL_POINT, + ~0x001f0000, 0x000A0000), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CCDRLF, + ~0x0000000f, 0x0000000b), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_PEAKING_AMP_CONFIG_DIAG, + ~0x000000f0, 0x000000f0), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_OFFSET_COR_CONFIG_DIAG, + ~0x000001c0, 0x00000000), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_VGA_GAIN_CONFIG_DIAG, + ~0x00000070, 0x00000020), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_REE_DAC_CONTROL, + ~0x00000002, 0x00000002), + REG_IOSF_RMW(IOSF_PORT_USHPHY, USHPHY_CDN_U1_POWER_STATE_DEF, + ~0x00000000, 0x00040000), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_script[] = { + /* CommonXhciHcInit() */ + /* BAR + 0x0c[31:16] = 0x0200 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0x0000ffff, 0x02000000), + /* BAR + 0x0c[7:0] = 0x0a */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x000c, 0xffffff00, 0x0000000a), + /* BAR + 0x8094[23,21,14]=111b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8094, 0x00a04000), + /* BAR + 0x8110[20,11,8,2]=1100b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8110, ~0x00000104, 0x00100800), + /* BAR + 0x8144[8,7,6]=111b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8144, 0x000001c0), + /* BAR + 0x8154[21,13,3]=010b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8154, ~0x00200008, 0x80002000), + /* BAR + 0x816c[19:0]=1110x100000000111100b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x816c, 0xfff08000, 0x000e0030), + /* BAR + 0x8188[26,24]=11b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8188, 0x05000000), + /* BAR + 0x8174=0x1000c0a*/ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8174, 0xfe000000, 0x01000c0a), + /* BAR + 0x854c[29]=0b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x854c, ~0x20000000, 0), + /* BAR + 0x8178[12:0]=0b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8178, ~0xffffe000, 0), + /* BAR + 0x8164[7:0]=0xff */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8164, 0x000000ff), + /* BAR + 0x0010[10,9,5]=110b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x0010, ~0x00000020, 0x00000600), + /* BAR + 0x8058[20,16,8]=110b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8058, ~0x00000100, 0x00110000), + /* BAR + 0x8060[25]=1b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8060, 0x02000000), + /* BAR + 0x80f0[20]=0b */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80f0, ~0x00100000, 0), + /* BAR + 0x8008[19]=1b (to enable LPM) */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x8008, 0x00080000), + /* BAR + 0x80fc[25]=1b */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x80fc, 0x02000000), + /* 0x40/0x44 are written as bytes to avoid touching bit31 */ + /* D20:F0:40[21,20,18,10,9,8]=111001b (don't write byte3) */ + REG_PCI_RMW8(0x41, ~0x06, 0x01), + /* Except [21,20,19,18]=0001b USB wake W/A is disable IIL1E */ + REG_PCI_RMW8(0x42, 0x3c, 0x04), + /* D20:F0:44[19:14,10,9,7,3:0]=1 (don't write byte3) */ + REG_PCI_RMW8(0x44, 0x00, 0x8f), + REG_PCI_RMW8(0x45, ~0xcf, 0xc6), + REG_PCI_RMW8(0x46, ~0x0f, 0x0f), + /* BAR + 0x8140 = 0xff00f03c */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x8140, 0, 0xff00f03c), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_boot_script[] = { + /* Setup USB3 phy */ + REG_SCRIPT_NEXT(usb3_phy_script), + /* Initialize host controller */ + REG_SCRIPT_NEXT(xhci_init_script), + /* BAR + 0x80e0[16,9,6]=001b, toggle bit 24=1 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x00010200, 0x01000040), + /* BAR + 0x80e0 toggle bit 24=0 */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01000000, 0), + REG_SCRIPT_END +}; + +const struct reg_script xhci_init_resume_script[] = { + /* Setup USB3 phy */ + REG_SCRIPT_NEXT(usb3_phy_script), + /* Initialize host controller */ + REG_SCRIPT_NEXT(xhci_init_script), + /* BAR + 0x80e0[16,9,6]=001b, leave bit 24=0 to prevent HC reset */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x80e0, ~0x01010200, 0x00000040), + REG_SCRIPT_END +}; + +const struct reg_script xhci_clock_gating_script[] = { + /* ConfigureXhciClockGating() */ + /* D20:F0:40[21:19,18,10:8]=000,1,001 (don't write byte 3) */ + REG_PCI_RMW16(0x40, ~0x0600, 0x0100), + REG_PCI_RMW8(0x42, ~0x38, 0x04), + /* D20:F0:44[5:3]=001b */ + REG_PCI_RMW16(0x44, ~0x0030, 0x0008), + /* D20:F0:A0[19:18]=01b */ + REG_PCI_RMW32(0xa0, ~0x00080000, 0x00040000), + /* D20:F0:A4[15:0]=0x00 */ + REG_PCI_WRITE16(0xa4, 0x0000), + /* D20:F0:B0[21:17,14:13]=0000000b */ + REG_PCI_RMW32(0xb0, ~0x00376000, 0x00000000), + /* D20:F0:50[31:0]=0x0bce6e5f */ + REG_PCI_WRITE32(0x50, 0x0bce6e5f), + REG_SCRIPT_END +}; + +/* Warm Reset a USB3 port */ +static void xhci_reset_port_usb3(device_t dev, int port) +{ + struct reg_script reset_port_usb3_script[] = { + /* Issue Warm Port Rest to the port */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + XHCI_USB3_PORTSC_WPR), + /* Wait up to 100ms for it to complete */ + REG_RES_POLL32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + XHCI_USB3_PORTSC_WRC, XHCI_USB3_PORTSC_WRC, + XHCI_RESET_TIMEOUT), + /* Clear change status bits, do not set PED */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), + ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), + REG_SCRIPT_END + }; + reg_script_run_on_dev(dev, reset_port_usb3_script); +} + +/* Prepare ports to be routed to EHCI or XHCI */ +static void xhci_route_all(device_t dev) +{ + static const struct reg_script xhci_route_all_script[] = { + /* USB3 SuperSpeed Enable */ + REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), + /* USB2 Port Route to XHCI */ + REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP), + REG_SCRIPT_END + }; + u32 port_disabled; + int port; + + printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); + + /* Route ports to XHCI controller */ + reg_script_run_on_dev(dev, xhci_route_all_script); + + if (acpi_is_wakeup_s3()) + return; + + /* Reset enabled USB3 ports */ + port_disabled = pci_read_config32(dev, XHCI_USB3PDO); + for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) { + if (port_disabled & (1 << port)) + continue; + xhci_reset_port_usb3(dev, port); + } +} + +static void xhci_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + struct reg_script xhci_hc_init[] = { + /* Initialize clock gating */ + REG_SCRIPT_NEXT(xhci_clock_gating_script), + /* Finalize XHCC1 and XHCC2 */ + REG_PCI_RMW32(0x44, ~0x00000000, 0x83c00000), + REG_PCI_RMW32(0x40, ~0x00800000, 0x80000000), + /* Set USB2 Port Routing Mask */ + REG_PCI_WRITE32(XHCI_USB2PRM, BYTM_USB2_PORT_MAP), + /* Set USB3 Port Routing Mask */ + REG_PCI_WRITE32(XHCI_USB3PRM, BYTM_USB3_PORT_MAP), + /* + * Disable ports if requested + */ + /* Open per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), + REG_PCI_WRITE32(XHCI_USB2PDO, config->usb2_port_disable_mask), + REG_PCI_WRITE32(XHCI_USB3PDO, config->usb3_port_disable_mask), + /* Close per-port disable control override */ + REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), + REG_SCRIPT_END + }; + + /* Initialize XHCI controller for boot or resume path */ + if (acpi_is_wakeup_s3()) + reg_script_run_on_dev(dev, xhci_init_resume_script); + else + reg_script_run_on_dev(dev, xhci_init_boot_script); + + /* C0 steppings change iCLK/USB PLL VCO settings from 5 to 7 */ + if (pattrs_get()->stepping == STEP_C0) { + uint32_t reg = iosf_ushphy_read(USHPHY_CDN_PLL_CONTROL); + reg |= 0x00700000; + iosf_ushphy_write(USHPHY_CDN_PLL_CONTROL, reg); + } + + /* Finalize Initialization */ + reg_script_run_on_dev(dev, xhci_hc_init); + + /* Route all ports to XHCI if requested */ + if (config->usb_route_to_xhci) + xhci_route_all(dev); +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xhci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver baytrail_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = XHCI_DEVID +};

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Patch set updated for coreboot: 776853b Add 82945G/GC/GZ Integrated Graphics Controller PCI IDs.
by HAOUAS Elyes 12 May '15

12 May '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9804 -gerrit commit 776853ba5fa0a1c0413e5f6ffa8cb353223410e3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue May 12 22:30:11 2015 +0200 Add 82945G/GC/GZ Integrated Graphics Controller PCI IDs. Change-Id: I548368ca580c2c4ec98d90778054ec12ad5b290e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/gma.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e5974c9..5b0072e 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -514,16 +514,27 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 }; +static const unsigned short i945_gma_func0_ids[] = { + 0x2772 + 0x27a2, + 0x27ae, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x2776, + 0x27a6, + 0 +}; static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, };

1 0

Patch set updated for coreboot: 3683ff7 intel i945: Add 82945G/GZ/P/PL Memory Controller PCI ID
by HAOUAS Elyes 12 May '15

12 May '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9802 -gerrit commit 3683ff73c68c95dfa174643f5e90bbbf578af7c3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue May 12 22:22:44 2015 +0200 intel i945: Add 82945G/GZ/P/PL Memory Controller PCI ID Change-Id: Iade9ad0c3e341af1e28745e70733dccdfbe2903f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/northbridge.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 1aaeb3b..ddc6ec9 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -268,8 +268,12 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a0, 0x27ac, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x2770, + 0x27a0, + 0x27ac, + 0 +}; static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops,

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coreboot-gerrit May 2015