coreboot-gerrit May 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: e76cb7e arm64: Reorganize payload entry code and related Kconfigs
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10245 -gerrit commit e76cb7e52894a8d2c166c3c198275f403fb0769e Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable: Make spintable handling optional through a kconfig flag. [pg: taken from patch linked below] Change-Id: I64610640835473fcc3d9eff01feb5f861b753eb8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/boot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 367aaac..c925c08 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -42,7 +42,8 @@ static void run_payload(struct prog *prog) uint8_t current_el = get_current_el(); /* Start the other CPUs spinning. */ - spintable_start(); + if (IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE)) + spintable_start(); printk(BIOS_SPEW, "entry = %p\n", doit);

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New patch to review for coreboot: 4953978 arm64: Reorganize payload entry code and related Kconfigs
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10244 -gerrit commit 4953978577790753e34bee6282d8164543308dd7 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable. Improve locality of code. [pg: taken from patch linked below] Change-Id: Ie9ea6a10b9d5e5c33bf020369afcae4f10ef068e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/boot.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 1fdc234..367aaac 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -36,16 +36,16 @@ static void run_payload(struct prog *prog) doit = prog_entry(prog); arg = prog_entry_arg(prog); - uint8_t current_el = get_current_el(); - - printk(BIOS_SPEW, "entry = %p\n", doit); - if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_MONITOR)) secmon_run(doit, arg); else { + uint8_t current_el = get_current_el(); + /* Start the other CPUs spinning. */ spintable_start(); + printk(BIOS_SPEW, "entry = %p\n", doit); + /* If current EL is not EL3, jump to payload at same EL. */ if (current_el != EL3) { cache_sync_instructions();

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New patch to review for coreboot: 669fcc5 arm64: Reorganize payload entry code and related Kconfigs
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10243 -gerrit commit 669fcc5e311d96b69fd4a6368c21f1a245a85d97 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs This patch slightly reorganizes arm64/boot.c with the aim of being more readable: the secure monitor entry is now guarded by an explicit if statement for its Kconfig rather than hiding than in the corresponding header file. This makes it clear that there are two (soon three) separate code paths here. Change-Id: I44993da7a982b08f485b93ffc522d193bb3fa118 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/boot.c | 34 ++++++++++++++++++---------------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index f62ceb6..1fdc234 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -40,27 +40,29 @@ static void run_payload(struct prog *prog) printk(BIOS_SPEW, "entry = %p\n", doit); - secmon_run(doit, arg); + if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_MONITOR)) + secmon_run(doit, arg); + else { + /* Start the other CPUs spinning. */ + spintable_start(); - /* Start the other CPUs spinning. */ - spintable_start(); + /* If current EL is not EL3, jump to payload at same EL. */ + if (current_el != EL3) { + cache_sync_instructions(); + /* Point of no-return */ + doit(arg); + } - /* If current EL is not EL3, jump to payload at same EL. */ - if (current_el != EL3) { - cache_sync_instructions(); - /* Point of no-return */ - doit(arg); - } - - /* If current EL is EL3, we transition to payload in EL2. */ - struct exc_state exc_state; + /* If current EL is EL3, we transition to payload in EL2. */ + struct exc_state exc_state; - memset(&exc_state, 0, sizeof(exc_state)); + memset(&exc_state, 0, sizeof(exc_state)); - exc_state.elx.spsr = get_eret_el(EL2, SPSR_USE_L); + exc_state.elx.spsr = get_eret_el(EL2, SPSR_USE_L); - cache_sync_instructions(); - transition_with_entry(doit, arg, &exc_state); + cache_sync_instructions(); + transition_with_entry(doit, arg, &exc_state); + } } void arch_prog_run(struct prog *prog)

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New patch to review for coreboot: 87d0310 arm64: Reorganize payload entry code and related Kconfigs
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10242 -gerrit commit 87d0310e99bf1cb1e0d2074beafe599b3da0726a Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs Rename Kconfig options for secmon and spintable to be prefixed with ARM64_ instead of ARCH_, which seems to be the standard throughout the rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this provides a clearer separation between generic options that are selected by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to some of the MAINBOARD_HAS_... we have) and options that only make sense in the context of a single architecture. Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/Kconfig | 5 +++-- src/arch/arm64/Makefile.inc | 2 +- src/arch/arm64/armv8/Makefile.inc | 4 ++-- src/arch/arm64/armv8/lib/Makefile.inc | 2 +- src/arch/arm64/include/arch/spintable.h | 6 +++--- src/mainboard/google/rush/Kconfig | 2 +- src/mainboard/google/rush_ryu/Kconfig | 2 +- src/soc/nvidia/tegra132/Kconfig | 2 +- src/soc/nvidia/tegra132/Makefile.inc | 2 +- 9 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 3d84a11..fd53972 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -28,12 +28,13 @@ config ARM64_BOOTBLOCK_CUSTOM bool default n -config ARCH_USE_SECURE_MONITOR +config ARM64_USE_SECURE_MONITOR bool default n select RELOCATABLE_MODULES + depends on ARCH_RAMSTAGE_ARM64 -config ARCH_SPINTABLE +config ARM64_USE_SPINTABLE bool default n depends on ARCH_RAMSTAGE_ARM64 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 92bb058..4a09190 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -153,7 +153,7 @@ ramstage-y += ../../lib/memcpy.c ramstage-y += ../../lib/memmove.c ramstage-y += stage_entry.S ramstage-y += cpu-stubs.c -ramstage-$(CONFIG_ARCH_SPINTABLE) += spintable.c spintable_asm.S +ramstage-$(CONFIG_ARM64_USE_SPINTABLE) += spintable.c spintable_asm.S ramstage-y += transition.c transition_asm.S rmodules_arm64-y += ../../lib/memset.c diff --git a/src/arch/arm64/armv8/Makefile.inc b/src/arch/arm64/armv8/Makefile.inc index 19684b2..bba493c 100644 --- a/src/arch/arm64/armv8/Makefile.inc +++ b/src/arch/arm64/armv8/Makefile.inc @@ -21,7 +21,7 @@ subdirs-y += lib/ -subdirs-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon/ +subdirs-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon/ armv8_flags = -march=armv8-a -I$(src)/arch/arm64/include/armv8/ -D__COREBOOT_ARM_ARCH__=8 @@ -92,7 +92,7 @@ ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += mmu.c -ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon_loader.c +ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon_loader.c ramstage-c-ccopts += $(armv8_flags) ramstage-S-ccopts += $(armv8_asm_flags) diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc index 7e647bd..48ceaf5 100644 --- a/src/arch/arm64/armv8/lib/Makefile.inc +++ b/src/arch/arm64/armv8/lib/Makefile.inc @@ -37,7 +37,7 @@ endif ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) ramstage-y += $(lib_access) -ifeq ($(CONFIG_ARCH_USE_SECURE_MONITOR),y) +ifeq ($(CONFIG_ARM64_USE_SECURE_MONITOR),y) secmon-y += $(lib_access) endif diff --git a/src/arch/arm64/include/arch/spintable.h b/src/arch/arm64/include/arch/spintable.h index b583ddb..930319a 100644 --- a/src/arch/arm64/include/arch/spintable.h +++ b/src/arch/arm64/include/arch/spintable.h @@ -25,7 +25,7 @@ struct spintable_attributes { void *addr; }; -#if IS_ENABLED(CONFIG_ARCH_SPINTABLE) +#if IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) /* Initialize spintable with provided monitor address. */ void spintable_init(void *monitor_address); @@ -36,7 +36,7 @@ void spintable_start(void); /* Return NULL on failure, otherwise the spintable info. */ const struct spintable_attributes *spintable_get_attributes(void); -#else /* IS_ENABLED(CONFIG_SPINTABLE) */ +#else /* IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) */ static inline void spintable_init(void *monitor_address) {} static inline void spintable_start(void) {} @@ -45,6 +45,6 @@ static inline const struct spintable_attributes *spintable_get_attributes(void) return NULL; } -#endif /* IS_ENABLED(CONFIG_SPINTABLE) */ +#endif /* IS_ENABLED(CONFIG_ARM64_USE_SPINTABLE) */ #endif /* __ARCH_SPINTABLE_H__ */ diff --git a/src/mainboard/google/rush/Kconfig b/src/mainboard/google/rush/Kconfig index 9cb0223..eb64f12 100644 --- a/src/mainboard/google/rush/Kconfig +++ b/src/mainboard/google/rush/Kconfig @@ -33,7 +33,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select VIRTUAL_DEV_SWITCH select BOARD_ROMSIZE_KB_4096 - select ARCH_SPINTABLE + select ARM64_USE_SPINTABLE select CHROMEOS_VBNV_EC config MAINBOARD_DIR diff --git a/src/mainboard/google/rush_ryu/Kconfig b/src/mainboard/google/rush_ryu/Kconfig index 2a7e0fb..a52589e 100644 --- a/src/mainboard/google/rush_ryu/Kconfig +++ b/src/mainboard/google/rush_ryu/Kconfig @@ -34,7 +34,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select BOARD_ROMSIZE_KB_8192 select VIRTUAL_DEV_SWITCH - select ARCH_SPINTABLE + select ARM64_USE_SPINTABLE select CHROMEOS_VBNV_EC config MAINBOARD_DIR diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig index ee0a0ef..f9dd14a 100644 --- a/src/soc/nvidia/tegra132/Kconfig +++ b/src/soc/nvidia/tegra132/Kconfig @@ -16,7 +16,7 @@ config SOC_NVIDIA_TEGRA132 select ARM_BOOTBLOCK_CUSTOM select DYNAMIC_CBMEM select SMP - select ARCH_USE_SECURE_MONITOR + select ARM64_USE_SECURE_MONITOR select GENERIC_GPIO_LIB if SOC_NVIDIA_TEGRA132 diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 8e0f6db..365dab3 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -96,7 +96,7 @@ ramstage-y += ramstage.c ramstage-y += mmu_operations.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c -ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon.c +ramstage-$(CONFIG_ARM64_USE_SECURE_MONITOR) += secmon.c secmon-y += 32bit_reset.S secmon-y += cpu.c

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New patch to review for coreboot: 1cdf218 arm64: Reorganize payload entry code and related Kconfigs
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10241 -gerrit commit 1cdf21857683e2723b4ed1dc41a17d8e67b3a227 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs Remove the secmon Kconfig guard from Makefiles that add to the secmon class since they are redundant (the class is simply not used when compiling without secmon) to improve readability/ease-of-use. [pg: taken out of the patch linked below] Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/Makefile.inc | 14 +++++++------- src/console/Makefile.inc | 6 +++--- src/soc/nvidia/tegra132/Makefile.inc | 16 ++++++++-------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 8787d42..92bb058 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -161,13 +161,13 @@ rmodules_arm64-y += ../../lib/memcpy.c rmodules_arm64-y += ../../lib/memmove.c rmodules_arm64-y += eabi_compat.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += stage_entry.S -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu-stubs.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += startup.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/malloc.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memset.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcmp.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += ../../lib/memcpy.c +secmon-y += stage_entry.S +secmon-y += cpu-stubs.c +secmon-y += startup.c +secmon-y += ../../lib/malloc.c +secmon-y += ../../lib/memset.c +secmon-y += ../../lib/memcmp.c +secmon-y += ../../lib/memcpy.c ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index cae8f60..60760a0 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -21,6 +21,6 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += die.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += vtxprintf.c printk.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += init.c console.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += die.c +secmon-y += vtxprintf.c printk.c +secmon-y += init.c console.c +secmon-y += die.c diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 44976d1..8e0f6db 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -98,14 +98,14 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += ../tegra/usb.c ramstage-$(CONFIG_ARCH_USE_SECURE_MONITOR) += secmon.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += 32bit_reset.S -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += cpu_lib.S -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += flow_ctrl.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += power.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += psci.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += uart.c -secmon-$(CONFIG_ARCH_USE_SECURE_MONITOR) += gic.c +secmon-y += 32bit_reset.S +secmon-y += cpu.c +secmon-y += cpu_lib.S +secmon-y += flow_ctrl.c +secmon-y += power.c +secmon-y += psci.c +secmon-y += uart.c +secmon-y += gic.c modules_arm-y += monotonic_timer.c VBOOT_STUB_DEPS += $(obj)/soc/nvidia/tegra132/monotonic_timer.rmodules_arm.o

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New patch to review for coreboot: ab452f2 arm64: Reorganize payload entry code and related Kconfigs
by Patrick Georgi 19 May '15

19 May '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10240 -gerrit commit ab452f2c67fea6b4d95b73e99c5530ded2a60a84 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu May 7 16:59:31 2015 -0700 arm64: Reorganize payload entry code and related Kconfigs Reorganize Kconfig (split out from the original patch linked below) Change-Id: I84ec8e453dd7a3980de95a455ad21494c601a98c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm64/Kconfig | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index c51387c..3d84a11 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -19,6 +19,15 @@ config ARCH_RAMSTAGE_ARM64 bool default n +source src/arch/arm64/armv8/Kconfig +source src/arch/arm64/cpu/Kconfig + +# If a custom bootblock is necessary, this option should be "select"-ed by +# the thing that needs it, probably the CPU. +config ARM64_BOOTBLOCK_CUSTOM + bool + default n + config ARCH_USE_SECURE_MONITOR bool default n @@ -28,12 +37,3 @@ config ARCH_SPINTABLE bool default n depends on ARCH_RAMSTAGE_ARM64 - -source src/arch/arm64/armv8/Kconfig -source src/arch/arm64/cpu/Kconfig - -# If a custom bootblock is necessary, this option should be "select"-ed by -# the thing that needs it, probably the CPU. -config ARM64_BOOTBLOCK_CUSTOM - bool - default n

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Patch merged into coreboot/master: 58d5e21 x86: garbage collect SMM programs
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit 58d5e21851ced6b475a87e3a4114b2c7e1125921 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 15:23:39 2015 -0500 x86: garbage collect SMM programs The non-module SMM programs were not being garbage collected during linking. Do this so that one doesn't have to add dependencies for unused functions in SMM. TEST=Interrogated readelf -e smm.elf on both builds as well as diffed the symbol table. Runtime testing was not done. Change-Id: I31991496d92191e540df6340c587eec09c7022b3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10219 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10219 for details. -gerrit

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Patch merged into coreboot/master: e645bca regions: add more helpers
by gerrit＠coreboot.org 19 May '15

19 May '15

the following patch was just integrated into master: commit e645bcae7ccf1d7e4e75aa7d9149df5dae1d19c4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 13:23:49 2015 -0500 regions: add more helpers Fill out functions to get the offset and size for both regions and region_devices. Additionally add a helper for memory mapping an entire region_device. Change-Id: I8896eaf5b29e4a67470f4adc6f5b541566cb93b5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10215 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/10215 for details. -gerrit

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New patch to review for coreboot: 03bb028 nehalem native gfx init: Adjust state to be compatible with OPROM.
by Vladimir Serbinenko 19 May '15

19 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10239 -gerrit commit 03bb028a433976b6a5d77c64ac3b67d22a43e8c3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue May 19 09:45:22 2015 +0200 nehalem native gfx init: Adjust state to be compatible with OPROM. My main payload is GRUB and I load SeaBIOS as secondary payload when for some reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom (SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either completely uninited gfx or some special state in gmbus and software scratch registers. Provide this state. The only alternative without this patch for such usecase is to use oprom and I'd like to avoid doing so when going my main boot path to GNU/Linux. Change-Id: Ic157a6a580d7a5048ac28155e0d6b3433bbd1f2c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/gma.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 9fc4bd4..7d24bd5 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -700,6 +700,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, power_port(mmio); intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128); + intel_gmbus_stop(mmio + PCH_GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); @@ -721,9 +722,8 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock : (2 * edid.pixel_clock); -#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); -#else +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_sr_write(1, 1); vga_sr_write(0x2, 0xf); vga_sr_write(0x3, 0x0); @@ -982,6 +982,11 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info, write32(mmio + DEIIR, 0xffffffff); write32(mmio + SDEIIR, 0xffffffff); + /* Doesn't change any hw behaviour but vga oprom expects it there. */ + write32(mmio + 0x0004f040, 0x01000008); + write32(mmio + 0x0004f04c, 0x7f7f0000); + write32(mmio + 0x0004f054, 0x0000020d); + #if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4); set_vbe_mode_info_valid(&edid, lfb);

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Patch set updated for coreboot: 3356478 nvramcui: reboot at the end as TODO suggests
by Vladimir Serbinenko 18 May '15

18 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4693 -gerrit commit 335647850ae9d73803706a7ce26f3c7b1b010688 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed Jan 15 22:09:25 2014 +0100 nvramcui: reboot at the end as TODO suggests Use cf9 to reboot at the end. Change-Id: I642a5ec89c864fb03bbcdf6e4fcbb1e28f3fc34c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- payloads/nvramcui/nvramcui.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/nvramcui/nvramcui.c b/payloads/nvramcui/nvramcui.c index 5a8ca50..72bdd1c 100644 --- a/payloads/nvramcui/nvramcui.c +++ b/payloads/nvramcui/nvramcui.c @@ -247,7 +247,8 @@ int main() unpost_form(form); free_form(form); - /* TODO: reboot */ + /* reboot */ + outb (0x6, 0xcf9); halt(); }

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coreboot-gerrit May 2015