coreboot-gerrit May 2015

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Patch set updated for coreboot: 22d50ce cbfs: add new API using region_device
by Aaron Durbin 18 May '15

18 May '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9134 -gerrit commit 22d50cec9a1998999ed0964b076f3521e3fb8800 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri May 15 23:39:23 2015 -0500 cbfs: add new API using region_device A new CBFS API is introduced to allow making CBFS access easier for providing multiple CBFS sources. That is achieved by decoupling the cbfs source from a CBFS file. A CBFS source is described by a descriptor. It contains the necessary properties for walking a CBFS to locate a file. The CBFS file is then decoupled from the CBFS descriptor in that it's no longer needed to access the contents of the file. All of this is accomplished using the regions infrastructure by repsenting CBFS sources and files as region_devices. Because region_devices can be chained together forming subregions this allows one to decouple a CBFS source from a file. This also allows one to provide CBFS files that came from other sources for payload and/or stage loading. Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/riscv/rom_media.c | 67 +--- src/arch/x86/lib/Makefile.inc | 3 - src/arch/x86/lib/mmap_boot.c | 44 +++ src/arch/x86/lib/rom_media.c | 98 ------ src/cpu/allwinner/a10/bootblock_media.c | 8 +- src/cpu/amd/microcode/microcode.c | 4 +- src/cpu/intel/microcode/microcode.c | 18 +- src/cpu/ti/am335x/bootblock_media.c | 71 +---- src/cpu/ti/am335x/nand.c | 8 +- src/cpu/via/nano/update_ucode.c | 5 +- src/device/dram/spd_cache.c | 4 +- src/device/oprom/realmode/x86.c | 14 +- src/device/oprom/yabel/vbe.c | 7 +- src/device/pci_rom.c | 8 +- src/drivers/intel/fsp1_0/fastboot_cache.c | 7 +- src/drivers/intel/fsp1_1/fastboot_cache.c | 3 +- src/drivers/pc80/mc146818rtc.c | 8 +- src/drivers/spi/spi_flash.c | 7 +- src/include/cbfs.h | 153 +++++---- src/include/cbfs_core.h | 128 -------- src/include/rmodule.h | 4 +- src/lib/Makefile.inc | 14 +- src/lib/cbfs.c | 354 ++++++++++++--------- src/lib/cbfs_boot_props.c | 70 ++++ src/lib/cbfs_core.c | 324 ------------------- src/lib/cbfs_core.h | 47 --- src/lib/cbfs_spi.c | 72 ----- src/lib/coreboot_table.c | 4 +- src/lib/loaders/cbfs_payload_loader.c | 5 +- src/lib/loaders/cbfs_ramstage_loader.c | 3 +- src/lib/loaders/cbfs_romstage_loader.c | 2 +- src/lib/rmodule.c | 48 ++- src/mainboard/emulation/qemu-armv7/media.c | 75 +---- src/mainboard/google/bolt/romstage.c | 4 +- src/mainboard/google/butterfly/mainboard.c | 5 +- src/mainboard/google/falco/romstage.c | 4 +- src/mainboard/google/link/romstage.c | 4 +- src/mainboard/google/panther/lan.c | 3 +- src/mainboard/google/peach_pit/romstage.c | 17 +- src/mainboard/google/peppy/romstage.c | 4 +- src/mainboard/google/rambi/romstage.c | 9 +- src/mainboard/google/samus/spd/spd.c | 13 +- src/mainboard/google/slippy/romstage.c | 4 +- src/mainboard/google/urara/boardid.c | 23 +- src/mainboard/samsung/lumpy/romstage.c | 4 +- src/mainboard/siemens/mc_tcu3/modhwinfo.c | 6 +- src/northbridge/amd/agesa/common/common.c | 3 +- src/northbridge/amd/agesa/def_callouts.c | 4 +- src/northbridge/amd/pi/agesawrapper.c | 11 +- src/northbridge/amd/pi/def_callouts.c | 4 +- src/northbridge/intel/haswell/mrccache.c | 3 +- src/northbridge/intel/haswell/raminit.c | 4 +- src/northbridge/intel/i82830/vga.c | 3 +- src/northbridge/intel/sandybridge/mrccache.c | 3 +- src/northbridge/intel/sandybridge/raminit.c | 3 +- src/soc/intel/baytrail/romstage/raminit.c | 3 +- src/soc/intel/broadwell/romstage/raminit.c | 3 +- src/soc/nvidia/tegra124/spi.c | 75 ----- src/soc/nvidia/tegra132/ccplex.c | 15 +- src/soc/nvidia/tegra132/spi.c | 75 ----- src/soc/qualcomm/ipq806x/blobs_init.c | 12 +- src/soc/samsung/exynos5250/alternate_cbfs.c | 64 ---- src/soc/samsung/exynos5420/alternate_cbfs.c | 64 ---- .../google/chromeos/vboot2/vboot_loader.c | 27 +- 64 files changed, 590 insertions(+), 1573 deletions(-) diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c index 484f1ee..04969f5 100644 --- a/src/arch/riscv/rom_media.c +++ b/src/arch/riscv/rom_media.c @@ -19,76 +19,13 @@ * MA 02110-1301 USA */ #include <boot_device.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> /* This assumes that the CBFS resides at 0x0, which is true for the default * configuration. */ -static const struct mem_region_device gboot_dev = +static const struct mem_region_device boot_dev = MEM_REGION_DEV_INIT(NULL, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { - return &gboot_dev.rdev; -} - -static int rom_media_open(struct cbfs_media *media) { - return 0; -} - -static void *rom_media_map(struct cbfs_media *media, size_t offset, size_t count) { - const struct region_device *boot_dev; - void *ptr; - - printk(BIOS_INFO, "%s: media %p, offset %lx, size %ld.\n", __func__, media, offset, count); - boot_dev = media->context; - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void *rom_media_unmap(struct cbfs_media *media, const void *address) { - const struct region_device *boot_dev; - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -static size_t rom_media_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - const struct region_device *boot_dev; - - boot_dev = media->context; - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static int rom_media_close(struct cbfs_media *media) { - return 0; -} - -static int init_rom_media_cbfs(struct cbfs_media *media) { - boot_device_init(); - media->context = (void *)boot_device_ro(); - media->open = rom_media_open; - media->close = rom_media_close; - media->map = rom_media_map; - media->unmap = rom_media_unmap; - media->read = rom_media_read; - return 0; -} - -int init_default_cbfs_media(struct cbfs_media *media) { - return init_rom_media_cbfs(media); + return &boot_dev.rdev; } diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index e308be9..0d88a6d 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -5,7 +5,6 @@ romstage-y += cbfs_and_run.c romstage-y += memset.c romstage-y += memcpy.c romstage-y += memmove.c -romstage-y += rom_media.c romstage-y += mmap_boot.c endif # CONFIG_ARCH_ROMSTAGE_X86_32 @@ -22,7 +21,6 @@ ramstage-y += memset.c ramstage-y += memcpy.c ramstage-y += memmove.c ramstage-y += ebda.c -ramstage-y += rom_media.c ramstage-y += mmap_boot.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S @@ -33,7 +31,6 @@ romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c smm-y += memset.c smm-y += memcpy.c smm-y += memmove.c -smm-y += rom_media.c smm-y += mmap_boot.c rmodules_x86_32-y += memset.c diff --git a/src/arch/x86/lib/mmap_boot.c b/src/arch/x86/lib/mmap_boot.c index eb7b23e..4dd269b 100644 --- a/src/arch/x86/lib/mmap_boot.c +++ b/src/arch/x86/lib/mmap_boot.c @@ -18,6 +18,10 @@ */ #include <boot_device.h> +#include <console/console.h> +#include <cbfs.h> +#include <endian.h> +#include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(-(int32_t)CONFIG_ROM_SIZE)) @@ -29,3 +33,43 @@ const struct region_device *boot_device_ro(void) { return &boot_dev.rdev; } + +int cbfs_boot_region_properties(struct cbfs_props *props) +{ + struct cbfs_header header; + int32_t offset; + const struct region_device *bdev; + + bdev = boot_device_ro(); + + rdev_readat(bdev, &offset, CONFIG_ROM_SIZE - sizeof(offset), + sizeof(offset)); + + /* The offset is relative to the end of the media. */ + offset += CONFIG_ROM_SIZE; + + rdev_readat(bdev, &header , offset, sizeof(header)); + + header.magic = ntohl(header.magic); + header.romsize = ntohl(header.romsize); + header.bootblocksize = ntohl(header.bootblocksize); + header.align = ntohl(header.align); + header.offset = ntohl(header.offset); + + if (header.magic != CBFS_HEADER_MAGIC) + return -1; + + props->align = header.align; + props->offset = header.offset; + if (CONFIG_ROM_SIZE != header.romsize) + props->size = CONFIG_ROM_SIZE; + else + props->size = header.romsize; + props->size -= props->offset; + props->size -= header.bootblocksize; + props->size = ALIGN_DOWN(props->size, props->align); + + printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} diff --git a/src/arch/x86/lib/rom_media.c b/src/arch/x86/lib/rom_media.c deleted file mode 100644 index c2c4721..0000000 --- a/src/arch/x86/lib/rom_media.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include <boot_device.h> -#include <cbfs.h> -#include <string.h> - -#ifdef LIBPAYLOAD -# define printk(x...) -# define init_default_cbfs_media libpayload_init_default_cbfs_media - extern int libpayload_init_default_cbfs_media(struct cbfs_media *media); -#else -# include <console/console.h> -#endif - -// Implementation of memory-mapped ROM media source on X86. - -static int x86_rom_open(struct cbfs_media *media) { - return 0; -} - -static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t count) { - void *ptr; - const struct region_device *boot_dev; - - boot_dev = media->context; - - /* Extremely large offsets are considered relative to end of region. */ - if ((uint32_t)offset > (uint32_t)0xf0000000) - offset += region_device_sz(boot_dev); - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void *x86_rom_unmap(struct cbfs_media *media, const void *address) { - return NULL; -} - -static size_t x86_rom_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) { - void *ptr; - - ptr = x86_rom_map(media, offset, count); - - if (ptr == (void *)-1) - return 0; - - memcpy(dest, ptr, count); - x86_rom_unmap(media, ptr); - return count; -} - -static int x86_rom_close(struct cbfs_media *media) { - return 0; -} - -static int init_x86rom_cbfs_media(struct cbfs_media *media) { - boot_device_init(); - - media->context = (void *)boot_device_ro(); - - if (media->context == NULL) - return -1; - - media->open = x86_rom_open; - media->close = x86_rom_close; - media->map = x86_rom_map; - media->unmap = x86_rom_unmap; - media->read = x86_rom_read; - return 0; -} - -int init_default_cbfs_media(struct cbfs_media *media) { - return init_x86rom_cbfs_media(media); -} diff --git a/src/cpu/allwinner/a10/bootblock_media.c b/src/cpu/allwinner/a10/bootblock_media.c index a585bca..17c6039 100644 --- a/src/cpu/allwinner/a10/bootblock_media.c +++ b/src/cpu/allwinner/a10/bootblock_media.c @@ -5,16 +5,10 @@ * Subject to the GNU GPL v2, or (at your option) any later version. */ #include <boot_device.h> -#include <cbfs.h> #include <console/console.h> const struct region_device *boot_device_ro(void) { - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ printk(BIOS_ERR, "Oh my! I don't know how to access CBFS yet."); - return -1; + return NULL; } diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 938f5f6..d5bf756 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -105,8 +105,8 @@ void amd_update_microcode_from_cbfs(u32 equivalent_processor_rev_id) return; } - ucode = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, MICROCODE_CBFS_FILE, - CBFS_TYPE_MICROCODE, &ucode_len); + ucode = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, + CBFS_TYPE_MICROCODE, &ucode_len); if (!ucode) { UCODE_DEBUG("microcode file not found. Skipping updates.\n"); return; diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c index 947dfd7..c4d2cd0 100644 --- a/src/cpu/intel/microcode/microcode.c +++ b/src/cpu/intel/microcode/microcode.c @@ -109,25 +109,29 @@ void intel_microcode_load_unlocked(const void *microcode_patch) const void *intel_microcode_find(void) { - struct cbfs_file *microcode_file; const struct microcode *ucode_updates; - u32 eax, microcode_len; + size_t microcode_len; + u32 eax; u32 pf, rev, sig, update_size; unsigned int x86_model, x86_family; msr_t msr; #ifdef __PRE_RAM__ - microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); -#else - microcode_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, - MICROCODE_CBFS_FILE); -#endif + struct cbfs_file *microcode_file; + microcode_file = walkcbfs_head((char *) MICROCODE_CBFS_FILE); if (!microcode_file) return NULL; ucode_updates = CBFS_SUBHEADER(microcode_file); microcode_len = ntohl(microcode_file->len); +#else + ucode_updates = cbfs_boot_map_with_leak(MICROCODE_CBFS_FILE, + CBFS_TYPE_MICROCODE, + &microcode_len); + if (ucode_updates == NULL) + return NULL; +#endif /* CPUID sets MSR 0x8B iff a microcode update has been loaded. */ msr.lo = 0; diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/cpu/ti/am335x/bootblock_media.c index 702d91a..8eb4c27 100644 --- a/src/cpu/ti/am335x/bootblock_media.c +++ b/src/cpu/ti/am335x/bootblock_media.c @@ -18,80 +18,13 @@ */ #include <boot_device.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> #include <symbols.h> /* FIXME: No idea how big the internal SRAM actually is. */ -static const struct mem_region_device gboot_dev = +static const struct mem_region_device boot_dev = MEM_REGION_DEV_INIT(_dram, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { - return &gboot_dev.rdev; -} - -static int dummy_open(struct cbfs_media *media) -{ - return 0; -} - -static int dummy_close(struct cbfs_media *media) -{ - return 0; -} - -static void * on_chip_memory_map(struct cbfs_media *media, size_t offset, - size_t count) -{ - const struct region_device *boot_dev; - void *ptr; - - boot_dev = media->context; - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void * dummy_unmap(struct cbfs_media *media, const void *address) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -static size_t on_chip_memory_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - boot_device_init(); - - media->context = (void *)boot_device_ro(); - media->open = dummy_open; - media->close = dummy_close; - media->map = on_chip_memory_map; - media->unmap = dummy_unmap; - media->read = on_chip_memory_read; - - return 0; + return &boot_dev.rdev; } diff --git a/src/cpu/ti/am335x/nand.c b/src/cpu/ti/am335x/nand.c index 7e67e97..73dedbb 100644 --- a/src/cpu/ti/am335x/nand.c +++ b/src/cpu/ti/am335x/nand.c @@ -18,15 +18,9 @@ */ #include <boot_device.h> -#include <cbfs.h> const struct region_device *boot_device_ro(void) { - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ /* FIXME: add support for reading coreboot from NAND */ - return -1; + return NULL; } diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index aa0adeb..a69a291 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -110,9 +110,8 @@ unsigned int nano_update_ucode(void) u32 *ucode_data; size_t ucode_len; - ucode_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "cpu_microcode_blob.bin", - CBFS_TYPE_MICROCODE, &ucode_len); + ucode_data = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, &ucode_len); /* Oops, did you forget to include the microcode ? */ if(ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index 8abb791..fcb1391 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -36,8 +36,8 @@ int read_spd_from_cbfs(u8 *buf, int idx) size_t min_len = (idx + 1) * SPD_SIZE; printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); if (spd_file_len < min_len) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 919fd6d..7f8c166 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -273,10 +273,9 @@ void vbe_set_graphics(void) vbe_set_mode(&mode_info); #if CONFIG_BOOTSPLASH struct jpeg_decdata *decdata; - unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); + unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", + CBFS_TYPE_BOOTSPLASH, + NULL); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; @@ -379,6 +378,9 @@ static u32 VSA_vrRead(u16 classIndex) void do_vsmbios(void) { + struct prog vsa = { + .name = "vsa", + }; printk(BIOS_DEBUG, "Preparing for VSA...\n"); /* Set up C interrupt handlers */ @@ -390,8 +392,8 @@ void do_vsmbios(void) /* Make sure the code is placed. */ setup_realmode_code(); - if ((unsigned int)cbfs_load_stage(CBFS_DEFAULT_MEDIA, "vsa") != - VSA2_ENTRY_POINT) { + if (cbfs_boot_load_stage(&vsa) || + (uintptr_t)prog_entry(&vsa) != VSA2_ENTRY_POINT) { printk(BIOS_ERR, "Failed to load VSA.\n"); return; } diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index ab92c0a..07eb1f3 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -724,10 +724,9 @@ void vbe_set_graphics(void) * cares. */ // int imagesize = 1024*768*2; - unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH, - NULL); + unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", + CBFS_TYPE_BOOTSPLASH, + NULL); if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index dbc05ac..dd70770 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -38,8 +38,7 @@ struct rom_header *pci_rom_probe(struct device *dev) struct pci_data *rom_data; /* If it's in FLASH, then don't check device for ROM. */ - rom_header = cbfs_load_optionrom(CBFS_DEFAULT_MEDIA, dev->vendor, - dev->device, NULL); + rom_header = cbfs_boot_map_optionrom(dev->vendor, dev->device); u32 vendev = (dev->vendor << 16) | dev->device; u32 mapped_vendev = vendev; @@ -48,10 +47,9 @@ struct rom_header *pci_rom_probe(struct device *dev) if (!rom_header) { if (vendev != mapped_vendev) { - rom_header = cbfs_load_optionrom( - CBFS_DEFAULT_MEDIA, + rom_header = cbfs_boot_map_optionrom( mapped_vendev >> 16, - mapped_vendev & 0xffff, NULL); + mapped_vendev & 0xffff); } } diff --git a/src/drivers/intel/fsp1_0/fastboot_cache.c b/src/drivers/intel/fsp1_0/fastboot_cache.c index e8651bb..9f45ed5 100644 --- a/src/drivers/intel/fsp1_0/fastboot_cache.c +++ b/src/drivers/intel/fsp1_0/fastboot_cache.c @@ -63,10 +63,9 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { size_t region_size; - *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", - CBFS_TYPE_MRC_CACHE, - &region_size); + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", + CBFS_TYPE_MRC_CACHE, + &region_size); return region_size; } diff --git a/src/drivers/intel/fsp1_1/fastboot_cache.c b/src/drivers/intel/fsp1_1/fastboot_cache.c index e8651bb..4ad17e8 100644 --- a/src/drivers/intel/fsp1_1/fastboot_cache.c +++ b/src/drivers/intel/fsp1_1/fastboot_cache.c @@ -63,8 +63,7 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { size_t region_size; - *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", CBFS_TYPE_MRC_CACHE, &region_size); diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index 4f034a2..fe2e1f3 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -212,8 +212,8 @@ enum cb_err get_option(void *dest, const char *name) namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); @@ -295,8 +295,8 @@ enum cb_err set_option(const char *name, void *value) namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); /* find the requested entry record */ - ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT, NULL); + ct = cbfs_boot_map_with_leak("cmos_layout.bin", + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "cmos_layout.bin could not be found. " "Options are disabled\n"); diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d2a3c66..b95a0a2 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -7,6 +7,7 @@ * Licensed under the GPL-2 or later. */ +#include <boot_device.h> #include <cbfs.h> #include <cpu/x86/smm.h> #include <delay.h> @@ -407,10 +408,8 @@ void lb_spi_flash(struct lb_header *header) flash->size = sizeof(*flash); /* Try to get the flash device if not loaded yet */ - if (!spi_flash_dev) { - struct cbfs_media media; - init_default_cbfs_media(&media); - } + if (!spi_flash_dev) + boot_device_init(); if (spi_flash_dev) { flash->flash_size = spi_flash_dev->size; diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 1d7917c..f914ffb 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -1,14 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> - * Copyright (C) 2013-2015 Google, Inc. + * Copyright 2015 Google Inc. * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -20,75 +14,100 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- + * Foundation, Inc. */ #ifndef _CBFS_H_ #define _CBFS_H_ -#include <cbfs_core.h> - -int init_backing_media(struct cbfs_media **media, struct cbfs_media *backing); -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device, void * dest); -void *cbfs_load_stage(struct cbfs_media *media, const char *name); -void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset); -/* Load a stage from a prog structure. Returns < 0 on error. 0 on success. */ -struct prog; -int cbfs_load_prog_stage(struct cbfs_media *media, struct prog *prog); -int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, - struct prog *prog, ssize_t offset); - -/* Simple buffer for streaming media. */ -struct cbfs_simple_buffer { - char *buffer; - size_t allocated; - size_t size; - size_t last_allocate; -}; +#include <cbfs_serialized.h> +#include <program_loading.h> +#include <region.h> + +/* + * CBFS operations consist of the following concepts: + * - region_device for the boot media + * - cbfsd which is a descriptor for representing a cbfs instance + * - cbfsf which is a file handle for manipulating cbfs files + */ -void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count); +/* Descriptor for cbfs lookup operations. */ +struct cbfsd; +/* File handle representing a cbfs file. */ +struct cbfsf; -void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address); +/*********************************************** + * Perform CBFS operations on the boot device. * + ***********************************************/ +/* Return mapping of option rom found in boot device. NULL on error. */ +void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device); +/* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ +int cbfs_boot_load_stage(struct prog *prog); +/* Locate file by name and optional type. Return 0 on success. < 0 on error. */ +int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type); +/* Map file into memory leaking the mapping. Only should be used when + * leaking mappings are a no-op. Returns NULL on error, else returns + * the mapping and sets the size of the file. */ +void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); -/* - * Defined in individual arch / board implementation. - * - * it returns 0 on success and non-zero on error. - */ -int init_default_cbfs_media(struct cbfs_media *media); +/************************************************* + * Perform CBFS operations on the provided file. * + *************************************************/ + +/* Map file into memory. Return NULL on error. */ +void *cbfs_file_mmap(const struct cbfsf *fh, size_t offset, size_t size); +/* Unmap previously mapped file. Returns 0 on success. < 0 on error. */ +int cbfs_file_munmap(const struct cbfsf *fh, void *mapping); +/* Read size bytes into b at offset in file. Returns the number of bytes + * read on success. Returns < 0 on error. */ +ssize_t cbfs_file_readat(const struct cbfsf *fh, void *b, size_t offset, + size_t size); +/* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ +int cbfs_file_stage_load(const struct cbfsf *fh, struct prog *prog); + +/******************************************************* + * Perform CBFS operations on the provided descriptor. * + *******************************************************/ -#if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) +/* Locate file by name and optional type. Returns 0 on succcess else < 0 on + * error.*/ +int cbfs_locate(struct cbfsf *fh, const struct cbfsd *cbfs, const char *name, + uint32_t *type); void cbfs_set_header_offset(size_t offset); -#else -static inline void cbfs_set_header_offset(size_t offset) {} -#endif +size_t cbfs_get_header_offset(void); + +/***************************************************************** + * Support structures and functions. Direct field access should * + * only be done by implementers of cbfs regions -- Not the above * + * API. * + *****************************************************************/ + +struct cbfsd { + const struct region_device *rdev; + size_t align; +}; + +struct cbfsf { + struct region_device rdev; +}; + +static inline size_t cbfs_file_size(const struct cbfsf *fh) +{ + return region_sz(&fh->rdev.region); +} + +/* The cbfs_props struct describes the properties associated with a CBFS. */ +struct cbfs_props { + /* Each file is aligned. */ + size_t align; + /* CBFS starts at the following offset within the boot region. */ + size_t offset; + /* CBFS size. */ + size_t size; +}; + +/* Return < 0 on error otherwise props are filled out accordingly. */ +int cbfs_boot_region_properties(struct cbfs_props *props); + #endif diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h deleted file mode 100644 index c71cc26..0000000 --- a/src/include/cbfs_core.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> - * Copyright (C) 2012 Google, Inc. - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- - */ - -#ifndef _CBFS_CORE_H_ -#define _CBFS_CORE_H_ - -#include <endian.h> -#include <stddef.h> -#include <stdint.h> -#include <cbfs_serialized.h> - -#define CBFS_HEADER_INVALID_ADDRESS ((void*)(0xffffffff)) - -#define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file)) -#define CBFS_SUBHEADER(_p) ( (void *) ((((uint8_t *) (_p)) + ntohl((_p)->offset))) ) - -/* - * ROMCC does not understand uint64_t, so we hide future definitions as they are - * unlikely to be ever needed from ROMCC - */ -#ifndef __ROMCC__ - -#define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) -#define CBFS_DEFAULT_MEDIA ((void*)(0x0)) - -/* Media for CBFS to load files. */ -struct cbfs_media { - - /* implementation dependent context, to hold resource references */ - void *context; - - /* opens media and returns 0 on success, -1 on failure */ - int (*open)(struct cbfs_media *media); - - /* returns number of bytes read from media into dest, starting from - * offset for count of bytes */ - size_t (*read)(struct cbfs_media *media, void *dest, size_t offset, - size_t count); - - /* returns a pointer to memory with count of bytes from media source - * starting from offset, or CBFS_MEDIA_INVALID_MAP_ADDRESS on failure. - * Note: mapped data can't be free unless unmap is called, even if you - * do close first. */ - void * (*map)(struct cbfs_media *media, size_t offset, size_t count); - - /* returns NULL and releases the memory by address, which was allocated - * by map */ - void * (*unmap)(struct cbfs_media *media, const void *address); - - /* closes media and returns 0 on success, -1 on failure. */ - int (*close)(struct cbfs_media *media); -}; - -/* - * Locate file by name and fill in cbfs_file in host byte order. Returns - * < 0 on error, else the offset of the file data. - */ -ssize_t cbfs_locate_file(struct cbfs_media *media, struct cbfs_file *file, - const char *name); - -/* Read count bytes at offset into dest. Return number of bytes read. */ -size_t cbfs_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count); - -/* returns pointer to a file entry inside CBFS or NULL */ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); - -/* returns pointer to file content inside CBFS after if type is correct */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz); - -/* returns decompressed size on success, 0 on failure */ -int cbfs_decompress(int algo, void *src, void *dst, int len); - -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); - -#endif /* __ROMCC__ */ - -#endif diff --git a/src/include/rmodule.h b/src/include/rmodule.h index 242ed91..5dc795c 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -54,7 +54,7 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, /* Support for loading rmodule stages. This API is only available when * using dynamic cbmem because it uses the dynamic cbmem API to obtain * the backing store region for the stage. */ -struct cbfs_stage; +struct cbfsf; struct prog; struct rmod_stage_load { @@ -63,7 +63,7 @@ struct rmod_stage_load { }; /* Both of the following functions return 0 on success, -1 on error. */ -int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage); +int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfsf *fh); int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl); struct rmodule { diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 6d685ff..1160b28 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,7 +19,8 @@ subdirs-y += loaders bootblock-y += prog_ops.c -bootblock-y += cbfs.c cbfs_core.c +bootblock-y += cbfs.c +bootblock-y += cbfs_boot_props.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c @@ -37,9 +38,9 @@ bootblock-y += fmap.c verstage-y += prog_ops.c verstage-y += delay.c verstage-y += cbfs.c -verstage-y += cbfs_core.c verstage-y += halt.c verstage-y += fmap.c +verstage-y += cbfs_boot_props.c verstage-y += memcmp.c verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c verstage-y += region.c @@ -66,7 +67,8 @@ $(foreach arch,$(ARCH_SUPPORTED),\ romstage-y += fmap.c romstage-$(CONFIG_I2C_TPM) += delay.c -romstage-y += cbfs.c cbfs_core.c +romstage-y += cbfs.c +romstage-y += cbfs_boot_props.c romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_COMPRESS_RAMSTAGE) += lzma.c lzmadecode.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c @@ -100,7 +102,8 @@ smm-$(CONFIG_SMM_TSEG) += malloc.c ramstage-y += delay.c ramstage-y += fallback_boot.c ramstage-y += compute_ip_checksum.c -ramstage-y += cbfs.c cbfs_core.c +ramstage-y += cbfs.c +ramstage-y += cbfs_boot_props.c ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c @@ -150,10 +153,11 @@ ramstage-y += region.c romstage-y += boot_device.c ramstage-y += boot_device.c +smm-y += cbfs.c memcmp.c +smm-y += region.c smm-y += region.c smm-y += boot_device.c smm-y += fmap.c -smm-y += cbfs.c cbfs_core.c memcmp.c smm-$(CONFIG_COMPILER_GCC) += gcc.c bootblock-y += version.c diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 8239f07..8027231 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -1,8 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2011 secunet Security Networks AG + * Copyright 2015 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,195 +15,265 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + * Foundation, Inc. */ +#include <assert.h> +#include <string.h> +#include <stdlib.h> +#include <boot_device.h> +#include <cbfs.h> +#include <endian.h> +#include <lib.h> +#include <symbols.h> + +#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) +#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) +#if IS_ENABLED(CONFIG_DEBUG_CBFS) +#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) +#else +#define DEBUG(x...) +#endif -#include <program_loading.h> -#include "cbfs_core.h" - -#ifndef __SMM__ -static inline int tohex4(unsigned int c) +void cbfs_set_header_offset(size_t offset) { - return (c <= 9) ? (c + '0') : (c - 10 + 'a'); + if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { + _cbfs_header_offset[0] = offset; + LOG("header set to: %#zx\n", offset); + } } -static void tohex16(unsigned int val, char* dest) +size_t cbfs_get_header_offset(void) { - dest[0] = tohex4(val>>12); - dest[1] = tohex4((val>>8) & 0xf); - dest[2] = tohex4((val>>4) & 0xf); - dest[3] = tohex4(val & 0xf); + if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) + return _cbfs_header_offset[0]; + return 0; } -void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, - uint16_t device, void *dest) +int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - char name[17] = "pciXXXX,XXXX.rom"; - struct cbfs_optionrom *orom; - uint8_t *src; + struct cbfsd cbfs; + struct region_device rdev; + const struct region_device *boot_dev; + struct cbfs_props props; - tohex16(vendor, name+3); - tohex16(device, name+8); + boot_device_init(); - orom = (struct cbfs_optionrom *) - cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); + if (cbfs_boot_region_properties(&props)) + return -1; - if (orom == NULL) - return NULL; + /* All boot CBFS operations are performed using the RO devie. */ + boot_dev = boot_device_ro(); - /* They might have specified a dest address. If so, we can decompress. - * If not, there's not much hope of decompressing or relocating the rom. - * in the common case, the expansion rom is uncompressed, we - * pass 0 in for the dest, and all we have to do is find the rom and - * return a pointer to it. - */ + if (boot_dev == NULL) + return -1; - /* BUG: the cbfstool is (not yet) including a cbfs_optionrom header */ - src = (uint8_t *)orom; // + sizeof(struct cbfs_optionrom); + if (rdev_chain(&rdev, boot_dev, props.offset, props.size)) + return -1; - if (! dest) - return src; + cbfs.rdev = &rdev; + cbfs.align = props.align; - if (!cbfs_decompress(ntohl(orom->compression), - src, - dest, - ntohl(orom->len))) + return cbfs_locate(fh, &cbfs, name, type); +} + +void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) +{ + struct cbfsf fh; + size_t fsize; + + if (cbfs_boot_locate(&fh, name, &type)) return NULL; - return dest; + fsize = cbfs_file_size(&fh); + + if (size != NULL) + *size = fsize; + + return cbfs_file_mmap(&fh, 0, fsize); } -int cbfs_load_prog_stage_by_offset(struct cbfs_media *media, - struct prog *prog, ssize_t offset) +void *cbfs_file_mmap(const struct cbfsf *fh, size_t offset, size_t size) { - struct cbfs_stage stage; - struct cbfs_media backing_store; + return rdev_mmap(&fh->rdev, offset, size); +} - if (init_backing_media(&media, &backing_store)) - return -1; +int cbfs_file_munmap(const struct cbfsf *fh, void *mapping) +{ + return rdev_munmap(&fh->rdev, mapping); +} - if (cbfs_read(media, &stage, offset, sizeof(stage)) != sizeof(stage)) { - ERROR("ERROR: failed to read stage header\n"); - return -1; - } +ssize_t cbfs_file_readat(const struct cbfsf *fh, void *b, size_t offset, + size_t size) +{ + return rdev_readat(&fh->rdev, b, offset, size); +} + +int cbfs_locate(struct cbfsf *fh, const struct cbfsd *cbfs, const char *name, + uint32_t *type) +{ + size_t offset; + const struct region_device *rd; + size_t align; + + offset = 0; + rd = cbfs->rdev; + align = cbfs->align; + + LOG("Locating '%s'\n", name); + + /* Try to scan the entire cbfs region looking for file name. */ + while (1) { + struct cbfs_file file; + const size_t fsz = sizeof(file); + char *fname; + int name_match; + size_t datasz; + + DEBUG("Checking offset %zx\n", offset); + + /* Can't read file. Nothing else to do but bail out. */ + if (rdev_readat(rd, &file, offset, fsz) != fsz) + break; + + if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) { + offset++; + offset = ALIGN_UP(offset, align); + continue; + } - LOG("loading stage from %#zx @ 0x%llx (%d bytes), entry @ 0x%llx\n", - offset, stage.load, stage.memlen, stage.entry); + file.len = ntohl(file.len); + file.type = ntohl(file.type); + file.offset = ntohl(file.offset); - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)(uintptr_t)stage.load, 0, stage.memlen); + /* See if names match. */ + fname = rdev_mmap(rd, offset + fsz, file.offset - fsz); - if (stage.compression == CBFS_COMPRESS_NONE) { - if (cbfs_read(media, (void *)(uintptr_t)stage.load, - offset + sizeof(stage), stage.len) != stage.len) { - ERROR("ERROR: Reading stage failed.\n"); - return -1; + if (fname == NULL) + break; + + name_match = !strcmp(fname, name); + rdev_munmap(rd, fname); + + if (!name_match) { + DEBUG(" Unmatched '%s' at %zx\n", fname, offset); + offset += file.offset + file.len; + offset = ALIGN_UP(offset, align); + continue; } - } else { - void *data = media->map(media, offset + sizeof(stage), - stage.len); - if (data == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Mapping stage failed.\n"); - return -1; + + if (type != NULL && *type != file.type) { + DEBUG(" Unmatched type %x at %zx\n", file.type, offset); + offset += file.offset + file.len; + offset = ALIGN_UP(offset, align); + continue; } - if (!cbfs_decompress(stage.compression, data, - (void *)(uintptr_t)stage.load, stage.len)) - return -1; - media->unmap(media, data); - } - arch_segment_loaded(stage.load, stage.memlen, SEG_FINAL); - DEBUG("stage loaded\n"); + LOG("Found @ offset %zx size %x\n", offset, file.len); + /* File and type match. Create a chained region_device to + * represent the cbfs file. */ + offset += file.offset; + datasz = file.len; + if (rdev_chain(&fh->rdev, rd, offset, datasz)) + break; + + /* Success. */ + return 0; + } - prog_set_area(prog, (void *)(uintptr_t)stage.load, stage.memlen); - prog_set_entry(prog, (void *)(uintptr_t)stage.entry, NULL); + LOG("'%s' not found.\n", name); + return -1; +} - return 0; +static size_t inflate(void *src, void *dst) +{ + if (ENV_BOOTBLOCK || ENV_VERSTAGE) + return 0; + if (ENV_ROMSTAGE && !IS_ENABLED(CONFIG_COMPRESS_RAMSTAGE)) + return 0; + return ulzma(src, dst); } -int cbfs_load_prog_stage(struct cbfs_media *media, struct prog *prog) +static inline int tohex4(unsigned int c) { - struct cbfs_file file; - ssize_t offset; - struct cbfs_media backing_store; + return (c <= 9) ? (c + '0') : (c - 10 + 'a'); +} - if (init_backing_media(&media, &backing_store)) - return -1; +static void tohex16(unsigned int val, char* dest) +{ + dest[0] = tohex4(val>>12); + dest[1] = tohex4((val>>8) & 0xf); + dest[2] = tohex4((val>>4) & 0xf); + dest[3] = tohex4(val & 0xf); +} - offset = cbfs_locate_file(media, &file, prog->name); - if (offset < 0 || file.type != CBFS_TYPE_STAGE) - return -1; +void *cbfs_boot_map_optionrom(uint16_t vendor, uint16_t device) +{ + char name[17] = "pciXXXX,XXXX.rom"; - if (cbfs_load_prog_stage_by_offset(media, prog, offset) < 0) - return -1; + tohex16(vendor, name+3); + tohex16(device, name+8); - return 0; + return cbfs_boot_map_with_leak(name, CBFS_TYPE_OPTIONROM, NULL); } -void *cbfs_load_stage_by_offset(struct cbfs_media *media, ssize_t offset) +int cbfs_boot_load_stage(struct prog *stage) { - struct prog prog = { - .name = NULL, - }; + struct cbfsf fh; + uint32_t type = CBFS_TYPE_STAGE; - if (cbfs_load_prog_stage_by_offset(media, &prog, offset) < 0) - return (void *)-1; + if (cbfs_boot_locate(&fh, stage->name, &type)) + return -1; - return prog_entry(&prog); + return cbfs_file_stage_load(&fh, stage); } -void *cbfs_load_stage(struct cbfs_media *media, const char *name) +int cbfs_file_stage_load(const struct cbfsf *fh, struct prog *pstage) { - struct prog prog = { - .name = name, - }; + struct cbfs_stage stage; + uint8_t *load; + void *entry; + size_t fsize; + size_t foffset; - if (cbfs_load_prog_stage(media, &prog) < 0) - return (void *)-1; + if (cbfs_file_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) + return 0; - return prog_entry(&prog); -} + fsize = cbfs_file_size(fh); + fsize -= sizeof(stage); + foffset = 0; + foffset += sizeof(stage); -/* Simple buffer */ - -void *cbfs_simple_buffer_map(struct cbfs_simple_buffer *buffer, - struct cbfs_media *media, - size_t offset, size_t count) { - void *address = buffer->buffer + buffer->allocated; - DEBUG("simple_buffer_map(offset=%zd, count=%zd): " - "allocated=%zd, size=%zd, last_allocate=%zd\n", - offset, count, buffer->allocated, buffer->size, - buffer->last_allocate); - if (buffer->allocated + count > buffer->size) { - ERROR("simple_buffer: no room to map %zd bytes from %#zx\n", - count, offset); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - } - if (media->read(media, address, offset, count) != count) { - ERROR("simple_buffer: fail to read %zd bytes from 0x%zx\n", - count, offset); - return CBFS_MEDIA_INVALID_MAP_ADDRESS; - } - buffer->allocated += count; - buffer->last_allocate = count; - return address; -} + assert(fsize == stage.len); -void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, - const void *address) { - // TODO Add simple buffer management so we can free more than last - // allocated one. - DEBUG("simple_buffer_unmap(address=0x%p): " - "allocated=%zd, size=%zd, last_allocate=%zd\n", - address, buffer->allocated, buffer->size, - buffer->last_allocate); - if ((buffer->buffer + buffer->allocated - buffer->last_allocate) == - address) { - buffer->allocated -= buffer->last_allocate; - buffer->last_allocate = 0; - } - return NULL; -} + /* Note: cbfs_stage fields are currently in the endianness of the + * running processor. */ + load = (void *)(uintptr_t)stage.load; + entry = (void *)(uintptr_t)stage.entry; -#endif + if (stage.compression == CBFS_COMPRESS_NONE) { + if (cbfs_file_readat(fh, load, foffset, fsize) != fsize) + return -1; + } else if (stage.compression == CBFS_COMPRESS_LZMA) { + void *map = cbfs_file_mmap(fh, foffset, fsize); + + if (map == NULL) + return -1; + + fsize = inflate(map, load); + + cbfs_file_munmap(fh, map); + + if (!fsize) + return -1; + } else + return -1; + + /* Clear area not covered by file. */ + memset(&load[fsize], 0, stage.memlen - fsize); + + prog_set_area(pstage, load, stage.memlen); + prog_set_entry(pstage, entry, NULL); + + return 0; +} diff --git a/src/lib/cbfs_boot_props.c b/src/lib/cbfs_boot_props.c new file mode 100644 index 0000000..7e7bb8a --- /dev/null +++ b/src/lib/cbfs_boot_props.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <console/console.h> +#include <endian.h> +#include <region.h> + +/* This function is marked as weak to allow a particular platform to + * override the logic. This implementation should work for most devices. */ +int __attribute__((weak)) cbfs_boot_region_properties(struct cbfs_props *props) +{ + struct cbfs_header header; + const struct region_device *bdev; + int32_t rel_offset; + size_t offset; + size_t base_offset; + + bdev = boot_device_ro(); + + if (bdev == NULL) + return -1; + + base_offset = cbfs_get_header_offset(); + base_offset += CONFIG_CBFS_SIZE; + + /* Find location of header using signed 32-bit offset from + * end of CBFS region. */ + offset = base_offset - sizeof(int32_t); + if (rdev_readat(bdev, &rel_offset, offset, sizeof(int32_t)) < 0) + return -1; + + offset = base_offset + rel_offset; + if (rdev_readat(bdev, &header, offset, sizeof(header)) < 0) + return -1; + + header.magic = ntohl(header.magic); + header.romsize = ntohl(header.romsize); + header.align = ntohl(header.align); + header.offset = ntohl(header.offset); + + if (header.magic != CBFS_HEADER_MAGIC) + return -1; + + props->align = header.align; + props->offset = header.offset; + props->size = header.romsize; + props->size -= props->offset; + + printk(BIOS_SPEW, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c deleted file mode 100644 index 9f45b3c..0000000 --- a/src/lib/cbfs_core.c +++ /dev/null @@ -1,324 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 secunet Security Networks AG - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* The CBFS core requires a couple of #defines or functions to adapt it to the - * target environment: - * - * CBFS_CORE_WITH_LZMA (must be #define) - * if defined, ulzma() must exist for decompression of data streams - * - * ERROR(x...) - * print an error message x (in printf format) - * - * LOG(x...) - * print a message x (in printf format) - * - * DEBUG(x...) - * print a debug message x (in printf format) - * - */ - -#include <cbfs.h> -#include <string.h> -#include <symbols.h> - -#if IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES) -void cbfs_set_header_offset(size_t offset) -{ - _cbfs_header_offset[0] = offset; - LOG("header set to: %#zx\n", offset); -} - -static size_t get_header_offset(void) -{ - return _cbfs_header_offset[0]; -} -#else -static size_t get_header_offset(void) -{ - return 0; -} -#endif - -#include "cbfs_core.h" - -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) -{ - size_t offset; - const struct cbfs_header *header; - struct cbfs_media default_media; - - if (media == CBFS_DEFAULT_MEDIA) { - media = &default_media; - if (init_default_cbfs_media(media) != 0) { - ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; - } - } - media->open(media); - - /* TODO: allow negative offsets from the end of the CBFS image at media - * layer (like libpayload) so we can combine these two cases. */ - if (IS_ENABLED(CONFIG_ARCH_X86)) { - offset = *(int32_t *)(uintptr_t)0xfffffffc; - header = media->map(media, offset, sizeof(*header)); - } else { - - offset = get_header_offset(); - - if (!offset) { - int32_t rel_offset; - size_t cbfs_top = CONFIG_CBFS_SIZE; - DEBUG("CBFS top at offset: 0x%zx\n", cbfs_top); - if (!media->read(media, &rel_offset, cbfs_top - - sizeof(int32_t), - sizeof(int32_t))) { - ERROR("Could not read master header offset!\n"); - media->close(media); - return CBFS_HEADER_INVALID_ADDRESS; - } - offset = cbfs_top + rel_offset; - } - header = media->map(media, offset, sizeof(*header)); - } - DEBUG("CBFS header offset: 0x%zx/0x%x\n", offset, CONFIG_ROM_SIZE); - media->close(media); - - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("Failed to load CBFS header from 0x%zx\n", offset); - return CBFS_HEADER_INVALID_ADDRESS; - } - - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { - ERROR("Could not find valid CBFS master header at %#zx: " - "magic %#.8x vs %#.8x.\n", offset, CBFS_HEADER_MAGIC, - ntohl(header->magic)); - if (header->magic == 0xffffffff) { - ERROR("Maybe ROM is not mapped properly?\n"); - } - return CBFS_HEADER_INVALID_ADDRESS; - } - return header; -} - - -int init_backing_media(struct cbfs_media **media, struct cbfs_media *backing) -{ - if (*media == CBFS_DEFAULT_MEDIA) { - *media = backing; - if (init_default_cbfs_media(*media) != 0) { - ERROR("Failed to initialize default media.\n"); - return -1; - } - } - return 0; -} - -/* public API starts here*/ -ssize_t cbfs_locate_file(struct cbfs_media *media, struct cbfs_file *file, - const char *name) -{ - const char *file_name; - uint32_t offset, align, romsize, name_len; - const struct cbfs_header *header; - struct cbfs_media default_media; - - if (init_backing_media(&media, &default_media)) - return -1; - - if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return -1; - - // Logical offset (for source media) of first file. - offset = ntohl(header->offset); - align = ntohl(header->align); - romsize = ntohl(header->romsize); - - // TODO Add a "size" in CBFS header for a platform independent way to - // determine the end of CBFS data. -#if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 - // resolve actual length of ROM used for CBFS components - // the bootblock size was not taken into account - romsize -= ntohl(header->bootblocksize); - - // fine tune the length to handle alignment positioning. - // using (bootblock size) % align, to derive the - // number of bytes the bootblock is off from the alignment size. - if ((ntohl(header->bootblocksize) % align)) - romsize -= (align - (ntohl(header->bootblocksize) % align)); - else - romsize -= 1; -#endif - - DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); - - media->open(media); - while (offset < romsize && - media->read(media, file, offset, sizeof(*file)) == sizeof(*file)) { - if (memcmp(CBFS_FILE_MAGIC, file->magic, - sizeof(file->magic)) != 0) { - uint32_t new_align = align; - if (offset % align) - new_align += align - (offset % align); - LOG("WARNING: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); - offset += new_align; - continue; - } - - file->len = ntohl(file->len); - file->type= ntohl(file->type); - file->offset = ntohl(file->offset); - - name_len = file->offset - sizeof(*file); - DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); - - // load file name (arbitrary length). - file_name = (const char *)media->map( - media, offset + sizeof(*file), name_len); - if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); - } else if (strcmp(file_name, name) == 0) { - DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file->offset, file->len); - media->unmap(media, file_name); - return offset + file->offset; - } else { - DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); - media->unmap(media, file_name); - } - - // Move to next file. - offset += file->len + file->offset; - if (offset % align) - offset += align - (offset % align); - } - media->close(media); - LOG("WARNING: '%s' not found.\n", name); - return -1; -} - -size_t cbfs_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) -{ - struct cbfs_media default_media; - size_t nread; - - if (init_backing_media(&media, &default_media)) - return 0; - - media->open(media); - nread = media->read(media, dest, offset, count); - media->close(media); - - return nread; -} - -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) -{ - struct cbfs_media default_media; - struct cbfs_file file, *file_ptr; - ssize_t offset; - - if (init_backing_media(&media, &default_media)) - return NULL; - - offset = cbfs_locate_file(media, &file, name); - if (offset < 0) - return NULL; - - /* Map both the metadata and the file contents. */ - media->open(media); - offset -= file.offset; - file_ptr = media->map(media, offset, file.offset + file.len); - media->close(media); - - if (file_ptr == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Mapping %s failed.\n", name); - return NULL; - } - - return file_ptr; -} - -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz) -{ - struct cbfs_file *file = cbfs_get_file(media, name); - - if (sz) - *sz = 0; - - if (file == NULL) { - ERROR("Could not find file '%s'.\n", name); - return NULL; - } - - if (ntohl(file->type) != type) { - ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); - return NULL; - } - - if (sz) - *sz = ntohl(file->len); - - return (void *)CBFS_SUBHEADER(file); -} - -int cbfs_decompress(int algo, void *src, void *dst, int len) -{ - switch (algo) { - case CBFS_COMPRESS_NONE: - /* Reads need to be aligned at 4 bytes to avoid - poor flash performance. */ - while (len && ((uintptr_t)src & 3)) { - *(u8*)dst++ = *(u8*)src++; - len--; - } - memmove(dst, src, len); - return len; -#ifdef CBFS_CORE_WITH_LZMA - case CBFS_COMPRESS_LZMA: - return ulzma(src, dst); -#endif - default: - ERROR("tried to decompress %d bytes with algorithm #%x," - "but that algorithm id is unsupported.\n", len, - algo); - return 0; - } -} diff --git a/src/lib/cbfs_core.h b/src/lib/cbfs_core.h deleted file mode 100644 index f9aeaa8..0000000 --- a/src/lib/cbfs_core.h +++ /dev/null @@ -1,47 +0,0 @@ -#ifndef __LIB_CBFS_CORE -#define __LIB_CBFS_CORE - -#include <cbfs.h> -#include <string.h> - -#ifdef LIBPAYLOAD -# include <libpayload-config.h> -# ifdef CONFIG_LZMA -# include <lzma.h> -# define CBFS_CORE_WITH_LZMA -# endif -# define CBFS_MINI_BUILD -#elif defined(__SMM__) -# define CBFS_MINI_BUILD -#elif defined(__BOOTBLOCK__) - /* No LZMA in boot block. */ -#elif defined(__VERSTAGE__) - /* No LZMA in verstage. */ -#elif defined(__PRE_RAM__) && !CONFIG_COMPRESS_RAMSTAGE - /* No LZMA in romstage if ramstage is not compressed. */ -#else -# define CBFS_CORE_WITH_LZMA -# include <lib.h> -#endif - -#include <cbfs.h> -#include <string.h> -#include <cbmem.h> - -#ifdef LIBPAYLOAD -# include <stdio.h> -# define DEBUG(x...) -# define LOG(x...) printf(x) -# define ERROR(x...) printf(x) -#else -# include <console/console.h> -# define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) -# define LOG(x...) printk(BIOS_INFO, "CBFS: " x) -# if CONFIG_DEBUG_CBFS -# define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -# else -# define DEBUG(x...) -# endif -#endif - -#endif /* __LIB_CBFS_CORE */ diff --git a/src/lib/cbfs_spi.c b/src/lib/cbfs_spi.c index 6637cdc..b11d92b 100644 --- a/src/lib/cbfs_spi.c +++ b/src/lib/cbfs_spi.c @@ -24,8 +24,6 @@ */ #include <boot_device.h> -#include <cbfs.h> -#include <region.h> #include <spi_flash.h> #include <symbols.h> @@ -69,73 +67,3 @@ const struct region_device *boot_device_ro(void) return &mdev.rdev; } - -static int cbfs_media_open(struct cbfs_media *media) -{ - return 0; -} - -static int cbfs_media_close(struct cbfs_media *media) -{ - return 0; -} - -static size_t cbfs_media_read(struct cbfs_media *media, - void *dest, size_t offset, - size_t count) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static void *cbfs_media_map(struct cbfs_media *media, - size_t offset, size_t count) -{ - const struct region_device *boot_dev; - void *ptr; - - boot_dev = media->context; - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void *cbfs_media_unmap(struct cbfs_media *media, - const void *address) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - boot_device_init(); - - media->context = (void *)boot_device_ro(); - - if (media->context == NULL) - return -1; - - media->open = cbfs_media_open; - media->close = cbfs_media_close; - media->read = cbfs_media_read; - media->map = cbfs_media_map; - media->unmap = cbfs_media_unmap; - - return 0; -} diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 4af50ed..1feb68e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -397,8 +397,8 @@ unsigned long write_coreboot_table( #if CONFIG_USE_OPTION_TABLE { - struct cmos_option_table *option_table = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "cmos_layout.bin", + struct cmos_option_table *option_table = + cbfs_boot_map_with_leak("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 3928613..fffb558 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -24,10 +24,9 @@ static int cbfs_locate_payload(struct prog *payload) { void *buffer; size_t size; - const int type = CBFS_TYPE_PAYLOAD; + const uint32_t type = CBFS_TYPE_PAYLOAD; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + buffer = cbfs_boot_map_with_leak(payload->name, type, &size); if (buffer == NULL) return -1; diff --git a/src/lib/loaders/cbfs_ramstage_loader.c b/src/lib/loaders/cbfs_ramstage_loader.c index c460653..bbbf695 100644 --- a/src/lib/loaders/cbfs_ramstage_loader.c +++ b/src/lib/loaders/cbfs_ramstage_loader.c @@ -44,8 +44,7 @@ static int cbfs_load_ramstage(struct prog *ramstage) static int cbfs_load_ramstage(struct prog *ramstage) { - return cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, ramstage); - + return cbfs_boot_load_stage(ramstage); } #endif /* CONFIG_RELOCATABLE_RAMSTAGE */ diff --git a/src/lib/loaders/cbfs_romstage_loader.c b/src/lib/loaders/cbfs_romstage_loader.c index e5b4215..7dde2ec 100644 --- a/src/lib/loaders/cbfs_romstage_loader.c +++ b/src/lib/loaders/cbfs_romstage_loader.c @@ -22,7 +22,7 @@ static int cbfs_load_romstage(struct prog *romstage) { - return cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, romstage); + return cbfs_boot_load_stage(romstage); } const struct prog_loader_ops cbfs_romstage_loader = { diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 799d8f0..d886800 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <lib.h> #include <console/console.h> #include <program_loading.h> #include <rmodule.h> @@ -252,34 +253,57 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, return region_alignment - sizeof(struct rmodule_header); } -int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) +int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfsf *fh) { struct rmodule rmod_stage; size_t region_size; char *stage_region; int rmodule_offset; int load_offset; + struct cbfs_stage stage; + void *rmod_loc; - if (stage == NULL || rsl->prog == NULL || rsl->prog->name == NULL) + if (fh == NULL || rsl->prog == NULL || rsl->prog->name == NULL) + return -1; + + if (cbfs_file_readat(fh, &stage, 0, sizeof(stage)) != sizeof(stage)) return -1; rmodule_offset = rmodule_calc_region(DYN_CBMEM_ALIGN_SIZE, - stage->memlen, &region_size, &load_offset); + stage.memlen, &region_size, &load_offset); stage_region = cbmem_add(rsl->cbmem_id, region_size); if (stage_region == NULL) return -1; + rmod_loc = &stage_region[rmodule_offset]; + printk(BIOS_INFO, "Decompressing stage %s @ 0x%p (%d bytes)\n", - rsl->prog->name, &stage_region[rmodule_offset], stage->memlen); + rsl->prog->name, rmod_loc, stage.memlen); + + if (stage.compression == CBFS_COMPRESS_NONE) { + if (cbfs_file_readat(fh, rmod_loc, sizeof(stage), stage.len) != + stage.len) + return -1; + } else if (stage.compression == CBFS_COMPRESS_LZMA) { + size_t fsize; + void *map = cbfs_file_mmap(fh, sizeof(stage), stage.len); - if (!cbfs_decompress(stage->compression, &stage[1], - &stage_region[rmodule_offset], stage->len)) + if (map == NULL) + return -1; + + fsize = ulzma(map, rmod_loc); + + cbfs_file_munmap(fh, map); + + if (!fsize) + return -1; + } else return -1; - if (rmodule_parse(&stage_region[rmodule_offset], &rmod_stage)) + if (rmodule_parse(rmod_loc, &rmod_stage)) return -1; if (rmodule_load(&stage_region[load_offset], &rmod_stage)) @@ -294,13 +318,11 @@ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl) { - struct cbfs_stage *stage; - - stage = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - rsl->prog->name, CBFS_TYPE_STAGE, NULL); + struct cbfsf fh; + uint32_t type = CBFS_TYPE_STAGE; - if (stage == NULL) + if (cbfs_boot_locate(&fh, rsl->prog->name, &type)) return -1; - return rmodule_stage_load(rsl, stage); + return rmodule_stage_load(rsl, &fh); } diff --git a/src/mainboard/emulation/qemu-armv7/media.c b/src/mainboard/emulation/qemu-armv7/media.c index e0f2251..cb0b275 100644 --- a/src/mainboard/emulation/qemu-armv7/media.c +++ b/src/mainboard/emulation/qemu-armv7/media.c @@ -13,83 +13,12 @@ * GNU General Public License for more details. */ #include <boot_device.h> -#include <cbfs.h> -#include <string.h> -#include <symbols.h> -#include <console/console.h> /* Maps directly to qemu memory mapped space of 0x10000 up to rom size. */ -static const struct mem_region_device gboot_dev = +static const struct mem_region_device boot_dev = MEM_REGION_DEV_INIT((void *)0x10000, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) { - return &gboot_dev.rdev; -} - -static int emu_rom_open(struct cbfs_media *media) -{ - return 0; -} - -static void *emu_rom_map(struct cbfs_media *media, size_t offset, size_t count) -{ - const struct region_device *boot_dev; - void *ptr; - - boot_dev = media->context; - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void *emu_rom_unmap(struct cbfs_media *media, const void *address) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -static size_t emu_rom_read(struct cbfs_media *media, void *dest, size_t offset, - size_t count) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static int emu_rom_close(struct cbfs_media *media) -{ - return 0; -} - -static int init_emu_rom_cbfs_media(struct cbfs_media *media) -{ - boot_device_init(); - - media->context = (void *)boot_device_ro(); - media->open = emu_rom_open; - media->close = emu_rom_close; - media->map = emu_rom_map; - media->unmap = emu_rom_unmap; - media->read = emu_rom_read; - return 0; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - return init_emu_rom_cbfs_media(media); + return &boot_dev.rdev; } diff --git a/src/mainboard/google/bolt/romstage.c b/src/mainboard/google/bolt/romstage.c index bead56f..e80aedf 100644 --- a/src/mainboard/google/bolt/romstage.c +++ b/src/mainboard/google/bolt/romstage.c @@ -78,8 +78,8 @@ static void copy_spd(struct pei_data *peid) int spd_index = 0; /* No GPIO selection, force index 0 for now */ printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 6d2af16..2f3cf1d 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -211,9 +211,8 @@ static void mainboard_init(device_t dev) } } } else { - vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "vpd.bin", CBFS_TYPE_RAW, - &search_length); + vpd_file = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, + &search_length); if (vpd_file) { search_address = (unsigned long)vpd_file; } else { diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 4e79159..d28a914 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -79,8 +79,8 @@ static void copy_spd(struct pei_data *peid) size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 5844aa6..d3e7c6a 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -94,8 +94,8 @@ static void copy_spd(struct pei_data *peid) int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 650d018..6dd5bec 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -127,8 +127,7 @@ static void program_mac_address(u16 io_base) search_length = region_device_sz(&rdev); } } else { - search_address = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "vpd.bin", + search_address = cbfs_boot_map_with_leak("vpd.bin", CBFS_TYPE_RAW, &search_length); } diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 443eafd..b2456fc 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -21,12 +21,14 @@ #include <arch/exception.h> #include <arch/stages.h> #include <armv7.h> +#include <boot_device.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> #include <device/i2c.h> #include <drivers/maxim/max77802/max77802.h> #include <program_loading.h> +#include <region.h> #include <soc/clk.h> #include <soc/cpu.h> #include <soc/dmc.h> @@ -176,29 +178,28 @@ static unsigned long primitive_mem_test(void) /* here is a simple SPI debug test, known to fid trouble */ static void simple_spi_test(void) { - struct cbfs_media default_media, *media; + const struct region_device *boot_dev; int i, amt = 4 * MiB, errors = 0; //u32 *data = (void *)0x40000000; u32 data[1024]; u32 in; + boot_device_init(); + boot_dev = boot_device_ro(); amt = sizeof(data); - media = &default_media; - if (init_default_cbfs_media(media) != 0) { + if (boot_dev == NULL) { printk(BIOS_SPEW, "Failed to initialize default media.\n"); return; } - - media->open(media); - if (media->read(media, data, (size_t) 0, amt) < amt){ + if (rdev_readat(boot_dev, data, 0, amt) < amt) { printk(BIOS_SPEW, "simple_spi_test fails\n"); return; } for(i = 0; i < amt; i += 4){ - if (media->read(media, &in, (size_t) i, 4) < 1){ + if (rdev_readat(boot_dev, &in, i, 4) < 4) { printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); return; } @@ -207,7 +208,7 @@ static void simple_spi_test(void) printk(BIOS_SPEW, "BAD at %d(%p):\nRAM %08lx\nSPI %08lx\n", i, &data[i/4], (unsigned long)data[i/4], (unsigned long)in); /* reread it to see which is wrong. */ - if (media->read(media, &in, (size_t) i, 4) < 1){ + if (rdev_readat(boot_dev, &in, i, 4) < 4) { printk(BIOS_SPEW, "simple_spi_test fails at %d\n", i); return; } diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 27962e1..6f00216 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -82,8 +82,8 @@ static void copy_spd(struct pei_data *peid) size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 0f431d9..b25e1dc 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -71,9 +71,10 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) void mainboard_romstage_entry(struct romstage_params *rp) { - struct cbfs_file *spd_file; void *spd_content; int dual_channel = 0; + void *spd_file; + size_t spd_fsize; struct mrc_params mp = { .mainboard = { @@ -83,12 +84,12 @@ void mainboard_romstage_entry(struct romstage_params *rp) }, }; - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_fsize); if (!spd_file) die("SPD data not found."); - spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), - ntohl(spd_file->len) / SPD_SIZE, + spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); mp.mainboard.dram_data[0] = spd_content; if (dual_channel) diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 1308ab2..a2f2973 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -90,8 +90,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) }; int spd_gpio[4]; int spd_index; - int spd_file_len; - struct cbfs_file *spd_file; + size_t spd_file_len; + char *spd_file; spd_gpio[0] = get_gpio(spd_bits[0]); spd_gpio[1] = get_gpio(spd_bits[1]); @@ -106,10 +106,9 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); if (!spd_file) die("SPD data not found."); - spd_file_len = ntohl(spd_file->len); if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); @@ -121,10 +120,8 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) /* Assume same memory in both channels */ spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], - ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], - ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); /* Make sure a valid SPD was found */ if (pei_data->spd_data[0][0][0] == 0) diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index c242ecd..c89687f 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -80,8 +80,8 @@ static void copy_spd(struct pei_data *peid) size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_file) die("SPD data not found."); diff --git a/src/mainboard/google/urara/boardid.c b/src/mainboard/google/urara/boardid.c index a95bc14..0b46408 100644 --- a/src/mainboard/google/urara/boardid.c +++ b/src/mainboard/google/urara/boardid.c @@ -23,7 +23,7 @@ #include <string.h> #include <boardid.h> -#include <cbfs_core.h> +#include <cbfs.h> #include <console/console.h> #include "mainboard/google/urara/urara_boardid.h" @@ -48,28 +48,17 @@ static int cached_board_id = -1; static uint8_t retrieve_board_id(void) { - struct cbfs_file *board_id_file; const char *board_id_file_name = CBFS_BOARD_ID_FILE_NAME; char *file_contents; int i; - unsigned length; + size_t length; - board_id_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, board_id_file_name); - if (!board_id_file) { - printk(BIOS_WARNING, - "board_id: failed to locate file '%s'\n", - board_id_file_name); - return 0; - } - - length = be32_to_cpu(board_id_file->len); - - file_contents = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - board_id_file_name, - CBFS_TYPE_RAW, NULL); + file_contents = cbfs_boot_map_with_leak(board_id_file_name, + CBFS_TYPE_RAW, &length); if (!file_contents) { - printk(BIOS_WARNING, "board_id: failed to read file '%s'\n", + printk(BIOS_WARNING, + "board_id: failed to locate file '%s'\n", board_id_file_name); return 0; } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 29a238a..169a21e 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -236,8 +236,8 @@ void main(unsigned long bist) break; } - spd_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", - CBFS_TYPE_SPD, &spd_file_len); + spd_data = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); if (!spd_data) die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.c b/src/mainboard/siemens/mc_tcu3/modhwinfo.c index 95bb76c..b077868 100644 --- a/src/mainboard/siemens/mc_tcu3/modhwinfo.c +++ b/src/mainboard/siemens/mc_tcu3/modhwinfo.c @@ -31,8 +31,7 @@ u8* get_first_linked_block(char *filename, u8 **file_offset) { u8* block_ptr = NULL; - block_ptr = (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, filename, - 0x50, NULL)); + block_ptr = cbfs_boot_map_with_leak(filename, 0x50, NULL); if (!block_ptr) return NULL; if (!strncmp((char*)block_ptr, "H1W2M3I4", LEN_MAGIC_NUM)) { @@ -57,8 +56,7 @@ struct hwinfo* get_hwinfo(char *filename) { struct hwinfo* main_hwinfo; - main_hwinfo = (struct hwinfo*)(cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - filename, 0x50, NULL)); + main_hwinfo = cbfs_boot_map_with_leak(filename, 0x50, NULL); if ((main_hwinfo) && (!strncmp(main_hwinfo->magicNumber, "H1W2M3I4", LEN_MAGIC_NUM)) && (main_hwinfo->length == LEN_MAIN_HWINFO)) diff --git a/src/northbridge/amd/agesa/common/common.c b/src/northbridge/amd/agesa/common/common.c index 29b4c2e..e4f8e9d 100644 --- a/src/northbridge/amd/agesa/common/common.c +++ b/src/northbridge/amd/agesa/common/common.c @@ -38,7 +38,8 @@ AGESA_STATUS common_ReadCbfsSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) char *spd_file; - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", CBFS_TYPE_SPD_BIN, &spd_file_length); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD_BIN, + &spd_file_length); if (!spd_file) die("file [spd.bin] not found in CBFS"); diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 26b1c0d..3f83e9e 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -117,8 +117,8 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", + pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( + "pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM, NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 8bcd8ac..fbf7a84 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -593,20 +593,13 @@ AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) const void *agesawrapper_locate_module (const CHAR8 name[8]) { - struct cbfs_media media; - struct cbfs_file* file; const void* agesa; const AMD_IMAGE_HEADER* image; const AMD_MODULE_HEADER* module; size_t file_size; - if (init_default_cbfs_media(&media)) - return NULL; - file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME); - if (!file) - return NULL; - agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME, - ntohl(file->type), &file_size); + agesa = cbfs_boot_map_with_leak((const char *)CONFIG_CBFS_AGESA_NAME, + CBFS_TYPE_RAW, &file_size); if (!agesa) return NULL; image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name); diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 2caf183..56a24ac 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -107,8 +107,8 @@ AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt) { GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; - pVbiosImageInfo->ImagePtr = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", + pVbiosImageInfo->ImagePtr = cbfs_boot_map_with_leak( + "pci"CONFIG_VGA_BIOS_ID".rom", CBFS_TYPE_OPTIONROM, NULL); printk(BIOS_DEBUG, "agesa_GfxGetVbiosImage: IMGptr=%p\n", pVbiosImageInfo->ImagePtr); return (pVbiosImageInfo->ImagePtr ? AGESA_SUCCESS : AGESA_WARNING); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index e4acda8..1150be2 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -74,8 +74,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) *mrc_region_ptr = rdev_mmap_full(&rdev); } } else { - *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", CBFS_TYPE_MRC_CACHE, &region_size); } diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 6bbb215..4740f73 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -162,8 +162,8 @@ void sdram_initialize(struct pei_data *pei_data) pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = (unsigned long)cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL); + entry = (unsigned long)cbfs_boot_map_with_leak("mrc.bin", + CBFS_TYPE_MRC, NULL); if (entry) { int rv; asm volatile ( diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index f846e37..cd07dcb 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -31,8 +31,7 @@ static void vga_init(device_t dev) { printk(BIOS_INFO, "Starting Graphics Initialization\n"); size_t mbi_len; - void *mbi = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mbi.bin", - CBFS_TYPE_MBI, &mbi_len); + void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len); if (mbi && mbi_len) { /* The GDT or coreboot table is going to live here. But diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index 1453390..eb6297a 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -74,8 +74,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) *mrc_region_ptr = rdev_mmap_full(&rdev); } } else { - *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", + *mrc_region_ptr = cbfs_boot_map_with_leak("mrc.cache", CBFS_TYPE_MRC_CACHE, &region_size); } diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index d8c7eef..fde0cfa 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -246,8 +246,7 @@ void sdram_initialize(struct pei_data *pei_data) pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ - entry = cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL); + entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); if (entry) { int rv; rv = entry (pei_data); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 61c122c..8611d70 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -148,8 +148,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) } /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, - NULL) == NULL) { + if (cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL) == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; } diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 52ea491..7b46a90 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -86,8 +86,7 @@ void raminit(struct pei_data *pei_data) } /* Determine if mrc.bin is in the cbfs. */ - entry = (pei_wrapper_entry_t)cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", CBFS_TYPE_MRC, NULL); + entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); if (entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 6fbb3c4..ca98eca 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -802,18 +802,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return ret; } -static int tegra_spi_cbfs_open(struct cbfs_media *media) -{ - DEBUG_SPI("tegra_spi_cbfs_open\n"); - return 0; -} - -static int tegra_spi_cbfs_close(struct cbfs_media *media) -{ - DEBUG_SPI("tegra_spi_cbfs_close\n"); - return 0; -} - #define JEDEC_READ 0x03 #define JEDEC_READ_OUTSIZE 0x04 #define JEDEC_FAST_READ_DUAL 0x3b @@ -877,69 +865,6 @@ tegra_spi_cbfs_read_exit: return ret; } -static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - printk(BIOS_ERR, "%s: reading %zx bytes from %zx\n", - __func__, count, offset); - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset, - size_t count) -{ - const struct region_device *boot_dev; - void *map; - - DEBUG_SPI("tegra_spi_cbfs_map\n"); - - boot_dev = media->context; - - map = rdev_mmap(boot_dev, offset, count); - - if (map == NULL) - map = (void *)-1; - - return map; -} - -static void *tegra_spi_cbfs_unmap(struct cbfs_media *media, - const void *address) -{ - const struct region_device *boot_dev; - - DEBUG_SPI("tegra_spi_cbfs_unmap\n"); - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - DEBUG_SPI("Initializing CBFS media on SPI\n"); - - boot_device_init(); - - media->context = (void *)boot_device_ro(); - media->open = tegra_spi_cbfs_open; - media->close = tegra_spi_cbfs_close; - media->read = tegra_spi_cbfs_read; - media->map = tegra_spi_cbfs_map; - media->unmap = tegra_spi_cbfs_unmap; - - return 0; -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct tegra_spi_channel *channel = to_tegra_spi(bus); diff --git a/src/soc/nvidia/tegra132/ccplex.c b/src/soc/nvidia/tegra132/ccplex.c index f9356a9..7f16d54 100644 --- a/src/soc/nvidia/tegra132/ccplex.c +++ b/src/soc/nvidia/tegra132/ccplex.c @@ -75,10 +75,9 @@ static int ccplex_start(void) int ccplex_load_mts(void) { - struct cbfs_file file; - ssize_t offset; - size_t nread; + ssize_t nread; struct stopwatch sw; + struct cbfsf fh; /* * MTS location is hard coded to this magic address. The hardware will @@ -86,21 +85,19 @@ int ccplex_load_mts(void) * place in the carveout region. */ void * const mts = (void *)(uintptr_t)MTS_LOAD_ADDRESS; - struct cbfs_media *media = CBFS_DEFAULT_MEDIA; stopwatch_init(&sw); - offset = cbfs_locate_file(media, &file, MTS_FILE_NAME); - if (offset < 0) { + if (cbfs_boot_locate(&fh, MTS_FILE_NAME, NULL)) { printk(BIOS_DEBUG, "MTS file not found: %s\n", MTS_FILE_NAME); return -1; } /* Read MTS file into the carveout region. */ - nread = cbfs_read(media, mts, offset, file.len); + nread = cbfs_file_readat(&fh, mts, 0, cbfs_file_size(&fh)); - if (nread != file.len) { + if (nread != cbfs_file_size(&fh)) { printk(BIOS_DEBUG, "MTS bytes read (%zu) != file length(%u)!\n", - nread, file.len); + nread, cbfs_file_size(&fh)); return -1; } diff --git a/src/soc/nvidia/tegra132/spi.c b/src/soc/nvidia/tegra132/spi.c index 746e96e..d481b87 100644 --- a/src/soc/nvidia/tegra132/spi.c +++ b/src/soc/nvidia/tegra132/spi.c @@ -817,18 +817,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return ret; } -static int tegra_spi_cbfs_open(struct cbfs_media *media) -{ - DEBUG_SPI("tegra_spi_cbfs_open\n"); - return 0; -} - -static int tegra_spi_cbfs_close(struct cbfs_media *media) -{ - DEBUG_SPI("tegra_spi_cbfs_close\n"); - return 0; -} - #define JEDEC_READ 0x03 #define JEDEC_READ_OUTSIZE 0x04 #define JEDEC_FAST_READ_DUAL 0x3b @@ -892,69 +880,6 @@ tegra_spi_cbfs_read_exit: return ret; } -static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) -{ - const struct region_device *boot_dev; - - boot_dev = media->context; - - DEBUG_SPI("%s: reading %zx bytes from %zx\n", __func__, count, offset); - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset, - size_t count) -{ - const struct region_device *boot_dev; - void *map; - - DEBUG_SPI("tegra_spi_cbfs_map\n"); - - boot_dev = media->context; - - map = rdev_mmap(boot_dev, offset, count); - - if (map == NULL) - map = (void *)-1; - - return map; -} - -static void *tegra_spi_cbfs_unmap(struct cbfs_media *media, - const void *address) -{ - const struct region_device *boot_dev; - - DEBUG_SPI("tegra_spi_cbfs_unmap\n"); - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - DEBUG_SPI("Initializing CBFS media on SPI\n"); - - boot_device_init(); - - media->context = (void *)boot_device_ro(); - media->open = tegra_spi_cbfs_open; - media->close = tegra_spi_cbfs_close; - media->read = tegra_spi_cbfs_read; - media->map = tegra_spi_cbfs_map; - media->unmap = tegra_spi_cbfs_unmap; - - return 0; -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct tegra_spi_channel *channel = to_tegra_spi(bus); diff --git a/src/soc/qualcomm/ipq806x/blobs_init.c b/src/soc/qualcomm/ipq806x/blobs_init.c index e3478a9..1465995 100644 --- a/src/soc/qualcomm/ipq806x/blobs_init.c +++ b/src/soc/qualcomm/ipq806x/blobs_init.c @@ -32,20 +32,18 @@ static void *load_ipq_blob(const char *file_name) { - struct cbfs_file *blob_file; struct mbn_header *blob_mbn; void *blob_dest; + size_t blob_size; - blob_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, file_name); - if (!blob_file) + blob_mbn = cbfs_boot_map_with_leak(file_name, CBFS_TYPE_RAW, + &blob_size); + if (!blob_mbn) return NULL; - blob_mbn = (struct mbn_header *)((uintptr_t)blob_file + - ntohl(blob_file->offset)); - /* some sanity checks on the headers */ if ((blob_mbn->mbn_version != 3) || - (blob_mbn->mbn_total_size > ntohl(blob_file->len))) + (blob_mbn->mbn_total_size > blob_size)) return NULL; blob_dest = (void *) blob_mbn->mbn_destination; diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index d6aa6e6..165171f 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -112,70 +112,6 @@ static int sdmmc_cbfs_open(void) return 0; } -static int exynos_cbfs_open(struct cbfs_media *media) { - return 0; -} - -static int exynos_cbfs_close(struct cbfs_media *media) { - return 0; -} - -static size_t exynos_cbfs_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) { - const struct region_device *boot_dev; - - boot_dev = media->context; - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static void *exynos_cbfs_map(struct cbfs_media *media, size_t offset, - size_t count) { - const struct region_device *boot_dev; - void *ptr; - - boot_dev = media->context; - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void *exynos_cbfs_unmap(struct cbfs_media *media, - const void *address) { - const struct region_device *boot_dev; - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - boot_device_init(); - - media->context = (void *)boot_device_ro(); - - if (media->context == NULL) - return -1; - - media->open = exynos_cbfs_open; - media->close = exynos_cbfs_close; - media->read = exynos_cbfs_read; - media->map = exynos_cbfs_map; - media->unmap = exynos_cbfs_unmap; - - return 0; -} - static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0); const struct region_device *boot_device_ro(void) diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index 9e1d323..3cea42a 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -119,70 +119,6 @@ static int sdmmc_cbfs_open(void) return 0; } -static int exynos_cbfs_open(struct cbfs_media *media) { - return 0; -} - -static int exynos_cbfs_close(struct cbfs_media *media) { - return 0; -} - -static size_t exynos_cbfs_read(struct cbfs_media *media, void *dest, - size_t offset, size_t count) { - const struct region_device *boot_dev; - - boot_dev = media->context; - - if (rdev_readat(boot_dev, dest, offset, count) < 0) - return 0; - - return count; -} - -static void *exynos_cbfs_map(struct cbfs_media *media, size_t offset, - size_t count) { - const struct region_device *boot_dev; - void *ptr; - - boot_dev = media->context; - - ptr = rdev_mmap(boot_dev, offset, count); - - if (ptr == NULL) - return (void *)-1; - - return ptr; -} - -static void *exynos_cbfs_unmap(struct cbfs_media *media, - const void *address) { - const struct region_device *boot_dev; - - boot_dev = media->context; - - rdev_munmap(boot_dev, (void *)address); - - return NULL; -} - -int init_default_cbfs_media(struct cbfs_media *media) -{ - boot_device_init(); - - media->context = (void *)boot_device_ro(); - - if (media->context == NULL) - return -1; - - media->open = exynos_cbfs_open; - media->close = exynos_cbfs_close; - media->read = exynos_cbfs_read; - media->map = exynos_cbfs_map; - media->unmap = exynos_cbfs_unmap; - - return 0; -} - static struct mem_region_device alternate_rdev = MEM_REGION_DEV_INIT(NULL, 0); const struct region_device *boot_device_ro(void) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c index 226578b..6e100a2 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_loader.c @@ -98,7 +98,7 @@ static int vboot_loader_active(struct prog *prog) printk(BIOS_DEBUG, "VBOOT: Loading verstage.\n"); /* load verstage from RO */ - if (cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, &verstage)) + if (cbfs_boot_load_stage(&verstage)) die("failed to load verstage"); /* verify and select a slot */ @@ -186,8 +186,7 @@ static int vboot_prepare(struct prog *prog) /* In the multi cbfs case the cbfs offset pointer has already been * updated after firmware verification. */ if (IS_ENABLED(CONFIG_MULTIPLE_CBFS_INSTANCES)) { - if (!ENV_RAMSTAGE && - cbfs_load_prog_stage(CBFS_DEFAULT_MEDIA, prog) != 0) + if (!ENV_RAMSTAGE && cbfs_boot_load_stage(prog) != 0) return -1; /* Need to load payload. */ @@ -195,8 +194,7 @@ static int vboot_prepare(struct prog *prog) void *payload; size_t size; - payload = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - prog->name, + payload = cbfs_boot_map_with_leak(prog->name, CBFS_TYPE_PAYLOAD, &size); @@ -228,7 +226,7 @@ static int vboot_prepare(struct prog *prog) prog_set_area(prog, payload_ptr, region_device_sz(&payload)); } else { - struct region_device stage; + struct cbfsf stage; int stage_index = 0; if (prog->type == PROG_ROMSTAGE) @@ -238,30 +236,19 @@ static int vboot_prepare(struct prog *prog) else die("Invalid program type for vboot."); - if (vboot_fw_region(stage_index, &fw_main, &stage)) + if (vboot_fw_region(stage_index, &fw_main, &stage.rdev)) die("Vboot stage load failed."); if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { - void *stage_ptr; struct rmod_stage_load rmod_ram = { .cbmem_id = CBMEM_ID_RAMSTAGE, .prog = prog, }; - stage_ptr = rdev_mmap_full(&stage); - - if (stage_ptr == NULL) - die("Vboot couldn't load stage."); - - if (rmodule_stage_load(&rmod_ram, stage_ptr)) + if (rmodule_stage_load(&rmod_ram, &stage)) die("Vboot couldn't load stage"); - } else { - size_t offset = region_device_offset(&stage); - - if (cbfs_load_prog_stage_by_offset(CBFS_DEFAULT_MEDIA, - prog, offset)) + } else if (cbfs_file_stage_load(&stage, prog)) die("Vboot couldn't load stage"); - } } return 0;

1 0

Patch merged into coreboot/master: df699d5 util/cbmem: Update cbmem utility to parse the new IMD structures
by gerrit＠coreboot.org 18 May '15

18 May '15

the following patch was just integrated into master: commit df699d545f38bc9529401d862f4a9a80228da6b7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat May 16 14:55:54 2015 -0500 util/cbmem: Update cbmem utility to parse the new IMD structures This resolves the cbmem table of contents access failure introduced in commit 0dff57dd. Change-Id: Ie143ae11d97f26bd17fe10e1382fae9e5ad1a60e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10236 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/10236 for details. -gerrit

1 0

Patch set updated for coreboot: f1c0e62 util/cbmem: Update cbmem utility to parse the new IMD structures
by Timothy Pearson 18 May '15

18 May '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10236 -gerrit commit f1c0e62511822dd716b3d479fd6135c052709916 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat May 16 14:55:54 2015 -0500 util/cbmem: Update cbmem utility to parse the new IMD structures This resolves the cbmem table of contents access failure introduced in commit 0dff57dd. Change-Id: Ie143ae11d97f26bd17fe10e1382fae9e5ad1a60e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/cbmem/cbmem.c | 58 ++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index e342d69..3c6eee4 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -58,6 +58,9 @@ static int verbose = 0; /* File handle used to access /dev/mem */ static int mem_fd; +/* IMD root pointer location */ +static uint64_t rootptr = 0; + /* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case * the buffer length is odd last byte is excluded from the calculation @@ -95,8 +98,14 @@ static void unmap_memory(void) fprintf(stderr, "Error unmapping memory\n"); return; } - debug("Unmapping %zuMB of virtual memory at %p.\n", - size_to_mib(mapped_size), mapped_virtual); + if (size_to_mib(mapped_size) == 0) { + debug("Unmapping %zuMB of virtual memory at %p.\n", + size_to_mib(mapped_size), mapped_virtual); + } + else { + debug("Unmapping %zuMB of virtual memory at %p.\n", + size_to_mib(mapped_size), mapped_virtual); + } munmap(mapped_virtual, mapped_size); mapped_virtual = NULL; mapped_size = 0; @@ -117,12 +126,31 @@ static void *map_memory_size(u64 physical, size_t size) padding = physical & (page-1); size += padding; - debug("Mapping %zuMB of physical memory at 0x%jx.\n", - size_to_mib(size), (intmax_t)p); + if (size_to_mib(size) == 0) { + debug("Mapping %zuB of physical memory at 0x%jx (requested 0x%jx).\n", + size, (intmax_t)p, (intmax_t)physical); + } + else { + debug("Mapping %zuMB of physical memory at 0x%jx (requested 0x%jx).\n", + size_to_mib(size), (intmax_t)p, (intmax_t)physical); + } v = mmap(NULL, size, PROT_READ, MAP_SHARED, mem_fd, p); if (v == MAP_FAILED) { + /* The mapped area may have overrun the upper cbmem boundary when trying to + * align to the page size. Try growing down instead of up... + */ + p -= page; + padding += page; + size &= ~(page - 1); + size = size + (page - 1); + v = mmap(NULL, size, PROT_READ, MAP_SHARED, mem_fd, p); + debug(" ... failed. Mapping %zuB of physical memory at 0x%jx.\n", + size, (intmax_t)p); + } + + if (v == MAP_FAILED) { fprintf(stderr, "Failed to mmap /dev/mem: %s\n", strerror(errno)); exit(1); @@ -588,17 +616,18 @@ static void dump_cbmem_hex(void) /* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ #define DYN_CBMEM_ALIGN_SIZE (4096) #define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define CBMEM_POINTER_MAGIC 0xc0389479 +#define CBMEM_POINTER_MAGIC 0xc0389481 #define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) struct cbmem_root_pointer { uint32_t magic; - uint32_t root; + /* Relative to upper limit/offset. */ + int32_t root_offset; } __attribute__((packed)); struct dynamic_cbmem_entry { uint32_t magic; - uint32_t start; + int32_t start_offset; uint32_t size; uint32_t id; } __attribute__((packed)); @@ -606,8 +635,9 @@ struct dynamic_cbmem_entry { struct cbmem_root { uint32_t max_entries; uint32_t num_entries; - uint32_t locked; - uint32_t size; + uint32_t flags; + uint32_t entry_align; + int32_t max_offset; struct dynamic_cbmem_entry entries[0]; } __attribute__((packed)); @@ -667,8 +697,8 @@ static void dump_static_cbmem_toc(struct cbmem_entry *entries) static void dump_dynamic_cbmem_toc(struct cbmem_root *root) { int i; - debug("CBMEM: max_entries=%d num_entries=%d locked=0x%x, size=%d\n\n", - root->max_entries, root->num_entries, root->locked, root->size); + debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n", + root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset); printf("CBMEM table of contents:\n"); printf(" ID START LENGTH\n"); @@ -677,7 +707,7 @@ static void dump_dynamic_cbmem_toc(struct cbmem_root *root) if(root->entries[i].magic != CBMEM_ENTRY_MAGIC) break; cbmem_print_entry(i, root->entries[i].id, - root->entries[i].start, root->entries[i].size); + rootptr + root->entries[i].start_offset, root->entries[i].size); } } @@ -700,8 +730,6 @@ static void dump_cbmem_toc(void) if (entries[0].magic == CBMEM_MAGIC) { dump_static_cbmem_toc(entries); } else { - uint64_t rootptr; - rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size); rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); rootptr -= sizeof(struct cbmem_root_pointer); @@ -710,7 +738,7 @@ static void dump_cbmem_toc(void) map_memory_size(rootptr, sizeof(*r)); if (r->magic == CBMEM_POINTER_MAGIC) { struct cbmem_root *root; - uint64_t rootaddr = r->root; + uint64_t rootaddr = rootptr + r->root_offset; unmap_memory(); root = map_memory_size(rootaddr, ROOT_MIN_SIZE); dump_dynamic_cbmem_toc(root);

1 0

Patch merged into coreboot/master: 7267ccb libpayload: add mediatek timer driver
by gerrit＠coreboot.org 18 May '15

18 May '15

the following patch was just integrated into master: commit 7267ccbae861d6acf7edfa256b758e2836e21945 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Feb 9 16:34:44 2015 +0800 libpayload: add mediatek timer driver Change-Id: Ifb19cf97d4db6c7394521e549968a0cfb6ed1c75 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0137652ca07e290bb3cb1cc82a00b44ac7bcc7bf Original-Change-Id: Ica649927d3533c847b24e520e8fe73d75fb9e786 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/257375 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/10170 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10170 for details. -gerrit

1 0

New patch to review for coreboot: 2d95d04 gma/edid: Fix gma register access.
by Vladimir Serbinenko 18 May '15

18 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10237 -gerrit commit 2d95d04614ff19960398c41ad5d90366d2a8bc6c Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon May 18 13:13:48 2015 +0200 gma/edid: Fix gma register access. 0x20 was incorrectly represented as 4 * 5 while in fact it's 4 * 8 Change-Id: I6053a3baa6de0da9f1d648009353bc1fe542f81f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 36d8813..e70156e 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -49,11 +49,11 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) write32(mmio + 4 * 0, bus); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + 4 * 5, 0); + write32(mmio + 4 * 8, 0); write32(mmio + 4 * 1, 0x46000000 | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ - write32(mmio + 4 * 5, 0); + write32(mmio + 4 * 8, 0); write32(mmio + 4 * 1, 0x4a000001 | (slave << 1) | (edid_size << 16)); for (i = 0; i < edid_size / 4; i++) {

1 0

Patch set updated for coreboot: a8611f4 ivybridge native gfx init: Adjust state to be compatible with OPROM.
by Vladimir Serbinenko 18 May '15

18 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10205 -gerrit commit a8611f45f9eb452dff9be4f42e3284c433977717 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Wed May 13 09:30:09 2015 +0200 ivybridge native gfx init: Adjust state to be compatible with OPROM. My main payload is GRUB and I load SeaBIOS as secondary payload when for some reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom (SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either completely uninited gfx or some special state in gmbus and software scratch registers. Provide this state. The only alternative without this patch for such usecase is to use oprom and I'd like to avoid doing so when going my main boot path to GNU/Linux. Change-Id: I38e78fb845e43b81df084cd4d65f4618bfb2506d Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/drivers/intel/gma/edid.c | 24 ++++++++++++++++++++++ src/drivers/intel/gma/edid.h | 1 + .../intel/sandybridge/gma_ivybridge_lvds.c | 11 ++++++++-- 3 files changed, 34 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index e70156e..052f099 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -37,6 +37,30 @@ static void wait_rdy(u8 *mmio) } } +static void intel_gmbus_stop_bus(u8 * mmio, u8 bus) +{ + wait_rdy(mmio); + write32(mmio + 4 * 0, bus); + wait_rdy(mmio); + write32(mmio + 4 * 8, 0); + write32(mmio + 4 * 1, 0x4e0400a1); + wait_rdy(mmio); + write32(mmio + 4 * 8, 0); + write32(mmio + 4 * 1, 0x80000000); + write32(mmio + 4 * 1, 0x00000000); + wait_rdy(mmio); + write32(mmio + 4 * 1, 0x480000a0); + wait_rdy(mmio); + write32(mmio + 4 * 0, 0x48000000); + write32(mmio + 4 * 2, 0x00008000); +} + +void intel_gmbus_stop(u8 *mmio) +{ + intel_gmbus_stop_bus(mmio, 6); + intel_gmbus_stop_bus(mmio, 2); +} + void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size) { int i; diff --git a/src/drivers/intel/gma/edid.h b/src/drivers/intel/gma/edid.h index c476391..d8214cf 100644 --- a/src/drivers/intel/gma/edid.h +++ b/src/drivers/intel/gma/edid.h @@ -1 +1,2 @@ void intel_gmbus_read_edid(u8 *gmbus_mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size); +void intel_gmbus_stop(u8 *gmbus_mmio); diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 6c1295a..8fa780f 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -206,6 +206,7 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, enable_port(mmio); intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128); + intel_gmbus_stop(mmio + PCH_GMBUS0); decode_edid(edid_data, sizeof(edid_data), &edid); @@ -236,9 +237,8 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 pixel_m1 = 1; u32 pixel_m2 = 1; -#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_textmode_init(); -#else +#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) vga_sr_write(1, 1); vga_sr_write(0x2, 0xf); vga_sr_write(0x3, 0x0); @@ -513,6 +513,13 @@ int i915lightup_sandy(const struct i915_gpu_controller_info *info, set_vbe_mode_info_valid(&edid, lfb); #endif + /* Doesn't change any hw behaviour but vga oprom expects it there. */ + write32(mmio + 0x0004f040, 0x01000008); + write32(mmio + 0x0004f044, 0x00001800); + write32(mmio + 0x0004f04c, 0x7f7f0000); + write32(mmio + 0x0004f054, 0x0000422d); + write32(mmio + 0x0004f05c, 0x00000008); + /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)), "$VBT SNB/IVB-MOBILE ");

1 0

Patch merged into coreboot/master: 589e63e drivers/gic: reprogram the GIC CPU interface to bypass IRQ
by gerrit＠coreboot.org 18 May '15

18 May '15

the following patch was just integrated into master: commit 589e63ee7c302a96ef7f9349838936dccdb19f52 Author: Joseph Lo <josephl(a)nvidia.com> Date: Wed Apr 29 17:14:03 2015 +0800 drivers/gic: reprogram the GIC CPU interface to bypass IRQ GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. So the CPU can exit from WFI when an asserted IRQ is coming. This is critical for power gating a CPU. BRANCH=none BUG=chrome-os-partner:39620 TEST=testing with CPU idle with power down state support and CPU can wake up normally Change-Id: I71ac642e28024a562db898665b74a5791fce325a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 3a3f098cbf3fbfdab8150ebd4fd688fdb472b529 Original-Change-Id: I20569a18f34a4b11b8c8c67ea255b3d0f021839f Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269116 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10172 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10172 for details. -gerrit

1 0

Patch merged into coreboot/master: b7d0ffd arm64: psci: add cpu_suspend support
by gerrit＠coreboot.org 18 May '15

18 May '15

the following patch was just integrated into master: commit b7d0ffd1edb358c089c0fe94711aac65eeb81d6a Author: Joseph Lo <josephl(a)nvidia.com> Date: Tue Dec 9 15:11:54 2014 +0800 arm64: psci: add cpu_suspend support Implement the cpu_suspend for the PSCI service in secmon. BRANCH=none BUG=chrome-os-partner:39620 TEST=test with CPU idle driver that invoke the cpu_suspend of PSCI Change-Id: I4cdfab88bf36bf432fb33c56c1ea114b384528f8 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 90b3ea3fcb21cb393e30a8359f0328054961f6d5 Original-Change-Id: Ieb76abc017b9c3e074cc018903cef72020306a8f Original-Signed-off-by: Joseph Lo <josephl(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269115 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/10171 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10171 for details. -gerrit

1 0

New patch to review for coreboot: 99b27c1 util/cbmem: Update cbmem utility to parse the new IMD structures
by Timothy Pearson 17 May '15

17 May '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10236 -gerrit commit 99b27c1dbdd3edee38c2d97519c885cf7d555aa8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat May 16 14:55:54 2015 -0500 util/cbmem: Update cbmem utility to parse the new IMD structures This resolves the cbmem table of contents access failure. Change-Id: Ie143ae11d97f26bd17fe10e1382fae9e5ad1a60e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/cbmem/cbmem.c | 58 ++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 15 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index e342d69..3c6eee4 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -58,6 +58,9 @@ static int verbose = 0; /* File handle used to access /dev/mem */ static int mem_fd; +/* IMD root pointer location */ +static uint64_t rootptr = 0; + /* * calculate ip checksum (16 bit quantities) on a passed in buffer. In case * the buffer length is odd last byte is excluded from the calculation @@ -95,8 +98,14 @@ static void unmap_memory(void) fprintf(stderr, "Error unmapping memory\n"); return; } - debug("Unmapping %zuMB of virtual memory at %p.\n", - size_to_mib(mapped_size), mapped_virtual); + if (size_to_mib(mapped_size) == 0) { + debug("Unmapping %zuMB of virtual memory at %p.\n", + size_to_mib(mapped_size), mapped_virtual); + } + else { + debug("Unmapping %zuMB of virtual memory at %p.\n", + size_to_mib(mapped_size), mapped_virtual); + } munmap(mapped_virtual, mapped_size); mapped_virtual = NULL; mapped_size = 0; @@ -117,12 +126,31 @@ static void *map_memory_size(u64 physical, size_t size) padding = physical & (page-1); size += padding; - debug("Mapping %zuMB of physical memory at 0x%jx.\n", - size_to_mib(size), (intmax_t)p); + if (size_to_mib(size) == 0) { + debug("Mapping %zuB of physical memory at 0x%jx (requested 0x%jx).\n", + size, (intmax_t)p, (intmax_t)physical); + } + else { + debug("Mapping %zuMB of physical memory at 0x%jx (requested 0x%jx).\n", + size_to_mib(size), (intmax_t)p, (intmax_t)physical); + } v = mmap(NULL, size, PROT_READ, MAP_SHARED, mem_fd, p); if (v == MAP_FAILED) { + /* The mapped area may have overrun the upper cbmem boundary when trying to + * align to the page size. Try growing down instead of up... + */ + p -= page; + padding += page; + size &= ~(page - 1); + size = size + (page - 1); + v = mmap(NULL, size, PROT_READ, MAP_SHARED, mem_fd, p); + debug(" ... failed. Mapping %zuB of physical memory at 0x%jx.\n", + size, (intmax_t)p); + } + + if (v == MAP_FAILED) { fprintf(stderr, "Failed to mmap /dev/mem: %s\n", strerror(errno)); exit(1); @@ -588,17 +616,18 @@ static void dump_cbmem_hex(void) /* The root region is at least DYN_CBMEM_ALIGN_SIZE . */ #define DYN_CBMEM_ALIGN_SIZE (4096) #define ROOT_MIN_SIZE DYN_CBMEM_ALIGN_SIZE -#define CBMEM_POINTER_MAGIC 0xc0389479 +#define CBMEM_POINTER_MAGIC 0xc0389481 #define CBMEM_ENTRY_MAGIC ~(CBMEM_POINTER_MAGIC) struct cbmem_root_pointer { uint32_t magic; - uint32_t root; + /* Relative to upper limit/offset. */ + int32_t root_offset; } __attribute__((packed)); struct dynamic_cbmem_entry { uint32_t magic; - uint32_t start; + int32_t start_offset; uint32_t size; uint32_t id; } __attribute__((packed)); @@ -606,8 +635,9 @@ struct dynamic_cbmem_entry { struct cbmem_root { uint32_t max_entries; uint32_t num_entries; - uint32_t locked; - uint32_t size; + uint32_t flags; + uint32_t entry_align; + int32_t max_offset; struct dynamic_cbmem_entry entries[0]; } __attribute__((packed)); @@ -667,8 +697,8 @@ static void dump_static_cbmem_toc(struct cbmem_entry *entries) static void dump_dynamic_cbmem_toc(struct cbmem_root *root) { int i; - debug("CBMEM: max_entries=%d num_entries=%d locked=0x%x, size=%d\n\n", - root->max_entries, root->num_entries, root->locked, root->size); + debug("CBMEM: max_entries=%d num_entries=%d flags=0x%x, entry_align=0x%x, max_offset=%d\n\n", + root->max_entries, root->num_entries, root->flags, root->entry_align, root->max_offset); printf("CBMEM table of contents:\n"); printf(" ID START LENGTH\n"); @@ -677,7 +707,7 @@ static void dump_dynamic_cbmem_toc(struct cbmem_root *root) if(root->entries[i].magic != CBMEM_ENTRY_MAGIC) break; cbmem_print_entry(i, root->entries[i].id, - root->entries[i].start, root->entries[i].size); + rootptr + root->entries[i].start_offset, root->entries[i].size); } } @@ -700,8 +730,6 @@ static void dump_cbmem_toc(void) if (entries[0].magic == CBMEM_MAGIC) { dump_static_cbmem_toc(entries); } else { - uint64_t rootptr; - rootptr = unpack_lb64(cbmem.start) + unpack_lb64(cbmem.size); rootptr &= ~(DYN_CBMEM_ALIGN_SIZE - 1); rootptr -= sizeof(struct cbmem_root_pointer); @@ -710,7 +738,7 @@ static void dump_cbmem_toc(void) map_memory_size(rootptr, sizeof(*r)); if (r->magic == CBMEM_POINTER_MAGIC) { struct cbmem_root *root; - uint64_t rootaddr = r->root; + uint64_t rootaddr = rootptr + r->root_offset; unmap_memory(); root = map_memory_size(rootaddr, ROOT_MIN_SIZE); dump_dynamic_cbmem_toc(root);

1 0

Patch set updated for coreboot: 64f0348 A try to add i945G based board.
by HAOUAS Elyes 17 May '15

17 May '15

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9971 -gerrit commit 64f034888af942818bb8e331b23e799ff3b89239 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun May 17 22:13:35 2015 +0200 A try to add i945G based board. the system hung on: Setting up Root Complex Topology CBMEM: IMD: root @ 7ffff000 254 entries. IMD: root @ 7fffec00 62 entries. here is the serial log: https://www.dropbox.com/s/msyu428hevogl5b/17052015.txt?dl=0 Change-Id: I97401a39a958a17f2f9120539362e3fa7819a742 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nec/945g-m4/Kconfig | 42 ++++ src/mainboard/nec/945g-m4/Kconfig.name | 2 + src/mainboard/nec/945g-m4/acpi/ec.asl | 1 + src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl | 83 ++++++++ src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl | 103 ++++++++++ src/mainboard/nec/945g-m4/acpi/platform.asl | 90 +++++++++ src/mainboard/nec/945g-m4/acpi/superio.asl | 92 +++++++++ src/mainboard/nec/945g-m4/acpi/thermal.asl | 94 +++++++++ src/mainboard/nec/945g-m4/acpi/video.asl | 43 ++++ src/mainboard/nec/945g-m4/acpi_tables.c | 77 ++++++++ src/mainboard/nec/945g-m4/board_info.txt | 15 ++ src/mainboard/nec/945g-m4/cmos.layout | 194 +++++++++++++++++++ src/mainboard/nec/945g-m4/devicetree.cb | 121 ++++++++++++ src/mainboard/nec/945g-m4/dsdt.asl | 44 +++++ src/mainboard/nec/945g-m4/hda_verb.c | 5 + src/mainboard/nec/945g-m4/irq_tables.c | 61 ++++++ src/mainboard/nec/945g-m4/mainboard.c | 94 +++++++++ src/mainboard/nec/945g-m4/mptable.c | 106 ++++++++++ src/mainboard/nec/945g-m4/romstage.c | 237 +++++++++++++++++++++++ src/mainboard/nec/945g-m4/smihandler.c | 49 +++++ src/mainboard/nec/945g-m4/superio_hwm.c | 161 +++++++++++++++ src/mainboard/nec/945g-m4/superio_hwm.h | 25 +++ src/northbridge/intel/i945/early_init.c | 30 ++- src/northbridge/intel/i945/gma.c | 17 +- src/northbridge/intel/i945/raminit.c | 156 ++++++++++----- 25 files changed, 1885 insertions(+), 57 deletions(-) diff --git a/src/mainboard/nec/945g-m4/Kconfig b/src/mainboard/nec/945g-m4/Kconfig new file mode 100644 index 0000000..791a8f9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig @@ -0,0 +1,42 @@ +if BOARD_NEC_945G_M4 +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_I945 + select NORTHBRIDGE_INTEL_SUBTYPE_I945GC + select CHECK_SLFRCS_ON_RESUME + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_WINBOND_W83627EHG + select HAVE_ACPI_TABLES + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION + +config MAINBOARD_DIR + string + default nec/945g-m4 + +config MAINBOARD_PART_NUMBER + string + default "945G-M4" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 4 + +#config VGA_BIOS_FILE +# string +# default "amipci_01.20" +endif # BOARD_NEC_945G_M4 diff --git a/src/mainboard/nec/945g-m4/Kconfig.name b/src/mainboard/nec/945g-m4/Kconfig.name new file mode 100644 index 0000000..46571f0 --- /dev/null +++ b/src/mainboard/nec/945g-m4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_NEC_945G_M4 + bool "945G-M" diff --git a/src/mainboard/nec/945g-m4/acpi/ec.asl b/src/mainboard/nec/945g-m4/acpi/ec.asl new file mode 100644 index 0000000..8f20f9d --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ec.asl @@ -0,0 +1 @@ +//to make the compiler happy diff --git a/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl new file mode 100644 index 0000000..fb57b5e --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/i945_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for i945G */ + + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, 0, 10 }, + Package() { 0x0001ffff, 1, 0, 11 }, + Package() { 0x0001ffff, 2, 0, 12 }, + Package() { 0x0001ffff, 3, 0, 13 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 10 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 10 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 10 }, + Package() { 0x001cffff, 1, 0, 11 }, + Package() { 0x001cffff, 2, 0, 12 }, + Package() { 0x001cffff, 3, 0, 13 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, 0, 17 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 13 }, + Package() { 0x001dffff, 3, 0, 12 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, 0, 11 }, + Package() { 0x001effff, 1, 0, 24 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, 0, 12 }, + Package() { 0x001fffff, 1, 0, 13 }, + }) + } Else { + Return (Package() { + // PCIe Graphics 0:1.0 + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + //Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // USB and EHCI 0:1d.x + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // AC97/IDE 0:1e.2, 0:1e.3 + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } +} diff --git a/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..c108d3f --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/ich7_pci_irqs.asl @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for the + * 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x0000ffff, 0, 0, 16}, + + Package() { 0x0001ffff, 0, 0, 20}, + Package() { 0x0001ffff, 1, 0, 21}, + Package() { 0x0001ffff, 2, 0, 22}, + Package() { 0x0001ffff, 3, 0, 23}, + + Package() { 0x0002ffff, 0, 0, 21}, + Package() { 0x0002ffff, 1, 0, 22}, + Package() { 0x0002ffff, 2, 0, 23}, + Package() { 0x0002ffff, 3, 0, 20}, + + Package() { 0x0003ffff, 0, 0, 22}, + Package() { 0x0003ffff, 1, 0, 23}, + Package() { 0x0003ffff, 2, 0, 20}, + Package() { 0x0003ffff, 3, 0, 21}, + + Package() { 0x0004ffff, 0, 0, 23}, + Package() { 0x0004ffff, 1, 0, 20}, + Package() { 0x0004ffff, 2, 0, 21}, + Package() { 0x0004ffff, 3, 0, 22}, + + Package() { 0x0005ffff, 0, 0, 19}, + Package() { 0x0005ffff, 1, 0, 18}, + Package() { 0x0005ffff, 2, 0, 17}, + Package() { 0x0005ffff, 3, 0, 16}, + + Package() { 0x0006ffff, 0, 0, 18}, + Package() { 0x0006ffff, 1, 0, 17}, + Package() { 0x0006ffff, 2, 0, 16}, + Package() { 0x0006ffff, 3, 0, 19}, + + Package() { 0x0009ffff, 0, 0, 21}, + Package() { 0x0009ffff, 1, 0, 22}, + Package() { 0x0009ffff, 2, 0, 23}, + Package() { 0x0009ffff, 3, 0, 20}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0}, + + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0}, + + Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0}, + + Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + + Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + + Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0}, + Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0}, + Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0}, + Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0}, + }) +} + diff --git a/src/mainboard/nec/945g-m4/acpi/platform.asl b/src/mainboard/nec/945g-m4/acpi/platform.asl new file mode 100644 index 0000000..6770348 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/platform.asl @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + // Call a trap so SMI can prepare for Sleep as well. + // TRAP(0x55) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + // CPU specific part + + // Notify PCI Express slots in case a card + // was inserted while a sleep state was active. + + // Are we going to S3? + If (LEqual(Arg0, 3)) { + // .. + } + + // Are we going to S4? + If (LEqual(Arg0, 4)) { + // .. + } + + // TODO: Windows XP SP2 P-State restore + + Return(Package(){0,0}) +} diff --git a/src/mainboard/nec/945g-m4/acpi/superio.asl b/src/mainboard/nec/945g-m4/acpi/superio.asl new file mode 100644 index 0000000..997a33a --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/superio.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +Device (SIO1) +{ + Name (_HID, EISAID("PNP0A05")) + Name (_UID, 1) + + Device (UAR1) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 1) + Name(_DDN, "COM1") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8) + IRQNoFlags() { 4 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } + + Device (UAR2) + { + Name(_HID, EISAID("PNP0501")) + Name(_UID, 2) + Name(_DDN, "COM2") + + Method (_STA, 0) + { + // always enable for now + Return (0x0f) + } + + Method (_DIS, 0) { /* NOOP */ } + + Name (_PRS, ResourceTemplate() { + StartDependentFn(0, 1) { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + } EndDependentFn() + }) + + Method (_CRS, 0) + { + Return(ResourceTemplate() { + IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8) + IRQNoFlags() { 3 } + }) + } + // Some methods need an implementation here: + // missing: _STA, _DIS, _CRS, _PRS, + // missing: _SRS, _PS0, _PS3 + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/thermal.asl b/src/mainboard/nec/945g-m4/acpi/thermal.asl new file mode 100644 index 0000000..ede22fa --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/thermal.asl @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + + // FIXME these could/should be read from the + // GNVS area, so they can be controlled by + // coreboot + Name(TC1V, 0x04) + Name(TC2V, 0x03) + Name(TSPV, 0x64) + + // At which temperature should the OS start + // active cooling? + Method (_AC0, 0, Serialized) + { + Return (0xf5c) // Value for Rocky + } + + // Method (_AC1, 0, Serialized) + // { + // Return (0xf5c) + // } + + // Critical shutdown temperature + Method (_CRT, 0, Serialized) + { + Return (Add (0x0aac, 0x50)) // FIXME + } + + // CPU throttling start temperature + Method (_PSV, 0, Serialized) + { + Return (0xaaf) // FIXME + } + + // Get DTS Temperature + Method (_TMP, 0, Serialized) + { + Return (0xaac) // FIXME + } + + // Processors used for active cooling + Method (_PSL, 0, Serialized) + { + If (MPEN) { + Return (Package() {\_PR.CPU1, \_PR.CPU2}) + } + Return (Package() {\_PR.CPU1}) + } + + // TC1 value for passive cooling + Method (_TC1, 0, Serialized) + { + Return (TC1V) + } + + // TC2 value for passive cooling + Method (_TC2, 0, Serialized) + { + Return (TC2V) + } + + // Sampling period for passive cooling + Method (_TSP, 0, Serialized) + { + Return (TSPV) + } + + + } +} + diff --git a/src/mainboard/nec/945g-m4/acpi/video.asl b/src/mainboard/nec/945g-m4/acpi/video.asl new file mode 100644 index 0000000..3ececa9 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi/video.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/nec/945g-m4/acpi_tables.c b/src/mainboard/nec/945g-m4/acpi_tables.c new file mode 100644 index 0000000..dba2953 --- /dev/null +++ b/src/mainboard/nec/945g-m4/acpi_tables.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> + +#include "southbridge/intel/i82801gx/nvs.h" +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Enable both COM ports */ + gnvs->cmap = 0x01; + gnvs->cmbp = 0x01; + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + diff --git a/src/mainboard/nec/945g-m4/board_info.txt b/src/mainboard/nec/945g-m4/board_info.txt new file mode 100644 index 0000000..dc67898 --- /dev/null +++ b/src/mainboard/nec/945g-m4/board_info.txt @@ -0,0 +1,15 @@ +Board name:945G-M4 (Rev: B) +Category: µATX 24.4 cm x 24.4 cm Form Factor +Board URL: http://www.nec-computers.com/support2/pib.asp?platform=spec_veracruz&mode=d… +ROM package: PLCC +ROM protocol: FWH +ROM socketed: y +Flashrom support: y + +superiotool: https://www.dropbox.com/s/bn3478cz1n4g76x/superIOtool.txt?dl=0 +inteltool: https://www.dropbox.com/s/fnygo2juum6qcth/inteltool-log.txt?dl=0 +facp.dsl: https://www.dropbox.com/s/7r9po39nn9vd8af/facp.dsl?dl=0 +dsdt.dsl: https://www.dropbox.com/s/uei35yaon0vtr2d/dsdt.dsl?dl=0 +ssdt1.dsl: https://www.dropbox.com/s/s20t7mr4invzcgj/ssdt1.dsl?dl=0 +ssdt2.dsl: https://www.dropbox.com/s/d71lqmc871lzgxi/ssdt2.dsl?dl=0 +getpir (irq_tables.c): https://www.dropbox.com/s/mf6gbdzxb2mx3ty/irq_tables.c?dl=0 \ No newline at end of file diff --git a/src/mainboard/nec/945g-m4/cmos.layout b/src/mainboard/nec/945g-m4/cmos.layout new file mode 100644 index 0000000..b3e8c4e --- /dev/null +++ b/src/mainboard/nec/945g-m4/cmos.layout @@ -0,0 +1,194 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +416 512 s 0 boot_devices +#928 40 r 0 unused + +# coreboot config options: mainboard specific options +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature + +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 + +#971 13 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ram initialization internal data +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# Fan Cruise Control +8 0 Disabled +8 1 Speed +#8 2 Thermal +# Fan Speed (Rotations per Minute) +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 +# +# Temperature (�C/�F) +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/nec/945g-m4/devicetree.cb b/src/mainboard/nec/945g-m4/devicetree.cb new file mode 100644 index 0000000..7423f30 --- /dev/null +++ b/src/mainboard/nec/945g-m4/devicetree.cb @@ -0,0 +1,121 @@ +chip northbridge/intel/i945 + device cpu_cluster 0 on + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + end + device domain 0 on + device pci 00.0 on end # 82945G/GZ/P/PL Memory Controller Hub [8086:2770] + device pci 02.0 on end # 82945G/GZ Integrated Graphics Controller [8086:2772] + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x8a" + register "pirqb_routing" = "0x85" + register "pirqc_routing" = "0x8a" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x87" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "1" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + + device pci 1c.0 on end # PCI Express Gigabit Ethernet Controller [10ec:8168] + device pci 1d.0 on end # NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] + device pci 1d.1 on end # NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9] + device pci 1d.2 on end # NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca] + device pci 1d.3 on end # NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb] + device pci 1d.7 on end # NM10/ICH7 Family USB2 EHCI Controller [8086:27cc] + device pci 1e.0 on end # 82801 PCI Bridge [8086:244e] + device pci 1e.2 on end # 82801G (ICH7 Family) AC'97 Audio Controller [8086:27de] + device pci 1f.0 on # 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] + + chip superio/winbond/w83627ehg # Super I/O Winbond + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.3 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + irq 0xf0 = 0x82 + end + + device pnp 2e.106 on # Serial flash interface + io 0x60 = 0x100 + end + + device pnp 2e.007 on # GPIO 1 + end + + device pnp 2e.107 off # Game port + io 0x60 = 0x201 + end + + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + + device pnp 2e.307 on # GPIO 6 + end + + device pnp 2e.8 off # WDTO#, PLED + end + + device pnp 2e.009 on # GPIO 2 + end + + device pnp 2e.109 on # GPIO 3 + end + + device pnp 2e.209 on # GPIO 4 + end + + device pnp 2e.309 on # GPIO 5 + end + + device pnp 2e.a on # ACPI + end + + device pnp 2e.b on # Hardware monitor + io 0x60 = 0xa10 + irq 0x70 = 0 + end + + end # Winbond + end # LPC + + device pci 1f.1 on end # 82801G (ICH7 Family) IDE Controller [8086:27df] + device pci 1f.2 on end # NM10/ICH7 Family SATA Controller [IDE mode] [8086:27c0] + device pci 1f.3 on end # NM10/ICH7 Family SMBus Controller [8086:27da] + end # i82801gx + end # domain 0 +end diff --git a/src/mainboard/nec/945g-m4/dsdt.asl b/src/mainboard/nec/945g-m4/dsdt.asl new file mode 100644 index 0000000..05a93d3 --- /dev/null +++ b/src/mainboard/nec/945g-m4/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +DefinitionBlock ("dsdt.aml", "DSDT", 1, "COREv4", "COREBOOT", 0x00000108) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + //#include "acpi/platform.asl" + + // General Purpose Events + //#include "acpi/gpe.asl" + + //#include "acpi/thermal.asl" + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/nec/945g-m4/hda_verb.c b/src/mainboard/nec/945g-m4/hda_verb.c new file mode 100644 index 0000000..aaa0a93 --- /dev/null +++ b/src/mainboard/nec/945g-m4/hda_verb.c @@ -0,0 +1,5 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; +const u32 pc_beep_verbs[0] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/nec/945g-m4/irq_tables.c b/src/mainboard/nec/945g-m4/irq_tables.c new file mode 100644 index 0000000..d51d2ef --- /dev/null +++ b/src/mainboard/nec/945g-m4/irq_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * 14, /* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x1f << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x27b0, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xb, /* Checksum (has to be set to some value that + * would give 0 after the sum of all bytes + * for this structure (including checksum). + */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1e << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1f << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x60, 0xdcf8}}, 0x0, 0x0}, + {0x00, (0x1b << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0}, + {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0}, + {0x03, (0x03 << 3) | 0x0, {{0x63, 0xdcf8}, {0x62, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x4, 0x0}, + {0x03, (0x04 << 3) | 0x0, {{0x62, 0xdcf8}, {0x6b, 0xdcf8}, {0x60, 0xdcf8}, {0x68, 0xdcf8}}, 0x5, 0x0}, + {0x03, (0x05 << 3) | 0x0, {{0x61, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x6, 0x0}, + {0x03, (0x01 << 3) | 0x0, {{0x62, 0xdcf8}, {0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}}, 0x1, 0x0}, + {0x03, (0x02 << 3) | 0x0, {{0x63, 0xdcf8}, {0x68, 0xdcf8}, {0x69, 0xdcf8}, {0x6a, 0xdcf8}}, 0x2, 0x0}, + {0x03, (0x08 << 3) | 0x0, {{0x68, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr, &intel_irq_routing_table); +} diff --git a/src/mainboard/nec/945g-m4/mainboard.c b/src/mainboard/nec/945g-m4/mainboard.c new file mode 100644 index 0000000..508d693 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mainboard.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include "superio_hwm.h" + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f40: /* Boot Panel Type */ + // M.x86.R_AX = 0x015f; // Supported but failed + X86_AX = 0x005f; // Success + X86_CL = 3; // Display ID + break; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif +/* Audio Setup */ + +extern u32 * cim_verb_data; +extern u32 cim_verb_data_size; + +static void verb_setup(void) +{ + // Default VERB is fine on this mainboard. + cim_verb_data = NULL; + cim_verb_data_size = 0; +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +// hwm_setup(); /* commented while debugging */ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/nec/945g-m4/mptable.c b/src/mainboard/nec/945g-m4/mptable.c new file mode 100644 index 0000000..eed8fa6 --- /dev/null +++ b/src/mainboard/nec/945g-m4/mptable.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#define INTA 0x00 +#define INTB 0x01 +#define INTC 0x02 +#define INTD 0x03 +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + smp_write_processors(mc); + /* Bus: Bus ID Type */ + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + my_smp_write_bus(mc, 2, "PCI "); + my_smp_write_bus(mc, 3, "PCI "); + my_smp_write_bus(mc, 4, "ISA "); + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, 0x1, 0x20, VIO_APIC_VADDR); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ + smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x0); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x1, 0x1, 0x1); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x0, 0x1, 0x2); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x3, 0x1, 0x3); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x4, 0x1, 0x4); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x6, 0x1, 0x6); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x7, 0x1, 0x7); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x4, 0x8, 0x1, 0x8); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0x9, 0x1, 0x9); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xc, 0x1, 0xc); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xd, 0x1, 0xd); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xe, 0x1, 0xe); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x4, 0xf, 0x1, 0xf); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x01 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1e << 2) | INTA, 0x1, 0x11); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTA, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1f << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTA, 0x1, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTB, 0x1, 0x13); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTC, 0x1, 0x12); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1d << 2) | INTD, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x1c << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | INTA, 0x1, 0x10); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x02 << 2) | INTA, 0x1, 0x13); + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, 0x0, 0x0, MP_APIC_ALL, 0x1); +/* mptable_lintsrc(mc, isa_bus); */ + /* Compute the checksums */ + return mptable_finalize(mc); +} +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 1); + return (unsigned long)smp_write_config_table(v); +} +/*MP Config Extended Table Entries: +-- +System Address Space + bus ID: 0 address type: I/O address + address base: 0x600000000000 + address range: 0x148000000000 +Extended Table HOSED! +*/ diff --git a/src/mainboard/nec/945g-m4/romstage.c b/src/mainboard/nec/945g-m4/romstage.c new file mode 100644 index 0000000..80679e7 --- /dev/null +++ b/src/mainboard/nec/945g-m4/romstage.c @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2014 coreboot + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/romstage.h> +#include <lib.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83627ehg/w83627ehg.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <cpu/intel/romstage.h> +#include <halt.h> +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void setup_ich7_gpios(void) +{ + + printk(BIOS_DEBUG, "GPIOS..."); + /* General Registers */ + outl(0x1f9fffc3, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xebffffbf, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + /* Output Control Registers */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + /* Input Control Registers */ + outl(0x0000af03, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ + outl(0x000000f7, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ +} + +static void ich7_enable_lpc(void) +{ + // Enable Serial IRQ + pci_write_config8(LPC_DEV, 0x64, 0xd0); + // LPC I/O decode range + pci_write_config16(LPC_DEV, 0x80, 0x0010); + // LPC Interface Enables + pci_write_config16(LPC_DEV, 0x82, 0x340f); + // GEN1_DEC. LPC interface generic decode Rang1 + pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); + // GEN2_DEC. LPC interface generic decode Rang2 + pci_write_config32(LPC_DEV, 0x88, 0x00fc4701); + +} + +static void rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(0x0014) = 0x80000001; + RCBA32(0x001c) = 0x03128010; + +/* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(0x310c) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(0x3110) = 0x00000001; + /* dev irq route register */ + RCBA16(0x3140) = 0x0132; + RCBA16(0x3142) = 0x0146; + RCBA16(0x3144) = 0x0237; + RCBA16(0x3146) = 0x3201; + RCBA16(0x3148) = 0x0146; + /* Enable IOAPIC */ + RCBA8(0x31ff) |= 3 << 24; + /* Enable upper 128bytes of CMOS */ + RCBA32(0x3400) = (1 << 2); + /* Enable PCIe Root Port Clock Gate */ + RCBA32(0x341c) = 0x00000001; +} + +static void early_ich7_init(void) +{ + uint8_t reg8; + uint32_t reg32; + printk(BIOS_DEBUG, "program secondary mlt XXX byte \n"); + pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); +printk(BIOS_DEBUG, "reset rtc power status \n"); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 &= ~(1 << 2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); +printk(BIOS_DEBUG, "usb transient disconnect \n"); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 |= (3 << 0); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); + reg32 |= (1 << 29) | (1 << 17); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); + reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); + reg32 |= (1 << 31) | (1 << 27); + pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); + + /*./inteltool -r on vendor bios*/ + RCBA32(0x0088) = 0x0011d000; + RCBA16(0x01fc) = 0x060f; + RCBA32(0x01f4) = 0x86000040; + RCBA32(0x0214) = 0x10030549; + RCBA32(0x0218) = 0x00020504; + RCBA8(0x0220) = 0xc5; + reg32 = RCBA32(0x3410); + reg32 |= (1 << 6); + RCBA32(0x3410) = reg32; + reg32 = RCBA32(0x3430); + reg32 &= ~(3 << 0); + reg32 |= (1 << 0); + RCBA32(0x3430) = reg32; + RCBA32(0x3418) |= (1 << 0); + RCBA16(0x0200) = 0x2008; + RCBA8(0x2027) = 0x0d; + RCBA16(0x3e08) |= (1 << 7); + RCBA16(0x3e48) |= (1 << 7); +// RCBA32(0x3e0e) |= (1 << 7); +// RCBA32(0x3e4e) |= (1 << 7); + // next step only on ich7m b0 and later: + reg32 = RCBA32(0x2034); + reg32 &= ~(0x0f << 16); + reg32 |= (5 << 16); + RCBA32(0x2034) = reg32; + + +} + +void main(unsigned long bist) +{ + int s3resume = 0; +device_t dev; + if (bist == 0) + enable_lapic(); + + ich7_enable_lpc(); + /* Set up the console */ +// winbond_enable_serial(SERIAL_DEV,CONFIG_TTYS0_BASE); + + dev=PNP_DEV(0x2e, W83627EHG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); +// SuperIO + dev=PNP_DEV(0x2e, W83627EHG_KBC); // Keyboard + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + //pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627EHG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + + dev=PNP_DEV(0x2e, W83627EHG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4 + + dev=PNP_DEV(0x2e, W83627EHG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev=PNP_DEV(0x2e, W83627EHG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + /* Enable HWM */ + dev=PNP_DEV(0x2e, W83627EHG_HWM); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); + pnp_set_enable(dev, 1); + + pnp_exit_ext_func_mode(dev); +// + console_init(); + + report_bist_failure(bist); + if (MCHBAR16(SSKPD) == 0xCAFE) { + printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); + outb(0x6, 0xcf9); + halt(); + } + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + + i945_early_initialization(); + s3resume = southbridge_detect_s3_resume(); + +printk(BIOS_DEBUG, "Enable SPD ROMs and DDR-II DRAM \n"); + enable_smbus(); + +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 + dump_spd_registers(); +#endif + sdram_initialize(s3resume ? 2 : 0, NULL); +printk(BIOS_DEBUG, "Perform some initialization that must run before stage2 \n"); + early_ich7_init(); + +rcba_config(); +printk(BIOS_DEBUG, "Chipset Errata! \n"); +// fixup_i945_errata(); this is probably not for desktop version. + +printk(BIOS_DEBUG, "Initialize the internal PCIe links before we go into stage2 \n"); + i945_late_initialization(s3resume); +} diff --git a/src/mainboard/nec/945g-m4/smihandler.c b/src/mainboard/nec/945g-m4/smihandler.c new file mode 100644 index 0000000..d1f4f7b --- /dev/null +++ b/src/mainboard/nec/945g-m4/smihandler.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/i82801gx/nvs.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + gnvs->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.c b/src/mainboard/nec/945g-m4/superio_hwm.c new file mode 100644 index 0000000..622f8e8 --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.c @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <device/device.h> +#include <console/console.h> +#include <arch/io.h> +#include <pc80/mc146818rtc.h> + +#include "superio_hwm.h" + +/* Hardware Monitor */ + +#define FAN_CRUISE_CONTROL_DISABLED 0 +#define FAN_CRUISE_CONTROL_SPEED 1 +#define FAN_CRUISE_CONTROL_THERMAL 2 + +#define FAN_SPEED_5625 0 +//#define FAN_TEMPERATURE_30DEGC 0 + +#define HWM_BASE 0x290 + +static void hwm_write(u8 reg, u8 value) +{ + outb(reg, HWM_BASE + 0x05); // Index port + outb(value, HWM_BASE + 0x06); // Data port +} + +static void hwm_bank(u8 bank) +{ + hwm_write(0x2e, bank); +} + +struct fan_speed { + u8 fan_in; + u16 fan_speed; +}; + +// FANIN Target Speed Register +// FANIN = 337500 / RPM +struct fan_speed fan_speeds[] = { + { 0x3c, 5625 }, { 0x41, 5192 }, { 0x47, 4753 }, { 0x4e, 4326 }, + { 0x56, 3924 }, { 0x5f, 3552 }, { 0x69, 3214 }, { 0x74, 2909 }, + { 0x80, 2636 }, { 0x8d, 2393 }, { 0x9b, 2177 }, { 0xaa, 1985 }, + { 0xba, 1814 }, { 0xcb, 1662 }, { 0xdd, 1527 }, { 0xf0, 1406 } +}; + +struct temperature { + u8 deg_celsius; + u8 deg_fahrenheit; +}; + +struct temperature temperatures[] = { + { 30, 86 }, { 33, 91 }, { 36, 96 }, { 39, 102 }, + { 42, 107 }, { 45, 113 }, { 48, 118 }, { 51, 123 }, + { 54, 129 }, { 57, 134 }, { 60, 140 }, { 63, 145 }, + { 66, 150 }, { 69, 156 }, { 72, 161 }, { 75, 167 } +}; + +void hwm_setup(void) +{ + int cpufan_control = 0, sysfan_control = 0; + int cpufan_speed = 0, sysfan_speed = 0; + int cpufan_temperature = 0, sysfan_temperature = 0; + + if (get_option(&cpufan_control, "cpufan_cruise_control") != CB_SUCCESS) + cpufan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&cpufan_speed, "cpufan_speed") != CB_SUCCESS) + cpufan_speed = FAN_SPEED_5625; + //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) + // cpufan_temperature = FAN_TEMPERATURE_30DEGC; + + if (get_option(&sysfan_control, "sysfan_cruise_control") != CB_SUCCESS) + sysfan_control = FAN_CRUISE_CONTROL_DISABLED; + if (get_option(&sysfan_speed, "sysfan_speed") != CB_SUCCESS) + sysfan_speed = FAN_SPEED_5625; + //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) + // sysfan_temperature = FAN_TEMPERATURE_30DEGC; + + // hwm_write(0x31, 0x20); // AVCC high limit + // hwm_write(0x34, 0x06); // VIN2 low limit + + hwm_bank(0); + hwm_write(0x59, 0x20); // Diode Selection + hwm_write(0x5d, 0x0f); // All Sensors Diode, not Thermistor + + hwm_bank(4); + hwm_write(0x54, 0xf1); // SYSTIN temperature offset + hwm_write(0x55, 0x19); // CPUTIN temperature offset + hwm_write(0x56, 0xfc); // AUXTIN temperature offset + + hwm_bank(0x80); // Default + + u8 fan_config = 0; + // 00 FANOUT is Manual Mode + // 01 FANOUT is Thermal Cruise Mode + // 10 FANOUT is Fan Speed Cruise Mode + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 4); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 4); break; + } + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: fan_config |= (2 << 2); break; + case FAN_CRUISE_CONTROL_THERMAL: fan_config |= (1 << 2); break; + } + // This register must be written first + hwm_write(0x04, fan_config); + + switch (cpufan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to %d RPM\n", + fan_speeds[cpufan_speed].fan_speed); + hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting CPU fan to activation at %d deg C/%d deg F\n", + temperatures[cpufan_temperature].deg_celsius, + temperatures[cpufan_temperature].deg_fahrenheit); + hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature + break; + } + + switch (sysfan_control) { + case FAN_CRUISE_CONTROL_SPEED: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to %d RPM\n", + fan_speeds[sysfan_speed].fan_speed); + hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed + break; + case FAN_CRUISE_CONTROL_THERMAL: + printk(BIOS_DEBUG, "Fan Cruise Control setting system fan to activation at %d deg C/%d deg F\n", + temperatures[sysfan_temperature].deg_celsius, + temperatures[sysfan_temperature].deg_fahrenheit); + hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature + break; + } + + hwm_write(0x0e, 0x02); // Fan Output Step Down Time + hwm_write(0x0f, 0x02); // Fan Output Step Up Time + + hwm_write(0x47, 0xaf); // FAN divisor register + hwm_write(0x4b, 0x84); // AUXFANIN speed divisor + + hwm_write(0x40, 0x01); // Init, but no SMI# +} diff --git a/src/mainboard/nec/945g-m4/superio_hwm.h b/src/mainboard/nec/945g-m4/superio_hwm.h new file mode 100644 index 0000000..346b97c --- /dev/null +++ b/src/mainboard/nec/945g-m4/superio_hwm.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_HWM_H +#define SUPERIO_HWM_H + +void hwm_setup(void); + +#endif /* SUPERIO_HWM_H */ diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 776c051..182294e 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -134,6 +134,9 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: + printk(BIOS_DEBUG, "up to DDR2-667"); /* 945G-M4 board support up to 667, (PCI_DEV(0, 0x00, 0), 0xe4) & 0x07) returns 2 */ + break; case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -232,6 +235,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 |= 0x14; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -248,6 +253,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0; @@ -255,9 +265,16 @@ static void i945_setup_egress_port(void) /* Is internal graphics enabled? */ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { - MCHBAR32(MMARB1) |= (1 << 17); + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) { + MCHBAR32(MMARB1) &= ~ (1 << 18); + MCHBAR32(C0DRC1) |= 2; + MCHBAR32(C1DRC1) |= 2; + }else{ + MCHBAR32(MMARB1) |= (1 << 17); + } } - + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) + MCHBAR32(MMARB1 +4) |= 0x3000; /* Assign Virtual Channel ID 1 to VC1 */ reg32 = EPBAR32(EPVC1RCTL); reg32 &= ~(7 << 24); @@ -422,8 +439,13 @@ static void i945_setup_dmi_rcrb(void) /* Last but not least, some additional steps */ reg32 = MCHBAR32(FSBSNPCTL); - reg32 &= ~(0xff << 2); - reg32 |= (0xaa << 2); + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + reg32 &= 0xfc; + reg32 &= 0x0fc; + }else{ + reg32 &= ~(0xff << 2); + reg32 |= (0xaa << 2); + } MCHBAR32(FSBSNPCTL) = reg32; DMIBAR32(0x2c) = 0x86000040; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index e5974c9..ed44895 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -514,16 +514,27 @@ static struct device_operations gma_func1_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 }; +static const unsigned short i945_gma_func0_ids[] = { + 0x2772, + 0x27a2, + 0x27ae, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x2776, + 0x27a6, + 0 +}; static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 4011287..ce7a967 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -894,8 +894,13 @@ static void sdram_program_dram_width(struct sys_info * sysinfo) c1dramw = 0; } - MCHBAR16(C0DRAMW) = c0dramw; - MCHBAR16(C1DRAMW) = c1dramw; + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + MCHBAR16(C0DRAMW) = 0x55; + MCHBAR16(C1DRAMW) = 0; + }else{ + MCHBAR16(C0DRAMW) = c0dramw; + MCHBAR16(C1DRAMW) = c1dramw; + } } static void sdram_write_slew_rates(u32 offset, const u32 *slew_rate_table) @@ -1240,14 +1245,29 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Programming DLL Timings... \n"); - MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) ); - MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); - + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + MCHBAR16(DQSMT) &= 0xfff0; + MCHBAR16(DQSMT) |= 0x0c; + }else{ + MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) ); + MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0); + } /* We drive both channels with the same speed */ switch (sysinfo->memory_frequency) { case 400: chan0dll = 0x26262626; chan1dll=0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll=0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll=0x11111111; break; /* 667MHz */ + case 533: + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + chan0dll = 0x24242424; chan1dll=0x24242424; + }else{ + chan0dll = 0x22222222; chan1dll=0x22222222; + }break; /* 533MHz */ + case 667: + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + chan0dll = 0x25252525; chan1dll=0x25252525; + }else{ + chan0dll = 0x11111111; chan1dll=0x11111111; + } + break; /* 667MHz */ } for (i=0; i < 4; i++) { @@ -1292,15 +1312,20 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo) printk(BIOS_DEBUG, "Initializing System Memory IO... \n"); /* Enable Data Half Clock Pushout */ - reg8 = MCHBAR8(C0HCTC); - reg8 &= ~0x1f; - reg8 |= ( 1 << 0); - MCHBAR8(C0HCTC) = reg8; + if ((pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770)||(pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2778)){ + MCHBAR8(C0HCTC) = 1; + MCHBAR8(C1HCTC) = 1; + }else{ + reg8 = MCHBAR8(C0HCTC); + reg8 &= ~0x1f; + reg8 |= ( 1 << 0); + MCHBAR8(C0HCTC) = reg8; - reg8 = MCHBAR8(C1HCTC); - reg8 &= ~0x1f; - reg8 |= ( 1 << 0); - MCHBAR8(C1HCTC) = reg8; + reg8 = MCHBAR8(C1HCTC); + reg8 &= ~0x1f; + reg8 |= ( 1 << 0); + MCHBAR8(C1HCTC) = reg8; + } MCHBAR16(WDLLBYPMODE) &= ~( (1 << 9) | (1 << 6) | (1 << 4) | (1 << 3) | (1 << 1) ); MCHBAR16(WDLLBYPMODE) |= (1 << 8) | (1 << 7) | (1 << 5) | (1 << 2) | (1 << 0); @@ -2109,8 +2134,20 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) switch (sysinfo->memory_frequency) { case 400: clkcfg |= (2 << 4); break; - case 533: clkcfg |= (3 << 4); break; - case 667: clkcfg |= (4 << 4); break; + case 533: + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + clkcfg |= (2 << 4); + }else{ + clkcfg |= (3 << 4); + } + break; + case 667: + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + clkcfg |= (3 << 4); + }else{ + clkcfg |= (4 << 4); + } + break; default: die("Target Memory Frequency Error"); } @@ -2251,7 +2288,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */ @@ -2312,17 +2349,30 @@ static void sdram_pre_jedec_initialization(void) u32 reg32; reg32 = MCHBAR32(WCC); - reg32 &= 0x113ff3ff; - reg32 |= (4 << 29) | (3 << 25) | (1 << 10); - MCHBAR32(WCC) = reg32; + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770){ + reg32 &= 0xf3fff7ff; + reg32 |= (1 << 25) | (3 << 22) | (1 << 10); + MCHBAR32(WCC) = reg32; + MCHBAR32(MMARB0) |= (3 << 7)|(3 << 8); + MCHBAR32(MMARB1) |= (1 << 18)|(3 << 12); + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0xe4) & 0x2000 && pci_read_config8(PCI_DEV(0, 0x00,0), 0x54) & 8){ + MCHBAR32(MMARB1) &= ~(1 << 18); + MCHBAR32(C0DRC1) |= 2; + MCHBAR32(C1DRC1) |= 2; + } + }else{ + reg32 &= 0x113ff3ff; + reg32 |= (4 << 29) | (3 << 25) | (1 << 10); + MCHBAR32(WCC) = reg32; - MCHBAR32(SMVREFC) |= (1 << 6); + MCHBAR32(SMVREFC) |= (1 << 6); - MCHBAR32(MMARB0) &= ~(3 << 17); - MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); + MCHBAR32(MMARB0) &= ~(3 << 17); + MCHBAR32(MMARB0) |= (1 << 21) | (1 << 16); - MCHBAR32(MMARB1) &= ~(7 << 8); - MCHBAR32(MMARB1) |= (3 << 8); + MCHBAR32(MMARB1) &= ~(7 << 8); + MCHBAR32(MMARB1) |= (3 << 8); + } /* Adaptive Idle Timer Control */ MCHBAR32(C0AIT) = 0x000006c4; @@ -2603,31 +2653,36 @@ static void sdram_power_management(struct sys_info *sysinfo) reg8 |= (1 << 2); pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); -#ifdef C2_SELF_REFRESH_DISABLE - - if (integrated_graphics) { - printk(BIOS_DEBUG, "C2 self-refresh with IGD\n"); - MCHBAR16(MIPMC4) = 0x0468; - MCHBAR16(MIPMC5) = 0x046c; - MCHBAR16(MIPMC6) = 0x046c; - } else { - MCHBAR16(MIPMC4) = 0x6468; - MCHBAR16(MIPMC5) = 0x646c; - MCHBAR16(MIPMC6) = 0x646c; - } -#else - if (integrated_graphics) { - MCHBAR16(MIPMC4) = 0x04f8; - MCHBAR16(MIPMC5) = 0x04fc; - MCHBAR16(MIPMC6) = 0x04fc; - } else { - MCHBAR16(MIPMC4) = 0x64f8; - MCHBAR16(MIPMC5) = 0x64fc; - MCHBAR16(MIPMC6) = 0x64fc; - } - -#endif +if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) == 0x2770) { + MCHBAR16(MIPMC4) |= 0x6000; + MCHBAR16(MIPMC5) |= 0x6000; + MCHBAR16(MIPMC6) |= 0x6000; +}else{ + #ifdef C2_SELF_REFRESH_DISABLE + + if (integrated_graphics) { + printk(BIOS_DEBUG, "C2 self-refresh with IGD\n"); + MCHBAR16(MIPMC4) = 0x0468; + MCHBAR16(MIPMC5) = 0x046c; + MCHBAR16(MIPMC6) = 0x046c; + } else { + MCHBAR16(MIPMC4) = 0x6468; + MCHBAR16(MIPMC5) = 0x646c; + MCHBAR16(MIPMC6) = 0x646c; + } + #else + if (integrated_graphics) { + MCHBAR16(MIPMC4) = 0x04f8; + MCHBAR16(MIPMC5) = 0x04fc; + MCHBAR16(MIPMC6) = 0x04fc; + } else { + MCHBAR16(MIPMC4) = 0x64f8; + MCHBAR16(MIPMC5) = 0x64fc; + MCHBAR16(MIPMC6) = 0x64fc; + } + #endif +} reg32 = MCHBAR32(PMCFG); reg32 &= ~(3 << 17); reg32 |= (2 << 17); @@ -3027,6 +3082,7 @@ static void sdram_setup_processor_side(void) if (i945_silicon_revision() == 0) MCHBAR32(FSBPMC3) |= (1 << 2); + if (pci_read_config16(PCI_DEV(0, 0x00,0), 0x02) != 0x2770) MCHBAR8(0xb00) |= 1; if (i945_silicon_revision() == 0)

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coreboot-gerrit May 2015