coreboot-gerrit May 2015

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Patch set updated for coreboot: cca3cfc southbridge/amd: add support for Bolton FCH
by Felix Held 31 May '15

31 May '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9623 -gerrit commit cca3cfcbaa7c6afbda3c64710a23a7e9b4c8f26b Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun May 31 20:28:17 2015 +0200 southbridge/amd: add support for Bolton FCH The Bolton FCH needs different firmware files than the Hudson FCH. A small patch to vendorcode is probably needed to make the XHCI controller work. XHCI_DEVID in pci_devs.h is probably wrong for Hudson. Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/southbridge/amd/agesa/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/Kconfig | 13 +++++++++++-- src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h | 6 ++++-- src/southbridge/amd/agesa/hudson/amd_pci_int_types.h | 2 +- src/southbridge/amd/agesa/hudson/pci_devs.h | 11 +++++++++-- src/southbridge/amd/common/Makefile.inc | 1 + 6 files changed, 27 insertions(+), 7 deletions(-) diff --git a/src/southbridge/amd/agesa/Makefile.inc b/src/southbridge/amd/agesa/Makefile.inc index 4a09eff..7797ba4 100644 --- a/src/southbridge/amd/agesa/Makefile.inc +++ b/src/southbridge/amd/agesa/Makefile.inc @@ -17,5 +17,6 @@ # Foundation, Inc. # +subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += hudson subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += hudson diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 13dfecc..67bf606 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -17,6 +17,12 @@ ## Foundation, Inc. ## +config SOUTHBRIDGE_AMD_AGESA_BOLTON + bool + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_HARD_RESET + config SOUTHBRIDGE_AMD_AGESA_HUDSON bool select IOAPIC @@ -29,7 +35,7 @@ config SOUTHBRIDGE_AMD_AGESA_YANGTZE select HAVE_USBDEBUG_OPTIONS select HAVE_HARD_RESET -if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +if SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE config BOOTBLOCK_SOUTHBRIDGE_INIT string @@ -79,18 +85,21 @@ config HUDSON_GEC_FWM config HUDSON_XHCI_FWM_FILE string "XHCI firmware path and filename" + default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE string "IMC firmware path and filename" + default "3rdparty/blobs/southbridge/amd/bolton/imc.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE string "GEC firmware path and filename" + default "3rdparty/blobs/southbridge/amd/bolton/gec.bin" if SOUTHBRIDGE_AMD_AGESA_BOLTON default "3rdparty/blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON default "3rdparty/blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM @@ -213,7 +222,7 @@ config ACPI_ENABLE_THERMAL_ZONE bool default y -endif # SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE +endif # SOUTHBRIDGE_AMD_AGESA_BOLTON || SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE if SOUTHBRIDGE_AMD_AGESA_YANGTZE config AZ_PIN diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h index 1a56f18..db99561 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_defs.h @@ -25,7 +25,7 @@ * into the FCH PCI_INTR 0xC00/0xC01 interrupt * routing table */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define FCH_INT_TABLE_SIZE 0x54 #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define FCH_INT_TABLE_SIZE 0x42 @@ -55,7 +55,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) #define PIRQ_SD 0x17 /* SD */ #endif #define PIRQ_IMC0 0x20 /* IMC INT0 */ @@ -75,6 +75,8 @@ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_SD 0x42 /* SD 14h.7 */ +#endif +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define PIRQ_GPP0 0x50 /* GPP INT 0 */ #define PIRQ_GPP1 0x51 /* GPP INT 1 */ #define PIRQ_GPP2 0x52 /* GPP INT 2 */ diff --git a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h index 5174de6..6ab001c 100644 --- a/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h +++ b/src/southbridge/amd/agesa/hudson/amd_pci_int_types.h @@ -20,7 +20,7 @@ #ifndef AMD_PCI_INT_TYPES_H #define AMD_PCI_INT_TYPES_H -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) const char * intr_types[] = { [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index e34f249..e43c71e 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -28,6 +28,13 @@ #define XHCI_DEVID 0x7814 #define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) +#define XHCI2_DEV 0x10 +#define XHCI2_FUNC 1 +#define XHCI2_DEVID 0x7814 +#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC) +#endif + /* SATA */ #define SATA_DEV 0x11 #define SATA_FUNC 0 @@ -70,7 +77,7 @@ #define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) /* IDE */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define IDE_DEV 0x14 #define IDE_FUNC 1 # define IDE_DEVID 0x780C @@ -103,7 +110,7 @@ #define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) /* PCIe Ports */ -#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) #define SB_PCIE_DEV 0x15 #define SB_PCIE_PORT1_FUNC 0 #define SB_PCIE_PORT2_FUNC 1 diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc index 1f847cd..a5c5a5c 100644 --- a/src/southbridge/amd/common/Makefile.inc +++ b/src/southbridge/amd/common/Makefile.inc @@ -1,6 +1,7 @@ ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE) += amd_pci_util.c ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_AVALON) += amd_pci_util.c

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Patch set updated for coreboot: eb1fc4b hudson: reintroduce HUDSON_DISABLE_IMC option
by Felix Held 31 May '15

31 May '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8089 -gerrit commit eb1fc4b0365d8bc0c5755cfaca8bab1230ee5622 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun May 31 16:49:34 2015 +0200 hudson: reintroduce HUDSON_DISABLE_IMC option HUDSON_DISABLE_IMC was introduced in commit 1a59039c option gets used in commit 99799d66 for asus/f2a85-m option gets killed in commit 1b1b795f, but is still used in source agesa based boards (asus/f2a85-m and asus/f2a85-m_le) The HUDSON_DISABLE_IMC option is reintroduced to exclude the IMC firmware on boards where the fan control is done by the SIO/EC and not by the FCH. Defaulting HUDSON_IMC_FWM to n, making it depend on USE_BLOBS and explicitly sourcing it in the board Kconfig file does not work as expected; when we explicitly select HUDSON_IMC_FWM in the mainboard Kconfig and USE_BLOBS is n, we get a warning due to unmet dependencies, but the IMC firmware still gets included in CBFS. gizmo2 uses the FCH-integrated fan control; most other boards use the SIO/EC Change-Id: I448a0dc7c9fef504f89cfd192ca74172425fb3e0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/southbridge/amd/agesa/hudson/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 610e1fd..13dfecc 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -59,8 +59,13 @@ config HUDSON_XHCI_FWM help Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 +config HUDSON_DISABLE_IMC + bool + default n + config HUDSON_IMC_FWM bool "Add imc firmware" + depends on !HUDSON_DISABLE_IMC default y if USE_BLOBS help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

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New patch to review for coreboot: 3496a83 superiotool: detect the NCT5572D
by Felix Held 31 May '15

31 May '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10386 -gerrit commit 3496a8326441fb08fe9389dacd26d29549a5e042 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Fri Jul 11 18:50:39 2014 +0200 superiotool: detect the NCT5572D Change-Id: I99717072679a51deecd6934ce7fb4aeb45135cd6 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- util/superiotool/nuvoton.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/superiotool/nuvoton.c b/util/superiotool/nuvoton.c index bc95869..e759dad 100644 --- a/util/superiotool/nuvoton.c +++ b/util/superiotool/nuvoton.c @@ -148,7 +148,7 @@ static const struct superio_registers reg_table[] = { {0xff,0xff,0xf7,0xff,0xfb,0xcb,0xff,0xff,0xff, 0xff,0x00,0x00,0x00,0x00,0x70,0xff,EOT}}, {EOT}}}, - {0xb473, "NCT6775F (B)", { + {0xb473, "NCT6775F (B) / NCT5572D (B) (not all LDN supported)", { {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28, 0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT},

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Patch set updated for coreboot: 24a9bc3 Make DSDT a file in CBFS rather than embedding it into ramstage.
by Vladimir Serbinenko 31 May '15

31 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10385 -gerrit commit 24a9bc3761b228b6316d2872e76e8ec649406744 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 31 12:31:59 2015 +0200 Make DSDT a file in CBFS rather than embedding it into ramstage. Makes it cleaner by putting AML into separate file rather than having an array in C code. Change-Id: Ia5d6b50ad9dabdb97ed05c837dc3ccc48b8f490f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Makefile.inc | 14 ++++++------ src/arch/x86/Makefile.inc | 14 +----------- src/arch/x86/boot/acpi.c | 25 ++++++++++++++++------ src/mainboard/amd/serengeti_cheetah/Makefile.inc | 3 +++ src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 19 ++++++++++------ .../amd/serengeti_cheetah_fam10/Makefile.inc | 4 ++++ .../amd/serengeti_cheetah_fam10/acpi_tables.c | 21 ++++++++++-------- src/mainboard/iwill/dk8_htx/Makefile.inc | 4 ++++ src/mainboard/iwill/dk8_htx/acpi_tables.c | 22 +++++++++++-------- 9 files changed, 75 insertions(+), 51 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 49e1ba3..3e28709 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -169,15 +169,15 @@ endef ####################################################################### # Add handler to compile ACPI's ASL -define ramstage-objs_asl_template -$$(call src-to-obj,ramstage,$(1).asl): $(1).asl $(obj)/config.h +define asl_template +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-file = $(obj)/$(1).aml +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-type = raw +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-compression = none +cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml +$(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ - cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$@) - mv $$(basename $$(a)).hex $$(basename $$(a)).c - $(CC_ramstage) $$(CFLAGS_ramstage) $$(CPPFLAGS_ramstage) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c - # keep %.o: %.c rule from catching the temporary .c file after a make clean - mv $$(basename $$(a)).c $$(basename $$(a)).hex + cd $$(dir $$@); $(IASL) -p $$(notdir $$@) $$(notdir $$@) endef ####################################################################### diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 49caef5..5da5a4a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -262,19 +262,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt2.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt2.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt3.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt3.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt4.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt4.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt5.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl -endif +$(eval $(call asl_template,dsdt)) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c endif diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 4ce5ed6..9c75008 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -723,8 +723,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) } #endif -extern const unsigned char AmlCode[]; - unsigned long __attribute__ ((weak)) fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -741,13 +739,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *slic_file, *slic; acpi_header_t *ssdt; - acpi_header_t *dsdt; + acpi_header_t *dsdt_file, *dsdt; acpi_mcfg_t *mcfg; acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; - size_t slic_size; + size_t slic_size, dsdt_size; char oem_id[6], oem_table_id[8]; current = start; @@ -759,6 +757,21 @@ unsigned long write_acpi_tables(unsigned long start) if (fw) return fw; + dsdt_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/dsdt.aml", + CBFS_TYPE_RAW, &dsdt_size); + if (!dsdt_file) { + printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); + return current; + } + + if (dsdt_file->length > dsdt_size + || dsdt_file->length < sizeof (acpi_header_t) + || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { + printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); + return current; + } + slic_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/slic", CBFS_TYPE_RAW, &slic_size); @@ -805,7 +818,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT\n"); dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); if (dsdt->length >= sizeof(acpi_header_t)) { current += sizeof(acpi_header_t); @@ -816,7 +829,7 @@ unsigned long write_acpi_tables(unsigned long start) } current = (unsigned long) acpigen_get_current(); memcpy((char *)current, - (char *)&AmlCode + sizeof(acpi_header_t), + (char *)dsdt_file + sizeof(acpi_header_t), dsdt->length - sizeof(acpi_header_t)); current += dsdt->length - sizeof(acpi_header_t); diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc new file mode 100644 index 0000000..876b3ed --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc @@ -0,0 +1,3 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 168793e..14ef938 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -17,14 +17,11 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> +#include <cbfs.h> #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" #include "mainboard.h" -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -127,6 +124,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp unsigned long current; acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -139,6 +137,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; if(i<7) { @@ -152,17 +151,23 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: //8151 - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: continue; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; + memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc new file mode 100644 index 0000000..e826e81 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc @@ -0,0 +1,4 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) +$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 8c24528..cc932d2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -26,15 +26,11 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cbfs.h> #include "mb_sysconf.h" #include "mainboard.h" -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -136,6 +132,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, { acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -145,6 +142,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, change HCIN, and recalculate the checknum and add_table */ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; if(i<7) { @@ -158,18 +156,23 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); diff --git a/src/mainboard/iwill/dk8_htx/Makefile.inc b/src/mainboard/iwill/dk8_htx/Makefile.inc new file mode 100644 index 0000000..e826e81 --- /dev/null +++ b/src/mainboard/iwill/dk8_htx/Makefile.inc @@ -0,0 +1,4 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) +$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e1c5c80..834d1fe 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -20,11 +20,7 @@ #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" #include "mainboard.h" - -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; +#include <cbfs.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -134,6 +130,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp unsigned long current; acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -146,6 +143,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; uint8_t c; if(i<7) { @@ -159,19 +157,25 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: //8151 - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; + memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length);

1 0

Patch set updated for coreboot: 7da593e Make DSDT a file in CBFS rather than embedding it into ramstage.
by Vladimir Serbinenko 31 May '15

31 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10385 -gerrit commit 7da593e3af2275a2e812590ebca80030dcf34294 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 31 12:31:59 2015 +0200 Make DSDT a file in CBFS rather than embedding it into ramstage. Makes it cleaner by putting AML into separate file rather than having an array in C code. Change-Id: Ia5d6b50ad9dabdb97ed05c837dc3ccc48b8f490f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Makefile.inc | 14 ++++++------ src/arch/x86/Makefile.inc | 14 +----------- src/arch/x86/boot/acpi.c | 25 ++++++++++++++++------ src/mainboard/amd/serengeti_cheetah/Makefile.inc | 3 +++ src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 19 ++++++++++------ .../amd/serengeti_cheetah_fam10/Makefile.inc | 4 ++++ .../amd/serengeti_cheetah_fam10/acpi_tables.c | 21 ++++++++++-------- src/mainboard/iwill/dk8_htx/Makefile.inc | 4 ++++ src/mainboard/iwill/dk8_htx/acpi_tables.c | 16 ++++++-------- 9 files changed, 69 insertions(+), 51 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 49e1ba3..3e28709 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -169,15 +169,15 @@ endef ####################################################################### # Add handler to compile ACPI's ASL -define ramstage-objs_asl_template -$$(call src-to-obj,ramstage,$(1).asl): $(1).asl $(obj)/config.h +define asl_template +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-file = $(obj)/$(1).aml +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-type = raw +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-compression = none +cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml +$(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ - cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$@) - mv $$(basename $$(a)).hex $$(basename $$(a)).c - $(CC_ramstage) $$(CFLAGS_ramstage) $$(CPPFLAGS_ramstage) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c - # keep %.o: %.c rule from catching the temporary .c file after a make clean - mv $$(basename $$(a)).c $$(basename $$(a)).hex + cd $$(dir $$@); $(IASL) -p $$(notdir $$@) $$(notdir $$@) endef ####################################################################### diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 49caef5..5da5a4a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -262,19 +262,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt2.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt2.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt3.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt3.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt4.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt4.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt5.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl -endif +$(eval $(call asl_template,dsdt)) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c endif diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 4ce5ed6..9c75008 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -723,8 +723,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) } #endif -extern const unsigned char AmlCode[]; - unsigned long __attribute__ ((weak)) fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -741,13 +739,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *slic_file, *slic; acpi_header_t *ssdt; - acpi_header_t *dsdt; + acpi_header_t *dsdt_file, *dsdt; acpi_mcfg_t *mcfg; acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; - size_t slic_size; + size_t slic_size, dsdt_size; char oem_id[6], oem_table_id[8]; current = start; @@ -759,6 +757,21 @@ unsigned long write_acpi_tables(unsigned long start) if (fw) return fw; + dsdt_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/dsdt.aml", + CBFS_TYPE_RAW, &dsdt_size); + if (!dsdt_file) { + printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); + return current; + } + + if (dsdt_file->length > dsdt_size + || dsdt_file->length < sizeof (acpi_header_t) + || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { + printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); + return current; + } + slic_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/slic", CBFS_TYPE_RAW, &slic_size); @@ -805,7 +818,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT\n"); dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); if (dsdt->length >= sizeof(acpi_header_t)) { current += sizeof(acpi_header_t); @@ -816,7 +829,7 @@ unsigned long write_acpi_tables(unsigned long start) } current = (unsigned long) acpigen_get_current(); memcpy((char *)current, - (char *)&AmlCode + sizeof(acpi_header_t), + (char *)dsdt_file + sizeof(acpi_header_t), dsdt->length - sizeof(acpi_header_t)); current += dsdt->length - sizeof(acpi_header_t); diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc new file mode 100644 index 0000000..876b3ed --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc @@ -0,0 +1,3 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 168793e..14ef938 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -17,14 +17,11 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdk8_sysconf.h> +#include <cbfs.h> #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" #include "mainboard.h" -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -127,6 +124,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp unsigned long current; acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -139,6 +137,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; if(i<7) { @@ -152,17 +151,23 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: //8151 - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: continue; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; + memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc new file mode 100644 index 0000000..e826e81 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc @@ -0,0 +1,4 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) +$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 8c24528..cc932d2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -26,15 +26,11 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam10_sysconf.h> +#include <cbfs.h> #include "mb_sysconf.h" #include "mainboard.h" -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -136,6 +132,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, { acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -145,6 +142,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, change HCIN, and recalculate the checknum and add_table */ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; if(i<7) { @@ -158,18 +156,23 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); diff --git a/src/mainboard/iwill/dk8_htx/Makefile.inc b/src/mainboard/iwill/dk8_htx/Makefile.inc new file mode 100644 index 0000000..e826e81 --- /dev/null +++ b/src/mainboard/iwill/dk8_htx/Makefile.inc @@ -0,0 +1,4 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) +$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e1c5c80..61745d1 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -20,11 +20,7 @@ #include "northbridge/amd/amdk8/acpi.h" #include "mb_sysconf.h" #include "mainboard.h" - -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; +#include <cbfs.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -134,6 +130,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp unsigned long current; acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -146,6 +143,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; uint8_t c; if(i<7) { @@ -159,17 +157,17 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: //8151 - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; } memcpy(ssdtx, p, sizeof(acpi_header_t));

1 0

New patch to review for coreboot: 252ebbe Make DSDT a file in CBFS rather than embedding it into ramstage.
by Vladimir Serbinenko 31 May '15

31 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10385 -gerrit commit 252ebbee7f1e4377ec23891736455fa69722f5f7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 31 12:31:59 2015 +0200 Make DSDT a file in CBFS rather than embedding it into ramstage. Makes it cleaner by putting AML into separate file rather than having an array in C code. Change-Id: Ia5d6b50ad9dabdb97ed05c837dc3ccc48b8f490f Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- Makefile.inc | 14 ++++++------ src/arch/x86/Makefile.inc | 14 +----------- src/arch/x86/boot/acpi.c | 25 ++++++++++++++++------ src/mainboard/amd/serengeti_cheetah/Makefile.inc | 3 +++ src/mainboard/amd/serengeti_cheetah/acpi_tables.c | 18 ++++++++++------ .../amd/serengeti_cheetah_fam10/Makefile.inc | 4 ++++ .../amd/serengeti_cheetah_fam10/acpi_tables.c | 20 +++++++++-------- src/mainboard/iwill/dk8_htx/Makefile.inc | 4 ++++ src/mainboard/iwill/dk8_htx/acpi_tables.c | 10 +++++---- 9 files changed, 66 insertions(+), 46 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 49e1ba3..824f1d0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -169,15 +169,15 @@ endef ####################################################################### # Add handler to compile ACPI's ASL -define ramstage-objs_asl_template -$$(call src-to-obj,ramstage,$(1).asl): $(1).asl $(obj)/config.h +define asl_template +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-file = $(obj)/$(1).aml +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-type = raw +$(call strip_quotes,$(CONFIG_CBFS_PREFIX))/$(1).aml-compression = none +cbfs-files-y += $(call strip_quotes,$(CONFIG_CBFS_PREFIX))/dsdt.aml +$(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ - cd $$(dir $$@); $(IASL) -p $$(notdir $$@) -tc $$(notdir $$@) - mv $$(basename $$(a)).hex $$(basename $$(a)).c - $(CC_ramstage) $$(CFLAGS_ramstage) $$(CPPFLAGS_ramstage) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c - # keep %.o: %.c rule from catching the temporary .c file after a make clean - mv $$(basename $$(a)).c $$(basename $$(a)).hex + cd $$(dir $$@); $(IASL) -p $$(notdir $$@) $$(notdir $$@) endef ####################################################################### diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 49caef5..5da5a4a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -262,19 +262,7 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/reset.c endif ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/dsdt.asl -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt2.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt2.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt3.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt3.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt4.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt4.asl -endif -ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/ssdt5.asl),) -ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/ssdt5.asl -endif +$(eval $(call asl_template,dsdt)) ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c endif diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index 4ce5ed6..9c75008 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -723,8 +723,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt) } #endif -extern const unsigned char AmlCode[]; - unsigned long __attribute__ ((weak)) fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -741,13 +739,13 @@ unsigned long write_acpi_tables(unsigned long start) acpi_facs_t *facs; acpi_header_t *slic_file, *slic; acpi_header_t *ssdt; - acpi_header_t *dsdt; + acpi_header_t *dsdt_file, *dsdt; acpi_mcfg_t *mcfg; acpi_tcpa_t *tcpa; acpi_madt_t *madt; struct device *dev; unsigned long fw; - size_t slic_size; + size_t slic_size, dsdt_size; char oem_id[6], oem_table_id[8]; current = start; @@ -759,6 +757,21 @@ unsigned long write_acpi_tables(unsigned long start) if (fw) return fw; + dsdt_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/dsdt.aml", + CBFS_TYPE_RAW, &dsdt_size); + if (!dsdt_file) { + printk(BIOS_ERR, "No DSDT file, skipping ACPI tables\n"); + return current; + } + + if (dsdt_file->length > dsdt_size + || dsdt_file->length < sizeof (acpi_header_t) + || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { + printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); + return current; + } + slic_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/slic", CBFS_TYPE_RAW, &slic_size); @@ -805,7 +818,7 @@ unsigned long write_acpi_tables(unsigned long start) printk(BIOS_DEBUG, "ACPI: * DSDT\n"); dsdt = (acpi_header_t *) current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + memcpy(dsdt, dsdt_file, sizeof(acpi_header_t)); if (dsdt->length >= sizeof(acpi_header_t)) { current += sizeof(acpi_header_t); @@ -816,7 +829,7 @@ unsigned long write_acpi_tables(unsigned long start) } current = (unsigned long) acpigen_get_current(); memcpy((char *)current, - (char *)&AmlCode + sizeof(acpi_header_t), + (char *)dsdt_file + sizeof(acpi_header_t), dsdt->length - sizeof(acpi_header_t)); current += dsdt->length - sizeof(acpi_header_t); diff --git a/src/mainboard/amd/serengeti_cheetah/Makefile.inc b/src/mainboard/amd/serengeti_cheetah/Makefile.inc new file mode 100644 index 0000000..876b3ed --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah/Makefile.inc @@ -0,0 +1,3 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) diff --git a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c index 168793e..958128b 100644 --- a/src/mainboard/amd/serengeti_cheetah/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/acpi_tables.c @@ -21,10 +21,6 @@ #include "mb_sysconf.h" #include "mainboard.h" -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -127,6 +123,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp unsigned long current; acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -139,6 +136,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; if(i<7) { @@ -152,17 +150,23 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: //8151 - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: continue; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; + memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc new file mode 100644 index 0000000..e826e81 --- /dev/null +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Makefile.inc @@ -0,0 +1,4 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) +$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index 8c24528..5bc366c 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -30,11 +30,6 @@ #include "mb_sysconf.h" #include "mainboard.h" -extern const unsigned char AmlCode_ssdt2[]; -extern const unsigned char AmlCode_ssdt3[]; -extern const unsigned char AmlCode_ssdt4[]; -extern const unsigned char AmlCode_ssdt5[]; - unsigned long acpi_fill_madt(unsigned long current) { u32 gsi_base=0x18; @@ -136,6 +131,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, { acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -145,6 +141,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, change HCIN, and recalculate the checknum and add_table */ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; u8 c; if(i<7) { @@ -158,18 +155,23 @@ unsigned long mainboard_write_acpi_tables(unsigned long current, ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; } + p = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, + file_name, + CBFS_TYPE_RAW, &p_size); + if (!p || p_size < sizeof(acpi_header_t)) + continue; memcpy(ssdtx, p, sizeof(acpi_header_t)); current += ssdtx->length; memcpy(ssdtx, p, ssdtx->length); diff --git a/src/mainboard/iwill/dk8_htx/Makefile.inc b/src/mainboard/iwill/dk8_htx/Makefile.inc new file mode 100644 index 0000000..e826e81 --- /dev/null +++ b/src/mainboard/iwill/dk8_htx/Makefile.inc @@ -0,0 +1,4 @@ +$(eval $(call asl_template,ssdt2)) +$(eval $(call asl_template,ssdt3)) +$(eval $(call asl_template,ssdt4)) +$(eval $(call asl_template,ssdt5)) diff --git a/src/mainboard/iwill/dk8_htx/acpi_tables.c b/src/mainboard/iwill/dk8_htx/acpi_tables.c index e1c5c80..8075b22 100644 --- a/src/mainboard/iwill/dk8_htx/acpi_tables.c +++ b/src/mainboard/iwill/dk8_htx/acpi_tables.c @@ -134,6 +134,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp unsigned long current; acpi_header_t *ssdtx; const void *p; + size_t p_size; int i; @@ -146,6 +147,7 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink + const char *file_name; if((sysconf.pci1234[i] & 1) != 1 ) continue; uint8_t c; if(i<7) { @@ -159,17 +161,17 @@ unsigned long mainboard_write_acpi_tables(unsigned long start, acpi_rsdp_t *rsdp ssdtx = (acpi_header_t *)current; switch(sysconf.hcid[i]) { case 1: //8132 - p = &AmlCode_ssdt2; + file_name = CONFIG_CBFS_PREFIX "/ssdt2.aml"; break; case 2: //8151 - p = &AmlCode_ssdt3; + file_name = CONFIG_CBFS_PREFIX "/ssdt3.aml"; break; case 3: //8131 - p = &AmlCode_ssdt4; + file_name = CONFIG_CBFS_PREFIX "/ssdt4.aml"; break; default: //HTX no io apic - p = &AmlCode_ssdt5; + file_name = CONFIG_CBFS_PREFIX "/ssdt5.aml"; break; } memcpy(ssdtx, p, sizeof(acpi_header_t));

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New patch to review for coreboot: da4bdc9 amd/torpedo: Remove stale ssdt*.asl
by Vladimir Serbinenko 31 May '15

31 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10384 -gerrit commit da4bdc9f6d56138a00bd987e39ba40196c2740e7 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 31 12:05:35 2015 +0200 amd/torpedo: Remove stale ssdt*.asl They're not referenced in the code anywhere. Change-Id: I4805e11523ca7d3cffb484c719f479b7a6ba3e15 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/amd/torpedo/acpi/ssdt2.asl | 83 ------------------------------- src/mainboard/amd/torpedo/acpi/ssdt3.asl | 83 ------------------------------- src/mainboard/amd/torpedo/acpi/ssdt4.asl | 83 ------------------------------- src/mainboard/amd/torpedo/acpi/ssdt5.asl | 84 -------------------------------- 4 files changed, 333 deletions(-) diff --git a/src/mainboard/amd/torpedo/acpi/ssdt2.asl b/src/mainboard/amd/torpedo/acpi/ssdt2.asl deleted file mode 100644 index 3367a06..0000000 --- a/src/mainboard/amd/torpedo/acpi/ssdt2.asl +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci2_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/torpedo/acpi/ssdt3.asl b/src/mainboard/amd/torpedo/acpi/ssdt3.asl deleted file mode 100644 index 77c7448..0000000 --- a/src/mainboard/amd/torpedo/acpi/ssdt3.asl +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci3_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/torpedo/acpi/ssdt4.asl b/src/mainboard/amd/torpedo/acpi/ssdt4.asl deleted file mode 100644 index 84dfbfa..0000000 --- a/src/mainboard/amd/torpedo/acpi/ssdt4.asl +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci4_hc.asl" - } - } - -} diff --git a/src/mainboard/amd/torpedo/acpi/ssdt5.asl b/src/mainboard/amd/torpedo/acpi/ssdt5.asl deleted file mode 100644 index f47bdaa..0000000 --- a/src/mainboard/amd/torpedo/acpi/ssdt5.asl +++ /dev/null @@ -1,84 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - - -DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-FAM10", "AMDACPI", 100925440) -{ - Scope (_SB) - { - External (DADD, MethodObj) - External (GHCE, MethodObj) - External (GHCN, MethodObj) - External (GHCL, MethodObj) - External (GHCD, MethodObj) - External (GNUS, MethodObj) - External (GIOR, MethodObj) - External (GMEM, MethodObj) - External (GWBN, MethodObj) - External (GBUS, MethodObj) - - External (PICF) - - External (\_SB.PCI0.LNKA, DeviceObj) - External (\_SB.PCI0.LNKB, DeviceObj) - External (\_SB.PCI0.LNKC, DeviceObj) - External (\_SB.PCI0.LNKD, DeviceObj) - - Device (PCIX) - { - - // BUS ? Second HT Chain - Name (HCIN, 0xcc) // HC2 0x01 - - Name (_UID, 0xdd) // HC 0x03 - - Name (_HID, "PNP0A03") - - Method (_ADR, 0, NotSerialized) //Fake bus should be 0 - { - Return (DADD(GHCN(HCIN), 0x00000000)) - } - - Method (_BBN, 0, NotSerialized) - { - Return (GBUS (GHCN(HCIN), GHCL(HCIN))) - } - - Method (_STA, 0, NotSerialized) - { - Return (\_SB.GHCE(HCIN)) - } - - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { }) - Store( GHCN(HCIN), Local4) - Store( GHCL(HCIN), Local5) - - Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1) - Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2) - Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3) - Return (Local3) - } - - #include "acpi/pci5_hc.asl" - } - } - -}

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New patch to review for coreboot: bff2760 SLIC: Check SLIC signature.
by Vladimir Serbinenko 31 May '15

31 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10383 -gerrit commit bff2760da19b6df3c4bdff583d1bd9ecf45c5501 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun May 31 11:32:09 2015 +0200 SLIC: Check SLIC signature. Change-Id: I79fd4d17b534274b1e84bc97ca5a2a6ee55e3114 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/acpi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c index a7a638f..4ce5ed6 100644 --- a/src/arch/x86/boot/acpi.c +++ b/src/arch/x86/boot/acpi.c @@ -762,8 +762,10 @@ unsigned long write_acpi_tables(unsigned long start) slic_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/slic", CBFS_TYPE_RAW, &slic_size); - if (slic_file && (slic_file->length > slic_size - || slic_file->length < sizeof (acpi_header_t))) { + if (slic_file + && (slic_file->length > slic_size + || slic_file->length < sizeof (acpi_header_t) + || memcmp(slic_file->signature, "SLIC", 4) != 0)) { slic_file = 0; }

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Patch set updated for coreboot: 3514086 lenovo: Hide SMBIOS config
by Vladimir Serbinenko 31 May '15

31 May '15

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7055 -gerrit commit 3514086b6c92f913593af63a9a88e6b22997c819 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 30 23:08:26 2015 +0200 lenovo: Hide SMBIOS config It's derived from EEPROM on Lenovo machines and not from user config which is ignored. Change-Id: I54fb76a3160e47cd36d33d2937c4bfaddcd36a69 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/Kconfig | 8 ++++++++ src/arch/x86/boot/smbios.c | 3 +++ src/drivers/i2c/Kconfig | 1 + src/drivers/i2c/at24rf08c/Kconfig | 7 +++++++ src/drivers/i2c/at24rf08c/lenovo_serials.c | 5 +++++ 5 files changed, 24 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index edcafe8..04619b5 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -586,9 +586,14 @@ config GENERATE_SMBIOS_TABLES If unsure, say Y. +config SMBIOS_PROVIDED_BY_MOBO + bool + default n + config MAINBOARD_SERIAL_NUMBER string "SMBIOS Serial Number" depends on GENERATE_SMBIOS_TABLES + depends on !SMBIOS_PROVIDED_BY_MOBO default "123456789" help The Serial Number to store in SMBIOS structures. @@ -596,6 +601,7 @@ config MAINBOARD_SERIAL_NUMBER config MAINBOARD_VERSION string "SMBIOS Version Number" depends on GENERATE_SMBIOS_TABLES + depends on !SMBIOS_PROVIDED_BY_MOBO default "1.0" help The Version Number to store in SMBIOS structures. @@ -603,6 +609,7 @@ config MAINBOARD_VERSION config MAINBOARD_SMBIOS_MANUFACTURER string "SMBIOS Manufacturer" depends on GENERATE_SMBIOS_TABLES + depends on !SMBIOS_PROVIDED_BY_MOBO default MAINBOARD_VENDOR help Override the default Manufacturer stored in SMBIOS structures. @@ -610,6 +617,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER config MAINBOARD_SMBIOS_PRODUCT_NAME string "SMBIOS Product name" depends on GENERATE_SMBIOS_TABLES + depends on !SMBIOS_PROVIDED_BY_MOBO default MAINBOARD_PART_NUMBER help Override the default Product name stored in SMBIOS structures. diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 11c2d1c..6260b0f 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -281,6 +281,8 @@ static int smbios_write_type0(unsigned long *current, int handle) return len; } +#if !CONFIG_SMBIOS_PROVIDED_BY_MOBO + const char *__attribute__((weak)) smbios_mainboard_serial_number(void) { return CONFIG_MAINBOARD_SERIAL_NUMBER; @@ -305,6 +307,7 @@ void __attribute__((weak)) smbios_mainboard_set_uuid(u8 *uuid) { /* leave all zero */ } +#endif #ifdef CONFIG_MAINBOARD_FAMILY const char *smbios_mainboard_family(void) diff --git a/src/drivers/i2c/Kconfig b/src/drivers/i2c/Kconfig index 1949fa6d..2831c3f 100644 --- a/src/drivers/i2c/Kconfig +++ b/src/drivers/i2c/Kconfig @@ -1,6 +1,7 @@ source src/drivers/i2c/adm1026/Kconfig source src/drivers/i2c/adm1027/Kconfig source src/drivers/i2c/adt7463/Kconfig +source src/drivers/i2c/at24rf08c/Kconfig source src/drivers/i2c/i2cmux/Kconfig source src/drivers/i2c/i2cmux2/Kconfig source src/drivers/i2c/lm63/Kconfig diff --git a/src/drivers/i2c/at24rf08c/Kconfig b/src/drivers/i2c/at24rf08c/Kconfig new file mode 100644 index 0000000..e8ee986 --- /dev/null +++ b/src/drivers/i2c/at24rf08c/Kconfig @@ -0,0 +1,7 @@ +if VENDOR_LENOVO + +config SMBIOS_PROVIDED_BY_MOBO + bool + default y + +endif diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index a5f1889..6595dd3 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -213,3 +213,8 @@ const char *smbios_mainboard_bios_version(void) s = strconcat("CBET4000 ", coreboot_version); return s; } + +const char *smbios_mainboard_manufacturer(void) +{ + return "LENOVO"; +}

1 0

Patch merged into coreboot/master: 72ee183 autoport: Update documentation to mention runtime prerequisites
by gerrit＠coreboot.org 31 May '15

31 May '15

the following patch was just integrated into master: commit 72ee183c384a759712f256f5f4faa7394bcea9ec Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri May 29 20:40:55 2015 +0200 autoport: Update documentation to mention runtime prerequisites Change-Id: I3b5fe953fa0e00fb827b66963d69f32d63a07b16 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/10369 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> See http://review.coreboot.org/10369 for details. -gerrit

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coreboot-gerrit May 2015