May 2015 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: 8bae6d4 scan-bus fam10 ht test [NOTFORMERGE]
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10346 -gerrit commit 8bae6d4bd6073d3d09d5ed754d5111e60e77d8da Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu May 28 05:04:21 2015 +0300 scan-bus fam10 ht test [NOTFORMERGE] Change-Id: I3abde7375ae14ac622e9a8e068135fb1f868b116 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device.c | 29 +++-- src/device/hypertransport.c | 22 ++-- src/device/pci_device.c | 138 ++++++++++----------- src/device/pciexp_device.c | 11 +- src/device/pcix_device.c | 6 +- src/device/root_device.c | 77 +++++++----- src/drivers/i2c/i2cmux/i2cmux.c | 7 +- src/drivers/i2c/i2cmux2/i2cmux2.c | 7 +- src/include/device/device.h | 10 +- src/include/device/hypertransport.h | 5 +- src/include/device/pci.h | 13 +- src/include/device/pciexp.h | 7 +- src/include/device/pcix.h | 5 +- src/mainboard/emulation/qemu-i440fx/northbridge.c | 5 +- src/mainboard/lippert/frontrunner/devicetree.cb | 6 +- src/northbridge/amd/agesa/family10/northbridge.c | 19 +-- src/northbridge/amd/agesa/family14/northbridge.c | 3 +- src/northbridge/amd/agesa/family15/northbridge.c | 20 +-- src/northbridge/amd/agesa/family15rl/northbridge.c | 3 +- src/northbridge/amd/agesa/family15tn/northbridge.c | 3 +- src/northbridge/amd/agesa/family16kb/northbridge.c | 3 +- src/northbridge/amd/amdfam10/northbridge.c | 35 +++--- src/northbridge/amd/amdk8/northbridge.c | 34 +++-- src/northbridge/amd/pi/00630F01/northbridge.c | 3 +- src/northbridge/amd/pi/00730F01/northbridge.c | 3 +- src/northbridge/intel/i3100/pciexp_porta.c | 5 +- src/northbridge/intel/i3100/pciexp_porta_ep80579.c | 5 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/vx800/lpc.c | 2 +- src/northbridge/via/vx900/lpc.c | 2 +- src/northbridge/via/vx900/traf_ctrl.c | 5 +- src/soc/intel/baytrail/pcie.c | 4 +- src/soc/intel/baytrail/southcluster.c | 2 +- src/soc/intel/broadwell/lpc.c | 2 +- src/soc/intel/broadwell/smbus.c | 2 +- src/soc/intel/fsp_baytrail/southcluster.c | 2 +- src/southbridge/amd/agesa/hudson/lpc.c | 2 +- src/southbridge/amd/agesa/hudson/sm.c | 2 +- src/southbridge/amd/amd8111/acpi.c | 2 +- src/southbridge/amd/amd8111/lpc.c | 2 +- src/southbridge/amd/amd8111/smbus.c | 2 +- src/southbridge/amd/amd8111/usb.c | 2 - src/southbridge/amd/amd8131/bridge.c | 16 ++- src/southbridge/amd/amd8132/bridge.c | 17 ++- src/southbridge/amd/cimx/sb700/late.c | 2 +- src/southbridge/amd/cimx/sb800/late.c | 2 +- src/southbridge/amd/cimx/sb900/late.c | 2 +- src/southbridge/amd/cs5535/cs5535.c | 1 - src/southbridge/amd/cs5536/cs5536.c | 9 +- src/southbridge/amd/pi/hudson/lpc.c | 2 +- src/southbridge/amd/pi/hudson/sm.c | 2 +- src/southbridge/amd/sb600/lpc.c | 2 +- src/southbridge/amd/sb600/sm.c | 2 +- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb800/lpc.c | 2 +- src/southbridge/amd/sb800/sm.c | 2 +- src/southbridge/broadcom/bcm5785/lpc.c | 2 +- src/southbridge/broadcom/bcm5785/sb_pci_main.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 1 - src/southbridge/intel/bd82x6x/me_8.x.c | 1 - src/southbridge/intel/bd82x6x/pcie.c | 7 +- src/southbridge/intel/bd82x6x/smbus.c | 2 +- src/southbridge/intel/esb6300/lpc.c | 2 +- src/southbridge/intel/esb6300/smbus.c | 2 +- src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me.c | 1 - src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 1 - src/southbridge/intel/fsp_rangeley/lpc.c | 2 +- src/southbridge/intel/fsp_rangeley/smbus.c | 2 +- src/southbridge/intel/i3100/lpc.c | 2 +- src/southbridge/intel/i3100/pciexp_portb.c | 5 +- src/southbridge/intel/i3100/smbus.c | 2 +- src/southbridge/intel/i82371eb/isa.c | 2 +- src/southbridge/intel/i82371eb/smbus.c | 2 +- src/southbridge/intel/i82801ax/lpc.c | 2 +- src/southbridge/intel/i82801ax/smbus.c | 2 +- src/southbridge/intel/i82801bx/lpc.c | 2 +- src/southbridge/intel/i82801bx/smbus.c | 2 +- src/southbridge/intel/i82801cx/lpc.c | 2 +- src/southbridge/intel/i82801dx/lpc.c | 2 +- src/southbridge/intel/i82801ex/lpc.c | 2 +- src/southbridge/intel/i82801ex/smbus.c | 2 +- src/southbridge/intel/i82801gx/lpc.c | 2 +- src/southbridge/intel/i82801gx/smbus.c | 2 +- src/southbridge/intel/i82801ix/lpc.c | 2 +- src/southbridge/intel/i82801ix/pcie.c | 7 +- src/southbridge/intel/i82801ix/smbus.c | 2 +- src/southbridge/intel/ibexpeak/lpc.c | 2 +- src/southbridge/intel/ibexpeak/me.c | 1 - src/southbridge/intel/ibexpeak/smbus.c | 2 +- src/southbridge/intel/lynxpoint/lpc.c | 2 +- src/southbridge/intel/lynxpoint/smbus.c | 2 +- src/southbridge/intel/sch/lpc.c | 2 +- src/southbridge/intel/sch/smbus.c | 2 +- src/southbridge/nvidia/ck804/lpc.c | 2 +- src/southbridge/nvidia/ck804/smbus.c | 2 +- src/southbridge/nvidia/mcp55/lpc.c | 2 +- src/southbridge/nvidia/mcp55/smbus.c | 2 +- src/southbridge/rdc/r8610/r8610.c | 1 - src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 6 +- src/superio/smsc/lpc47b397/superio.c | 1 - 105 files changed, 350 insertions(+), 340 deletions(-) diff --git a/src/device/device.c b/src/device/device.c index 35bb6e2..6bdeae1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -913,25 +913,22 @@ int reset_bus(struct bus *bus) * required, reset the bus and scan it again. * * @param busdev Pointer to the bus device. - * @param max Current bus number. - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int scan_bus(struct device *busdev, unsigned int max) +static void scan_bus(struct device *busdev) { - unsigned int new_max; int do_scan_bus; - if (!busdev || !busdev->enabled || !busdev->ops || - !busdev->ops->scan_bus) { - return max; - } + if (!busdev->enabled) + return; + + printk(BIOS_SPEW, "%s scanning...\n", dev_path(busdev)); post_log_path(busdev); do_scan_bus = 1; while (do_scan_bus) { struct bus *link; - new_max = busdev->ops->scan_bus(busdev, max); + busdev->ops->scan_bus(busdev); do_scan_bus = 0; for (link = busdev->link_list; link; link = link->next) { if (link->reset_needed) { @@ -942,7 +939,17 @@ unsigned int scan_bus(struct device *busdev, unsigned int max) } } } - return new_max; +} + +void scan_bridges(struct bus *bus) +{ + struct device *child; + + for (child = bus->children; child; child = child->sibling) { + if (!child->ops || !child->ops->scan_bus) + continue; + scan_bus(child); + } } /** @@ -986,7 +993,7 @@ void dev_enumerate(void) printk(BIOS_ERR, "dev_root missing scan_bus operation"); return; } - scan_bus(root, 0); + scan_bus(root); post_log_clear(); printk(BIOS_INFO, "done\n"); } diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index a15a021..584ac78 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -249,7 +249,7 @@ static void ht_collapse_early_enumeration(struct bus *bus, } unsigned int hypertransport_scan_chain(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max, + unsigned max_devfn, unsigned *ht_unitid_base, unsigned offset_unitid) { @@ -474,9 +474,7 @@ end_of_chain: last_func->sibling = old_devices; } - /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7, max); - return max; + return next_unitid; } /** @@ -490,21 +488,23 @@ end_of_chain: * @param bus TODO * @param min_devfn TODO * @param max_devfn TODO - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate busses. */ -static unsigned int hypertransport_scan_chain_x(struct bus *bus, - unsigned int min_devfn, unsigned int max_devfn, unsigned int max) +static void hypertransport_scan_chain_x(struct bus *bus, + unsigned int min_devfn, unsigned int max_devfn) { unsigned int ht_unitid_base[4]; unsigned int offset_unitid = 1; - return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, + + unsigned int next_unitid = hypertransport_scan_chain(bus, min_devfn, max_devfn, ht_unitid_base, offset_unitid); + + /* Now that nothing is overlapping it is safe to scan the children. */ + pci_scan_bus(bus, 0x00, ((next_unitid - 1) << 3) | 7); } -unsigned int ht_scan_bridge(struct device *dev, unsigned int max) +void ht_scan_bridge(struct device *dev) { - return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x); + do_pci_scan_bridge(dev, hypertransport_scan_chain_x); } /** Default device operations for hypertransport bridges */ diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 4651258..6332209 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1074,21 +1074,15 @@ unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev) * Determine the existence of devices and bridges on a PCI bus. If there are * bridges on the bus, recursively scan the buses behind the bridges. * - * This function is the default scan_bus() method for the root device - * 'dev_root'. - * * @param bus Pointer to the bus structure. * @param min_devfn Minimum devfn to look at in the scan, usually 0x00. * @param max_devfn Maximum devfn to look at in the scan, usually 0xff. - * @param max Current bus number. - * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, - unsigned max_devfn, unsigned int max) +void pci_scan_bus(struct bus *bus, unsigned min_devfn, + unsigned max_devfn) { unsigned int devfn; struct device *old_devices; - struct device *child; printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary); @@ -1149,17 +1143,67 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, * For all children that implement scan_bus() (i.e. bridges) * scan the bus behind that child. */ - for (child = bus->children; child; child = child->sibling) - max = scan_bus(child, max); + + scan_bridges(bus); /* * We've scanned the bus and so we know all about what's on the other * side of any bridges that may be on this bus plus any devices. * Return how far we've got finding sub-buses. */ - printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max); post_code(0x55); - return max; +} + +typedef enum { + PCI_ROUTE_CLOSE, + PCI_ROUTE_SCAN, + PCI_ROUTE_FINAL, +} scan_state; + +static void pci_bridge_route(struct bus *link, scan_state state) +{ + struct device *dev = link->dev; + struct bus *parent = dev->bus; + u32 reg, buses = 0; + + if (state == PCI_ROUTE_SCAN) { + link->secondary = parent->subordinate + 1; + link->subordinate = link->secondary; + } + + if (state == PCI_ROUTE_CLOSE) { + buses |= 0xfeff << 8; + } else if (state == PCI_ROUTE_SCAN) { + buses |= ((u32) link->secondary & 0xff) << 8; + buses |= 0xff << 16; /* MAX PCI_BUS number here */ + } else if (state == PCI_ROUTE_FINAL) { + buses |= parent->secondary & 0xff; + buses |= ((u32) link->secondary & 0xff) << 8; + buses |= ((u32) link->subordinate & 0xff) << 16; + } + + if (state == PCI_ROUTE_SCAN) { + /* Clear all status bits and turn off memory, I/O and master enables. */ + link->bridge_cmd = pci_read_config16(dev, PCI_COMMAND); + pci_write_config16(dev, PCI_COMMAND, 0x0000); + pci_write_config16(dev, PCI_STATUS, 0xffff); + } + + /* + * Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is not + * correctly configured. + */ + + reg = pci_read_config32(dev, PCI_PRIMARY_BUS); + reg &= 0xff000000; + reg |= buses; + pci_write_config32(dev, PCI_PRIMARY_BUS, reg); + + if (state == PCI_ROUTE_FINAL) { + pci_write_config16(dev, PCI_COMMAND, link->bridge_cmd); + parent->subordinate = link->subordinate; + } } /** @@ -1171,19 +1215,14 @@ unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, * This function is the default scan_bus() method for PCI bridge devices. * * @param dev Pointer to the bridge device. - * @param max The highest bus number assigned up to now. * @param do_scan_bus TODO - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, - unsigned int (*do_scan_bus) (struct bus * bus, +void do_pci_scan_bridge(struct device *dev, + void (*do_scan_bus) (struct bus * bus, unsigned min_devfn, - unsigned max_devfn, - unsigned int max)) + unsigned max_devfn)) { struct bus *bus; - u32 buses; - u16 cr; printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev)); @@ -1199,50 +1238,11 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, bus = dev->link_list; - /* - * Set up the primary, secondary and subordinate bus numbers. We have - * no idea how many buses are behind this bridge yet, so we set the - * subordinate bus number to 0xff for the moment. - */ - bus->secondary = ++max; - bus->subordinate = 0xff; - - /* Clear all status bits and turn off memory, I/O and master enables. */ - cr = pci_read_config16(dev, PCI_COMMAND); - pci_write_config16(dev, PCI_COMMAND, 0x0000); - pci_write_config16(dev, PCI_STATUS, 0xffff); - - /* - * Read the existing primary/secondary/subordinate bus - * number configuration. - */ - buses = pci_read_config32(dev, PCI_PRIMARY_BUS); - - /* - * Configure the bus numbers for this bridge: the configuration - * transactions will not be propagated by the bridge if it is not - * correctly configured. - */ - buses &= 0xff000000; - buses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(bus->secondary) << 8) | - ((unsigned int)(bus->subordinate) << 16)); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - - /* Now we can scan all subordinate buses (those behind the bridge). */ - max = do_scan_bus(bus, 0x00, 0xff, max); + pci_bridge_route(bus, PCI_ROUTE_SCAN); - /* - * We know the number of buses behind this bridge. Set the subordinate - * bus number to its real value. - */ - bus->subordinate = max; - buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16); - pci_write_config32(dev, PCI_PRIMARY_BUS, buses); - pci_write_config16(dev, PCI_COMMAND, cr); + do_scan_bus(bus, 0x00, 0xff); - printk(BIOS_SPEW, "%s returns max %d\n", __func__, max); - return max; + pci_bridge_route(bus, PCI_ROUTE_FINAL); } /** @@ -1254,12 +1254,10 @@ unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max, * This function is the default scan_bus() method for PCI bridge devices. * * @param dev Pointer to the bridge device. - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate buses. */ -unsigned int pci_scan_bridge(struct device *dev, unsigned int max) +void pci_scan_bridge(struct device *dev) { - return do_pci_scan_bridge(dev, max, pci_scan_bus); + do_pci_scan_bridge(dev, pci_scan_bus); } /** @@ -1268,13 +1266,11 @@ unsigned int pci_scan_bridge(struct device *dev, unsigned int max) * This function is the default scan_bus() method for PCI domains. * * @param dev Pointer to the domain. - * @param max The highest bus number assigned up to now. - * @return The maximum bus number found, after scanning all subordinate busses. */ -unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +void pci_domain_scan_bus(device_t dev) { - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max); - return max; + struct bus *link = dev->link_list; + pci_scan_bus(link, PCI_DEVFN(0, 0), 0xff); } /** diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index f6127b2..ee24456 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -416,12 +416,12 @@ static void pciexp_tune_dev(device_t dev) #endif } -unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max) +void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn) { device_t child; - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); for (child = bus->children; child; child = child->sibling) { if ((child->path.pci.devfn < min_devfn) || @@ -430,12 +430,11 @@ unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, } pciexp_tune_dev(child); } - return max; } -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max) +void pciexp_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); + do_pci_scan_bridge(dev, pciexp_scan_bus); } /** Default device operations for PCI Express bridges */ diff --git a/src/device/pcix_device.c b/src/device/pcix_device.c index cfa2f91..7ed64df 100644 --- a/src/device/pcix_device.c +++ b/src/device/pcix_device.c @@ -112,12 +112,12 @@ const char *pcix_speed(u16 sstatus) return result; } -unsigned int pcix_scan_bridge(device_t dev, unsigned int max) +void pcix_scan_bridge(device_t dev) { unsigned int pos; u16 sstatus; - max = do_pci_scan_bridge(dev, max, pci_scan_bus); + do_pci_scan_bridge(dev, pci_scan_bus); /* Find the PCI-X capability. */ pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); @@ -129,8 +129,6 @@ unsigned int pcix_scan_bridge(device_t dev, unsigned int max) /* Print the PCI-X bus speed. */ printk(BIOS_DEBUG, "PCI: %02x: %s\n", dev->link_list->secondary, pcix_speed(sstatus)); - - return max; } /** Default device operations for PCI-X bridges */ diff --git a/src/device/root_device.c b/src/device/root_device.c index 1ec6f7f..0185275 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -44,57 +44,67 @@ const char mainboard_name[] = CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_ * debug device. Those virtual devices have to be listed in the config * file under some static bus in order to be enumerated at run time. * - * This function is the default scan_bus() method for the root device and - * LPC bridges. - * * @param bus Pointer to the device to which the static buses are attached to. - * @param max Maximum bus number currently used before scanning. - * @return The largest bus number used. */ -static int smbus_max = 0; -unsigned int scan_static_bus(device_t bus, unsigned int max) + +static void scan_static_bus(device_t bus) { device_t child; struct bus *link; - printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); - for (link = bus->link_list; link; link = link->next) { - /* For SMBus bus enumerate. */ - child = link->children; - - if (child && child->path.type == DEVICE_PATH_I2C) - link->secondary = ++smbus_max; - for (child = link->children; child; child = child->sibling) { + if (child->chip_ops && child->chip_ops->enable_dev) child->chip_ops->enable_dev(child); if (child->ops && child->ops->enable) child->ops->enable(child); - if (child->path.type == DEVICE_PATH_I2C) { - printk(BIOS_DEBUG, "smbus: %s[%d]->", - dev_path(child->bus->dev), - child->bus->link_num); - } printk(BIOS_DEBUG, "%s %s\n", dev_path(child), child->enabled ? "enabled" : "disabled"); } } +} + +void scan_lpc_bus(device_t bus) +{ + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + + scan_static_bus(bus); + + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); +} + +void scan_smbus(device_t bus) +{ + device_t child; + struct bus *link; + static int smbus_max = 0; + + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); for (link = bus->link_list; link; link = link->next) { + + link->secondary = ++smbus_max; + for (child = link->children; child; child = child->sibling) { - if (!child->ops || !child->ops->scan_bus) - continue; - printk(BIOS_SPEW, "%s scanning...\n", dev_path(child)); - max = scan_bus(child, max); + + if (child->chip_ops && child->chip_ops->enable_dev) + child->chip_ops->enable_dev(child); + + if (child->ops && child->ops->enable) + child->ops->enable(child); + + printk(BIOS_DEBUG, "smbus: %s[%d]->", dev_path(child->bus->dev), + child->bus->link_num); + + printk(BIOS_DEBUG, "%s %s\n", dev_path(child), + child->enabled ? "enabled" : "disabled"); } } printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); - - return max; } /** @@ -103,12 +113,19 @@ unsigned int scan_static_bus(device_t bus, unsigned int max) * This function is the default scan_bus() method of the root device. * * @param root The root device structure. - * @param max The current bus number scanned so far, usually 0x00. - * @return The largest bus number used. */ -static unsigned int root_dev_scan_bus(device_t root, unsigned int max) +static void root_dev_scan_bus(device_t bus) { - return scan_static_bus(root, max); + struct bus *link; + + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); + + scan_static_bus(bus); + + for (link = bus->link_list; link; link = link->next) + scan_bridges(link); + + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } static void root_dev_reset(struct bus *bus) diff --git a/src/drivers/i2c/i2cmux/i2cmux.c b/src/drivers/i2c/i2cmux/i2cmux.c index 1091653..ef5ab3a 100644 --- a/src/drivers/i2c/i2cmux/i2cmux.c +++ b/src/drivers/i2c/i2cmux/i2cmux.c @@ -1,10 +1,5 @@ -#include <console/console.h> #include <device/device.h> #include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> static void i2cmux_set_link(struct device *dev, unsigned int link) { @@ -21,7 +16,7 @@ static struct device_operations i2cmux_operations = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .set_link = i2cmux_set_link, }; diff --git a/src/drivers/i2c/i2cmux2/i2cmux2.c b/src/drivers/i2c/i2cmux2/i2cmux2.c index fe48e76..4d1241a 100644 --- a/src/drivers/i2c/i2cmux2/i2cmux2.c +++ b/src/drivers/i2c/i2cmux2/i2cmux2.c @@ -1,10 +1,5 @@ -#include <console/console.h> #include <device/device.h> #include <device/smbus.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <cpu/x86/msr.h> static void i2cmux2_set_link(struct device *dev, unsigned int link) { @@ -20,7 +15,7 @@ static struct device_operations i2cmux2_operations = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .set_link = i2cmux2_set_link, }; diff --git a/src/include/device/device.h b/src/include/device/device.h index 0acebb8..9c53f95 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -46,7 +46,7 @@ struct device_operations { void (*enable_resources)(device_t dev); void (*init)(device_t dev); void (*final)(device_t dev); - unsigned int (*scan_bus)(device_t bus, unsigned int _max); + void (*scan_bus)(device_t bus); void (*enable)(device_t dev); void (*disable)(device_t dev); void (*set_link)(device_t dev, unsigned int link); @@ -81,6 +81,7 @@ struct bus { ROMSTAGE_CONST struct device * children; /* devices behind this bridge */ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */ unsigned bridge_ctrl; /* Bridge control register */ + uint16_t bridge_cmd; /* Bridge command register */ unsigned char link_num; /* The index of this link */ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ @@ -171,7 +172,7 @@ void dev_finalize_chips(void); /* Generic device helper functions */ int reset_bus(struct bus *bus); -unsigned int scan_bus(struct device *bus, unsigned int _max); +void scan_bridges(struct bus *bus); void assign_resources(struct bus *bus); const char *dev_name(device_t dev); const char *dev_path(device_t dev); @@ -223,12 +224,13 @@ void show_all_devs_resources(int debug_level, const char* msg); extern struct device_operations default_dev_ops_root; void pci_domain_read_resources(struct device *dev); -unsigned int pci_domain_scan_bus(struct device *dev, unsigned int _max); -unsigned int scan_static_bus(device_t bus, unsigned int _max); +void pci_domain_scan_bus(struct device *dev); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); +void scan_smbus(device_t bus); +void scan_lpc_bus(device_t bus); /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. diff --git a/src/include/device/hypertransport.h b/src/include/device/hypertransport.h index e927d61..22e0ac4 100644 --- a/src/include/device/hypertransport.h +++ b/src/include/device/hypertransport.h @@ -4,8 +4,9 @@ #include <device/hypertransport_def.h> unsigned int hypertransport_scan_chain(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unit_base, unsigned offset_unitid); -unsigned int ht_scan_bridge(struct device *dev, unsigned int max); + unsigned min_devfn, unsigned max_devfn, unsigned *ht_unit_base, unsigned offset_unitid); +void ht_scan_bridge(struct device *dev); + extern struct device_operations default_ht_ops_bus; #define HT_IO_HOST_ALIGN 4096 diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 141d2e8..2a76ba9 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -70,11 +70,14 @@ void pci_dev_enable_resources(device_t dev); void pci_bus_enable_resources(device_t dev); void pci_bus_reset(struct bus *bus); device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn); -unsigned int do_pci_scan_bridge(device_t bus, unsigned int max, - unsigned int (*do_scan_bus)(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max)); -unsigned int pci_scan_bridge(device_t bus, unsigned int max); -unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn, unsigned int max); + +void do_pci_scan_bridge(device_t bus, + void (*do_scan_bus)(struct bus *bus, + unsigned min_devfn, unsigned max_devfn)); + +void pci_scan_bridge(device_t bus); +void pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn); + uint8_t pci_moving_config8(struct device *dev, unsigned reg); uint16_t pci_moving_config16(struct device *dev, unsigned reg); uint32_t pci_moving_config32(struct device *dev, unsigned reg); diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 1146557..f3df1a5 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -9,9 +9,10 @@ enum aspm_type { PCIE_ASPM_BOTH = 3, }; -unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); -unsigned int pciexp_scan_bridge(device_t dev, unsigned int max); +void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, + unsigned int max_devfn); + +void pciexp_scan_bridge(device_t dev); extern struct device_operations default_pciexp_ops_bus; diff --git a/src/include/device/pcix.h b/src/include/device/pcix.h index 4ffab5b..024c548 100644 --- a/src/include/device/pcix.h +++ b/src/include/device/pcix.h @@ -2,9 +2,8 @@ #define DEVICE_PCIX_H /* (c) 2005 Linux Networx GPL see COPYING for details */ -unsigned int pcix_scan_bus(struct bus *bus, unsigned int min_devfn, - unsigned int max_devfn, unsigned int max); -unsigned int pcix_scan_bridge(device_t dev, unsigned int max); +void pcix_scan_bridge(device_t dev); + const char *pcix_speed(u16 sstatus); extern struct device_operations default_pcix_ops_bus; diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index f12a272..26cbda5 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -241,14 +241,14 @@ static void cpu_bus_init(device_t dev) initialize_cpus(dev->link_list); } -static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +static void cpu_bus_scan(device_t bus) { int max_cpus = fw_cfg_max_cpus(); device_t cpu; int i; if (max_cpus < 0) - return 0; + return; /* * TODO: This only handles the simple "qemu -smp $nr" case @@ -261,7 +261,6 @@ static unsigned int cpu_bus_scan(device_t bus, unsigned int max) if (cpu) set_cpu_topology(cpu, 1, 0, i, 0); } - return max_cpus; } static struct device_operations cpu_bus_ops = { diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb index 78d099a..239f1f9 100644 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ b/src/mainboard/lippert/frontrunner/devicetree.cb @@ -6,10 +6,10 @@ chip northbridge/amd/gx2 end device domain 0 on - device pci 0.0 on end + device pci 0.0 on chip southbridge/amd/cs5535 - register "setupflash" = "0" - device pci 12.0 on + register "setupflash" = "0" + device pci 12.0 on end device pci 12.1 off end # SMI device pci 12.2 on end # IDE device pci 12.3 off end # Audio diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 6d0b1b7..0fe1910 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -554,16 +554,18 @@ static void mcf0_control_init(struct device *dev) { } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; device_t io_hub = NULL; u32 next_unitid = 0xff; + unsigned int max = dev->bus->subordinate; nodeid = amdfam10_nodeid(dev); if (nodeid == 0) { + ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[3] */ io_hub = link->children; @@ -571,12 +573,13 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); } /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); } } + max = dev->bus->subordinate; } - return max; + dev->bus->subordinate = max; } static struct device_operations northbridge_operations = { @@ -902,7 +905,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static void amdfam10_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -913,7 +916,9 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) } for (link = dev->link_list; link; link = link->next) { - max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + link->secondary = dev->bus->subordinate; + pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); + dev->bus->subordinate = link->subordinate; } /* Tune the hypertransport transaction for best performance. @@ -937,7 +942,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; } @@ -1005,7 +1009,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1181,7 +1185,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 355a458..32b74f6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -765,7 +765,7 @@ static void domain_enable_resources(device_t dev) /* Bus related code */ -static u32 cpu_bus_scan(struct device *dev, u32 max) +static void cpu_bus_scan(struct device *dev) { struct bus *cpu_bus = dev->link_list; device_t cpu; @@ -784,7 +784,6 @@ static u32 cpu_bus_scan(struct device *dev, u32 max) if (cpu) amd_cpu_topology(cpu, 0, apic_id); } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index b2d8abd..94e16ac 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -459,14 +459,17 @@ static void nb_set_resources(device_t dev) } } -static unsigned scan_chains(device_t dev, unsigned max) +static void scan_chains(device_t dev) { unsigned nodeid; struct bus *link; device_t io_hub = NULL; u32 next_unitid = 0x18; + unsigned int max = dev->bus->subordinate; + nodeid = amdfam15_nodeid(dev); if (nodeid == 0) { + ASSERT(dev->bus->secondary == 0); for (link = dev->link_list; link; link = link->next) { //if (link->link_num == sblink) { /* devicetree put IO Hub on link_lsit[sblink] */ if (link->link_num == 0) { /* devicetree put IO Hub on link_lsit[0] */ @@ -475,11 +478,13 @@ static unsigned scan_chains(device_t dev, unsigned max) die("I can't find the IO Hub, or IO Hub not enabled, please check the device tree.\n"); } /* Now that nothing is overlapping it is safe to scan the children. */ - max = pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7, 0); + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); } } + max = dev->bus->subordinate; } - return max; + + dev->bus->subordinate = max; } @@ -946,10 +951,10 @@ static void domain_set_resources(device_t dev) } /* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ -static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +static void f15_pci_domain_scan_bus(device_t dev) { - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); - return max; + struct bus *link = dev->link_list; + pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); } static struct device_operations pci_domain_ops = { @@ -1003,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1179,7 +1184,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 1f11f1d..0a1e7d3 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -992,7 +992,7 @@ static void add_more_links(struct device *dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1166,7 +1166,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(struct device *dev) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index c39ebd1..37b6a8e 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -991,7 +991,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1165,7 +1165,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index d1b06ec..9bbc279 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -1008,7 +1008,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1182,7 +1182,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3fb0beb..4734522 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -165,6 +165,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; + unsigned int next_unitid; u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; @@ -226,7 +227,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool max_bus = 0xfc; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = link->secondary; /* Read the existing primary/secondary/subordinate bus * number configuration. @@ -244,7 +245,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* set the config map space */ - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, max_bus, sysconf.segbit, sysconf.nodes); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -259,16 +260,14 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); + + /* Now that nothing is overlapping it is safe to scan the children. */ + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - if(ht_c_index>3) { // clear the extend reg - clear_config_map_reg(nodeid, link->link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes); - } - - link->subordinate = max; set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); sysconf.ht_c_num++; @@ -282,15 +281,16 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool sysconf.hcdn_reg[ht_c_index] = temp; } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); - return max; + store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); + return link->subordinate; } -static unsigned amdfam10_scan_chains(device_t dev, unsigned max) +static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; unsigned sblink = sysconf.sblk; + unsigned int max = dev->bus->subordinate; nodeid = amdfam10_nodeid(dev); @@ -308,7 +308,8 @@ static unsigned amdfam10_scan_chains(device_t dev, unsigned max) max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } - return max; + + dev->bus->subordinate = max; } @@ -909,7 +910,7 @@ static void amdfam10_domain_set_resources(device_t dev) } } -static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) +static void amdfam10_domain_scan_bus(device_t dev) { u32 reg; int i; @@ -920,7 +921,9 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) } for(link = dev->link_list; link; link = link->next) { - max = pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); + link->secondary = dev->bus->subordinate; + pci_scan_bus(link, PCI_DEVFN(CONFIG_CDB, 0), 0xff); + dev->bus->subordinate = link->subordinate; } /* Tune the hypertransport transaction for best performance. @@ -944,7 +947,6 @@ static u32 amdfam10_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; } #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) @@ -1209,7 +1211,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1378,7 +1380,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index f2e0e4c..45cff9e 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -105,6 +105,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ u32 max) { int i; + unsigned int next_unitid; u32 busses, config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain @@ -170,7 +171,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ max_bus = 0xff; link->secondary = min_bus; - link->subordinate = max_bus; + link->subordinate = link->secondary; /* Read the existing primary/secondary/subordinate bus * number configuration. @@ -185,7 +186,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ busses &= 0xff000000; busses |= (((unsigned int)(dev->bus->secondary) << 0) | ((unsigned int)(link->secondary) << 8) | - ((unsigned int)(link->subordinate) << 16)); + (max_bus << 16)); pci_write_config32(dev, link->cap + 0x14, busses); config_busses &= 0x000fc88; @@ -194,7 +195,7 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ (( nodeid & 7) << 4) | ((link->link_num & 3) << 8) | ((link->secondary) << 16) | - ((link->subordinate) << 24); + (max_bus << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the @@ -209,12 +210,14 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ else max_devfn = (0x1f<<3) | 7; - max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unit_id(is_sblink)); + next_unitid = hypertransport_scan_chain(link, 0, max_devfn, ht_unitid_base, offset_unit_id(is_sblink)); + + /* Now that nothing is overlapping it is safe to scan the children. */ + pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - link->subordinate = max; busses = (busses & 0xff00ffff) | ((unsigned int) (link->subordinate) << 16); pci_write_config32(dev, link->cap + 0x14, busses); @@ -235,14 +238,15 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ sysconf.hcdn_reg[index] = temp; } - return max; + return link->subordinate; } -static unsigned amdk8_scan_chains(device_t dev, unsigned max) +static void amdk8_scan_chains(device_t dev) { unsigned nodeid; struct bus *link; unsigned sblink = 0; + unsigned int max = dev->bus->subordinate; nodeid = amdk8_nodeid(dev); if (nodeid == 0) @@ -262,7 +266,8 @@ static unsigned amdk8_scan_chains(device_t dev, unsigned max) max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } - return max; + + dev->bus->subordinate = max; } @@ -1088,15 +1093,20 @@ static void amdk8_domain_set_resources(device_t dev) } -static u32 amdk8_domain_scan_bus(device_t dev, u32 max) +static void amdk8_domain_scan_bus(device_t dev) { u32 reg; int i; + struct bus *link = dev->link_list; + /* Unmap all of the HT chains */ for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } - max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); + + link->secondary = dev->bus->subordinate; + pci_scan_bus(link, PCI_DEVFN(0x18, 0), 0xff); + dev->bus->subordinate = link->subordinate; /* Tune the hypertransport transaction for best performance. * Including enabling relaxed ordering if it is safe. @@ -1119,7 +1129,6 @@ static u32 amdk8_domain_scan_bus(device_t dev, u32 max) pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc); } } - return max; } static struct device_operations pci_domain_ops = { @@ -1168,7 +1177,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1307,7 +1316,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 15892c6..60a1d49 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -985,7 +985,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1176,7 +1176,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index c44c189..8e340ce 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1001,7 +1001,7 @@ static void add_more_links(device_t dev, unsigned total_links) last->next = NULL; } -static u32 cpu_bus_scan(device_t dev, u32 max) +static void cpu_bus_scan(device_t dev) { struct bus *cpu_bus; device_t dev_mc; @@ -1187,7 +1187,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max) amd_cpu_topology(cpu, i, j); } //j } - return max; } static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i3100/pciexp_porta.c b/src/northbridge/intel/i3100/pciexp_porta.c index b37e3cf..a4be7a6 100644 --- a/src/northbridge/intel/i3100/pciexp_porta.c +++ b/src/northbridge/intel/i3100/pciexp_porta.c @@ -45,7 +45,7 @@ static void pcie_init(struct device *dev) } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -62,7 +62,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c index 31cd29f..f7e3a6a 100644 --- a/src/northbridge/intel/i3100/pciexp_porta_ep80579.c +++ b/src/northbridge/intel/i3100/pciexp_porta_ep80579.c @@ -67,7 +67,7 @@ static void pcie_bus_enable_resources(struct device *dev) } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -84,7 +84,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 91a9930..483f19e 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -297,7 +297,7 @@ static struct device_operations cx700_lpc_ops = { .set_resources = cx700_set_resources, .enable_resources = cx700_enable_resources, .init = cx700_lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 00955b0..be39acd 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -362,7 +362,7 @@ static struct device_operations vx800_lpc_ops = { .set_resources = vx800_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index 61a8a7b..f6c4c6a 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -192,7 +192,7 @@ static struct device_operations vx900_lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index fb15193..011bb41 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -134,8 +134,9 @@ static struct device_operations traf_ctrl_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_traf_ctr_init, - /* Need this here, or the IOAPIC driver won't be called */ - .scan_bus = scan_static_bus, + /* Need this here, or the IOAPIC driver won't be called. + * FIXME: Technically not a LPC bus. */ + .scan_bus = scan_lpc_bus, }; static const struct pci_driver traf_ctrl_driver __pci_driver = { diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index e4c0654..4a050fa 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -230,7 +230,7 @@ static void byt_pcie_enable(device_t dev) southcluster_enable_dev(dev); } -static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) +static void byt_pciexp_scan_bridge(device_t dev) { static const struct reg_script wait_for_link_active[] = { REG_PCI_POLL32(LCTL, (1 << 29) , (1 << 29), 50000), @@ -240,7 +240,7 @@ static unsigned int byt_pciexp_scan_bridge(device_t dev, unsigned int max) /* wait for Link Active with 50ms timeout */ reg_script_run_on_dev(dev, wait_for_link_active); - return do_pci_scan_bridge(dev, max, pciexp_scan_bus); + do_pci_scan_bridge(dev, pciexp_scan_bus); } static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 365ac3d..26e0156 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -546,7 +546,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 0acfe78..13c975f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -643,7 +643,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southcluster_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = &lpc_init, - .scan_bus = &scan_static_bus, + .scan_bus = &scan_lpc_bus, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/smbus.c b/src/soc/intel/broadwell/smbus.c index e0f9b8a..5660a41 100644 --- a/src/soc/intel/broadwell/smbus.c +++ b/src/soc/intel/broadwell/smbus.c @@ -94,7 +94,7 @@ static struct device_operations smbus_ops = { .read_resources = &smbus_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_static_bus, + .scan_bus = &scan_smbus, .init = &pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &broadwell_pci_ops, diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 44127ee..ac80478 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -607,7 +607,7 @@ static struct device_operations device_ops = { .enable_resources = NULL, .init = sc_init, .enable = southcluster_enable_dev, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &soc_pci_ops, }; diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index f3a525c..65cb955 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -333,7 +333,7 @@ static struct device_operations lpc_ops = { #endif .enable_resources = hudson_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index fd8e6ad..09fbf8b 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -163,7 +163,7 @@ static struct device_operations smbus_ops = { .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 6d0ce26..396b7c4 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -226,7 +226,7 @@ static struct device_operations acpi_ops = { .set_resources = pci_dev_set_resources, .enable_resources = acpi_enable_resources, .init = acpi_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, /* We don't need amd8111_enable, chip ops takes care of it. * It could be useful if these devices were not * enabled by default. diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index 2ded0cb..47b9ae7 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -151,7 +151,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/amd8111/smbus.c b/src/southbridge/amd/amd8111/smbus.c index 0a0c58d..def1377 100644 --- a/src/southbridge/amd/amd8111/smbus.c +++ b/src/southbridge/amd/amd8111/smbus.c @@ -28,7 +28,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = amd8111_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/amd8111/usb.c b/src/southbridge/amd/amd8111/usb.c index 13dccf4..feb7793 100644 --- a/src/southbridge/amd/amd8111/usb.c +++ b/src/southbridge/amd/amd8111/usb.c @@ -25,8 +25,6 @@ static struct device_operations usb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, -// .enable = amd8111_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c index e638fae..1587268 100644 --- a/src/southbridge/amd/amd8131/bridge.c +++ b/src/southbridge/amd/amd8131/bridge.c @@ -192,16 +192,15 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr) pci_write_config16(dev, cap + PCI_X_CMD, cmd); } } -static unsigned int amd8131_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void amd8131_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn) { struct amd8131_bus_info info; struct bus *pbus; unsigned pos; - /* Find the children on the bus */ - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); /* Find the revision of the 8131 */ info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); @@ -243,13 +242,13 @@ static unsigned int amd8131_scan_bus(struct bus *bus, pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - return max; + return; } /* If we are in conventional PCI mode nothing more is necessary. */ if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return max; + return; } @@ -264,12 +263,11 @@ static unsigned int amd8131_scan_bus(struct bus *bus, bus_path(pbus)); pbus->disable_relaxed_ordering = 1; } - return max; } -static unsigned int amd8131_scan_bridge(device_t dev, unsigned int max) +static void amd8131_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, amd8131_scan_bus); + do_pci_scan_bridge(dev, amd8131_scan_bus); } diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 2684e7c..027a085 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -138,15 +138,14 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr) } -static unsigned int amd8132_scan_bus(struct bus *bus, - unsigned min_devfn, unsigned max_devfn, unsigned int max) +static void amd8132_scan_bus(struct bus *bus, + unsigned min_devfn, unsigned max_devfn) { struct amd8132_bus_info info; unsigned pos; - /* Find the children on the bus */ - max = pci_scan_bus(bus, min_devfn, max_devfn, max); + pci_scan_bus(bus, min_devfn, max_devfn); /* Find the revision of the 8132 */ info.rev = pci_read_config8(bus->dev, PCI_CLASS_REVISION); @@ -181,25 +180,23 @@ static unsigned int amd8132_scan_bus(struct bus *bus, pcix_misc &= ~(0x1f << 16); pci_write_config32(bus->dev, 0x40, pcix_misc); - return max; + return; } #endif /* If we are in conventional PCI mode nothing more is necessary. */ if (PCI_X_SSTATUS_MFREQ(info.sstatus) == PCI_X_SSTATUS_CONVENTIONAL_PCI) { - return max; + return; } /* Tune the devices on the bus */ amd8132_walk_children(bus, amd8132_pcix_tune_dev, &info); - - return max; } -static unsigned int amd8132_scan_bridge(device_t dev, unsigned int max) +static void amd8132_scan_bridge(device_t dev) { - return do_pci_scan_bridge(dev, max, amd8132_scan_bus); + do_pci_scan_bridge(dev, amd8132_scan_bus); } diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 4254a5c..cd36fac 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -111,7 +111,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 79c2203..0ada673 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -161,7 +161,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 7249ec5..fbff7df 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -132,7 +132,7 @@ static struct device_operations lpc_ops = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c index e66a1e2..70b8386 100644 --- a/src/southbridge/amd/cs5535/cs5535.c +++ b/src/southbridge/amd/cs5535/cs5535.c @@ -94,7 +94,6 @@ static struct device_operations southbridge_ops = { .enable_resources = pci_dev_enable_resources, .init = southbridge_init, .enable = southbridge_enable, - .scan_bus = scan_static_bus, }; static const struct pci_driver cs5535_pci_driver __pci_driver = { diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 0db8195..67eabb0 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -688,13 +688,18 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; +static void scan_lpc_smbus(device_t dev) +{ + /* FIXME. Do we have mixed LPC/SMBus device node here. */ + scan_smbus(dev); +} + static struct device_operations southbridge_ops = { .read_resources = cs5536_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, -// .enable = southbridge_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_smbus, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 840ff7a..b813d12 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -340,7 +340,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index fd8e6ad..09fbf8b 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -163,7 +163,7 @@ static struct device_operations smbus_ops = { .set_resources = hudson_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 62c88de..2fb9e22 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -242,7 +242,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, /* .enable = sb600_enable, */ .ops_pci = &lops_pci, }; diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c index 0254f83..40fde47 100644 --- a/src/southbridge/amd/sb600/sm.c +++ b/src/southbridge/amd/sb600/sm.c @@ -361,7 +361,7 @@ static struct device_operations smbus_ops = { .set_resources = sb600_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, /* .enable = sb600_enable, */ .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index be3c4d6..94d8dcb 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -287,7 +287,7 @@ static struct device_operations lpc_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 2a88a80..f544c88 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -452,7 +452,7 @@ static struct device_operations smbus_ops = { .set_resources = sb700_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 5a40a8d..0cd5b32 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -254,7 +254,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; static const struct pci_driver lpc_driver __pci_driver = { diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index b34cfbd..1523c60 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -343,7 +343,7 @@ static struct device_operations smbus_ops = { .set_resources = sb800_sm_set_resources, .enable_resources = pci_dev_enable_resources, .init = sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c index 28e8a8f..ef70df6 100644 --- a/src/southbridge/broadcom/bcm5785/lpc.c +++ b/src/southbridge/broadcom/bcm5785/lpc.c @@ -135,7 +135,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = bcm5785_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index bddb090..3390b0d 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -154,7 +154,7 @@ static struct device_operations sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = sb_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, // .enable = bcm5785_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 19b4757..192de74 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -619,7 +619,7 @@ static struct device_operations vortex_sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = 0, .ops_pci = 0, }; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index c1bc45f..fec0d5c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -827,7 +827,7 @@ static struct device_operations device_ops = { .init = lpc_init, .final = lpc_final, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index ed25e44..ab3d475 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -760,7 +760,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 75e517f..6bd26c4 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -763,7 +763,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 42a8578..1b8ac76 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -273,13 +273,12 @@ static void pch_pcie_enable(device_t dev) pch_pcie_pm_early(dev); } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_bd82x6x_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); @@ -287,8 +286,6 @@ static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) /* Late Power Management init after bridge device enumeration */ pch_pcie_pm_late(dev); - - return ret; } static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 94546a7..0198841 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -151,7 +151,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/esb6300/lpc.c b/src/southbridge/intel/esb6300/lpc.c index 22bb150..e1718bb 100644 --- a/src/southbridge/intel/esb6300/lpc.c +++ b/src/southbridge/intel/esb6300/lpc.c @@ -362,7 +362,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = esb6300_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = esb6300_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/esb6300/smbus.c b/src/southbridge/intel/esb6300/smbus.c index 92cb288..2c026b8 100644 --- a/src/southbridge/intel/esb6300/smbus.c +++ b/src/southbridge/intel/esb6300/smbus.c @@ -35,7 +35,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = esb6300_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 1d92532..b410332 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -761,7 +761,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index ab6ae09..8f65da3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -759,7 +759,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 5e7b661..292dbba 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -762,7 +762,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 3aee7ed..22de62d 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -463,7 +463,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .enable = soc_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 8368afe..7864b1e 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -87,7 +87,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, }; diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c index b29180c..aef855f 100644 --- a/src/southbridge/intel/i3100/lpc.c +++ b/src/southbridge/intel/i3100/lpc.c @@ -457,7 +457,7 @@ static struct device_operations lpc_ops = { #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .write_acpi_tables = acpi_write_hpet, #endif - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i3100_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i3100/pciexp_portb.c b/src/southbridge/intel/i3100/pciexp_portb.c index 815c081..41e921c 100644 --- a/src/southbridge/intel/i3100/pciexp_portb.c +++ b/src/southbridge/intel/i3100/pciexp_portb.c @@ -39,7 +39,7 @@ static void pcie_init(struct device *dev) { } -static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) +static void pcie_scan_bridge(struct device *dev) { u16 val; u16 ctl; @@ -56,7 +56,8 @@ static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max) hard_reset(); } } while (val & (3<<10)); - return pciexp_scan_bridge(dev, max); + + pciexp_scan_bridge(dev); } static struct device_operations pcie_ops = { diff --git a/src/southbridge/intel/i3100/smbus.c b/src/southbridge/intel/i3100/smbus.c index 445b668..2feb00f 100644 --- a/src/southbridge/intel/i3100/smbus.c +++ b/src/southbridge/intel/i3100/smbus.c @@ -74,7 +74,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i3100_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 1945fae..024604b 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -145,7 +145,7 @@ static const struct device_operations isa_ops = { .acpi_fill_ssdt_generator = southbridge_acpi_fill_ssdt_generator, #endif .init = isa_init, - .scan_bus = scan_static_bus, /* TODO: Needed? */ + .scan_bus = scan_lpc_bus, /* TODO: Needed? */ .enable = 0, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ }; diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 82647e1..3817357 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -121,7 +121,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = pwrmgt_enable, .ops_pci = 0, /* No subsystem IDs on 82371EB! */ .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 4bd69d6..e960551 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -286,7 +286,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801ax_enable, }; diff --git a/src/southbridge/intel/i82801ax/smbus.c b/src/southbridge/intel/i82801ax/smbus.c index cbe9e4a..76a78d1 100644 --- a/src/southbridge/intel/i82801ax/smbus.c +++ b/src/southbridge/intel/i82801ax/smbus.c @@ -48,7 +48,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801ax_enable, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index edadf40..7247cdc 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -304,7 +304,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801bx_enable, }; diff --git a/src/southbridge/intel/i82801bx/smbus.c b/src/southbridge/intel/i82801bx/smbus.c index 8feb75b..836c256 100644 --- a/src/southbridge/intel/i82801bx/smbus.c +++ b/src/southbridge/intel/i82801bx/smbus.c @@ -48,7 +48,7 @@ static const struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801bx_enable, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 22671c3..a348c95 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -230,7 +230,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = 0, }; diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 9f2a23f..29a457a 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -336,7 +336,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801dx_enable, }; diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 0a2f6e3..630484a 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -369,7 +369,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = i82801ex_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801ex_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/intel/i82801ex/smbus.c b/src/southbridge/intel/i82801ex/smbus.c index fe49e11..75ea119 100644 --- a/src/southbridge/intel/i82801ex/smbus.c +++ b/src/southbridge/intel/i82801ex/smbus.c @@ -35,7 +35,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801ex_enable, .ops_pci = &lops_pci, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index bf61855..5ff8c24 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -667,7 +667,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .enable = i82801gx_enable, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 585d16c..e556d72 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -258,7 +258,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .enable = i82801gx_enable, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 3cc053b..8713e55 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -582,7 +582,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 58c0e19..5858176 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -110,19 +110,16 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max) +static void pch_pciexp_scan_bridge(device_t dev) { - unsigned int ret; struct southbridge_intel_i82801ix_config *config = dev->chip_info; /* Normal PCIe Scan */ - ret = pciexp_scan_bridge(dev, max); + pciexp_scan_bridge(dev); if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { intel_acpi_pcie_hotplug_scan_slot(dev->link_list); } - - return ret; } static struct pci_operations pci_ops = { diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 635cb19..9ae267d 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -101,7 +101,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f066b35..e46bea6 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -805,7 +805,7 @@ static struct device_operations device_ops = { .write_acpi_tables = acpi_write_hpet, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e68bb01..96e16e3 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -634,7 +634,6 @@ static struct device_operations device_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = intel_me_init, - .scan_bus = scan_static_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index 085aec0..2bb4cbf 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -108,7 +108,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c055da5..4b7de54 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -834,7 +834,7 @@ static struct device_operations device_ops = { .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .enable = pch_lpc_enable, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index ae16a92..b7c8503 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -155,7 +155,7 @@ static struct device_operations smbus_ops = { .read_resources = smbus_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .init = pch_smbus_init, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c index e40b051..e961e4f 100644 --- a/src/southbridge/intel/sch/lpc.c +++ b/src/southbridge/intel/sch/lpc.c @@ -222,7 +222,7 @@ static struct device_operations device_ops = { .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, }; diff --git a/src/southbridge/intel/sch/smbus.c b/src/southbridge/intel/sch/smbus.c index d208fcc..c3bff67 100644 --- a/src/southbridge/intel/sch/smbus.c +++ b/src/southbridge/intel/sch/smbus.c @@ -65,7 +65,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_smbus_bus = &lops_smbus_bus, .ops_pci = &smbus_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index c6f8c24..406b4f2 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -329,7 +329,7 @@ static struct device_operations lpc_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &ck804_pci_ops, }; diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index f5fa1d5..2803df0 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -96,7 +96,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = 0, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, .ops_pci = &ck804_pci_ops, .ops_smbus_bus = &lops_smbus_bus, }; diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index d9c6211..d3399f3 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -261,7 +261,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 91d5830..2a56069 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -127,7 +127,7 @@ static struct device_operations smbus_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = mcp55_sm_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_smbus, // .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, .ops_smbus_bus = &lops_smbus_bus, diff --git a/src/southbridge/rdc/r8610/r8610.c b/src/southbridge/rdc/r8610/r8610.c index 338a133..328f3be 100644 --- a/src/southbridge/rdc/r8610/r8610.c +++ b/src/southbridge/rdc/r8610/r8610.c @@ -105,7 +105,6 @@ static struct device_operations r8610_sb_ops = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = &southbridge_init, - .scan_bus = scan_static_bus, .enable = 0, .ops_pci = 0, }; diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 9194420..e5eaa06 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -259,7 +259,7 @@ static struct device_operations lpc_ops = { .set_resources = pci_dev_set_resources, .enable_resources = sis966_lpc_enable_resources, .init = lpc_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, // .enable = sis966_enable, .ops_pci = &lops_pci, }; diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index ebaaa04..f7f2dbe 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -657,7 +657,7 @@ static const struct device_operations vt8237r_lpc_ops_s = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237s_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; @@ -666,7 +666,7 @@ static const struct device_operations vt8237r_lpc_ops_r = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237r_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; @@ -675,7 +675,7 @@ static const struct device_operations vt8237r_lpc_ops_a = { .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = vt8237a_init, - .scan_bus = scan_static_bus, + .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, }; diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 8c7d70f..a9a8092 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -134,7 +134,6 @@ static struct device_operations ops_hwm = { .enable_resources = lpc47b397_pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b397_init, - .scan_bus = scan_static_bus, .ops_smbus_bus = &lops_smbus_bus, .ops_pnp_mode = &pnp_conf_mode_55_aa, };

1 0

Patch set updated for coreboot: 24a64c0 AMD fam10: Fix add_more_links FIXME
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8555 -gerrit commit 24a64c0381647eba01f02509fdf79b652c364683 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 23:56:07 2015 +0200 AMD fam10: Fix add_more_links FIXME One PCI function may contain upto 4 links, further links must be added to PCI function 4 on the same device. To have support for 8 links starts with HT 3.0 specs? There is no requirement that in dev->link_list the last element would have the highest link->link_num. Also fix off-by-one error when allocating for more links. Change-Id: If7ebdd1ad52653d3757b5930bd0a83e2cf2fcac6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 56 ++++++++++++++++++------------ 1 file changed, 33 insertions(+), 23 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 4734522..b456e9d 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -176,18 +176,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool #endif u32 max_devfn; - if (link->link_num > 3) { - u32 regpos; - u32 reg; - regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 - reg = pci_read_config32(dev, regpos); - if(reg & 1) return max; // already ganged no sblink1 - - dev = get_node_pci(nodeid, 4); - } - /* Check for connected link. */ - link->cap = 0x80 + ((link->link_num & 3) * 0x20); + link->cap = 0x80 + (link->link_num * 0x20); if (!is_non_coherent_link(dev, link)) return max; @@ -1175,17 +1165,34 @@ static void sysconf_init(device_t dev) // first node #endif } +#if 0 +static void FIXME_add_more_links(); +{ + if (link->link_num > 3) { + u32 regpos; + u32 reg; + regpos = 0x170 + 4 * (link->link_num & 3); // it is only on sublink0 + reg = pci_read_config32(dev, regpos); + if (reg & 1) return max; // already ganged no sblink1 + + dev = get_node_pci(nodeid, 4); + } +} +#endif + static void add_more_links(device_t dev, unsigned total_links) { struct bus *link, *last = NULL; - int link_num; + int link_num = -1; - for (link = dev->link_list; link; link = link->next) + for (link = dev->link_list; link; link = link->next) { + if (link_num < link->link_num) + link_num = link->link_num; last = link; + } if (last) { - int links = total_links - last->link_num; - link_num = last->link_num; + int links = total_links - (link_num + 1); if (links > 0) { link = malloc(links*sizeof(*link)); if (!link) @@ -1195,7 +1202,6 @@ static void add_more_links(device_t dev, unsigned total_links) } } else { - link_num = -1; link = malloc(total_links*sizeof(*link)); memset(link, 0, total_links*sizeof(*link)); dev->link_list = link; @@ -1337,15 +1343,19 @@ static void cpu_bus_scan(device_t dev) cdb_dev = pci_probe_dev(NULL, pbus, PCI_DEVFN(devn, fn)); } - cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - } - if (cdb_dev) { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 8); } + /* Ok, We need to set the links for that device. + * otherwise the device under it will not be scanned + */ + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (cdb_dev) + add_more_links(cdb_dev, 4); + + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 4)); + if (cdb_dev) + add_more_links(cdb_dev, 4); + cores_found = 0; // one core cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); int enable_node = cdb_dev && cdb_dev->enabled;

1 0

Patch set updated for coreboot: fff8dae devicetree: Add fields for HyperTransport scans
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8557 -gerrit commit fff8daee2bb6228823177e012aeac9f73daf5376 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 11:38:49 2015 +0200 devicetree: Add fields for HyperTransport scans Change-Id: I3b00e5e4e45089fbd7d0d6243d5e441bd8929c0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/device/device.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/device/device.h b/src/include/device/device.h index 9c53f95..396ecf8 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -86,6 +86,8 @@ struct bus { uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* max subordinate bus number */ unsigned char cap; /* PCi capability offset */ + uint32_t hcdn_reg; /* For HyperTransport link */ + unsigned reset_needed : 1; unsigned disable_relaxed_ordering : 1; };

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Patch set updated for coreboot: aa715cc AMD K8 fam10: Add ht_route_link()
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8556 -gerrit commit aa715cc105ba36e1de6f20caa43b511eb78a2aeb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 23 12:05:33 2015 +0200 AMD K8 fam10: Add ht_route_link() Change-Id: I41aeb80121f120641b65759c8502150ce89caa30 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 50 +++++++++++++++++-------- src/northbridge/amd/amdk8/northbridge.c | 60 +++++++++++++++++++----------- 2 files changed, 73 insertions(+), 37 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index b456e9d..2bca59c 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -158,6 +158,37 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link) return !!(link_type & NonCoherent); } +typedef enum { + HT_ROUTE_CLOSE, + HT_ROUTE_SCAN, + HT_ROUTE_FINAL, +} scan_state; + +static void ht_route_link(struct bus *link, scan_state mode) +{ + struct bus *parent = link->dev->bus; + u32 busses; + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xff000000; + busses |= parent->secondary & 0xff; + if (mode == HT_ROUTE_CLOSE) { + busses |= 0xfeff << 8; + } else if (mode == HT_ROUTE_SCAN) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= 0xfc << 16; + } else if (mode == HT_ROUTE_FINAL) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->subordinate & 0xff) << 16; + } + pci_write_config32(link->dev, link->cap + 0x14, busses); + +} + static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_sblink, u32 max) { @@ -170,7 +201,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_bus; u32 min_bus; - u32 busses; #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 u32 busn = max&0xff; #endif @@ -219,23 +249,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool link->secondary = min_bus; link->subordinate = link->secondary; - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xffff00ff; - busses |= ((u32)(link->secondary) << 8); - pci_write_config32(dev, link->cap + 0x14, busses); - + ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, max_bus, sysconf.segbit, sysconf.nodes); + set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -255,6 +273,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* Now that nothing is overlapping it is safe to scan the children. */ pci_scan_bus(link, 0x00, ((next_unitid - 1) << 3) | 7); + ht_route_link(link, HT_ROUTE_FINAL); + /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 45cff9e..018b68a 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -96,6 +96,38 @@ static bool is_non_coherent_link(struct device *dev, struct bus *link) return !!(link_type & NonCoherent); } +typedef enum { + HT_ROUTE_CLOSE, + HT_ROUTE_SCAN, + HT_ROUTE_FINAL, +} scan_state; + +static void ht_route_link(struct bus *link, scan_state mode) +{ + struct device *dev = link->dev; + struct bus *parent = dev->bus; + u32 busses; + + /* Configure the bus numbers for this bridge: the configuration + * transactions will not be propagated by the bridge if it is + * not correctly configured + */ + busses = pci_read_config32(link->dev, link->cap + 0x14); + busses &= 0xff000000; + busses |= parent->secondary & 0xff; + if (mode == HT_ROUTE_CLOSE) { + busses |= 0xfeff << 8; + } else if (mode == HT_ROUTE_SCAN) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= 0xff << 16; + } else if (mode == HT_ROUTE_FINAL) { + busses |= ((u32) link->secondary & 0xff) << 8; + busses |= ((u32) link->subordinate & 0xff) << 16; + } + pci_write_config32(link->dev, link->cap + 0x14, busses); + +} + static u32 amdk8_nodeid(device_t dev) { return (dev->path.pci.devfn >> 3) - 0x18; @@ -106,10 +138,9 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ { int i; unsigned int next_unitid; - u32 busses, config_busses; + u32 config_busses; u32 free_reg, config_reg; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain - u32 max_bus; u32 min_bus; u32 max_devfn; @@ -168,34 +199,20 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ #else min_bus = ++max; #endif - max_bus = 0xff; link->secondary = min_bus; link->subordinate = link->secondary; - /* Read the existing primary/secondary/subordinate bus - * number configuration. - */ - busses = pci_read_config32(dev, link->cap + 0x14); - config_busses = f1_read_config32(config_reg); - - /* Configure the bus numbers for this bridge: the configuration - * transactions will not be propagates by the bridge if it is - * not correctly configured - */ - busses &= 0xff000000; - busses |= (((unsigned int)(dev->bus->secondary) << 0) | - ((unsigned int)(link->secondary) << 8) | - (max_bus << 16)); - pci_write_config32(dev, link->cap + 0x14, busses); + ht_route_link(link, HT_ROUTE_SCAN); + config_busses = f1_read_config32(config_reg); config_busses &= 0x000fc88; config_busses |= (3 << 0) | /* rw enable, no device compare */ (( nodeid & 7) << 4) | ((link->link_num & 3) << 8) | ((link->secondary) << 16) | - (max_bus << 24); + (0xff << 24); f1_write_config32(config_reg, config_busses); /* Now we can scan all of the subordinate busses i.e. the @@ -218,9 +235,8 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - busses = (busses & 0xff00ffff) | - ((unsigned int) (link->subordinate) << 16); - pci_write_config32(dev, link->cap + 0x14, busses); + + ht_route_link(link, HT_ROUTE_FINAL); config_busses = (config_busses & 0x00ffffff) | (link->subordinate << 24);

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Patch set updated for coreboot: 7bb9d6c AMD K8: Refactor calls for HT configuration
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8559 -gerrit commit 7bb9d6ca0749a56a35e0ca006ecd33a901a8afd2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 11:19:01 2015 +0200 AMD K8: Refactor calls for HT configuration Change-Id: I24ca1dce025e00064f9209affa27586292c7650e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdk8/northbridge.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 9907a6b..00503ce 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -232,18 +232,15 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ (link->subordinate << 24); f1_write_config32(config_reg, config_busses); - { - // use config_reg and ht_unitid_base to update hcdn_reg - int index; - u32 temp = 0; - index = (config_reg-0xe0) >> 2; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } - sysconf.hcdn_reg[index] = temp; + // use config_reg and ht_unitid_base to update hcdn_reg + link->hcdn_reg = 0; + for (i = 0; i < 4; i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + int index = (config_reg-0xe0) >> 2; + sysconf.hcdn_reg[index] = link->hcdn_reg; - } return link->subordinate; }

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Patch set updated for coreboot: 41f9a74 AMD fam10: Refactor calls for HT configuration
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8558 -gerrit commit 41f9a74d99ff3e0f52224456dcfe4ad0451c22aa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 19 16:49:47 2015 +0200 AMD fam10: Refactor calls for HT configuration Change-Id: Ic8fbafdfadbc4ef0896d93e61c8a54ce69297e07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/ht_config.c | 71 +++++++++++++++++------------- src/northbridge/amd/amdfam10/ht_config.h | 15 +++---- src/northbridge/amd/amdfam10/northbridge.c | 33 +++++++------- 3 files changed, 60 insertions(+), 59 deletions(-) diff --git a/src/northbridge/amd/amdfam10/ht_config.c b/src/northbridge/amd/amdfam10/ht_config.c index 3110980..6eec534 100644 --- a/src/northbridge/amd/amdfam10/ht_config.c +++ b/src/northbridge/amd/amdfam10/ht_config.c @@ -47,54 +47,51 @@ struct dram_base_mask_t get_dram_base_mask(u32 nodeid) return d; } - -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes) +void set_config_map_reg(struct bus *link) { u32 tempreg; u32 i; + u32 ht_c_index = get_ht_c_index(link); + u32 linkn = link->link_num & 0x0f; + u32 busn_min = (link->secondary >> sysconf.segbit) & 0xff; + u32 busn_max = (link->subordinate >> sysconf.segbit) & 0xff; + u32 nodeid = amdfam10_nodeid(link->dev); - busn_min>>=segbit; - busn_max>>=segbit; + tempreg = ((nodeid & 0x30) << (12-4)) | ((nodeid & 0xf) << 4) | 3; + tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8); - tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } } -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes) +void clear_config_map_reg(struct bus *link) { u32 i; + u32 ht_c_index = get_ht_c_index(link); - for (i=0; i<nodes; i++) { + for (i=0; i < sysconf.nodes; i++) { device_t dev = __f1_dev[i]; pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } } -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) +static u32 ht_c_key(struct bus *link) { - u32 tempreg; - u32 ht_c_index = 0; + u32 nodeid = amdfam10_nodeid(link->dev); + u32 linkn = link->link_num & 0x0f; + u32 val = (linkn << 8) | ((nodeid & 0x3f) << 2) | 3; + return val; +} -#if 0 - tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); +static u32 get_ht_c_index_by_key(u32 key, sys_info_conf_t *sysinfo) +{ + u32 ht_c_index = 0; - for (ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); - if (((reg & 0xffff) == 0x0000)) { /*found free*/ - break; - } - } -#endif - tempreg = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); for (ht_c_index=0; ht_c_index<32; ht_c_index++) { - if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == tempreg) { + if ((sysinfo->ht_c_conf_bus[ht_c_index] & 0xfff) == key) { return ht_c_index; } } @@ -108,14 +105,26 @@ u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) return -1; } -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo) +u32 get_ht_c_index(struct bus *link) { - u32 val; - val = 3 | ((nodeid & 0x3f)<<2) | (linkn<<8); - sysinfo->ht_c_conf_bus[ht_c_index] = val | ((busn_min & 0xff) <<12) | (busn_max<<20); // same node need segn are same + u32 val = ht_c_key(link); + return get_ht_c_index_by_key(val, &sysconf); +} + +void store_ht_c_conf_bus(struct bus *link) +{ + u32 val = ht_c_key(link); + u32 ht_c_index = get_ht_c_index_by_key(val, &sysconf); + + u32 segn = (link->subordinate >> 8) & 0x0f; + u32 busn_min = link->secondary & 0xff; + u32 busn_max = link->subordinate & 0xff; + + val |= (segn << 28) | (busn_max << 20) | (busn_min << 12); + sysconf.ht_c_conf_bus[ht_c_index] = val; + sysconf.hcdn_reg[ht_c_index] = link->hcdn_reg; + sysconf.ht_c_num++; } u32 get_io_addr_index(u32 nodeid, u32 linkn) diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index 08c5263..fcec368 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -20,6 +20,7 @@ typedef struct amdfam10_sysconf_t sys_info_conf_t; /* FIXME */ +u32 amdfam10_nodeid(device_t dev); extern device_t __f1_dev[]; struct dram_base_mask_t { @@ -29,17 +30,11 @@ struct dram_base_mask_t { struct dram_base_mask_t get_dram_base_mask(u32 nodeid); -void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 segbit, - u32 nodes); -void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, u32 nodes); +u32 get_ht_c_index(struct bus *link); +void store_ht_c_conf_bus(struct bus *link); -void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, - u32 busn_min, u32 busn_max, - sys_info_conf_t *sysinfo); - -u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo); +void set_config_map_reg(struct bus *link); +void clear_config_map_reg(struct bus *link); void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index fb7020a..d4c5c1f 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -114,7 +114,7 @@ static void f1_write_config32(unsigned reg, u32 value) } } -static u32 amdfam10_nodeid(device_t dev) +u32 amdfam10_nodeid(device_t dev) { #if NODE_NUMS == 64 unsigned busn; @@ -197,7 +197,6 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool int i; unsigned int next_unitid; - u32 ht_c_index; u32 ht_unitid_base[4]; // here assume only 4 HT device on chain u32 max_devfn; @@ -209,9 +208,8 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* See if there is an available configuration space mapping * register in function 1. */ - ht_c_index = get_ht_c_index(nodeid, link->link_num, &sysconf); - - if(ht_c_index>=4) return max; + if (get_ht_c_index(link) >= 4) + return max; /* Set up the primary, secondary and subordinate bus numbers. * We have no idea how many busses are behind this bridge yet, @@ -239,8 +237,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool ht_route_link(link, HT_ROUTE_SCAN); /* set the config map space */ - - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); + set_config_map_reg(link); /* Now we can scan all of the subordinate busses i.e. the * chain on the hypertranport link @@ -265,20 +262,20 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool /* We know the number of busses behind this bridge. Set the * subordinate bus number to it's real value */ - set_config_map_reg(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes); - sysconf.ht_c_num++; + if (0) { + /* Clear the extend reg. */ + clear_config_map_reg(link); + } - { - // use ht_unitid_base to update hcdn_reg - u32 temp = 0; - for(i=0;i<4;i++) { - temp |= (ht_unitid_base[i] & 0xff) << (i*8); - } + set_config_map_reg(link); - sysconf.hcdn_reg[ht_c_index] = temp; + /* Use ht_unitid_base to update hcdn_reg. */ + link->hcdn_reg = 0; + for (i = 0; i < 4;i++) + link->hcdn_reg |= (ht_unitid_base[i] & 0xff) << (i*8); + + store_ht_c_conf_bus(link); - } - store_ht_c_conf_bus(nodeid, link->link_num, ht_c_index, link->secondary, link->subordinate, &sysconf); return link->subordinate; }

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Patch set updated for coreboot: c0102cc AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8352 -gerrit commit c0102cc2f045cb2c67f9dc2f82fb0777f95dae1d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 22 09:24:59 2015 +0200 AMD K8 fam10: Fix preprocessor use with SB_HT_CHAIN_ON_BUS0 Change-Id: I6bbd1b5eaa66a640e0a2e132c8d67f38f103caf5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 36 +++++++++++++----------------- src/northbridge/amd/amdk8/northbridge.c | 28 +++++++++-------------- 2 files changed, 26 insertions(+), 38 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 29ac5fe..68bf336 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -218,29 +218,25 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if (is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 - // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. - else { + + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { + min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + // second chain will be on 0x40, third 0x80, forth 0xc0 + // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 + // >4 will use more segments, + // We can have 16 segmment and every segment have 256 bus, + // For that case need the kernel support mmio pci config. + /* One node can have 8 link and segn is the same. */ min_bus = (((max & 0xff) >> 3) + 1) << 3; + max = min_bus; } - max = min_bus; - #else - //other ... - else { - min_bus = ++max; - } - #endif -#else - min_bus = ++max; -#endif link->secondary = min_bus; link->subordinate = link->secondary; diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 018b68a..b27404e 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -179,26 +179,18 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 - // first chain will on bus 0 - if(is_sblink) { // actually max is 0 here - min_bus = max; - } - #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 - // second chain will be on 0x40, third 0x80, forth 0xc0 - else { - min_bus = ((max>>6) + 1) * 0x40; - } - max = min_bus; - #else - //other ... - else { + if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) { + min_bus = ++max; + } else if (is_sblink) { + // first chain will on bus 0 + min_bus = max; /* actually max is 0 here */ + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) { min_bus = ++max; + } else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) { + /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ + min_bus = (max & ~0x3f) + 0x40; + max = min_bus; } - #endif -#else - min_bus = ++max; -#endif link->secondary = min_bus; link->subordinate = link->secondary;

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Patch set updated for coreboot: 55b46d4 AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8353 -gerrit commit 55b46d4314558e47f967820757840de1079c661c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 14:05:51 2015 +0200 AMD K8: Move SB_HT_CHAIN_ON_BUS0 default 0 Define the default value under northbridge. The list of boards this patchset touches will change to use SB_HT_CHAIN_ON_BUS0 with follow-up patch. Based on code analysis, these boards already scan system bus as the first (active) HT chain, so it is placed as bus 0 even when this option was not explicitly selected. Change-Id: I5a00d6372cb89151940aeee517ea613398825c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/ibm/e325/Kconfig | 4 ---- src/mainboard/ibm/e326/Kconfig | 4 ---- src/mainboard/iwill/dk8s2/Kconfig | 4 ---- src/mainboard/iwill/dk8x/Kconfig | 4 ---- src/mainboard/newisys/khepri/Kconfig | 4 ---- src/mainboard/tyan/s2850/Kconfig | 4 ---- src/mainboard/tyan/s2875/Kconfig | 4 ---- src/mainboard/tyan/s2880/Kconfig | 4 ---- src/mainboard/tyan/s2882/Kconfig | 4 ---- src/mainboard/tyan/s4880/Kconfig | 4 ---- src/mainboard/tyan/s4882/Kconfig | 4 ---- src/northbridge/amd/amdk8/Kconfig | 4 ++++ 12 files changed, 4 insertions(+), 44 deletions(-) diff --git a/src/mainboard/ibm/e325/Kconfig b/src/mainboard/ibm/e325/Kconfig index 10b6fde..0400677 100644 --- a/src/mainboard/ibm/e325/Kconfig +++ b/src/mainboard/ibm/e325/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/ibm/e326/Kconfig b/src/mainboard/ibm/e326/Kconfig index 005012a..bd2bb26 100644 --- a/src/mainboard/ibm/e326/Kconfig +++ b/src/mainboard/ibm/e326/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index c4de3a1..6b54645 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/iwill/dk8x/Kconfig b/src/mainboard/iwill/dk8x/Kconfig index af35bb6..f2660c6 100644 --- a/src/mainboard/iwill/dk8x/Kconfig +++ b/src/mainboard/iwill/dk8x/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/newisys/khepri/Kconfig b/src/mainboard/newisys/khepri/Kconfig index 7f618af..f1c2687 100644 --- a/src/mainboard/newisys/khepri/Kconfig +++ b/src/mainboard/newisys/khepri/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "Khepri" diff --git a/src/mainboard/tyan/s2850/Kconfig b/src/mainboard/tyan/s2850/Kconfig index e6e3df2..2866b0c 100644 --- a/src/mainboard/tyan/s2850/Kconfig +++ b/src/mainboard/tyan/s2850/Kconfig @@ -40,10 +40,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2875/Kconfig b/src/mainboard/tyan/s2875/Kconfig index 30aa01e..85c3ab4 100644 --- a/src/mainboard/tyan/s2875/Kconfig +++ b/src/mainboard/tyan/s2875/Kconfig @@ -42,10 +42,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config APIC_ID_OFFSET hex default 0x0 diff --git a/src/mainboard/tyan/s2880/Kconfig b/src/mainboard/tyan/s2880/Kconfig index 5186337..62b4e70 100644 --- a/src/mainboard/tyan/s2880/Kconfig +++ b/src/mainboard/tyan/s2880/Kconfig @@ -22,10 +22,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2880" diff --git a/src/mainboard/tyan/s2882/Kconfig b/src/mainboard/tyan/s2882/Kconfig index 646b5a8..bf980d7 100644 --- a/src/mainboard/tyan/s2882/Kconfig +++ b/src/mainboard/tyan/s2882/Kconfig @@ -23,10 +23,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S2882" diff --git a/src/mainboard/tyan/s4880/Kconfig b/src/mainboard/tyan/s4880/Kconfig index d4feacb..6c85c6c 100644 --- a/src/mainboard/tyan/s4880/Kconfig +++ b/src/mainboard/tyan/s4880/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4880" diff --git a/src/mainboard/tyan/s4882/Kconfig b/src/mainboard/tyan/s4882/Kconfig index 2bd3854..7723acf 100644 --- a/src/mainboard/tyan/s4882/Kconfig +++ b/src/mainboard/tyan/s4882/Kconfig @@ -30,10 +30,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 0 - config MAINBOARD_PART_NUMBER string default "S4882" diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index e5161ab..cc0cc66 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -64,6 +64,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + int + default 0 + config QRANK_DIMM_SUPPORT bool default n

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Patch set updated for coreboot: 6d38978 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8560 -gerrit commit 6d389782ce004a88c62ed6d50df34cd2008a7468 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 21 14:31:01 2015 +0200 AMD K8 fam10: Relocate SB_HT_CHAIN in devicetree When we want to scan the HT chain to southbridge first, we relocate it as the first item of dev->link_list of node 0. Change-Id: Ic73ba43aadb3c5e0c8d4b82ed7d41094692ea37f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/amdfam10/northbridge.c | 45 +++++++++++++++++++++++------ src/northbridge/amd/amdk8/northbridge.c | 46 +++++++++++++++++++++++------- 2 files changed, 72 insertions(+), 19 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 8503afd..a305f65 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -271,6 +271,36 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool return link->subordinate; } +/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + if (!CONFIG_SB_HT_CHAIN_ON_BUS0) + return; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 7; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; + } + prev = link; + link = link->next; + } +} + static void amdfam10_scan_chains(device_t dev) { unsigned nodeid; @@ -283,15 +313,6 @@ static void amdfam10_scan_chains(device_t dev) /* Do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 */ for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; - max = amdfam10_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -582,9 +603,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1200, }; +static void amdfam10_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdfam10_ops = { CHIP_NAME("AMD FAM10 Northbridge") .enable_dev = 0, + .init = amdfam10_nb_init, }; static void amdfam10_domain_read_resources(device_t dev) diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index edd1e1f..d1f3d81 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -240,6 +240,36 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ return link->subordinate; } +/* Do sb ht chain at first, in case s2885 put sb chain + * (8131/8111) on link2, but put 8151 on link0. + */ +static void relocate_sb_ht_chain(void) +{ + struct device *dev; + struct bus *link, *prev = NULL; + u8 sblink; + + if (!CONFIG_SB_HT_CHAIN_ON_BUS0) + return; + + dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); + sblink = (pci_read_config32(dev, 0x64)>>8) & 3; + link = dev->link_list; + + while (link) { + if (link->link_num == sblink) { + if (!prev) + return; + prev->next = link->next; + link->next = dev->link_list; + dev->link_list = link; + return; + } + prev = link; + link = link->next; + } +} + static void amdk8_scan_chains(device_t dev) { unsigned nodeid; @@ -251,18 +281,8 @@ static void amdk8_scan_chains(device_t dev) if (nodeid == 0) sblink = (pci_read_config32(dev, 0x64)>>8) & 3; - // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 for (link = dev->link_list; link; link = link->next) { bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); - } - - for (link = dev->link_list; link; link = link->next) { - bool is_sblink = (nodeid == 0) && (link->link_num == sblink); - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 0) && is_sblink) - continue; - max = amdk8_scan_chain(dev, nodeid, link, is_sblink, max); } @@ -604,9 +624,15 @@ static const struct pci_driver mcf0_driver __pci_driver = { .device = 0x1100, }; +static void amdk8_nb_init(void *chip_info) +{ + relocate_sb_ht_chain(); +} + struct chip_operations northbridge_amd_amdk8_ops = { CHIP_NAME("AMD K8 Northbridge") .enable_dev = 0, + .init = amdk8_nb_init, }; static void amdk8_domain_read_resources(device_t dev)

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Patch set updated for coreboot: 60eb39f AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0
by Kyösti Mälkki May 31, 2015

May 31, 2015

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8366 -gerrit commit 60eb39f8a9cbdc71b2aef1fd4c895474aa8097fb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 5 15:48:38 2015 +0200 AMD K8 fam10: Refactor Kconfig SB_HT_CHAIN_ON_BUS0 If SB_HT_CHAIN_ON_BUS0 is selected, HyperTransport chain for System Bus is the first to scan and it will be assigned with bus number 0. If HT_CHAIN_DISTRIBUTE is selected, each link will reserve a fixed range of bus numbers instead of assigning consecutive numbers across all the links. All fam10 have SB_HT_CHAIN_ON_BUS0 selected under northbridge. Follow-up can easily drop this if we find this is dictated by architecture. Change-Id: I8deddcb4c3fd679b6b27e2879d9dba3895c4dd6f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/advansus/a785e-i/Kconfig | 4 ---- src/mainboard/amd/bimini_fam10/Kconfig | 4 ---- src/mainboard/amd/dbm690t/Kconfig | 4 ---- src/mainboard/amd/mahogany/Kconfig | 4 ---- src/mainboard/amd/mahogany_fam10/Kconfig | 4 ---- src/mainboard/amd/pistachio/Kconfig | 4 ---- src/mainboard/amd/serengeti_cheetah/Kconfig | 5 +---- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 5 +---- src/mainboard/amd/tilapia_fam10/Kconfig | 4 ---- src/mainboard/arima/hdama/Kconfig | 4 ---- src/mainboard/asrock/939a785gmh/Kconfig | 4 ---- src/mainboard/asus/a8n_e/Kconfig | 5 +---- src/mainboard/asus/a8v-e_deluxe/Kconfig | 4 ---- src/mainboard/asus/a8v-e_se/Kconfig | 4 ---- src/mainboard/asus/k8v-x/Kconfig | 4 ---- src/mainboard/asus/kfsn4-dre/Kconfig | 4 ---- src/mainboard/asus/m2n-e/Kconfig | 5 +---- src/mainboard/asus/m2v-mx_se/Kconfig | 4 ---- src/mainboard/asus/m2v/Kconfig | 4 ---- src/mainboard/asus/m4a78-em/Kconfig | 4 ---- src/mainboard/asus/m4a785-m/Kconfig | 4 ---- src/mainboard/asus/m4a785t-m/Kconfig | 4 ---- src/mainboard/asus/m5a88-v/Kconfig | 4 ---- src/mainboard/avalue/eax-785e/Kconfig | 4 ---- src/mainboard/broadcom/blast/Kconfig | 4 ---- src/mainboard/gigabyte/ga_2761gxdk/Kconfig | 5 +---- src/mainboard/gigabyte/m57sli/Kconfig | 5 +---- src/mainboard/gigabyte/ma785gm/Kconfig | 4 ---- src/mainboard/gigabyte/ma785gmt/Kconfig | 4 ---- src/mainboard/gigabyte/ma78gm/Kconfig | 4 ---- src/mainboard/hp/dl145_g1/Kconfig | 5 +---- src/mainboard/hp/dl145_g3/Kconfig | 5 +---- src/mainboard/hp/dl165_g6_fam10/Kconfig | 5 +---- src/mainboard/iei/kino-780am2-fam10/Kconfig | 4 ---- src/mainboard/iwill/dk8_htx/Kconfig | 5 +---- src/mainboard/jetway/pa78vm5/Kconfig | 4 ---- src/mainboard/kontron/kt690/Kconfig | 4 ---- src/mainboard/msi/ms7135/Kconfig | 5 +---- src/mainboard/msi/ms7260/Kconfig | 5 +---- src/mainboard/msi/ms9185/Kconfig | 5 +---- src/mainboard/msi/ms9282/Kconfig | 4 ---- src/mainboard/msi/ms9652_fam10/Kconfig | 4 ---- src/mainboard/nvidia/l1_2pvv/Kconfig | 5 +---- src/mainboard/siemens/sitemp_g1p1/Kconfig | 4 ---- src/mainboard/sunw/ultra40/Kconfig | 5 +---- src/mainboard/supermicro/h8dme/Kconfig | 5 +---- src/mainboard/supermicro/h8dmr/Kconfig | 5 +---- src/mainboard/supermicro/h8dmr_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8qme_fam10/Kconfig | 5 +---- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ---- src/mainboard/technexion/tim5690/Kconfig | 4 ---- src/mainboard/technexion/tim8690/Kconfig | 4 ---- src/mainboard/tyan/s2881/Kconfig | 5 +---- src/mainboard/tyan/s2885/Kconfig | 5 +---- src/mainboard/tyan/s2891/Kconfig | 5 +---- src/mainboard/tyan/s2892/Kconfig | 5 +---- src/mainboard/tyan/s2895/Kconfig | 5 +---- src/mainboard/tyan/s2912/Kconfig | 5 +---- src/mainboard/tyan/s2912_fam10/Kconfig | 5 +---- src/mainboard/winent/mb6047/Kconfig | 5 +---- src/northbridge/amd/amdfam10/Kconfig | 6 ++++++ src/northbridge/amd/amdfam10/northbridge.c | 4 ++-- src/northbridge/amd/amdk8/Kconfig | 6 ++++-- src/northbridge/amd/amdk8/northbridge.c | 4 ++-- 64 files changed, 41 insertions(+), 246 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/Kconfig b/src/mainboard/advansus/a785e-i/Kconfig index 388249f..b6213d5 100644 --- a/src/mainboard/advansus/a785e-i/Kconfig +++ b/src/mainboard/advansus/a785e-i/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/bimini_fam10/Kconfig b/src/mainboard/amd/bimini_fam10/Kconfig index 369cb7e..261c60a 100644 --- a/src/mainboard/amd/bimini_fam10/Kconfig +++ b/src/mainboard/amd/bimini_fam10/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 70d63ad..77bafc5 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany/Kconfig b/src/mainboard/amd/mahogany/Kconfig index 394ad77..8861b4a 100644 --- a/src/mainboard/amd/mahogany/Kconfig +++ b/src/mainboard/amd/mahogany/Kconfig @@ -47,10 +47,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig index ec5ca0b..393882c 100644 --- a/src/mainboard/amd/mahogany_fam10/Kconfig +++ b/src/mainboard/amd/mahogany_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 9a91eec..2296e82 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -44,10 +44,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/amd/serengeti_cheetah/Kconfig b/src/mainboard/amd/serengeti_cheetah/Kconfig index e1363eb..2d2d4d1 100644 --- a/src/mainboard/amd/serengeti_cheetah/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah/Kconfig @@ -10,6 +10,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -55,10 +56,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index 2a3e6a7..3e6e025 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -41,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/amd/tilapia_fam10/Kconfig b/src/mainboard/amd/tilapia_fam10/Kconfig index 901d6b1..254cf66 100644 --- a/src/mainboard/amd/tilapia_fam10/Kconfig +++ b/src/mainboard/amd/tilapia_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/arima/hdama/Kconfig b/src/mainboard/arima/hdama/Kconfig index 49860b3..66177f5 100644 --- a/src/mainboard/arima/hdama/Kconfig +++ b/src/mainboard/arima/hdama/Kconfig @@ -38,10 +38,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asrock/939a785gmh/Kconfig b/src/mainboard/asrock/939a785gmh/Kconfig index cfaa599..2148385 100644 --- a/src/mainboard/asrock/939a785gmh/Kconfig +++ b/src/mainboard/asrock/939a785gmh/Kconfig @@ -49,10 +49,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig index 5b7c1e6..1852ae4 100644 --- a/src/mainboard/asus/a8n_e/Kconfig +++ b/src/mainboard/asus/a8n_e/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_939 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8712F select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT @@ -54,10 +55,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig index 8ebff31..a1c2fd9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/Kconfig +++ b/src/mainboard/asus/a8v-e_deluxe/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E Deluxe" diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig index d819b0d..dffe9eb 100644 --- a/src/mainboard/asus/a8v-e_se/Kconfig +++ b/src/mainboard/asus/a8v-e_se/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "A8V-E SE" diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig index 1deb5b6..52bf661 100644 --- a/src/mainboard/asus/k8v-x/Kconfig +++ b/src/mainboard/asus/k8v-x/Kconfig @@ -32,10 +32,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "K8V-X" diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 47fccda..2750c17 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -44,10 +44,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "KFSN4-DRE" diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig index b7375f2..02e516e 100644 --- a/src/mainboard/asus/m2n-e/Kconfig +++ b/src/mainboard/asus/m2n-e/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -57,10 +58,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "M2N-E" diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index ab155b9..efcfc81 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -67,10 +67,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x20 diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig index 35ad38d..72527be 100644 --- a/src/mainboard/asus/m2v/Kconfig +++ b/src/mainboard/asus/m2v/Kconfig @@ -36,10 +36,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "M2V" diff --git a/src/mainboard/asus/m4a78-em/Kconfig b/src/mainboard/asus/m4a78-em/Kconfig index b00a0b6..0382daf 100644 --- a/src/mainboard/asus/m4a78-em/Kconfig +++ b/src/mainboard/asus/m4a78-em/Kconfig @@ -39,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785-m/Kconfig b/src/mainboard/asus/m4a785-m/Kconfig index f93c484..a945d2a 100644 --- a/src/mainboard/asus/m4a785-m/Kconfig +++ b/src/mainboard/asus/m4a785-m/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index d98ad95..a347f02 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -42,10 +42,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig index 1430189..a5f19f5 100644 --- a/src/mainboard/asus/m5a88-v/Kconfig +++ b/src/mainboard/asus/m5a88-v/Kconfig @@ -50,10 +50,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/avalue/eax-785e/Kconfig b/src/mainboard/avalue/eax-785e/Kconfig index 38a3aa3..9d7c2e0 100644 --- a/src/mainboard/avalue/eax-785e/Kconfig +++ b/src/mainboard/avalue/eax-785e/Kconfig @@ -52,10 +52,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/broadcom/blast/Kconfig b/src/mainboard/broadcom/blast/Kconfig index b821f7a..ddd2aca 100644 --- a/src/mainboard/broadcom/blast/Kconfig +++ b/src/mainboard/broadcom/blast/Kconfig @@ -31,10 +31,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "Blast" diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig index a79c28f..e182c99 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Kconfig +++ b/src/mainboard/gigabyte/ga_2761gxdk/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_SIS_SIS966 + select HT_CHAIN_DISTRIBUTE select SUPERIO_ITE_IT8716F select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -37,10 +38,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-2761GXDK" diff --git a/src/mainboard/gigabyte/m57sli/Kconfig b/src/mainboard/gigabyte/m57sli/Kconfig index 6ef94ce..cc8be43 100644 --- a/src/mainboard/gigabyte/m57sli/Kconfig +++ b/src/mainboard/gigabyte/m57sli/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_ITE_IT8716F @@ -41,10 +42,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "GA-M57SLI-S4" diff --git a/src/mainboard/gigabyte/ma785gm/Kconfig b/src/mainboard/gigabyte/ma785gm/Kconfig index 8f44e76..bf441e9 100644 --- a/src/mainboard/gigabyte/ma785gm/Kconfig +++ b/src/mainboard/gigabyte/ma785gm/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma785gmt/Kconfig b/src/mainboard/gigabyte/ma785gmt/Kconfig index 03b9237..827c8da 100644 --- a/src/mainboard/gigabyte/ma785gmt/Kconfig +++ b/src/mainboard/gigabyte/ma785gmt/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/gigabyte/ma78gm/Kconfig b/src/mainboard/gigabyte/ma78gm/Kconfig index 32421e8..3d85708 100644 --- a/src/mainboard/gigabyte/ma78gm/Kconfig +++ b/src/mainboard/gigabyte/ma78gm/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/hp/dl145_g1/Kconfig b/src/mainboard/hp/dl145_g1/Kconfig index 0c6d642..74ce0e7 100644 --- a/src/mainboard/hp/dl145_g1/Kconfig +++ b/src/mainboard/hp/dl145_g1/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_HARD_RESET select HAVE_OPTION_TABLE @@ -28,10 +29,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "ProLiant DL145 G1" diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index 439188a..da20fb3 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index 8376d89..ca36aaf 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 @@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x6 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 15 diff --git a/src/mainboard/iei/kino-780am2-fam10/Kconfig b/src/mainboard/iei/kino-780am2-fam10/Kconfig index deea898..4b3bce6 100644 --- a/src/mainboard/iei/kino-780am2-fam10/Kconfig +++ b/src/mainboard/iei/kino-780am2-fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/iwill/dk8_htx/Kconfig b/src/mainboard/iwill/dk8_htx/Kconfig index cdfd99a..929f47f 100644 --- a/src/mainboard/iwill/dk8_htx/Kconfig +++ b/src/mainboard/iwill/dk8_htx/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT select HAVE_OPTION_TABLE @@ -38,10 +39,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config HT_CHAIN_END_UNITID_BASE hex default 0x6 diff --git a/src/mainboard/jetway/pa78vm5/Kconfig b/src/mainboard/jetway/pa78vm5/Kconfig index b13bead..30478d2 100644 --- a/src/mainboard/jetway/pa78vm5/Kconfig +++ b/src/mainboard/jetway/pa78vm5/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 8d1f039..e679e66 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/msi/ms7135/Kconfig b/src/mainboard/msi/ms7135/Kconfig index f2cfd9a..50f989e 100644 --- a/src/mainboard/msi/ms7135/Kconfig +++ b/src/mainboard/msi/ms7135/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_754 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 13 diff --git a/src/mainboard/msi/ms7260/Kconfig b/src/mainboard/msi/ms7260/Kconfig index 0e7e592..e3863a0 100644 --- a/src/mainboard/msi/ms7260/Kconfig +++ b/src/mainboard/msi/ms7260/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_DDR2 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -39,10 +40,6 @@ config MEM_TRAIN_SEQ int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-7260" diff --git a/src/mainboard/msi/ms9185/Kconfig b/src/mainboard/msi/ms9185/Kconfig index 0b0ff1c..355fdcf 100644 --- a/src/mainboard/msi/ms9185/Kconfig +++ b/src/mainboard/msi/ms9185/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM5780 select SOUTHBRIDGE_BROADCOM_BCM5785 + select HT_CHAIN_DISTRIBUTE select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -34,10 +35,6 @@ config APIC_ID_OFFSET hex default 0x8 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MS-9185" diff --git a/src/mainboard/msi/ms9282/Kconfig b/src/mainboard/msi/ms9282/Kconfig index f109375..dd96992 100644 --- a/src/mainboard/msi/ms9282/Kconfig +++ b/src/mainboard/msi/ms9282/Kconfig @@ -33,10 +33,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config MAINBOARD_PART_NUMBER string default "MS-9282" diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index c1c095b..c64fdda 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -76,10 +76,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x00 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config VAR_MTRR_HOLE bool default n diff --git a/src/mainboard/nvidia/l1_2pvv/Kconfig b/src/mainboard/nvidia/l1_2pvv/Kconfig index 57911f7..e9664ac 100644 --- a/src/mainboard/nvidia/l1_2pvv/Kconfig +++ b/src/mainboard/nvidia/l1_2pvv/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627EHG @@ -43,10 +44,6 @@ config MCP55_NUM int default 2 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "l1_2pvv" diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index dff329f..d9ad74b 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -43,10 +43,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 8f3ff2a..a29cf16 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE @@ -56,10 +57,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dme/Kconfig b/src/mainboard/supermicro/h8dme/Kconfig index 52d5581..35f9bf0 100644 --- a/src/mainboard/supermicro/h8dme/Kconfig +++ b/src/mainboard/supermicro/h8dme/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -60,10 +61,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr/Kconfig b/src/mainboard/supermicro/h8dmr/Kconfig index f85460b..9efc5d2 100644 --- a/src/mainboard/supermicro/h8dmr/Kconfig +++ b/src/mainboard/supermicro/h8dmr/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -59,10 +60,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8dmr_fam10/Kconfig b/src/mainboard/supermicro/h8dmr_fam10/Kconfig index 0f94620..0d20204 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Kconfig +++ b/src/mainboard/supermicro/h8dmr_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select MCP55_USE_AZA select SUPERIO_WINBOND_W83627HF @@ -55,10 +56,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8qme_fam10/Kconfig b/src/mainboard/supermicro/h8qme_fam10/Kconfig index 5b195bb..27a74bb 100644 --- a/src/mainboard/supermicro/h8qme_fam10/Kconfig +++ b/src/mainboard/supermicro/h8qme_fam10/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -53,10 +54,6 @@ config HT_CHAIN_UNITID_BASE hex default 0x1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index 3105493..0673390 100644 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -40,10 +40,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 98dce39..0220d77 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -37,10 +37,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 4e0b25a..ad80e85 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -36,10 +36,6 @@ config MAX_PHYSICAL_CPUS int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 1 - config HT_CHAIN_END_UNITID_BASE hex default 0x1 diff --git a/src/mainboard/tyan/s2881/Kconfig b/src/mainboard/tyan/s2881/Kconfig index 6c759e1..de641cd 100644 --- a/src/mainboard/tyan/s2881/Kconfig +++ b/src/mainboard/tyan/s2881/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8111 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -24,10 +25,6 @@ config APIC_ID_OFFSET hex default 0x0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2881" diff --git a/src/mainboard/tyan/s2885/Kconfig b/src/mainboard/tyan/s2885/Kconfig index 86e43f8..b218ab7 100644 --- a/src/mainboard/tyan/s2885/Kconfig +++ b/src/mainboard/tyan/s2885/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 select SOUTHBRIDGE_AMD_AMD8151 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2885" diff --git a/src/mainboard/tyan/s2891/Kconfig b/src/mainboard/tyan/s2891/Kconfig index 3d1c1fb..238f5bc 100644 --- a/src/mainboard/tyan/s2891/Kconfig +++ b/src/mainboard/tyan/s2891/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -23,10 +24,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2891" diff --git a/src/mainboard/tyan/s2892/Kconfig b/src/mainboard/tyan/s2892/Kconfig index b9c4105..cbe076c 100644 --- a/src/mainboard/tyan/s2892/Kconfig +++ b/src/mainboard/tyan/s2892/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627HF select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -43,10 +44,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2895/Kconfig b/src/mainboard/tyan/s2895/Kconfig index 544b0c5..21db63c 100644 --- a/src/mainboard/tyan/s2895/Kconfig +++ b/src/mainboard/tyan/s2895/Kconfig @@ -6,6 +6,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 select SOUTHBRIDGE_AMD_AMD8131 + select HT_CHAIN_DISTRIBUTE select SUPERIO_SMSC_LPC47B397 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -47,10 +48,6 @@ config HT_CHAIN_END_UNITID_BASE hex default 0x20 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config IRQ_SLOT_COUNT int default 11 diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig index 26d9a53..7ad1a1c 100644 --- a/src/mainboard/tyan/s2912/Kconfig +++ b/src/mainboard/tyan/s2912/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -38,10 +39,6 @@ config MEM_TRAIN_SEQ int default 1 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912" diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 1dd74ca..b5e31fa 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_NVIDIA_MCP55 + select HT_CHAIN_DISTRIBUTE select MCP55_USE_NIC select SUPERIO_WINBOND_W83627HF select PARALLEL_CPU_INIT @@ -35,10 +36,6 @@ config APIC_ID_OFFSET hex default 0 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "S2912 (Fam10)" diff --git a/src/mainboard/winent/mb6047/Kconfig b/src/mainboard/winent/mb6047/Kconfig index 86b0ae0..622441e 100644 --- a/src/mainboard/winent/mb6047/Kconfig +++ b/src/mainboard/winent/mb6047/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select HT_CHAIN_DISTRIBUTE select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE @@ -25,10 +26,6 @@ config APIC_ID_OFFSET hex default 0x10 -config SB_HT_CHAIN_ON_BUS0 - int - default 2 - config MAINBOARD_PART_NUMBER string default "MB6047" diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index b298ee1..fa8a26a 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -64,6 +64,12 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY bool default n +config SB_HT_CHAIN_ON_BUS0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n + config DIMM_FBDIMM bool default n diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index a305f65..8586b60 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -216,11 +216,11 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; /* One node can have 8 link and segn is the same. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 8); link->secondary = min_bus; diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index cc0cc66..b293ce3 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -65,8 +65,10 @@ config SB_HT_CHAIN_UNITID_OFFSET_ONLY default n config SB_HT_CHAIN_ON_BUS0 - int - default 0 + def_bool y + +config HT_CHAIN_DISTRIBUTE + def_bool n config QRANK_DIMM_SUPPORT bool diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index d1f3d81..b46e104 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -179,11 +179,11 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_ * so we set the subordinate bus number to 0xff for the moment. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink) + if (!CONFIG_SB_HT_CHAIN_ON_BUS0 || !is_sblink) max++; /* Second chain will be on 0x40, third 0x80, forth 0xc0. */ - if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink) + if (CONFIG_HT_CHAIN_DISTRIBUTE && !is_sblink) max = ALIGN_UP(max, 0x40); link->secondary = min_bus;

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